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Red Hat Bugzilla – Attachment 645400 Details for
Bug 876864
[abrt] xorg-x11-server-Xorg-1.12.3-1.fc17: Xorg server crashed
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File: Xorg.0.log
Xorg.0.log (text/plain), 7.81 MB, created by
JORA
on 2012-11-15 07:39:26 UTC
(
hide
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Description:
File: Xorg.0.log
Filename:
MIME Type:
Creator:
JORA
Created:
2012-11-15 07:39:26 UTC
Size:
7.81 MB
patch
obsolete
>[ 35.198] >X.Org X Server 1.12.3 >Release Date: 2012-07-09 >[ 35.198] X Protocol Version 11, Revision 0 >[ 35.198] Build Operating System: 2.6.32-279.2.1.el6.x86_64 >[ 35.198] Current Operating System: Linux big 3.5.3-1.fc17.x86_64 #1 SMP Wed Aug 29 18:46:34 UTC 2012 x86_64 >[ 35.198] Kernel command line: BOOT_IMAGE=/vmlinuz-3.5.3-1.fc17.x86_64 root=/dev/mapper/vg-lv_root ro rd.md=0 rd.dm=0 SYSFONT=True rd.lvm.lv=vg/lv_root rd.luks=0 KEYTABLE=ru rd.lvm.lv=vg/lv_swap LANG=en_US.UTF-8 rhgb quiet >[ 35.198] Build Date: 20 August 2012 02:12:31AM >[ 35.198] Build ID: xorg-x11-server 1.12.3-1.fc17 >[ 35.198] Current version of pixman: 0.24.4 >[ 35.198] Before reporting problems, check http://wiki.x.org > to make sure that you have the latest version. >[ 35.198] Markers: (--) probed, (**) from config file, (==) default setting, > (++) from command line, (!!) notice, (II) informational, > (WW) warning, (EE) error, (NI) not implemented, (??) unknown. >[ 35.198] (==) Log file: "/var/log/Xorg.0.log", Time: Fri Oct 19 08:08:43 2012 >[ 35.226] (==) Using config directory: "/etc/X11/xorg.conf.d" >[ 35.226] (==) Using system config directory "/usr/share/X11/xorg.conf.d" >[ 35.226] (==) No Layout section. Using the first Screen section. >[ 35.226] (==) No screen section available. Using defaults. >[ 35.226] (**) |-->Screen "Default Screen Section" (0) >[ 35.226] (**) | |-->Monitor "<default monitor>" >[ 35.226] (==) No monitor specified for screen "Default Screen Section". > Using a default monitor configuration. >[ 35.226] (==) Automatically adding devices >[ 35.226] (==) Automatically enabling devices >[ 35.226] (==) FontPath set to: > catalogue:/etc/X11/fontpath.d, > built-ins >[ 35.226] (==) ModulePath set to "/usr/lib64/xorg/modules" >[ 35.226] (II) The server relies on udev to provide the list of input devices. > If no devices become available, reconfigure udev or disable AutoAddDevices. >[ 35.226] (II) Loader magic: 0x7c6ac0 >[ 35.226] (II) Module ABI versions: >[ 35.226] X.Org ANSI C Emulation: 0.4 >[ 35.226] X.Org Video Driver: 12.0 >[ 35.226] X.Org XInput driver : 16.0 >[ 35.226] X.Org Server Extension : 6.0 >[ 35.228] (--) PCI:*(0:1:0:0) 1002:95c4:1043:19d3 rev 0, Mem @ 0xe0000000/268435456, 0xfdef0000/65536, I/O @ 0x00009000/256, BIOS @ 0x????????/131072 >[ 35.228] (II) LoadModule: "extmod" >[ 35.228] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so >[ 35.229] (II) Module extmod: vendor="X.Org Foundation" >[ 35.229] compiled for 1.12.3, module version = 1.0.0 >[ 35.229] Module class: X.Org Server Extension >[ 35.229] ABI class: X.Org Server Extension, version 6.0 >[ 35.229] (II) Loading extension SELinux >[ 35.229] (II) Loading extension MIT-SCREEN-SAVER >[ 35.229] (II) Loading extension XFree86-VidModeExtension >[ 35.229] (II) Loading extension XFree86-DGA >[ 35.229] (II) Loading extension DPMS >[ 35.229] (II) Loading extension XVideo >[ 35.229] (II) Loading extension XVideo-MotionCompensation >[ 35.229] (II) Loading extension X-Resource >[ 35.229] (II) LoadModule: "dbe" >[ 35.230] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so >[ 35.230] (II) Module dbe: vendor="X.Org Foundation" >[ 35.230] compiled for 1.12.3, module version = 1.0.0 >[ 35.230] Module class: X.Org Server Extension >[ 35.230] ABI class: X.Org Server Extension, version 6.0 >[ 35.230] (II) Loading extension DOUBLE-BUFFER >[ 35.230] (II) LoadModule: "glx" >[ 35.230] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so >[ 35.230] (II) Module glx: vendor="X.Org Foundation" >[ 35.230] compiled for 1.12.3, module version = 1.0.0 >[ 35.230] ABI class: X.Org Server Extension, version 6.0 >[ 35.230] (==) AIGLX enabled >[ 35.230] (II) Loading extension GLX >[ 35.230] (II) LoadModule: "record" >[ 35.231] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so >[ 35.231] (II) Module record: vendor="X.Org Foundation" >[ 35.231] compiled for 1.12.3, module version = 1.13.0 >[ 35.231] Module class: X.Org Server Extension >[ 35.231] ABI class: X.Org Server Extension, version 6.0 >[ 35.231] (II) Loading extension RECORD >[ 35.231] (II) LoadModule: "dri" >[ 35.231] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so >[ 35.231] (II) Module dri: vendor="X.Org Foundation" >[ 35.232] compiled for 1.12.3, module version = 1.0.0 >[ 35.232] ABI class: X.Org Server Extension, version 6.0 >[ 35.232] (II) Loading extension XFree86-DRI >[ 35.232] (II) LoadModule: "dri2" >[ 35.232] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so >[ 35.232] (II) Module dri2: vendor="X.Org Foundation" >[ 35.232] compiled for 1.12.3, module version = 1.2.0 >[ 35.232] ABI class: X.Org Server Extension, version 6.0 >[ 35.232] (II) Loading extension DRI2 >[ 35.232] (==) Matched ati as autoconfigured driver 0 >[ 35.232] (==) Matched vesa as autoconfigured driver 1 >[ 35.232] (==) Matched modesetting as autoconfigured driver 2 >[ 35.232] (==) Matched fbdev as autoconfigured driver 3 >[ 35.232] (==) Assigned the driver to the xf86ConfigLayout >[ 35.232] (II) LoadModule: "ati" >[ 35.232] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so >[ 35.232] (II) Module ati: vendor="X.Org Foundation" >[ 35.232] compiled for 1.12.0, module version = 6.14.99 >[ 35.232] Module class: X.Org Video Driver >[ 35.232] ABI class: X.Org Video Driver, version 12.0 >[ 35.232] (II) LoadModule: "radeon" >[ 35.233] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so >[ 35.233] (II) Module radeon: vendor="X.Org Foundation" >[ 35.233] compiled for 1.12.0, module version = 6.14.99 >[ 35.233] Module class: X.Org Video Driver >[ 35.233] ABI class: X.Org Video Driver, version 12.0 >[ 35.233] (II) LoadModule: "vesa" >[ 35.233] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so >[ 35.233] (II) Module vesa: vendor="X.Org Foundation" >[ 35.233] compiled for 1.12.0, module version = 2.3.1 >[ 35.233] Module class: X.Org Video Driver >[ 35.233] ABI class: X.Org Video Driver, version 12.0 >[ 35.233] (II) LoadModule: "modesetting" >[ 35.234] (WW) Warning, couldn't open module modesetting >[ 35.234] (II) UnloadModule: "modesetting" >[ 35.234] (II) Unloading modesetting >[ 35.234] (EE) Failed to load module "modesetting" (module does not exist, 0) >[ 35.234] (II) LoadModule: "fbdev" >[ 35.234] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so >[ 35.234] (II) Module fbdev: vendor="X.Org Foundation" >[ 35.234] compiled for 1.11.99.901, module version = 0.4.2 >[ 35.234] ABI class: X.Org Video Driver, version 12.0 >[ 35.234] (II) RADEON: Driver for ATI Radeon chipsets: > ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI), > ATI Radeon Mobility X300 (M24) 3152 (PCIE), > ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI), > ATI Radeon X600 (RV380) 3E50 (PCIE), > ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136, > ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP), > ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), > ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP), > ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), > ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP), > ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), > ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650, > ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237, > ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336, > ATI Radeon IGP330M/340M/350M (U2) 4337, > ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI), > ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP), > ATI Radeon X800PRO (R420) JI (AGP), > ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), > ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), > ATI Radeon Mobility 9800 (M18) JN (AGP), > ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP), > ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP), > ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP), > ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP), > ATI Radeon Mobility M7 LW (AGP), > ATI Mobility FireGL 7800 M7 LX (AGP), > ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), > ATI FireGL Mobility 9000 (M9) Ld (AGP), > ATI Radeon Mobility 9000 (M9) Lf (AGP), > ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI, > ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), > ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP), > ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), > ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), > ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), > ATI Radeon Mobility 9600 (M10) NQ (AGP), > ATI Radeon Mobility 9600 (M11) NR (AGP), > ATI Radeon Mobility 9600 (M10) NS (AGP), > ATI FireGL Mobility T2 (M10) NT (AGP), > ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP), > ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), > ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), > ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI), > ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI), > ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI), > ATI Radeon Mobility X300 (M22) 5460 (PCIE), > ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE), > ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE), > ATI Radeon X800PRO (R423) UI (PCIE), > ATI Radeon X800LE (R423) UJ (PCIE), > ATI Radeon X800SE (R423) UK (PCIE), > ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE), > ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE), > ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE), > ATI FireGL unknown (R423) UR (PCIE), > ATI FireGL unknown (R423) UT (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility Radeon X700 XL (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834, > ATI Radeon Mobility 9100 IGP (U3) 5835, > ATI Radeon XPRESS 200 5954 (PCIE), > ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP), > ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), > ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI), > ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE), > ATI Radeon XPRESS 200M 5975 (PCIE), > ATI Radeon XPRESS 200 5A41 (PCIE), > ATI Radeon XPRESS 200M 5A42 (PCIE), > ATI Radeon XPRESS 200 5A61 (PCIE), > ATI Radeon XPRESS 200M 5A62 (PCIE), > ATI Radeon X300 (RV370) 5B60 (PCIE), > ATI Radeon X600 (RV370) 5B62 (PCIE), > ATI Radeon X550 (RV370) 5B63 (PCIE), > ATI FireGL V3100 (RV370) 5B64 (PCIE), > ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), > ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), > ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), > ATI Mobility Radeon X800 XT (M28) (PCIE), > ATI Mobility FireGL V5100 (M28) (PCIE), > ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE), > ATI Radeon X850 XT PE (R480) (PCIE), > ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE), > ATI unknown Radeon / FireGL (R480) 5D50 (PCIE), > ATI Radeon X850 XT (R480) (PCIE), > ATI Radeon X800XT (R423) 5D57 (PCIE), > ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE), > ATI Radeon X700 PRO (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800, > ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800, > ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300, > ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800, > ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800, > ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505, > ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL, > ATI Mobility Radeon X1400, ATI Radeon X1300/X1550, > ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300, > ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350, > ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550, > ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450, > ATI Radeon X1300/X1550, ATI Mobility Radeon X2300, > ATI Mobility Radeon X2300, ATI Mobility Radeon X1350, > ATI Mobility Radeon X1350, ATI Mobility Radeon X1450, > ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350, > ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600, > ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600, > ATI Mobility FireGL V5200, ATI Mobility Radeon X1600, > ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600, > ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400, > ATI Mobility FireGL V5250, ATI Mobility Radeon X1700, > ATI Mobility Radeon X1700 XT, ATI FireGL V5200, > ATI Mobility Radeon X1700, ATI Radeon X2300HD, > ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300, > ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950, > ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560, > ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400, > ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560, > ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835, > ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200, > ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740, > ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT, > ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT, > ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600, > ATI Radeon 4800 Series, ATI Radeon HD 4870 x2, > ATI Radeon 4800 Series, ATI Radeon HD 4850 x2, > ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL), > ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2, > ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270, > AMD FireStream 9250, ATI FirePro V8700 (FireGL), > ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98, > ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series, > ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98, > ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP), > ATI Mobility Radeon HD 4670, ATI FirePro M5750, > ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP), > ATI RV730XT [Radeon HD 4670], ATI RADEON E4600, > ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650], > ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL), > ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830, > ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740, > ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770, > ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT, > ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000, > ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT, > ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610, > ATI FireMV 2260, ATI RV670, ATI Radeon HD3870, > ATI Mobility Radeon HD 3850, ATI Radeon HD3850, > ATI Mobility Radeon HD 3850 X2, ATI RV670, > ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2, > ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850, > ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550, > ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710, > ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series, > ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series, > ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630, > ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT, > ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP, > ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630, > ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600, > ATI FireGL V3600, ATI Radeon HD 2600 LE, > ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470, > ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series, > ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430, > ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450, > ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series, > ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO, > ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO, > ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670, > ATI Mobility FireGL V5700, ATI Mobility FireGL V5725, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics, > ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2, > SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200, > ATI Radeon 4100, ATI Mobility Radeon HD 4200, > ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250, > AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics, > AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics, > AMD Radeon HD 6300 Series Graphics, > AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370, > AMD Firestream 9350, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series, > ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series, > ATI Mobility Radeon HD 5800 Series, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670, > ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics, > ATI Mobility Radeon Graphics, CEDAR, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR, > ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN, > CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series, > BARTS, BARTS, Mobility Radeon HD 6000 Series, > Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS, > AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series, > AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA, > ARUBA, ARUBA, ARUBA, ARUBA >[ 35.238] (II) VESA: driver for VESA chipsets: vesa >[ 35.238] (II) FBDEV: driver for framebuffer: fbdev >[ 35.239] (++) using VT number 1 > >[ 35.240] (II) [KMS] Kernel modesetting enabled. >[ 35.240] (WW) Falling back to old probe method for vesa >[ 35.240] (WW) Falling back to old probe method for fbdev >[ 35.240] (II) Loading sub module "fbdevhw" >[ 35.240] (II) LoadModule: "fbdevhw" >[ 35.240] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so >[ 35.240] (II) Module fbdevhw: vendor="X.Org Foundation" >[ 35.240] compiled for 1.12.3, module version = 0.0.2 >[ 35.240] ABI class: X.Org Video Driver, version 12.0 >[ 35.240] (II) RADEON(0): RADEONPreInit_KMS >[ 35.240] (II) RADEON(0): Creating default Display subsection in Screen section > "Default Screen Section" for depth/fbbpp 24/32 >[ 35.240] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32 >[ 35.240] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) >[ 35.240] (==) RADEON(0): Default visual is TrueColor >[ 35.240] (==) RADEON(0): RGB weight 888 >[ 35.241] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) >[ 35.241] (--) RADEON(0): Chipset: "ATI Mobility Radeon HD 3400 Series" (ChipID = 0x95c4) >[ 35.241] (II) RADEON(0): PCIE card detected >[ 35.241] drmOpenDevice: node name is /dev/dri/card0 >[ 35.241] drmOpenDevice: open result is 8, (OK) >[ 35.241] drmOpenByBusid: Searching for BusID pci:0000:01:00.0 >[ 35.241] drmOpenDevice: node name is /dev/dri/card0 >[ 35.241] drmOpenDevice: open result is 8, (OK) >[ 35.241] drmOpenByBusid: drmOpenMinor returns 8 >[ 35.241] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0 >[ 35.241] (II) Loading sub module "exa" >[ 35.241] (II) LoadModule: "exa" >[ 35.241] (II) Loading /usr/lib64/xorg/modules/libexa.so >[ 35.241] (II) Module exa: vendor="X.Org Foundation" >[ 35.241] compiled for 1.12.3, module version = 2.5.0 >[ 35.241] ABI class: X.Org Video Driver, version 12.0 >[ 35.241] (II) RADEON(0): KMS Color Tiling: enabled >[ 35.241] (II) RADEON(0): KMS Pageflipping: enabled >[ 35.241] (II) RADEON(0): SwapBuffers wait for vsync: enabled >[ 35.255] (II) RADEON(0): Output VGA-0 has no monitor section >[ 35.255] (II) RADEON(0): Output LVDS has no monitor section >[ 35.257] (II) RADEON(0): Output HDMI-0 has no monitor section >[ 35.272] (II) RADEON(0): EDID for output VGA-0 >[ 35.272] (II) RADEON(0): EDID for output LVDS >[ 35.272] (II) RADEON(0): Manufacturer: AUO Model: 8174 Serial#: 0 >[ 35.272] (II) RADEON(0): Year: 2006 Week: 1 >[ 35.272] (II) RADEON(0): EDID Version: 1.3 >[ 35.272] (II) RADEON(0): Digital Display Input >[ 35.272] (II) RADEON(0): Max Image Size [cm]: horiz.: 33 vert.: 21 >[ 35.272] (II) RADEON(0): Gamma: 2.20 >[ 35.272] (II) RADEON(0): No DPMS capabilities specified >[ 35.272] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 >[ 35.272] (II) RADEON(0): First detailed timing is preferred mode >[ 35.272] (II) RADEON(0): redX: 0.590 redY: 0.345 greenX: 0.315 greenY: 0.555 >[ 35.272] (II) RADEON(0): blueX: 0.155 blueY: 0.155 whiteX: 0.313 whiteY: 0.329 >[ 35.272] (II) RADEON(0): Manufacturer's mask: 0 >[ 35.272] (II) RADEON(0): Supported detailed timing: >[ 35.272] (II) RADEON(0): clock: 71.1 MHz Image Size: 331 x 207 mm >[ 35.272] (II) RADEON(0): h_active: 1280 h_sync: 1328 h_sync_end 1360 h_blank_end 1440 h_border: 0 >[ 35.272] (II) RADEON(0): v_active: 800 v_sync: 803 v_sync_end 809 v_blanking: 823 v_border: 0 >[ 35.272] (II) RADEON(0): Unknown vendor-specific block f >[ 35.273] (II) RADEON(0): AUO >[ 35.273] (II) RADEON(0): B154EW08 V1 >[ 35.273] (II) RADEON(0): EDID (in hex): >[ 35.273] (II) RADEON(0): 00ffffffffffff0006af748100000000 >[ 35.273] (II) RADEON(0): 01100103802115780a1cf59758508e27 >[ 35.273] (II) RADEON(0): 27505400000001010101010101010101 >[ 35.273] (II) RADEON(0): 010101010101c71b00a0502017303020 >[ 35.273] (II) RADEON(0): 36004bcf100000180000000f00000000 >[ 35.273] (II) RADEON(0): 00000000000000000020000000fe0041 >[ 35.273] (II) RADEON(0): 554f0a202020202020202020000000fe >[ 35.273] (II) RADEON(0): 004231353445573038205631200a0043 >[ 35.273] (II) RADEON(0): Printing probed modes for output LVDS >[ 35.273] (II) RADEON(0): Modeline "1280x800"x60.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 35.273] (II) RADEON(0): Modeline "1280x720"x59.9 74.50 1280 1344 1472 1664 720 723 728 748 -hsync +vsync (44.8 kHz) >[ 35.273] (II) RADEON(0): Modeline "1152x768"x59.8 71.75 1152 1216 1328 1504 768 771 781 798 -hsync +vsync (47.7 kHz) >[ 35.273] (II) RADEON(0): Modeline "1024x768"x120.1 133.47 1024 1100 1212 1400 768 768 770 794 doublescan -hsync +vsync (95.3 kHz d) >[ 35.273] (II) RADEON(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz d) >[ 35.273] (II) RADEON(0): Modeline "1024x768"x59.9 63.50 1024 1072 1176 1328 768 771 775 798 -hsync +vsync (47.8 kHz) >[ 35.273] (II) RADEON(0): Modeline "960x720"x120.0 117.00 960 1024 1128 1300 720 720 722 750 doublescan -hsync +vsync (90.0 kHz d) >[ 35.273] (II) RADEON(0): Modeline "928x696"x120.1 109.15 928 976 1088 1264 696 696 698 719 doublescan -hsync +vsync (86.4 kHz d) >[ 35.273] (II) RADEON(0): Modeline "896x672"x120.0 102.40 896 960 1060 1224 672 672 674 697 doublescan -hsync +vsync (83.7 kHz d) >[ 35.273] (II) RADEON(0): Modeline "800x600"x120.0 81.00 800 832 928 1080 600 600 602 625 doublescan +hsync +vsync (75.0 kHz d) >[ 35.273] (II) RADEON(0): Modeline "800x600"x60.3 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz d) >[ 35.273] (II) RADEON(0): Modeline "800x600"x59.9 38.25 800 832 912 1024 600 603 607 624 -hsync +vsync (37.4 kHz) >[ 35.273] (II) RADEON(0): Modeline "800x600"x56.2 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (35.2 kHz d) >[ 35.273] (II) RADEON(0): Modeline "848x480"x59.7 31.50 848 872 952 1056 480 483 493 500 -hsync +vsync (29.8 kHz) >[ 35.273] (II) RADEON(0): Modeline "700x525"x120.0 61.00 700 744 820 940 525 526 532 541 doublescan +hsync +vsync (64.9 kHz d) >[ 35.273] (II) RADEON(0): Modeline "720x480"x59.7 26.75 720 744 808 896 480 483 493 500 -hsync +vsync (29.9 kHz) >[ 35.273] (II) RADEON(0): Modeline "640x512"x120.0 54.00 640 664 720 844 512 512 514 533 doublescan +hsync +vsync (64.0 kHz d) >[ 35.273] (II) RADEON(0): Modeline "640x480"x120.0 54.00 640 688 744 900 480 480 482 500 doublescan +hsync +vsync (60.0 kHz d) >[ 35.273] (II) RADEON(0): Modeline "640x480"x59.9 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz d) >[ 35.274] (II) RADEON(0): Modeline "640x480"x59.4 23.75 640 664 720 800 480 483 487 500 -hsync +vsync (29.7 kHz) >[ 35.274] (II) RADEON(0): Modeline "512x384"x120.0 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (48.4 kHz d) >[ 35.274] (II) RADEON(0): Modeline "400x300"x120.6 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (37.9 kHz d) >[ 35.274] (II) RADEON(0): Modeline "400x300"x112.7 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (35.2 kHz d) >[ 35.274] (II) RADEON(0): Modeline "320x240"x120.1 12.59 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (31.5 kHz d) >[ 35.276] (II) RADEON(0): EDID for output HDMI-0 >[ 35.276] (II) RADEON(0): Output VGA-0 disconnected >[ 35.276] (II) RADEON(0): Output LVDS connected >[ 35.276] (II) RADEON(0): Output HDMI-0 disconnected >[ 35.276] (II) RADEON(0): Using exact sizes for initial modes >[ 35.276] (II) RADEON(0): Output LVDS using initial mode 1280x800 +0+0 >[ 35.276] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated. >[ 35.276] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fbd8000 >[ 35.276] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM >[ 35.276] (==) RADEON(0): DPI set to (96, 96) >[ 35.276] (II) Loading sub module "fb" >[ 35.276] (II) LoadModule: "fb" >[ 35.276] (II) Loading /usr/lib64/xorg/modules/libfb.so >[ 35.277] (II) Module fb: vendor="X.Org Foundation" >[ 35.277] compiled for 1.12.3, module version = 1.0.0 >[ 35.277] ABI class: X.Org ANSI C Emulation, version 0.4 >[ 35.277] (II) Loading sub module "ramdac" >[ 35.277] (II) LoadModule: "ramdac" >[ 35.277] (II) Module "ramdac" already built-in >[ 35.277] (II) UnloadModule: "vesa" >[ 35.277] (II) Unloading vesa >[ 35.277] (II) UnloadModule: "fbdev" >[ 35.277] (II) Unloading fbdev >[ 35.277] (II) UnloadSubModule: "fbdevhw" >[ 35.277] (II) Unloading fbdevhw >[ 35.277] (--) Depth 24 pixmap format is 32 bpp >[ 35.277] (II) RADEON(0): [DRI2] Setup complete >[ 35.277] (II) RADEON(0): [DRI2] DRI driver: r600 >[ 35.277] (II) RADEON(0): [DRI2] VDPAU driver: r600 >[ 35.278] (II) RADEON(0): Front buffer size: 4000K >[ 35.278] (II) RADEON(0): VRAM usage limit set to 228499K >[ 35.278] (II) RADEON(0): Initializing backing store >[ 35.278] (==) RADEON(0): Backing store disabled >[ 35.278] (II) RADEON(0): Direct rendering enabled >[ 35.278] (II) RADEON(0): Initializing Acceleration >[ 35.278] (II) RADEON(0): Setting EXA maxPitchBytes >[ 35.278] (II) EXA(0): Driver allocated offscreen pixmaps >[ 35.278] (II) EXA(0): Driver registered support for the following operations: >[ 35.278] (II) Solid >[ 35.278] (II) Copy >[ 35.278] (II) Composite (RENDER acceleration) >[ 35.278] (II) UploadToScreen >[ 35.278] (II) DownloadFromScreen >[ 35.278] (II) RADEON(0): Acceleration enabled >[ 35.278] (II) RADEON(0): Initializing DPMS >[ 35.278] (==) RADEON(0): DPMS enabled >[ 35.278] (II) RADEON(0): Initializing Cursor >[ 35.278] (==) RADEON(0): Silken mouse enabled >[ 35.278] (II) RADEON(0): Initializing Xv >[ 35.278] (II) RADEON(0): Set up textured video >[ 35.278] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video. >[ 35.278] (II) RADEON(0): [XvMC] Extension initialized. >[ 35.279] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message. >[ 35.279] (II) RADEON(0): Initializing kms color map >[ 35.279] (II) RADEON(0): RADEONScreenInit finished >[ 35.279] (--) RandR disabled >[ 35.279] (II) Initializing built-in extension Generic Event Extension >[ 35.279] (II) Initializing built-in extension SHAPE >[ 35.279] (II) Initializing built-in extension MIT-SHM >[ 35.279] (II) Initializing built-in extension XInputExtension >[ 35.279] (II) Initializing built-in extension XTEST >[ 35.279] (II) Initializing built-in extension BIG-REQUESTS >[ 35.279] (II) Initializing built-in extension SYNC >[ 35.279] (II) Initializing built-in extension XKEYBOARD >[ 35.279] (II) Initializing built-in extension XC-MISC >[ 35.279] (II) Initializing built-in extension XINERAMA >[ 35.279] (II) Initializing built-in extension XFIXES >[ 35.279] (II) Initializing built-in extension RENDER >[ 35.279] (II) Initializing built-in extension RANDR >[ 35.279] (II) Initializing built-in extension COMPOSITE >[ 35.279] (II) Initializing built-in extension DAMAGE >[ 35.282] (II) SELinux: Disabled by boolean >[ 35.873] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer >[ 35.873] (II) AIGLX: enabled GLX_INTEL_swap_event >[ 35.873] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control >[ 35.873] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects >[ 35.874] (II) AIGLX: Loaded and initialized r600 >[ 35.874] (II) GLX: Initialized DRI2 GL provider for screen 0 >[ 35.875] (II) RADEON(0): Setting screen physical size to 338 x 211 >[ 35.994] (II) XKB: Reusing cached keymap >[ 35.998] (II) config/udev: Adding input device Power Button (/dev/input/event2) >[ 35.998] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 35.998] (**) Power Button: Applying InputClass "system-setup-keyboard" >[ 35.998] (II) LoadModule: "evdev" >[ 35.999] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so >[ 35.999] (II) Module evdev: vendor="X.Org Foundation" >[ 35.999] compiled for 1.12.0, module version = 2.7.0 >[ 35.999] Module class: X.Org XInput Driver >[ 35.999] ABI class: X.Org XInput driver, version 16.0 >[ 35.999] (II) Using input driver 'evdev' for 'Power Button' >[ 35.999] Option "XkbRules" "evdev" >[ 35.999] Option "XkbModel" "pc105" >[ 35.999] Option "XkbLayout" "ru,us" >[ 35.999] Option "_source" "server/udev" >[ 35.999] Option "name" "Power Button" >[ 35.999] Option "path" "/dev/input/event2" >[ 35.999] Option "device" "/dev/input/event2" >[ 35.999] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2" >[ 35.999] Option "driver" "evdev" >[ 35.999] Option "XkbVariant" "" >[ 35.999] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 35.999] (**) Power Button: always reports core events >[ 35.999] (**) evdev: Power Button: Device: "/dev/input/event2" >[ 35.999] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 35.999] (--) evdev: Power Button: Found keys >[ 35.999] (II) evdev: Power Button: Configuring as keyboard >[ 35.999] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2" >[ 35.999] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6) >[ 35.999] (**) Option "xkb_rules" "evdev" >[ 35.999] (**) Option "xkb_model" "pc105" >[ 35.999] (**) Option "xkb_layout" "ru,us" >[ 35.999] (WW) Option "xkb_variant" requires an string value >[ 35.999] (WW) Option "XkbVariant" requires an string value >[ 35.999] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.032] (II) config/udev: Adding input device Video Bus (/dev/input/event7) >[ 36.032] (**) Video Bus: Applying InputClass "evdev keyboard catchall" >[ 36.032] (**) Video Bus: Applying InputClass "system-setup-keyboard" >[ 36.032] (II) Using input driver 'evdev' for 'Video Bus' >[ 36.032] Option "XkbRules" "evdev" >[ 36.032] Option "XkbModel" "pc105" >[ 36.032] Option "XkbLayout" "ru,us" >[ 36.032] Option "_source" "server/udev" >[ 36.032] Option "name" "Video Bus" >[ 36.032] Option "path" "/dev/input/event7" >[ 36.032] Option "device" "/dev/input/event7" >[ 36.032] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:02/LNXVIDEO:00/input/input7/event7" >[ 36.032] Option "driver" "evdev" >[ 36.032] Option "XkbVariant" "" >[ 36.032] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.032] (**) Video Bus: always reports core events >[ 36.032] (**) evdev: Video Bus: Device: "/dev/input/event7" >[ 36.032] (--) evdev: Video Bus: Vendor 0 Product 0x6 >[ 36.032] (--) evdev: Video Bus: Found keys >[ 36.032] (II) evdev: Video Bus: Configuring as keyboard >[ 36.033] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:02/LNXVIDEO:00/input/input7/event7" >[ 36.033] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7) >[ 36.033] (**) Option "xkb_rules" "evdev" >[ 36.033] (**) Option "xkb_model" "pc105" >[ 36.033] (**) Option "xkb_layout" "ru,us" >[ 36.033] (WW) Option "xkb_variant" requires an string value >[ 36.033] (WW) Option "XkbVariant" requires an string value >[ 36.033] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.033] (II) XKB: Reusing cached keymap >[ 36.033] (II) config/udev: Adding input device Lid Switch (/dev/input/event1) >[ 36.033] (II) No input driver specified, ignoring this device. >[ 36.033] (II) This device may have been added with another device file. >[ 36.034] (II) config/udev: Adding input device Sleep Button (/dev/input/event0) >[ 36.034] (**) Sleep Button: Applying InputClass "evdev keyboard catchall" >[ 36.034] (**) Sleep Button: Applying InputClass "system-setup-keyboard" >[ 36.034] (II) Using input driver 'evdev' for 'Sleep Button' >[ 36.034] Option "XkbRules" "evdev" >[ 36.034] Option "XkbModel" "pc105" >[ 36.034] Option "XkbLayout" "ru,us" >[ 36.034] Option "_source" "server/udev" >[ 36.034] Option "name" "Sleep Button" >[ 36.034] Option "path" "/dev/input/event0" >[ 36.034] Option "device" "/dev/input/event0" >[ 36.034] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0" >[ 36.034] Option "driver" "evdev" >[ 36.034] Option "XkbVariant" "" >[ 36.034] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.034] (**) Sleep Button: always reports core events >[ 36.034] (**) evdev: Sleep Button: Device: "/dev/input/event0" >[ 36.034] (--) evdev: Sleep Button: Vendor 0 Product 0x3 >[ 36.034] (--) evdev: Sleep Button: Found keys >[ 36.034] (II) evdev: Sleep Button: Configuring as keyboard >[ 36.034] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0" >[ 36.034] (II) XINPUT: Adding extended input device "Sleep Button" (type: KEYBOARD, id 8) >[ 36.034] (**) Option "xkb_rules" "evdev" >[ 36.034] (**) Option "xkb_model" "pc105" >[ 36.034] (**) Option "xkb_layout" "ru,us" >[ 36.034] (WW) Option "xkb_variant" requires an string value >[ 36.034] (WW) Option "XkbVariant" requires an string value >[ 36.034] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.034] (II) XKB: Reusing cached keymap >[ 36.035] (II) config/udev: Adding input device HDA ATI HDMI HDMI/DP,pcm=3 (/dev/input/event16) >[ 36.035] (II) No input driver specified, ignoring this device. >[ 36.035] (II) This device may have been added with another device file. >[ 36.035] (II) config/udev: Adding input device HDA Intel Mic (/dev/input/event11) >[ 36.035] (II) No input driver specified, ignoring this device. >[ 36.035] (II) This device may have been added with another device file. >[ 36.035] (II) config/udev: Adding input device HDA Intel Headphone (/dev/input/event12) >[ 36.035] (II) No input driver specified, ignoring this device. >[ 36.035] (II) This device may have been added with another device file. >[ 36.036] (II) config/udev: Adding input device HDA Intel Headphone (/dev/input/event13) >[ 36.036] (II) No input driver specified, ignoring this device. >[ 36.036] (II) This device may have been added with another device file. >[ 36.036] (II) config/udev: Adding input device Apple, Inc Apple Keyboard (/dev/input/event5) >[ 36.036] (**) Apple, Inc Apple Keyboard: Applying InputClass "evdev keyboard catchall" >[ 36.036] (**) Apple, Inc Apple Keyboard: Applying InputClass "system-setup-keyboard" >[ 36.036] (II) Using input driver 'evdev' for 'Apple, Inc Apple Keyboard' >[ 36.036] Option "XkbRules" "evdev" >[ 36.036] Option "XkbModel" "pc105" >[ 36.036] Option "XkbLayout" "ru,us" >[ 36.036] Option "_source" "server/udev" >[ 36.036] Option "name" "Apple, Inc Apple Keyboard" >[ 36.036] Option "path" "/dev/input/event5" >[ 36.036] Option "device" "/dev/input/event5" >[ 36.036] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.2/2-2.2:1.0/input/input5/event5" >[ 36.036] Option "driver" "evdev" >[ 36.036] Option "XkbVariant" "" >[ 36.036] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.036] (**) Apple, Inc Apple Keyboard: always reports core events >[ 36.036] (**) evdev: Apple, Inc Apple Keyboard: Device: "/dev/input/event5" >[ 36.036] (--) evdev: Apple, Inc Apple Keyboard: Vendor 0x5ac Product 0x221 >[ 36.036] (--) evdev: Apple, Inc Apple Keyboard: Found keys >[ 36.036] (II) evdev: Apple, Inc Apple Keyboard: Configuring as keyboard >[ 36.036] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.2/2-2.2:1.0/input/input5/event5" >[ 36.036] (II) XINPUT: Adding extended input device "Apple, Inc Apple Keyboard" (type: KEYBOARD, id 9) >[ 36.036] (**) Option "xkb_rules" "evdev" >[ 36.036] (**) Option "xkb_model" "pc105" >[ 36.036] (**) Option "xkb_layout" "ru,us" >[ 36.036] (WW) Option "xkb_variant" requires an string value >[ 36.036] (WW) Option "XkbVariant" requires an string value >[ 36.036] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.037] (II) XKB: Reusing cached keymap >[ 36.037] (II) config/udev: Adding input device Apple, Inc Apple Keyboard (/dev/input/event6) >[ 36.037] (**) Apple, Inc Apple Keyboard: Applying InputClass "evdev keyboard catchall" >[ 36.037] (**) Apple, Inc Apple Keyboard: Applying InputClass "system-setup-keyboard" >[ 36.037] (II) Using input driver 'evdev' for 'Apple, Inc Apple Keyboard' >[ 36.037] Option "XkbRules" "evdev" >[ 36.037] Option "XkbModel" "pc105" >[ 36.037] Option "XkbLayout" "ru,us" >[ 36.037] Option "_source" "server/udev" >[ 36.037] Option "name" "Apple, Inc Apple Keyboard" >[ 36.037] Option "path" "/dev/input/event6" >[ 36.037] Option "device" "/dev/input/event6" >[ 36.037] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.2/2-2.2:1.1/input/input6/event6" >[ 36.037] Option "driver" "evdev" >[ 36.037] Option "XkbVariant" "" >[ 36.037] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.037] (**) Apple, Inc Apple Keyboard: always reports core events >[ 36.037] (**) evdev: Apple, Inc Apple Keyboard: Device: "/dev/input/event6" >[ 36.038] (--) evdev: Apple, Inc Apple Keyboard: Vendor 0x5ac Product 0x221 >[ 36.038] (--) evdev: Apple, Inc Apple Keyboard: Found keys >[ 36.038] (II) evdev: Apple, Inc Apple Keyboard: Configuring as keyboard >[ 36.038] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.2/2-2.2:1.1/input/input6/event6" >[ 36.038] (II) XINPUT: Adding extended input device "Apple, Inc Apple Keyboard" (type: KEYBOARD, id 10) >[ 36.038] (**) Option "xkb_rules" "evdev" >[ 36.038] (**) Option "xkb_model" "pc105" >[ 36.038] (**) Option "xkb_layout" "ru,us" >[ 36.038] (WW) Option "xkb_variant" requires an string value >[ 36.038] (WW) Option "XkbVariant" requires an string value >[ 36.038] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.038] (II) XKB: Reusing cached keymap >[ 36.038] (II) config/udev: Adding input device Logitech Unifying Device. Wireless PID:1017 (/dev/input/event8) >[ 36.038] (**) Logitech Unifying Device. Wireless PID:1017: Applying InputClass "evdev pointer catchall" >[ 36.038] (II) Using input driver 'evdev' for 'Logitech Unifying Device. Wireless PID:1017' >[ 36.038] Option "XkbRules" "evdev" >[ 36.038] Option "XkbModel" "evdev" >[ 36.038] Option "XkbLayout" "us" >[ 36.038] Option "_source" "server/udev" >[ 36.039] Option "name" "Logitech Unifying Device. Wireless PID:1017" >[ 36.039] Option "path" "/dev/input/event8" >[ 36.039] Option "device" "/dev/input/event8" >[ 36.039] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.3/2-2.3:1.2/0003:046D:C52B.0005/input/input8/event8" >[ 36.039] Option "driver" "evdev" >[ 36.039] (**) Logitech Unifying Device. Wireless PID:1017: always reports core events >[ 36.039] (**) evdev: Logitech Unifying Device. Wireless PID:1017: Device: "/dev/input/event8" >[ 36.039] (--) evdev: Logitech Unifying Device. Wireless PID:1017: Vendor 0x46d Product 0xc52b >[ 36.039] (--) evdev: Logitech Unifying Device. Wireless PID:1017: Found 20 mouse buttons >[ 36.039] (--) evdev: Logitech Unifying Device. Wireless PID:1017: Found scroll wheel(s) >[ 36.039] (--) evdev: Logitech Unifying Device. Wireless PID:1017: Found relative axes >[ 36.039] (--) evdev: Logitech Unifying Device. Wireless PID:1017: Found x and y relative axes >[ 36.039] (II) evdev: Logitech Unifying Device. Wireless PID:1017: Configuring as mouse >[ 36.039] (II) evdev: Logitech Unifying Device. Wireless PID:1017: Adding scrollwheel support >[ 36.039] (**) evdev: Logitech Unifying Device. Wireless PID:1017: YAxisMapping: buttons 4 and 5 >[ 36.039] (**) evdev: Logitech Unifying Device. Wireless PID:1017: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200 >[ 36.039] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-2/2-2.3/2-2.3:1.2/0003:046D:C52B.0005/input/input8/event8" >[ 36.039] (II) XINPUT: Adding extended input device "Logitech Unifying Device. Wireless PID:1017" (type: MOUSE, id 11) >[ 36.039] (II) evdev: Logitech Unifying Device. Wireless PID:1017: initialized for relative axes. >[ 36.039] (**) Logitech Unifying Device. Wireless PID:1017: (accel) keeping acceleration scheme 1 >[ 36.039] (**) Logitech Unifying Device. Wireless PID:1017: (accel) acceleration profile 0 >[ 36.039] (**) Logitech Unifying Device. Wireless PID:1017: (accel) acceleration factor: 2.000 >[ 36.039] (**) Logitech Unifying Device. Wireless PID:1017: (accel) acceleration threshold: 4 >[ 36.040] (II) config/udev: Adding input device Logitech Unifying Device. Wireless PID:1017 (/dev/input/mouse1) >[ 36.040] (II) No input driver specified, ignoring this device. >[ 36.040] (II) This device may have been added with another device file. >[ 36.040] (II) config/udev: Adding input device USB2.0 1.3M UVC WebCam (/dev/input/event15) >[ 36.040] (**) USB2.0 1.3M UVC WebCam: Applying InputClass "evdev keyboard catchall" >[ 36.040] (**) USB2.0 1.3M UVC WebCam: Applying InputClass "system-setup-keyboard" >[ 36.040] (II) Using input driver 'evdev' for 'USB2.0 1.3M UVC WebCam' >[ 36.040] Option "XkbRules" "evdev" >[ 36.040] Option "XkbModel" "pc105" >[ 36.040] Option "XkbLayout" "ru,us" >[ 36.040] Option "_source" "server/udev" >[ 36.040] Option "name" "USB2.0 1.3M UVC WebCam" >[ 36.040] Option "path" "/dev/input/event15" >[ 36.040] Option "device" "/dev/input/event15" >[ 36.040] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-6/2-6:1.0/input/input15/event15" >[ 36.040] Option "driver" "evdev" >[ 36.040] Option "XkbVariant" "" >[ 36.040] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.040] (**) USB2.0 1.3M UVC WebCam: always reports core events >[ 36.040] (**) evdev: USB2.0 1.3M UVC WebCam: Device: "/dev/input/event15" >[ 36.040] (--) evdev: USB2.0 1.3M UVC WebCam: Vendor 0x4f2 Product 0xb033 >[ 36.040] (--) evdev: USB2.0 1.3M UVC WebCam: Found keys >[ 36.040] (II) evdev: USB2.0 1.3M UVC WebCam: Configuring as keyboard >[ 36.040] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb2/2-6/2-6:1.0/input/input15/event15" >[ 36.040] (II) XINPUT: Adding extended input device "USB2.0 1.3M UVC WebCam" (type: KEYBOARD, id 12) >[ 36.040] (**) Option "xkb_rules" "evdev" >[ 36.040] (**) Option "xkb_model" "pc105" >[ 36.040] (**) Option "xkb_layout" "ru,us" >[ 36.040] (WW) Option "xkb_variant" requires an string value >[ 36.040] (WW) Option "XkbVariant" requires an string value >[ 36.040] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.040] (II) XKB: Reusing cached keymap >[ 36.041] (II) config/udev: Adding input device Asus Laptop extra buttons (/dev/input/event9) >[ 36.041] (**) Asus Laptop extra buttons: Applying InputClass "evdev keyboard catchall" >[ 36.041] (**) Asus Laptop extra buttons: Applying InputClass "system-setup-keyboard" >[ 36.041] (II) Using input driver 'evdev' for 'Asus Laptop extra buttons' >[ 36.041] Option "XkbRules" "evdev" >[ 36.041] Option "XkbModel" "pc105" >[ 36.041] Option "XkbLayout" "ru,us" >[ 36.041] Option "_source" "server/udev" >[ 36.041] Option "name" "Asus Laptop extra buttons" >[ 36.041] Option "path" "/dev/input/event9" >[ 36.041] Option "device" "/dev/input/event9" >[ 36.041] Option "config_info" "udev:/sys/devices/platform/asus_laptop/input/input9/event9" >[ 36.041] Option "driver" "evdev" >[ 36.041] Option "XkbVariant" "" >[ 36.041] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.041] (**) Asus Laptop extra buttons: always reports core events >[ 36.041] (**) evdev: Asus Laptop extra buttons: Device: "/dev/input/event9" >[ 36.041] (--) evdev: Asus Laptop extra buttons: Vendor 0 Product 0 >[ 36.041] (--) evdev: Asus Laptop extra buttons: Found keys >[ 36.041] (II) evdev: Asus Laptop extra buttons: Configuring as keyboard >[ 36.041] (**) Option "config_info" "udev:/sys/devices/platform/asus_laptop/input/input9/event9" >[ 36.041] (II) XINPUT: Adding extended input device "Asus Laptop extra buttons" (type: KEYBOARD, id 13) >[ 36.041] (**) Option "xkb_rules" "evdev" >[ 36.041] (**) Option "xkb_model" "pc105" >[ 36.041] (**) Option "xkb_layout" "ru,us" >[ 36.041] (WW) Option "xkb_variant" requires an string value >[ 36.041] (WW) Option "XkbVariant" requires an string value >[ 36.041] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.041] (II) XKB: Reusing cached keymap >[ 36.042] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event3) >[ 36.042] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall" >[ 36.042] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard" >[ 36.042] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard' >[ 36.042] Option "XkbRules" "evdev" >[ 36.042] Option "XkbModel" "pc105" >[ 36.042] Option "XkbLayout" "ru,us" >[ 36.042] Option "_source" "server/udev" >[ 36.042] Option "name" "AT Translated Set 2 keyboard" >[ 36.042] Option "path" "/dev/input/event3" >[ 36.042] Option "device" "/dev/input/event3" >[ 36.042] Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3" >[ 36.042] Option "driver" "evdev" >[ 36.042] Option "XkbVariant" "" >[ 36.042] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.042] (**) AT Translated Set 2 keyboard: always reports core events >[ 36.042] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event3" >[ 36.042] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1 >[ 36.042] (--) evdev: AT Translated Set 2 keyboard: Found keys >[ 36.042] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard >[ 36.042] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3" >[ 36.042] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 14) >[ 36.042] (**) Option "xkb_rules" "evdev" >[ 36.042] (**) Option "xkb_model" "pc105" >[ 36.042] (**) Option "xkb_layout" "ru,us" >[ 36.042] (WW) Option "xkb_variant" requires an string value >[ 36.042] (WW) Option "XkbVariant" requires an string value >[ 36.042] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.042] (II) XKB: Reusing cached keymap >[ 36.044] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event4) >[ 36.044] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall" >[ 36.044] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall" >[ 36.044] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons" >[ 36.044] (II) LoadModule: "synaptics" >[ 36.044] (II) Loading /usr/lib64/xorg/modules/input/synaptics_drv.so >[ 36.044] (II) Module synaptics: vendor="X.Org Foundation" >[ 36.044] compiled for 1.12.0, module version = 1.6.2 >[ 36.044] Module class: X.Org XInput Driver >[ 36.044] ABI class: X.Org XInput driver, version 16.0 >[ 36.044] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad' >[ 36.044] Option "_source" "server/udev" >[ 36.044] Option "name" "SynPS/2 Synaptics TouchPad" >[ 36.044] Option "path" "/dev/input/event4" >[ 36.044] Option "device" "/dev/input/event4" >[ 36.044] Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4" >[ 36.044] Option "driver" "synaptics" >[ 36.044] Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0" >[ 36.045] (**) SynPS/2 Synaptics TouchPad: always reports core events >[ 36.045] (**) Option "Device" "/dev/input/event4" >[ 36.066] (**) Option "Device" "/dev/input/event4" >[ 36.066] port opened successfully >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5472 >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4448 >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255 >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15 >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7 >[ 36.066] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found >[ 36.066] (**) SynPS/2 Synaptics TouchPad: always reports core events >[ 36.077] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4" >[ 36.077] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 15) >[ 36.077] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5 >[ 36.077] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75 >[ 36.077] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.040 >[ 36.077] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1 >[ 36.077] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1 >[ 36.077] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000 >[ 36.077] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4 >[ 36.077] (**) Option "Device" "/dev/input/event4" >[ 36.077] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found >[ 36.078] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0) >[ 36.078] (II) No input driver specified, ignoring this device. >[ 36.078] (II) This device may have been added with another device file. >[ 36.078] (II) config/udev: Adding input device MCE IR Keyboard/Mouse (ite-cir) (/dev/input/event14) >[ 36.078] (**) MCE IR Keyboard/Mouse (ite-cir): Applying InputClass "evdev pointer catchall" >[ 36.078] (**) MCE IR Keyboard/Mouse (ite-cir): Applying InputClass "evdev keyboard catchall" >[ 36.078] (**) MCE IR Keyboard/Mouse (ite-cir): Applying InputClass "system-setup-keyboard" >[ 36.078] (II) Using input driver 'evdev' for 'MCE IR Keyboard/Mouse (ite-cir)' >[ 36.078] Option "XkbRules" "evdev" >[ 36.078] Option "XkbModel" "pc105" >[ 36.078] Option "XkbLayout" "ru,us" >[ 36.078] Option "_source" "server/udev" >[ 36.078] Option "name" "MCE IR Keyboard/Mouse (ite-cir)" >[ 36.078] Option "path" "/dev/input/event14" >[ 36.078] Option "device" "/dev/input/event14" >[ 36.078] Option "config_info" "udev:/sys/devices/virtual/input/input14/event14" >[ 36.078] Option "driver" "evdev" >[ 36.078] Option "XkbVariant" "" >[ 36.078] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.079] (**) MCE IR Keyboard/Mouse (ite-cir): always reports core events >[ 36.079] (**) evdev: MCE IR Keyboard/Mouse (ite-cir): Device: "/dev/input/event14" >[ 36.079] (--) evdev: MCE IR Keyboard/Mouse (ite-cir): Vendor 0 Product 0 >[ 36.079] (--) evdev: MCE IR Keyboard/Mouse (ite-cir): Found 3 mouse buttons >[ 36.079] (--) evdev: MCE IR Keyboard/Mouse (ite-cir): Found relative axes >[ 36.079] (--) evdev: MCE IR Keyboard/Mouse (ite-cir): Found x and y relative axes >[ 36.079] (--) evdev: MCE IR Keyboard/Mouse (ite-cir): Found keys >[ 36.079] (II) evdev: MCE IR Keyboard/Mouse (ite-cir): Configuring as mouse >[ 36.079] (II) evdev: MCE IR Keyboard/Mouse (ite-cir): Configuring as keyboard >[ 36.079] (**) evdev: MCE IR Keyboard/Mouse (ite-cir): YAxisMapping: buttons 4 and 5 >[ 36.079] (**) evdev: MCE IR Keyboard/Mouse (ite-cir): EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200 >[ 36.079] (**) Option "config_info" "udev:/sys/devices/virtual/input/input14/event14" >[ 36.079] (II) XINPUT: Adding extended input device "MCE IR Keyboard/Mouse (ite-cir)" (type: KEYBOARD, id 16) >[ 36.079] (**) Option "xkb_rules" "evdev" >[ 36.079] (**) Option "xkb_model" "pc105" >[ 36.079] (**) Option "xkb_layout" "ru,us" >[ 36.079] (WW) Option "xkb_variant" requires an string value >[ 36.079] (WW) Option "XkbVariant" requires an string value >[ 36.079] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.079] (II) XKB: Reusing cached keymap >[ 36.079] (II) evdev: MCE IR Keyboard/Mouse (ite-cir): initialized for relative axes. >[ 36.079] (**) MCE IR Keyboard/Mouse (ite-cir): (accel) keeping acceleration scheme 1 >[ 36.079] (**) MCE IR Keyboard/Mouse (ite-cir): (accel) acceleration profile 0 >[ 36.079] (**) MCE IR Keyboard/Mouse (ite-cir): (accel) acceleration factor: 2.000 >[ 36.079] (**) MCE IR Keyboard/Mouse (ite-cir): (accel) acceleration threshold: 4 >[ 36.080] (II) config/udev: Adding input device MCE IR Keyboard/Mouse (ite-cir) (/dev/input/mouse2) >[ 36.080] (**) MCE IR Keyboard/Mouse (ite-cir): Applying InputClass "system-setup-keyboard" >[ 36.080] (II) No input driver specified, ignoring this device. >[ 36.080] (II) This device may have been added with another device file. >[ 36.080] (II) config/udev: Adding input device ITE8708 CIR transceiver (/dev/input/event10) >[ 36.080] (**) ITE8708 CIR transceiver: Applying InputClass "evdev keyboard catchall" >[ 36.080] (**) ITE8708 CIR transceiver: Applying InputClass "system-setup-keyboard" >[ 36.080] (II) Using input driver 'evdev' for 'ITE8708 CIR transceiver' >[ 36.080] Option "XkbRules" "evdev" >[ 36.080] Option "XkbModel" "pc105" >[ 36.080] Option "XkbLayout" "ru,us" >[ 36.080] Option "_source" "server/udev" >[ 36.080] Option "name" "ITE8708 CIR transceiver" >[ 36.080] Option "path" "/dev/input/event10" >[ 36.080] Option "device" "/dev/input/event10" >[ 36.080] Option "config_info" "udev:/sys/devices/virtual/rc/rc0/input10/event10" >[ 36.080] Option "driver" "evdev" >[ 36.080] Option "XkbVariant" "" >[ 36.080] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.080] (**) ITE8708 CIR transceiver: always reports core events >[ 36.080] (**) evdev: ITE8708 CIR transceiver: Device: "/dev/input/event10" >[ 36.080] (--) evdev: ITE8708 CIR transceiver: Vendor 0x1283 Product 0 >[ 36.080] (--) evdev: ITE8708 CIR transceiver: Found keys >[ 36.080] (II) evdev: ITE8708 CIR transceiver: Configuring as keyboard >[ 36.080] (**) Option "config_info" "udev:/sys/devices/virtual/rc/rc0/input10/event10" >[ 36.080] (II) XINPUT: Adding extended input device "ITE8708 CIR transceiver" (type: KEYBOARD, id 17) >[ 36.080] (**) Option "xkb_rules" "evdev" >[ 36.080] (**) Option "xkb_model" "pc105" >[ 36.080] (**) Option "xkb_layout" "ru,us" >[ 36.081] (WW) Option "xkb_variant" requires an string value >[ 36.081] (WW) Option "XkbVariant" requires an string value >[ 36.081] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 36.081] (II) XKB: Reusing cached keymap >[ 36.088] (II) RADEON(0): RADEONSaveScreen(2) >[ 36.106] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 36.106] (II) RADEON(0): Printing DDC gathered Modelines: >[ 36.106] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 37.308] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 37.308] (II) RADEON(0): Printing DDC gathered Modelines: >[ 37.308] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 39.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f16e0] >[ 39.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f16e0] width 1280 pitch 5120 (/4 1280) >[ 39.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f16e0] >[ 39.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f16e0] width 1280 pitch 5120 (/4 1280) >[ 39.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f16e0] >[ 39.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f16e0] width 1280 pitch 5120 (/4 1280) >[ 39.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f16e0] >[ 39.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f16e0] width 1280 pitch 5120 (/4 1280) >[ 39.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f16e0] >[ 39.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f16e0] width 1280 pitch 5120 (/4 1280) >[ 39.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1740] >[ 39.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1740] width 1280 pitch 5120 (/4 1280) >[ 39.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 39.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 39.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 39.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 39.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 40.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 40.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 40.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 40.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 42.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 42.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 42.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f34f0] >[ 42.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f34f0] width 1280 pitch 5120 (/4 1280) >[ 42.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3550] >[ 42.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3550] width 1280 pitch 5120 (/4 1280) >[ 42.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 42.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 42.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 42.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 42.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 43.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f3600] >[ 43.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f3600] width 1280 pitch 5120 (/4 1280) >[ 43.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f1890] >[ 43.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f1890] width 1280 pitch 5120 (/4 1280) >[ 44.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 44.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 44.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 44.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 45.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 45.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 45.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 45.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 47.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 47.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 47.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 47.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 47.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 47.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 48.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 48.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 48.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 48.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 49.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 49.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 49.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 49.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 49.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 49.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 50.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 50.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 50.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 50.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 50.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 50.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 50.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 50.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 51.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2760] >[ 51.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2760] width 1280 pitch 5120 (/4 1280) >[ 52.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10c2700] >[ 52.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10c2700] width 1280 pitch 5120 (/4 1280) >[ 52.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xfd0a70] >[ 54.429] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 54.429] (II) RADEON(0): Printing DDC gathered Modelines: >[ 54.429] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 55.642] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 55.642] (II) RADEON(0): Printing DDC gathered Modelines: >[ 55.642] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 56.318] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 56.318] (II) RADEON(0): Printing DDC gathered Modelines: >[ 56.318] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 65.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114ab20] >[ 65.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114ab20] width 1280 pitch 5120 (/4 1280) >[ 65.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147f90] >[ 65.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147f90] width 1280 pitch 5120 (/4 1280) >[ 65.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147f90] >[ 65.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147f90] width 1280 pitch 5120 (/4 1280) >[ 65.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147f90] >[ 65.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147f90] width 1280 pitch 5120 (/4 1280) >[ 65.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147f90] >[ 65.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147f90] width 1280 pitch 5120 (/4 1280) >[ 65.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147f90] >[ 65.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147f90] width 1280 pitch 5120 (/4 1280) >[ 65.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 65.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 65.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 65.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 66.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 66.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 66.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 66.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 69.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114ef20] >[ 69.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114ef20] width 1280 pitch 5120 (/4 1280) >[ 69.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 69.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 69.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 69.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 70.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114ee00] >[ 70.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114ee00] width 1280 pitch 5120 (/4 1280) >[ 70.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114eda0] >[ 70.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114eda0] width 1280 pitch 5120 (/4 1280) >[ 70.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 70.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 70.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 70.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 70.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 70.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 70.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 70.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 70.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 70.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 70.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 70.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 70.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 70.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 70.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 70.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 71.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 71.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 71.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b460] >[ 71.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b460] width 1280 pitch 5120 (/4 1280) >[ 72.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114a6b0] >[ 72.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114a6b0] width 1280 pitch 5120 (/4 1280) >[ 78.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187460] >[ 78.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187460] width 1280 pitch 5120 (/4 1280) >[ 78.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187330] >[ 78.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187330] width 1280 pitch 5120 (/4 1280) >[ 83.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b7700] >[ 83.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b7700] width 1280 pitch 5120 (/4 1280) >[ 83.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c20f0] >[ 83.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c20f0] width 1280 pitch 5120 (/4 1280) >[ 90.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c1590] >[ 90.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c1590] width 1280 pitch 5120 (/4 1280) >[ 91.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e94f0] >[ 91.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e94f0] width 1280 pitch 5120 (/4 1280) >[ 91.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d2390] >[ 91.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d2390] width 1280 pitch 5120 (/4 1280) >[ 91.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115e7b0] >[ 91.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115e7b0] width 1280 pitch 5120 (/4 1280) >[ 91.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bce80] >[ 91.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bce80] width 1280 pitch 5120 (/4 1280) >[ 91.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b8da0] >[ 91.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b8da0] width 1280 pitch 5120 (/4 1280) >[ 92.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e3b40] >[ 92.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e3b40] width 1280 pitch 5120 (/4 1280) >[ 92.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cffd0] >[ 92.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cffd0] width 1280 pitch 5120 (/4 1280) >[ 92.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b6c10] >[ 92.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b6c10] width 1280 pitch 5120 (/4 1280) >[ 92.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b6c10] >[ 92.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b6c10] width 1280 pitch 5120 (/4 1280) >[ 92.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b6c10] >[ 92.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b6c10] width 1280 pitch 5120 (/4 1280) >[ 92.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b6c10] >[ 92.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b6c10] width 1280 pitch 5120 (/4 1280) >[ 92.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cffd0] >[ 92.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cffd0] width 1280 pitch 5120 (/4 1280) >[ 92.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cbaa0] >[ 92.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cbaa0] width 1280 pitch 5120 (/4 1280) >[ 93.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c1590] >[ 93.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c1590] width 1280 pitch 5120 (/4 1280) >[ 93.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b6c10] >[ 93.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b6c10] width 1280 pitch 5120 (/4 1280) >[ 93.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cbaa0] >[ 93.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cbaa0] width 1280 pitch 5120 (/4 1280) >[ 93.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d2260] >[ 93.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d2260] width 1280 pitch 5120 (/4 1280) >[ 93.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cbaa0] >[ 93.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cbaa0] width 1280 pitch 5120 (/4 1280) >[ 93.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d2260] >[ 93.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d2260] width 1280 pitch 5120 (/4 1280) >[ 93.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e3b40] >[ 93.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e3b40] width 1280 pitch 5120 (/4 1280) >[ 93.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e4240] >[ 93.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e4240] width 1280 pitch 5120 (/4 1280) >[ 93.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e3b40] >[ 93.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e3b40] width 1280 pitch 5120 (/4 1280) >[ 93.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e4240] >[ 93.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e4240] width 1280 pitch 5120 (/4 1280) >[ 93.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e4240] >[ 93.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e4240] width 1280 pitch 5120 (/4 1280) >[ 99.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134b0c0] >[ 99.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134b0c0] width 1280 pitch 5120 (/4 1280) >[ 99.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134b0c0] >[ 99.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134b0c0] width 1280 pitch 5120 (/4 1280) >[ 100.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1339fa0] >[ 100.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1339fa0] width 1280 pitch 5120 (/4 1280) >[ 101.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13295a0] >[ 101.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13295a0] width 1280 pitch 5120 (/4 1280) >[ 101.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134b0c0] >[ 101.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134b0c0] width 1280 pitch 5120 (/4 1280) >[ 101.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134b0c0] >[ 101.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134b0c0] width 1280 pitch 5120 (/4 1280) >[ 103.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13295a0] >[ 103.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13295a0] width 1280 pitch 5120 (/4 1280) >[ 104.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132b170] >[ 104.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132b170] width 1280 pitch 5120 (/4 1280) >[ 106.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132cb00] >[ 106.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132cb00] width 1280 pitch 5120 (/4 1280) >[ 106.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132b110] >[ 106.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132b110] width 1280 pitch 5120 (/4 1280) >[ 107.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1422c70] >[ 107.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1422c70] width 1280 pitch 5120 (/4 1280) >[ 109.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12792f0] >[ 109.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12792f0] width 1280 pitch 5120 (/4 1280) >[ 109.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1287d60] >[ 109.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1287d60] width 1280 pitch 5120 (/4 1280) >[ 109.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1279530] >[ 109.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1279530] width 1280 pitch 5120 (/4 1280) >[ 111.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142ce00] >[ 111.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142ce00] width 1280 pitch 5120 (/4 1280) >[ 112.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142e370] >[ 112.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142e370] width 1280 pitch 5120 (/4 1280) >[ 112.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142c9f0] >[ 112.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142c9f0] width 1280 pitch 5120 (/4 1280) >[ 112.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142da40] >[ 112.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142da40] width 1280 pitch 5120 (/4 1280) >[ 112.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d9f0] >[ 112.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d9f0] width 1280 pitch 5120 (/4 1280) >[ 112.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142c9f0] >[ 112.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142c9f0] width 1280 pitch 5120 (/4 1280) >[ 112.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d030] >[ 112.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d030] width 1280 pitch 5120 (/4 1280) >[ 113.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d9f0] >[ 113.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d9f0] width 1280 pitch 5120 (/4 1280) >[ 113.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142da40] >[ 113.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142da40] width 1280 pitch 5120 (/4 1280) >[ 113.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d800] >[ 113.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d800] width 1280 pitch 5120 (/4 1280) >[ 113.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d1d0] >[ 113.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d1d0] width 1280 pitch 5120 (/4 1280) >[ 113.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d1d0] >[ 113.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d1d0] width 1280 pitch 5120 (/4 1280) >[ 113.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14301f0] >[ 113.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14301f0] width 1280 pitch 5120 (/4 1280) >[ 113.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430640] >[ 113.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430640] width 1280 pitch 5120 (/4 1280) >[ 113.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d5b0] >[ 113.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d5b0] width 1280 pitch 5120 (/4 1280) >[ 114.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 114.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 114.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430690] >[ 114.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430690] width 1280 pitch 5120 (/4 1280) >[ 114.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 114.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 114.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430690] >[ 114.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430690] width 1280 pitch 5120 (/4 1280) >[ 114.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 114.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 114.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430690] >[ 114.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430690] width 1280 pitch 5120 (/4 1280) >[ 114.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 114.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 114.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d1d0] >[ 114.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d1d0] width 1280 pitch 5120 (/4 1280) >[ 114.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142d1d0] >[ 114.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142d1d0] width 1280 pitch 5120 (/4 1280) >[ 116.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 116.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 116.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 116.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 116.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 116.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 116.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 116.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 116.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 116.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 116.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1430590] >[ 116.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1430590] width 1280 pitch 5120 (/4 1280) >[ 118.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231a30] >[ 118.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231a30] width 1280 pitch 5120 (/4 1280) >[ 118.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5070] >[ 118.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5070] width 1280 pitch 5120 (/4 1280) >[ 118.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 118.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 118.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c4a60] >[ 118.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c4a60] width 1280 pitch 5120 (/4 1280) >[ 118.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c4a60] >[ 118.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c4a60] width 1280 pitch 5120 (/4 1280) >[ 118.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c4a60] >[ 118.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c4a60] width 1280 pitch 5120 (/4 1280) >[ 118.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 118.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 118.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231a30] >[ 118.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231a30] width 1280 pitch 5120 (/4 1280) >[ 118.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 118.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 119.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c4060] >[ 119.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c4060] width 1280 pitch 5120 (/4 1280) >[ 119.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 119.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 119.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 119.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 119.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 119.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 119.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 119.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 119.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 119.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 119.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 119.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 119.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 119.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 119.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 119.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 119.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 119.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 119.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 119.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 120.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114afb0] >[ 120.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114afb0] width 1280 pitch 5120 (/4 1280) >[ 120.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1493e20] >[ 120.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1493e20] width 1280 pitch 5120 (/4 1280) >[ 120.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d0dc0] >[ 120.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d0dc0] width 1280 pitch 5120 (/4 1280) >[ 120.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1258ec0] >[ 120.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1258ec0] width 1280 pitch 5120 (/4 1280) >[ 122.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14543f0] >[ 122.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14543f0] width 1280 pitch 5120 (/4 1280) >[ 124.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f1640] >[ 124.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f1640] width 1280 pitch 5120 (/4 1280) >[ 124.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 124.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 124.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f1640] >[ 124.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f1640] width 1280 pitch 5120 (/4 1280) >[ 124.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 124.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 124.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f1640] >[ 124.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f1640] width 1280 pitch 5120 (/4 1280) >[ 124.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 124.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 124.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f1640] >[ 124.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f1640] width 1280 pitch 5120 (/4 1280) >[ 125.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9740] >[ 125.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9740] width 1280 pitch 5120 (/4 1280) >[ 125.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9740] >[ 125.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9740] width 1280 pitch 5120 (/4 1280) >[ 125.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13001a0] >[ 125.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13001a0] width 1280 pitch 5120 (/4 1280) >[ 125.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1300050] >[ 125.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1300050] width 1280 pitch 5120 (/4 1280) >[ 125.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f61f0] >[ 125.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f61f0] width 1280 pitch 5120 (/4 1280) >[ 125.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1300050] >[ 125.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1300050] width 1280 pitch 5120 (/4 1280) >[ 126.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f61f0] >[ 126.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f61f0] width 1280 pitch 5120 (/4 1280) >[ 126.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1300050] >[ 126.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1300050] width 1280 pitch 5120 (/4 1280) >[ 126.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fee50] >[ 126.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fee50] width 1280 pitch 5120 (/4 1280) >[ 126.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 126.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 126.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13000b0] >[ 126.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13000b0] width 1280 pitch 5120 (/4 1280) >[ 126.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1302210] >[ 126.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1302210] width 1280 pitch 5120 (/4 1280) >[ 126.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 126.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 126.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 126.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 126.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 126.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 126.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 126.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 126.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 126.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 126.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 126.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 126.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 126.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 126.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 126.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 127.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 127.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 127.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 127.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 127.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 127.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 127.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 127.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 127.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301da0] >[ 127.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301da0] width 1280 pitch 5120 (/4 1280) >[ 127.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fed40] >[ 127.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fed40] width 1280 pitch 5120 (/4 1280) >[ 128.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1971f00] >[ 128.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1971f00] width 1280 pitch 5120 (/4 1280) >[ 128.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491eb0] >[ 128.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491eb0] width 1280 pitch 5120 (/4 1280) >[ 128.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14922d0] >[ 128.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14922d0] width 1280 pitch 5120 (/4 1280) >[ 129.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d99c0] >[ 129.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d99c0] width 1280 pitch 5120 (/4 1280) >[ 129.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e0e0] >[ 129.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e0e0] width 1280 pitch 5120 (/4 1280) >[ 130.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 130.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 130.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152ef00] >[ 130.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152ef00] width 1280 pitch 5120 (/4 1280) >[ 130.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b97b0] >[ 130.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b97b0] width 1280 pitch 5120 (/4 1280) >[ 130.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a649e0] >[ 130.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a649e0] width 1280 pitch 5120 (/4 1280) >[ 130.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bd090] >[ 130.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bd090] width 1280 pitch 5120 (/4 1280) >[ 130.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b97b0] >[ 130.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b97b0] width 1280 pitch 5120 (/4 1280) >[ 130.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bd090] >[ 130.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bd090] width 1280 pitch 5120 (/4 1280) >[ 130.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b97b0] >[ 130.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b97b0] width 1280 pitch 5120 (/4 1280) >[ 130.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bd090] >[ 130.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bd090] width 1280 pitch 5120 (/4 1280) >[ 134.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b8b0] >[ 134.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b8b0] width 1280 pitch 5120 (/4 1280) >[ 134.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e3e0] >[ 134.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e3e0] width 1280 pitch 5120 (/4 1280) >[ 134.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9df0] >[ 134.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9df0] width 1280 pitch 5120 (/4 1280) >[ 134.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e3e0] >[ 134.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e3e0] width 1280 pitch 5120 (/4 1280) >[ 134.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9df0] >[ 134.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9df0] width 1280 pitch 5120 (/4 1280) >[ 134.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e3e0] >[ 134.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e3e0] width 1280 pitch 5120 (/4 1280) >[ 134.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9d90] >[ 134.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9d90] width 1280 pitch 5120 (/4 1280) >[ 134.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e3e0] >[ 134.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e3e0] width 1280 pitch 5120 (/4 1280) >[ 134.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9d90] >[ 134.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9d90] width 1280 pitch 5120 (/4 1280) >[ 134.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e3e0] >[ 135.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e3e0] width 1280 pitch 5120 (/4 1280) >[ 135.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9e80] >[ 135.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9e80] width 1280 pitch 5120 (/4 1280) >[ 136.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 136.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 136.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b770] >[ 136.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b770] width 1280 pitch 5120 (/4 1280) >[ 136.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 136.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 136.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b770] >[ 136.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b770] width 1280 pitch 5120 (/4 1280) >[ 136.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 136.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 136.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9cb0] >[ 136.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9cb0] width 1280 pitch 5120 (/4 1280) >[ 136.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 136.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 136.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9cb0] >[ 136.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9cb0] width 1280 pitch 5120 (/4 1280) >[ 136.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b7a0] >[ 136.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b7a0] width 1280 pitch 5120 (/4 1280) >[ 136.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9cb0] >[ 136.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9cb0] width 1280 pitch 5120 (/4 1280) >[ 136.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b7a0] >[ 136.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b7a0] width 1280 pitch 5120 (/4 1280) >[ 136.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c9cb0] >[ 136.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c9cb0] width 1280 pitch 5120 (/4 1280) >[ 136.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b7a0] >[ 136.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b7a0] width 1280 pitch 5120 (/4 1280) >[ 136.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf460] >[ 136.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf460] width 1280 pitch 5120 (/4 1280) >[ 136.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ddb90] >[ 136.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ddb90] width 1280 pitch 5120 (/4 1280) >[ 136.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf460] >[ 136.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf460] width 1280 pitch 5120 (/4 1280) >[ 137.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 137.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cf5e0] >[ 138.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cf5e0] width 1280 pitch 5120 (/4 1280) >[ 138.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d7e30] >[ 138.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d7e30] width 1280 pitch 5120 (/4 1280) >[ 138.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 138.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 138.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306d30] >[ 138.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306d30] width 1280 pitch 5120 (/4 1280) >[ 139.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5230] >[ 139.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5230] width 1280 pitch 5120 (/4 1280) >[ 139.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cc250] >[ 139.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cc250] width 1280 pitch 5120 (/4 1280) >[ 139.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 139.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 141.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab85d0] >[ 141.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab85d0] width 1280 pitch 5120 (/4 1280) >[ 141.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aae850] >[ 141.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aae850] width 1280 pitch 5120 (/4 1280) >[ 142.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 142.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aadc80] >[ 142.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aadc80] width 1280 pitch 5120 (/4 1280) >[ 142.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7a20] >[ 142.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7a20] width 1280 pitch 5120 (/4 1280) >[ 143.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d540] >[ 143.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d540] width 1280 pitch 5120 (/4 1280) >[ 143.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d310] >[ 143.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d310] width 1280 pitch 5120 (/4 1280) >[ 143.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d2b0] >[ 143.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d2b0] width 1280 pitch 5120 (/4 1280) >[ 143.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d310] >[ 143.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d310] width 1280 pitch 5120 (/4 1280) >[ 143.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d2b0] >[ 143.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d2b0] width 1280 pitch 5120 (/4 1280) >[ 143.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d310] >[ 143.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d310] width 1280 pitch 5120 (/4 1280) >[ 143.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d2b0] >[ 143.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d2b0] width 1280 pitch 5120 (/4 1280) >[ 143.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d310] >[ 143.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d310] width 1280 pitch 5120 (/4 1280) >[ 143.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d2b0] >[ 143.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d2b0] width 1280 pitch 5120 (/4 1280) >[ 143.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d1d0] >[ 143.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d1d0] width 1280 pitch 5120 (/4 1280) >[ 143.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3d2b0] >[ 143.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3d2b0] width 1280 pitch 5120 (/4 1280) >[ 143.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab6460] >[ 143.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab6460] width 1280 pitch 5120 (/4 1280) >[ 143.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3ec80] >[ 143.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3ec80] width 1280 pitch 5120 (/4 1280) >[ 143.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab6460] >[ 143.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab6460] width 1280 pitch 5120 (/4 1280) >[ 143.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3ec80] >[ 143.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3ec80] width 1280 pitch 5120 (/4 1280) >[ 143.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7880] >[ 143.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7880] width 1280 pitch 5120 (/4 1280) >[ 143.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3ec80] >[ 143.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3ec80] width 1280 pitch 5120 (/4 1280) >[ 143.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7880] >[ 143.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7880] width 1280 pitch 5120 (/4 1280) >[ 143.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3ec80] >[ 143.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3ec80] width 1280 pitch 5120 (/4 1280) >[ 143.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab7880] >[ 143.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab7880] width 1280 pitch 5120 (/4 1280) >[ 144.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae54c0] >[ 144.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae54c0] width 1280 pitch 5120 (/4 1280) >[ 144.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5920] >[ 144.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5920] width 1280 pitch 5120 (/4 1280) >[ 144.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 144.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5840] >[ 144.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5840] width 1280 pitch 5120 (/4 1280) >[ 144.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e2660] >[ 144.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e2660] width 1280 pitch 5120 (/4 1280) >[ 154.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 154.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 154.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 154.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb3d0] >[ 154.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb3d0] width 1280 pitch 5120 (/4 1280) >[ 158.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aeb370] >[ 158.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aeb370] width 1280 pitch 5120 (/4 1280) >[ 184.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 184.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 184.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 184.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 184.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 184.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 184.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff860] >[ 184.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff860] width 1280 pitch 5120 (/4 1280) >[ 184.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff550] >[ 184.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff550] width 1280 pitch 5120 (/4 1280) >[ 184.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff860] >[ 184.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff860] width 1280 pitch 5120 (/4 1280) >[ 184.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff860] >[ 184.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff860] width 1280 pitch 5120 (/4 1280) >[ 184.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff800] >[ 184.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff800] width 1280 pitch 5120 (/4 1280) >[ 184.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 184.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 184.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec80] >[ 184.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec80] width 1280 pitch 5120 (/4 1280) >[ 184.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff8d0] >[ 184.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff8d0] width 1280 pitch 5120 (/4 1280) >[ 184.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff740] >[ 184.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff740] width 1280 pitch 5120 (/4 1280) >[ 184.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec80] >[ 184.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec80] width 1280 pitch 5120 (/4 1280) >[ 184.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff8a0] >[ 184.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff8a0] width 1280 pitch 5120 (/4 1280) >[ 184.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 184.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 184.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec80] >[ 184.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec80] width 1280 pitch 5120 (/4 1280) >[ 184.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff7a0] >[ 184.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff7a0] width 1280 pitch 5120 (/4 1280) >[ 184.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff550] >[ 184.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff550] width 1280 pitch 5120 (/4 1280) >[ 184.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1affc00] >[ 184.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1affc00] width 1280 pitch 5120 (/4 1280) >[ 184.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff980] >[ 184.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff980] width 1280 pitch 5120 (/4 1280) >[ 184.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6e0] >[ 184.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6e0] width 1280 pitch 5120 (/4 1280) >[ 184.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec80] >[ 184.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec80] width 1280 pitch 5120 (/4 1280) >[ 184.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 184.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 184.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff980] >[ 184.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff980] width 1280 pitch 5120 (/4 1280) >[ 184.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 184.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 184.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff980] >[ 184.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff980] width 1280 pitch 5120 (/4 1280) >[ 184.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 184.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 184.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff980] >[ 184.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff980] width 1280 pitch 5120 (/4 1280) >[ 185.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff710] >[ 185.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff710] width 1280 pitch 5120 (/4 1280) >[ 185.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff760] >[ 185.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff760] width 1280 pitch 5120 (/4 1280) >[ 185.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff6b0] >[ 185.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff6b0] width 1280 pitch 5120 (/4 1280) >[ 185.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff580] >[ 185.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff580] width 1280 pitch 5120 (/4 1280) >[ 185.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 185.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 185.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 185.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 185.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 186.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 186.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 186.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff4d0] >[ 186.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff4d0] width 1280 pitch 5120 (/4 1280) >[ 186.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 186.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 187.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 187.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 187.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afff80] >[ 187.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afff80] width 1280 pitch 5120 (/4 1280) >[ 187.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aff9b0] >[ 187.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aff9b0] width 1280 pitch 5120 (/4 1280) >[ 187.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afff80] >[ 187.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afff80] width 1280 pitch 5120 (/4 1280) >[ 187.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05a40] >[ 187.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05a40] width 1280 pitch 5120 (/4 1280) >[ 187.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b058d0] >[ 187.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b058d0] width 1280 pitch 5120 (/4 1280) >[ 187.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aed000] >[ 187.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aed000] width 1280 pitch 5120 (/4 1280) >[ 187.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b058d0] >[ 187.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b058d0] width 1280 pitch 5120 (/4 1280) >[ 187.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aed000] >[ 188.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aed000] width 1280 pitch 5120 (/4 1280) >[ 188.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bdf90] >[ 188.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bdf90] width 1280 pitch 5120 (/4 1280) >[ 188.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5700] >[ 188.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5700] width 1280 pitch 5120 (/4 1280) >[ 194.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c3160] >[ 194.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c3160] width 1280 pitch 5120 (/4 1280) >[ 194.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c43e0] >[ 194.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c43e0] width 1280 pitch 5120 (/4 1280) >[ 557.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 557.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 557.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 557.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 557.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 558.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 558.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 558.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 558.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 559.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 559.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 559.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 559.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 561.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 561.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 561.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 561.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 561.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 561.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 561.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 561.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ac3f0] >[ 562.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ac3f0] width 1280 pitch 5120 (/4 1280) >[ 562.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 562.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a9ee0] >[ 562.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a9ee0] width 1280 pitch 5120 (/4 1280) >[ 562.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 562.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 632.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44040] >[ 632.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44040] width 1280 pitch 5120 (/4 1280) >[ 633.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387890] >[ 633.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387890] width 1280 pitch 5120 (/4 1280) >[ 633.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 633.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 633.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387890] >[ 633.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387890] width 1280 pitch 5120 (/4 1280) >[ 633.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 633.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 633.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387890] >[ 633.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387890] width 1280 pitch 5120 (/4 1280) >[ 633.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 633.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 633.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387890] >[ 633.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387890] width 1280 pitch 5120 (/4 1280) >[ 634.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 634.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 634.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387890] >[ 634.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387890] width 1280 pitch 5120 (/4 1280) >[ 634.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 634.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 634.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b474f0] >[ 635.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b474f0] width 1280 pitch 5120 (/4 1280) >[ 635.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 635.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 635.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b474f0] >[ 635.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b474f0] width 1280 pitch 5120 (/4 1280) >[ 635.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c00] >[ 635.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c00] width 1280 pitch 5120 (/4 1280) >[ 635.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b474f0] >[ 635.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b474f0] width 1280 pitch 5120 (/4 1280) >[ 635.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113dbe0] >[ 635.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113dbe0] width 1280 pitch 5120 (/4 1280) >[ 905.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14237c0] >[ 905.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14237c0] width 1280 pitch 5120 (/4 1280) >[ 905.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14237c0] >[ 905.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14237c0] width 1280 pitch 5120 (/4 1280) >[ 905.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 905.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 905.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 905.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 905.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14237c0] >[ 906.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14237c0] width 1280 pitch 5120 (/4 1280) >[ 906.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14237c0] >[ 906.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14237c0] width 1280 pitch 5120 (/4 1280) >[ 906.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b306e0] >[ 906.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b306e0] width 1280 pitch 5120 (/4 1280) >[ 906.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b306e0] >[ 906.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b306e0] width 1280 pitch 5120 (/4 1280) >[ 906.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b306e0] >[ 906.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b306e0] width 1280 pitch 5120 (/4 1280) >[ 906.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 906.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30680] >[ 906.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30680] width 1280 pitch 5120 (/4 1280) >[ 906.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 906.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 908.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 908.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 908.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 908.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 909.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 909.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 909.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 909.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 909.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 909.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 933.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 933.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 933.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 933.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 933.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 933.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 933.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 933.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 933.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 933.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 933.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 933.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 933.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 933.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 937.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 937.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 937.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 937.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 937.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 937.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 937.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 937.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 937.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 937.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 937.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 937.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 938.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 938.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 938.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 965.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 965.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 965.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 965.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 965.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 965.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 965.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 965.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 965.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 965.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 966.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 966.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 966.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 966.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 966.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 966.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1026.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1026.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1026.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1026.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1027.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1027.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1027.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1027.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1027.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1027.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1027.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1027.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1027.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1027.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1027.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1027.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1027.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1027.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1027.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1027.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1027.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1028.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1028.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1028.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1028.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1028.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1028.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1029.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1029.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1029.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1029.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1029.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1029.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1029.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1029.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1029.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1029.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1029.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1029.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1029.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1030.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113da70] >[ 1030.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113da70] width 1280 pitch 5120 (/4 1280) >[ 1030.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1030.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1030.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1030.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1030.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1030.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1030.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1030.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1030.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1030.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1030.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecbba0] >[ 1030.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecbba0] width 1280 pitch 5120 (/4 1280) >[ 1030.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1372290] >[ 1030.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1372290] width 1280 pitch 5120 (/4 1280) >[ 1034.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4e6f0] >[ 1034.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4e6f0] width 1280 pitch 5120 (/4 1280) >[ 1034.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x136eef0] >[ 1034.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x136eef0] width 1280 pitch 5120 (/4 1280) >[ 1188.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4ee0] >[ 1188.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4ee0] width 1280 pitch 5120 (/4 1280) >[ 1188.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b50b0] >[ 1188.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b50b0] width 1280 pitch 5120 (/4 1280) >[ 1189.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14380c0] >[ 1189.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14380c0] width 1280 pitch 5120 (/4 1280) >[ 1189.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b50b0] >[ 1189.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b50b0] width 1280 pitch 5120 (/4 1280) >[ 1204.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1426170] >[ 1204.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1426170] width 1280 pitch 5120 (/4 1280) >[ 1204.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x150fbe0] >[ 1204.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x150fbe0] width 1280 pitch 5120 (/4 1280) >[ 1229.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12782b0] >[ 1229.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12782b0] width 1280 pitch 5120 (/4 1280) >[ 1229.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e8750] >[ 1229.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e8750] width 1280 pitch 5120 (/4 1280) >[ 1337.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1337.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1337.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1337.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1337.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1338.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1338.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1338.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1338.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1339.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1339.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1339.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1339.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1340.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1340.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1340.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1340.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1340.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1340.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1341.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1341.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1341.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1341.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1341.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1341.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1341.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1341.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1341.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1341.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1341.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1341.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1341.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1341.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1345.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1345.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1345.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1345.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1345.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1345.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1345.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 1345.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 1345.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 1345.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 1345.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 1345.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 1345.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 1345.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 1345.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 1345.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 1345.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 1345.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 1345.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1345.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1345.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1345.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1345.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1345.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1345.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1345.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1345.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1345.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1345.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1345.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1345.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1345.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1345.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1345.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1345.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 1345.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 1345.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1346.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1346.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 1346.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 1346.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1346.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1346.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 1346.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 1346.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1346.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1346.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 1346.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 1346.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1346.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1346.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1346.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1346.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec80] >[ 1346.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec80] width 1280 pitch 5120 (/4 1280) >[ 1346.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1346.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1346.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 1346.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 1346.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1346.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1346.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1346.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1346.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1346.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1346.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1346.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1346.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1346.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1346.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1346.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1346.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1346.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1346.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1346.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1346.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1346.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1346.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1346.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1346.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1347.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1347.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1347.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1347.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1347.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1347.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113c150] >[ 1347.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113c150] width 1280 pitch 5120 (/4 1280) >[ 1347.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 1347.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 1347.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 1347.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 1347.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 1347.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 1347.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 1347.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 1347.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 1347.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 1347.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14238b0] >[ 1347.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14238b0] width 1280 pitch 5120 (/4 1280) >[ 1347.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 1347.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 1347.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1347.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1347.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203100] >[ 1347.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203100] width 1280 pitch 5120 (/4 1280) >[ 1347.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adee20] >[ 1347.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adee20] width 1280 pitch 5120 (/4 1280) >[ 1347.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1347.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1347.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1347.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1347.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1347.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1347.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1347.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1347.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1347.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1347.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1348.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1348.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1348.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1348.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[ 1348.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[ 1348.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 1348.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 1348.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 1348.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 1348.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 1348.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 1348.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 1348.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 1348.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 1348.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 1348.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1348.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1348.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1348.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1348.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1348.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1348.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1348.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1348.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1348.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1348.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1348.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1348.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1348.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1348.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46500] >[ 1348.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46500] width 1280 pitch 5120 (/4 1280) >[ 1348.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 1349.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 1349.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 1349.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 1349.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30840] >[ 1349.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30840] width 1280 pitch 5120 (/4 1280) >[ 1349.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 1349.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 1349.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b30840] >[ 1349.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b30840] width 1280 pitch 5120 (/4 1280) >[ 1349.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1387180] >[ 1349.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1387180] width 1280 pitch 5120 (/4 1280) >[ 1349.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1349.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1349.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1349.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1349.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1349.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1349.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1349.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1349.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44c60] >[ 1349.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44c60] width 1280 pitch 5120 (/4 1280) >[ 1349.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 1349.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 1349.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 1349.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 1349.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1349.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1349.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 1349.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 1349.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1349.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1349.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 1349.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 1349.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1349.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1349.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 1350.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 1350.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 1350.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 1350.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 1350.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 1350.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19dc2d0] >[ 1350.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19dc2d0] width 1280 pitch 5120 (/4 1280) >[ 1350.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152dda0] >[ 1350.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152dda0] width 1280 pitch 5120 (/4 1280) >[ 1350.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152dda0] >[ 1350.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152dda0] width 1280 pitch 5120 (/4 1280) >[ 1350.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19dc2d0] >[ 1350.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19dc2d0] width 1280 pitch 5120 (/4 1280) >[ 1350.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1350.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1350.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aec7b0] >[ 1350.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aec7b0] width 1280 pitch 5120 (/4 1280) >[ 1350.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4f820] >[ 1351.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4f820] width 1280 pitch 5120 (/4 1280) >[ 1351.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05340] >[ 1351.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05340] width 1280 pitch 5120 (/4 1280) >[ 1351.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05340] >[ 1351.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05340] width 1280 pitch 5120 (/4 1280) >[ 1351.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05340] >[ 1351.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05340] width 1280 pitch 5120 (/4 1280) >[ 1351.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05770] >[ 1351.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05770] width 1280 pitch 5120 (/4 1280) >[ 1351.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1351.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1351.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1351.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1351.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1364.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7aa0] >[ 1364.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7aa0] width 1280 pitch 5120 (/4 1280) >[ 1368.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae8010] >[ 1368.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae8010] width 1280 pitch 5120 (/4 1280) >[ 1370.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b39f20] >[ 1370.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b39f20] width 1280 pitch 5120 (/4 1280) >[ 1370.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1370.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1371.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65720] >[ 1371.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65720] width 1280 pitch 5120 (/4 1280) >[ 1371.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1371.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1371.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65720] >[ 1371.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65720] width 1280 pitch 5120 (/4 1280) >[ 1371.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1371.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1371.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65720] >[ 1371.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65720] width 1280 pitch 5120 (/4 1280) >[ 1371.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1371.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1371.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65720] >[ 1371.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65720] width 1280 pitch 5120 (/4 1280) >[ 1371.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1371.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1371.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65720] >[ 1371.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65720] width 1280 pitch 5120 (/4 1280) >[ 1371.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1371.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1372.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad930] >[ 1372.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad930] width 1280 pitch 5120 (/4 1280) >[ 1372.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3fb50] >[ 1372.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3fb50] width 1280 pitch 5120 (/4 1280) >[ 1372.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65e80] >[ 1372.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65e80] width 1280 pitch 5120 (/4 1280) >[ 1373.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38fb0] >[ 1373.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38fb0] width 1280 pitch 5120 (/4 1280) >[ 1373.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1373.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1373.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1373.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1373.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1373.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1373.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1373.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1373.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1374.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1374.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1374.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19778a0] >[ 1374.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19778a0] width 1280 pitch 5120 (/4 1280) >[ 1374.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1374.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1374.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b48c70] >[ 1374.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b48c70] width 1280 pitch 5120 (/4 1280) >[ 1374.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38d30] >[ 1374.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38d30] width 1280 pitch 5120 (/4 1280) >[ 1374.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b48c70] >[ 1374.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b48c70] width 1280 pitch 5120 (/4 1280) >[ 1374.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38d30] >[ 1374.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38d30] width 1280 pitch 5120 (/4 1280) >[ 1374.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b48c70] >[ 1374.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b48c70] width 1280 pitch 5120 (/4 1280) >[ 1374.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38d30] >[ 1374.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38d30] width 1280 pitch 5120 (/4 1280) >[ 1374.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b48c70] >[ 1374.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b48c70] width 1280 pitch 5120 (/4 1280) >[ 1374.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b38d30] >[ 1374.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b38d30] width 1280 pitch 5120 (/4 1280) >[ 1375.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1375.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1376.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1376.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1376.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf870] >[ 1376.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf870] width 1280 pitch 5120 (/4 1280) >[ 1376.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1376.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1376.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1376.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1376.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f780] >[ 1376.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f780] width 1280 pitch 5120 (/4 1280) >[ 1376.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1377.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1377.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f780] >[ 1377.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f780] width 1280 pitch 5120 (/4 1280) >[ 1377.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19777b0] >[ 1377.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19777b0] width 1280 pitch 5120 (/4 1280) >[ 1380.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd890] >[ 1380.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd890] width 1280 pitch 5120 (/4 1280) >[ 1380.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf970] >[ 1380.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf970] width 1280 pitch 5120 (/4 1280) >[ 1380.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113dd40] >[ 1380.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113dd40] width 1280 pitch 5120 (/4 1280) >[ 1380.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf970] >[ 1380.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf970] width 1280 pitch 5120 (/4 1280) >[ 1380.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab20c0] >[ 1380.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab20c0] width 1280 pitch 5120 (/4 1280) >[ 1380.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab20c0] >[ 1380.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab20c0] width 1280 pitch 5120 (/4 1280) >[ 1380.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ade3f0] >[ 1380.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ade3f0] width 1280 pitch 5120 (/4 1280) >[ 1380.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113dd40] >[ 1380.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113dd40] width 1280 pitch 5120 (/4 1280) >[ 1380.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf970] >[ 1380.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf970] width 1280 pitch 5120 (/4 1280) >[ 1380.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113dd40] >[ 1380.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113dd40] width 1280 pitch 5120 (/4 1280) >[ 1380.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaf970] >[ 1380.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaf970] width 1280 pitch 5120 (/4 1280) >[ 1380.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113dd40] >[ 1380.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113dd40] width 1280 pitch 5120 (/4 1280) >[ 1386.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafcb0] >[ 1386.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafcb0] width 1280 pitch 5120 (/4 1280) >[ 1386.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1386.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1386.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbd310] >[ 1386.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbd310] width 1280 pitch 5120 (/4 1280) >[ 1386.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65750] >[ 1386.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65750] width 1280 pitch 5120 (/4 1280) >[ 1390.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05120] >[ 1390.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05120] width 1280 pitch 5120 (/4 1280) >[ 1390.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1390.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1390.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1390.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1390.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1390.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1390.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1390.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1390.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1390.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1390.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1390.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1390.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1390.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1390.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1390.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1390.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1390.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1390.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1390.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1390.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1390.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1390.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1391.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1391.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1391.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1391.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1391.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1391.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1391.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1391.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1391.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1391.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1391.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1391.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1391.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1391.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1391.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1391.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1391.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1391.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1392.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65ee0] >[ 1392.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65ee0] width 1280 pitch 5120 (/4 1280) >[ 1393.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1393.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1393.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65ee0] >[ 1393.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65ee0] width 1280 pitch 5120 (/4 1280) >[ 1393.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1393.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1393.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1393.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1394.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1394.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1394.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65ee0] >[ 1394.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65ee0] width 1280 pitch 5120 (/4 1280) >[ 1394.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1394.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1394.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1394.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1394.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65ee0] >[ 1394.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65ee0] width 1280 pitch 5120 (/4 1280) >[ 1395.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1395.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1395.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1395.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1395.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1395.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1395.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1395.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1395.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1395.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1395.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1395.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1395.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b65ee0] >[ 1396.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b65ee0] width 1280 pitch 5120 (/4 1280) >[ 1396.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aad9b0] >[ 1396.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aad9b0] width 1280 pitch 5120 (/4 1280) >[ 1398.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aafe20] >[ 1398.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aafe20] width 1280 pitch 5120 (/4 1280) >[ 1398.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8570] >[ 1398.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8570] width 1280 pitch 5120 (/4 1280) >[ 1400.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f9b0] >[ 1400.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f9b0] width 1280 pitch 5120 (/4 1280) >[ 1400.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f950] >[ 1400.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f950] width 1280 pitch 5120 (/4 1280) >[ 1400.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f9b0] >[ 1400.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f9b0] width 1280 pitch 5120 (/4 1280) >[ 1400.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3f950] >[ 1400.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3f950] width 1280 pitch 5120 (/4 1280) >[ 1400.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b59130] >[ 1400.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b59130] width 1280 pitch 5120 (/4 1280) >[ 1400.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a26720] >[ 1400.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a26720] width 1280 pitch 5120 (/4 1280) >[ 1400.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3a580] >[ 1400.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3a580] width 1280 pitch 5120 (/4 1280) >[ 1401.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a26720] >[ 1401.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a26720] width 1280 pitch 5120 (/4 1280) >[ 1407.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e0f60] >[ 1407.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e0f60] width 1280 pitch 5120 (/4 1280) >[ 1407.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12300f0] >[ 1407.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12300f0] width 1280 pitch 5120 (/4 1280) >[ 1407.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e16a0] >[ 1407.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e16a0] width 1280 pitch 5120 (/4 1280) >[ 1407.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f970] >[ 1407.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f970] width 1280 pitch 5120 (/4 1280) >[ 1407.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a3660] >[ 1407.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a3660] width 1280 pitch 5120 (/4 1280) >[ 1407.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e16a0] >[ 1407.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e16a0] width 1280 pitch 5120 (/4 1280) >[ 1407.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e16a0] >[ 1407.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e16a0] width 1280 pitch 5120 (/4 1280) >[ 1407.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae5060] >[ 1407.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae5060] width 1280 pitch 5120 (/4 1280) >[ 1407.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e16a0] >[ 1407.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e16a0] width 1280 pitch 5120 (/4 1280) >[ 1407.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae4300] >[ 1407.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae4300] width 1280 pitch 5120 (/4 1280) >[ 1407.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae4d00] >[ 1407.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae4d00] width 1280 pitch 5120 (/4 1280) >[ 1407.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x193c520] >[ 1407.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x193c520] width 1280 pitch 5120 (/4 1280) >[ 1407.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae51a0] >[ 1407.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae51a0] width 1280 pitch 5120 (/4 1280) >[ 1408.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ce30] >[ 1408.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ce30] width 1280 pitch 5120 (/4 1280) >[ 1408.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4c9d0] >[ 1408.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4c9d0] width 1280 pitch 5120 (/4 1280) >[ 1408.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1408.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1408.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1408.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1408.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1408.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1408.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1408.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1408.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1408.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1408.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1408.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1408.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1408.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1408.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1408.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1408.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1408.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d620] >[ 1409.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d620] width 1280 pitch 5120 (/4 1280) >[ 1409.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d600] >[ 1409.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d600] width 1280 pitch 5120 (/4 1280) >[ 1409.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d600] >[ 1409.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d600] width 1280 pitch 5120 (/4 1280) >[ 1409.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d600] >[ 1409.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d600] width 1280 pitch 5120 (/4 1280) >[ 1409.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d600] >[ 1409.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d600] width 1280 pitch 5120 (/4 1280) >[ 1409.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4ccb0] >[ 1409.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4ccb0] width 1280 pitch 5120 (/4 1280) >[ 1409.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d600] >[ 1409.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d600] width 1280 pitch 5120 (/4 1280) >[ 1409.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1409.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1409.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1409.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1409.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1409.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1409.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1409.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1409.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4cd30] >[ 1409.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4cd30] width 1280 pitch 5120 (/4 1280) >[ 1409.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1409.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d720] >[ 1410.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d720] width 1280 pitch 5120 (/4 1280) >[ 1410.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5aff0] >[ 1410.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5aff0] width 1280 pitch 5120 (/4 1280) >[ 1410.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d5c0] >[ 1410.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d5c0] width 1280 pitch 5120 (/4 1280) >[ 1410.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4d760] >[ 1410.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4d760] width 1280 pitch 5120 (/4 1280) >[ 1452.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2270] >[ 1452.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2270] width 1280 pitch 5120 (/4 1280) >[ 1452.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ab3bd0] >[ 1452.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ab3bd0] width 1280 pitch 5120 (/4 1280) >[ 1564.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c43ba0] >[ 1564.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c43ba0] width 1280 pitch 5120 (/4 1280) >[ 1564.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3d6c0] >[ 1564.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3d6c0] width 1280 pitch 5120 (/4 1280) >[ 1659.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ac7040] >[ 1659.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ac7040] width 1280 pitch 5120 (/4 1280) >[ 1659.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c30] >[ 1659.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c30] width 1280 pitch 5120 (/4 1280) >[ 1660.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ac7040] >[ 1660.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ac7040] width 1280 pitch 5120 (/4 1280) >[ 1660.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c30] >[ 1660.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c30] width 1280 pitch 5120 (/4 1280) >[ 1660.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0cb0] >[ 1660.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0cb0] width 1280 pitch 5120 (/4 1280) >[ 1661.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0d10] >[ 1661.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0d10] width 1280 pitch 5120 (/4 1280) >[ 1661.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0cb0] >[ 1661.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0cb0] width 1280 pitch 5120 (/4 1280) >[ 1661.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0d10] >[ 1661.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0d10] width 1280 pitch 5120 (/4 1280) >[ 1661.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0cb0] >[ 1661.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0cb0] width 1280 pitch 5120 (/4 1280) >[ 1661.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0d10] >[ 1661.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0d10] width 1280 pitch 5120 (/4 1280) >[ 1661.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0cb0] >[ 1661.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0cb0] width 1280 pitch 5120 (/4 1280) >[ 1661.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c90] >[ 1661.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c90] width 1280 pitch 5120 (/4 1280) >[ 1661.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c30] >[ 1661.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c30] width 1280 pitch 5120 (/4 1280) >[ 1662.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c90] >[ 1662.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c90] width 1280 pitch 5120 (/4 1280) >[ 1663.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad0c30] >[ 1663.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad0c30] width 1280 pitch 5120 (/4 1280) >[ 1663.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5d7f0] >[ 1663.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5d7f0] width 1280 pitch 5120 (/4 1280) >[ 1663.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e1ae0] >[ 1663.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e1ae0] width 1280 pitch 5120 (/4 1280) >[ 1663.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c30360] >[ 1663.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c30360] width 1280 pitch 5120 (/4 1280) >[ 1663.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a26160] >[ 1663.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a26160] width 1280 pitch 5120 (/4 1280) >[ 1663.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c30360] >[ 1663.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c30360] width 1280 pitch 5120 (/4 1280) >[ 1663.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a26160] >[ 1663.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a26160] width 1280 pitch 5120 (/4 1280) >[ 1665.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1665.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1666.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1666.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1666.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1666.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1667.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1667.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1667.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1667.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1667.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1667.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1667.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1667.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1667.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1667.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1667.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1667.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1667.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1667.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1667.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1667.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1667.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1667.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1667.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[ 1667.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[ 1668.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144cf30] >[ 1668.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144cf30] width 1280 pitch 5120 (/4 1280) >[ 1668.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2300] >[ 1668.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2300] width 1280 pitch 5120 (/4 1280) >[ 1668.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1668.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1668.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2300] >[ 1668.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2300] width 1280 pitch 5120 (/4 1280) >[ 1668.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b03000] >[ 1668.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b03000] width 1280 pitch 5120 (/4 1280) >[ 1668.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1668.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1668.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b03000] >[ 1668.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b03000] width 1280 pitch 5120 (/4 1280) >[ 1669.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1669.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1669.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1669.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1669.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1669.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1669.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1669.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1669.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1669.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1669.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1669.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1670.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3b600] >[ 1670.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3b600] width 1280 pitch 5120 (/4 1280) >[ 1670.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1670.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1672.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4e590] >[ 1672.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4e590] width 1280 pitch 5120 (/4 1280) >[ 1673.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1673.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1674.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1674.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1674.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1674.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1674.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1674.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1674.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1674.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1674.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1674.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1674.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1674.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1674.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1674.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1674.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1674.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1674.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d1d0] >[ 1674.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d1d0] width 1280 pitch 5120 (/4 1280) >[ 1674.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5dd30] >[ 1674.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5dd30] width 1280 pitch 5120 (/4 1280) >[ 1677.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c872e0] >[ 1677.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c872e0] width 1280 pitch 5120 (/4 1280) >[ 1680.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[ 1680.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[ 1680.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9db60] >[ 1681.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9db60] width 1280 pitch 5120 (/4 1280) >[ 1729.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d505e0] >[ 1729.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d505e0] width 1280 pitch 5120 (/4 1280) >[ 1729.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d17f60] >[ 1729.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d17f60] width 1280 pitch 5120 (/4 1280) >[ 1730.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d505e0] >[ 1730.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d505e0] width 1280 pitch 5120 (/4 1280) >[ 1730.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d505e0] >[ 1730.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d505e0] width 1280 pitch 5120 (/4 1280) >[ 1730.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d505e0] >[ 1730.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d505e0] width 1280 pitch 5120 (/4 1280) >[ 1734.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c86ee0] >[ 1734.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c86ee0] width 1280 pitch 5120 (/4 1280) >[ 1769.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c932f0] >[ 1769.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c932f0] width 1280 pitch 5120 (/4 1280) >[ 1773.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1773.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1773.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0c30] >[ 1773.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0c30] width 1280 pitch 5120 (/4 1280) >[ 1774.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0c30] >[ 1774.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0c30] width 1280 pitch 5120 (/4 1280) >[ 1774.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1774.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c92800] >[ 1774.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c92800] width 1280 pitch 5120 (/4 1280) >[ 1774.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1774.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1793.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1793.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1794.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1794.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1794.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1794.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1794.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1794.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1794.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c6c770] >[ 1794.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c6c770] width 1280 pitch 5120 (/4 1280) >[ 1794.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1794.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1794.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1794.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1795.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c904c0] >[ 1795.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c904c0] width 1280 pitch 5120 (/4 1280) >[ 1795.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1795.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1795.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c904c0] >[ 1795.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c904c0] width 1280 pitch 5120 (/4 1280) >[ 1795.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1795.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1795.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c904c0] >[ 1795.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c904c0] width 1280 pitch 5120 (/4 1280) >[ 1795.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301ec0] >[ 1795.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301ec0] width 1280 pitch 5120 (/4 1280) >[ 1795.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1795.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1795.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1301ec0] >[ 1795.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1301ec0] width 1280 pitch 5120 (/4 1280) >[ 1795.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c904c0] >[ 1795.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c904c0] width 1280 pitch 5120 (/4 1280) >[ 1795.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1795.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1798.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1798.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1798.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d116c0] >[ 1798.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d116c0] width 1280 pitch 5120 (/4 1280) >[ 1798.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1798.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1798.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1798.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1798.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1798.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1798.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96600] >[ 1798.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96600] width 1280 pitch 5120 (/4 1280) >[ 1925.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1925.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1925.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1925.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1925.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1925.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1925.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1925.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1925.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1926.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1926.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1926.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1926.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1926.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1926.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1927.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1927.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6810] >[ 1927.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6810] width 1280 pitch 5120 (/4 1280) >[ 1927.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 1927.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 1927.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522cc0] >[ 1927.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522cc0] width 1280 pitch 5120 (/4 1280) >[ 1927.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 1927.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 1927.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1927.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1927.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0200] >[ 1927.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0200] width 1280 pitch 5120 (/4 1280) >[ 1927.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1927.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1927.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0200] >[ 1927.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0200] width 1280 pitch 5120 (/4 1280) >[ 1927.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1927.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1927.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 1927.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 1928.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1928.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1929.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1929.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1929.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1929.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1929.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1930.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 1930.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 1930.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1930.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1931.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1931.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1931.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 1931.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 1931.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1931.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1931.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1931.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1931.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1931.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1931.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1932.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1932.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1932.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1932.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1932.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1932.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1932.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1932.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1932.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1932.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1932.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1932.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 1932.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 1932.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 1932.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 1933.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1977880] >[ 1933.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1977880] width 1280 pitch 5120 (/4 1280) >[ 1933.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 1933.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 1934.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d8c0] >[ 1934.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d8c0] width 1280 pitch 5120 (/4 1280) >[ 1935.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1935.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1935.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1935.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1935.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1935.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1935.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1935.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1935.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1935.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1935.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1935.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1935.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1935.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1935.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1935.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1935.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1935.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1935.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1935.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1935.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 1936.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6690] >[ 1936.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6690] width 1280 pitch 5120 (/4 1280) >[ 1936.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 1936.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 2024.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 2024.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 2024.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2024.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2024.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 2024.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 2024.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2024.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2024.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 2024.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 2024.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2024.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2025.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c96460] >[ 2025.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c96460] width 1280 pitch 5120 (/4 1280) >[ 2025.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2025.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2025.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcfee0] >[ 2025.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcfee0] width 1280 pitch 5120 (/4 1280) >[ 2025.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2025.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2025.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2025.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2025.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2025.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2025.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2025.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2026.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2026.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2026.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2026.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2026.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2026.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2026.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2026.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2026.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2026.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2027.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2027.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2027.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2027.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2027.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e7aa0] >[ 2027.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e7aa0] width 1280 pitch 5120 (/4 1280) >[ 2028.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae7cc0] >[ 2028.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae7cc0] width 1280 pitch 5120 (/4 1280) >[ 2028.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae7620] >[ 2028.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae7620] width 1280 pitch 5120 (/4 1280) >[ 2028.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2028.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2028.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae7620] >[ 2028.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae7620] width 1280 pitch 5120 (/4 1280) >[ 2028.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144ac00] >[ 2028.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144ac00] width 1280 pitch 5120 (/4 1280) >[ 2033.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae79b0] >[ 2033.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae79b0] width 1280 pitch 5120 (/4 1280) >[ 2161.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2161.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2161.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2161.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2161.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2161.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2161.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2161.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2161.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2161.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2161.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2161.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2161.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2162.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2162.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2162.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2162.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2162.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2162.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2162.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2162.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2163.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2163.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2163.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2163.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2163.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2163.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2163.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2163.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2163.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2163.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2164.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2164.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2165.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2165.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2165.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2165.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2165.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2165.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2166.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2166.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2166.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2166.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2178.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2178.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2178.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2178.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2178.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2178.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2178.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2178.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2179.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2179.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2179.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2179.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2179.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2179.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2179.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2179.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2179.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2179.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2179.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2179.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2179.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2179.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2179.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2179.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2179.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2179.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2181.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2181.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2181.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2181.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2182.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2182.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2182.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2182.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2183.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2183.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2183.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2183.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2183.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2183.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2183.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2183.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2183.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2183.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2183.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2183.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2183.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2183.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2183.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2183.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2183.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2183.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2183.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2183.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2184.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2184.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2184.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2184.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2184.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2184.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2184.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2184.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2184.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2184.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2184.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2184.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2184.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2184.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2184.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2184.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2184.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2185.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2185.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2185.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2185.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2185.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2185.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2185.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2185.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2185.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2185.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2185.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2185.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2185.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2185.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2185.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2185.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2185.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2185.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2185.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2185.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2185.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2186.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2186.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2186.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5db00] >[ 2186.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5db00] width 1280 pitch 5120 (/4 1280) >[ 2186.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2186.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2186.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2186.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2186.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2186.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2186.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2186.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2186.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2186.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2186.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2186.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2187.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2187.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2187.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2187.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2187.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2187.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2187.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2187.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2187.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2187.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2187.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2187.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2187.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2187.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2187.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2187.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2187.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2187.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2188.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2188.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2188.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2188.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2188.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2188.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2188.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2188.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2188.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2188.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2188.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2188.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2188.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2188.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2188.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2188.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2188.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2188.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2188.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2188.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2189.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2189.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2189.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2189.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2189.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2189.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2189.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2189.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2189.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2189.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b10] >[ 2189.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b10] width 1280 pitch 5120 (/4 1280) >[ 2189.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2189.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2190.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2190.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2190.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2190.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2190.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2190.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2190.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2190.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2190.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2191.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2191.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2191.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7de90] >[ 2191.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7de90] width 1280 pitch 5120 (/4 1280) >[ 2192.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2192.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2192.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b16ec0] >[ 2192.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b16ec0] width 1280 pitch 5120 (/4 1280) >[ 2192.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2192.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2192.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2192.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2192.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d64c0] >[ 2192.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d64c0] width 1280 pitch 5120 (/4 1280) >[ 2192.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2192.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2192.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d24b00] >[ 2192.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d24b00] width 1280 pitch 5120 (/4 1280) >[ 2195.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6a6f0] >[ 2195.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6a6f0] width 1280 pitch 5120 (/4 1280) >[ 2197.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d8bdd0] >[ 2197.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d8bdd0] width 1280 pitch 5120 (/4 1280) >[ 2198.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2198.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e29760] >[ 2198.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e29760] width 1280 pitch 5120 (/4 1280) >[ 2198.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2198.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e578e0] >[ 2198.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e578e0] width 1280 pitch 5120 (/4 1280) >[ 2198.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2198.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e3340] >[ 2198.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e3340] width 1280 pitch 5120 (/4 1280) >[ 2198.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e578e0] >[ 2198.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e578e0] width 1280 pitch 5120 (/4 1280) >[ 2198.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e3340] >[ 2198.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e3340] width 1280 pitch 5120 (/4 1280) >[ 2198.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2198.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e3340] >[ 2198.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e3340] width 1280 pitch 5120 (/4 1280) >[ 2198.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2198.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e3340] >[ 2198.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e3340] width 1280 pitch 5120 (/4 1280) >[ 2198.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e58620] >[ 2198.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e58620] width 1280 pitch 5120 (/4 1280) >[ 2200.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1244e50] >[ 2200.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1244e50] width 1280 pitch 5120 (/4 1280) >[ 2200.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9bb90] >[ 2200.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9bb90] width 1280 pitch 5120 (/4 1280) >[ 2200.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d846c0] >[ 2200.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d846c0] width 1280 pitch 5120 (/4 1280) >[ 2200.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f25b0] >[ 2200.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f25b0] width 1280 pitch 5120 (/4 1280) >[ 2200.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1244e50] >[ 2201.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1244e50] width 1280 pitch 5120 (/4 1280) >[ 2201.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f25b0] >[ 2201.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f25b0] width 1280 pitch 5120 (/4 1280) >[ 2201.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d846c0] >[ 2201.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d846c0] width 1280 pitch 5120 (/4 1280) >[ 2201.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9bb90] >[ 2201.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9bb90] width 1280 pitch 5120 (/4 1280) >[ 2201.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1244e50] >[ 2201.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1244e50] width 1280 pitch 5120 (/4 1280) >[ 2263.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14fe490] >[ 2263.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14fe490] width 1280 pitch 5120 (/4 1280) >[ 2263.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e65b80] >[ 2263.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e65b80] width 1280 pitch 5120 (/4 1280) >[ 2269.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d6440] >[ 2269.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d6440] width 1280 pitch 5120 (/4 1280) >[ 2269.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d935c0] >[ 2269.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d935c0] width 1280 pitch 5120 (/4 1280) >[ 2292.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2292.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2293.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b86760] >[ 2293.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b86760] width 1280 pitch 5120 (/4 1280) >[ 2293.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2293.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2297.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b86760] >[ 2297.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b86760] width 1280 pitch 5120 (/4 1280) >[ 2298.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b86760] >[ 2298.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b86760] width 1280 pitch 5120 (/4 1280) >[ 2298.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2298.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2301.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2301.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2301.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2301.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2339.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2339.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2339.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2339.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2339.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2339.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2339.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2339.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2339.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2340.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2340.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2340.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2340.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2340.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2340.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2340.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2340.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2340.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2340.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2340.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2340.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2340.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2340.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2340.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2340.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2341.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2341.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2341.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2341.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2341.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2341.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2341.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2341.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2341.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2341.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2341.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2341.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2341.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2341.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2341.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2342.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2342.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2342.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2342.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2342.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2342.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2342.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2342.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2342.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2342.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2342.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2342.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2342.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2342.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2342.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2342.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2342.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2342.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2342.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2342.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2343.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2343.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2343.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2343.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2343.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2343.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2343.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2343.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2343.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2343.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 2344.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 2344.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2344.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2344.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2344.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2344.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2344.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2344.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2345.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2345.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2345.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 2345.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 2345.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d9d40] >[ 2345.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d9d40] width 1280 pitch 5120 (/4 1280) >[ 2345.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8eab0] >[ 2345.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8eab0] width 1280 pitch 5120 (/4 1280) >[ 2345.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2346.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2346.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b3d6e0] >[ 2346.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b3d6e0] width 1280 pitch 5120 (/4 1280) >[ 2347.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d99d0] >[ 2347.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d99d0] width 1280 pitch 5120 (/4 1280) >[ 2347.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2347.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2347.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2347.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2347.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2347.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2347.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d28e50] >[ 2347.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d28e50] width 1280 pitch 5120 (/4 1280) >[ 2347.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e52b0] >[ 2347.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e52b0] width 1280 pitch 5120 (/4 1280) >[ 2347.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2347.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2347.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e52b0] >[ 2348.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e52b0] width 1280 pitch 5120 (/4 1280) >[ 2348.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2348.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2348.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e52b0] >[ 2348.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e52b0] width 1280 pitch 5120 (/4 1280) >[ 2348.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7880] >[ 2348.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7880] width 1280 pitch 5120 (/4 1280) >[ 2369.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2369.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e5500] >[ 2369.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e5500] width 1280 pitch 5120 (/4 1280) >[ 2369.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1522c60] >[ 2369.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1522c60] width 1280 pitch 5120 (/4 1280) >[ 2389.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3b450] >[ 2389.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3b450] width 1280 pitch 5120 (/4 1280) >[ 2390.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7d750] >[ 2390.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7d750] width 1280 pitch 5120 (/4 1280) >[ 2473.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2473.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2474.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c88d0] >[ 2474.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c88d0] width 1280 pitch 5120 (/4 1280) >[ 2474.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2a580] >[ 2474.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2a580] width 1280 pitch 5120 (/4 1280) >[ 2476.441] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 2476.441] (II) RADEON(0): Printing DDC gathered Modelines: >[ 2476.441] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 3076.415] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 3076.415] (II) RADEON(0): Printing DDC gathered Modelines: >[ 3076.415] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 3166.889] (II) RADEON(0): RADEONSaveScreen(2) >[ 3166.889] (II) RADEON(0): RADEONSaveScreen(0) >[ 35979.098] (II) RADEON(0): RADEONSaveScreen(1) >[ 35983.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 35983.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 35984.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 35984.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 35984.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b429c0] >[ 35984.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b429c0] width 1280 pitch 5120 (/4 1280) >[ 35986.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae6d60] >[ 35986.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae6d60] width 1280 pitch 5120 (/4 1280) >[ 35986.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 35986.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 35986.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 35986.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 35986.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 35986.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 35986.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 35986.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 35986.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b429c0] >[ 35986.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b429c0] width 1280 pitch 5120 (/4 1280) >[ 35986.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 35987.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 35987.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 35987.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 35987.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 35987.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 35987.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 35987.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 35987.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 35987.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 35987.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 35987.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 35987.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d89d0] >[ 35987.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d89d0] width 1280 pitch 5120 (/4 1280) >[ 35987.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 35987.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 35987.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 35987.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 35987.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d89d0] >[ 35987.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d89d0] width 1280 pitch 5120 (/4 1280) >[ 35987.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 35987.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 35987.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d89d0] >[ 35987.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d89d0] width 1280 pitch 5120 (/4 1280) >[ 35987.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 35987.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 35987.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c3b00] >[ 35987.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c3b00] width 1280 pitch 5120 (/4 1280) >[ 35987.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0a20] >[ 35987.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0a20] width 1280 pitch 5120 (/4 1280) >[ 35987.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c3b00] >[ 35988.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c3b00] width 1280 pitch 5120 (/4 1280) >[ 35988.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0a20] >[ 35988.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0a20] width 1280 pitch 5120 (/4 1280) >[ 35988.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c3b00] >[ 35988.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c3b00] width 1280 pitch 5120 (/4 1280) >[ 35988.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 35988.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 35988.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113d3e0] >[ 35988.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113d3e0] width 1280 pitch 5120 (/4 1280) >[ 35989.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35989.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35989.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35989.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35989.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afe7b0] >[ 35989.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afe7b0] width 1280 pitch 5120 (/4 1280) >[ 35989.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b459c0] >[ 35989.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b459c0] width 1280 pitch 5120 (/4 1280) >[ 35989.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35989.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35989.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b459c0] >[ 35989.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b459c0] width 1280 pitch 5120 (/4 1280) >[ 35989.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35989.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35989.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35989.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35989.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 35989.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 35989.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 35989.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 35989.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 35989.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 35989.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1d8c0] >[ 35989.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1d8c0] width 1280 pitch 5120 (/4 1280) >[ 35989.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5da40] >[ 35989.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5da40] width 1280 pitch 5120 (/4 1280) >[ 35989.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 35990.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 35990.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 35990.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 35990.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1203990] >[ 35990.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1203990] width 1280 pitch 5120 (/4 1280) >[ 35990.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1491d60] >[ 35990.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1491d60] width 1280 pitch 5120 (/4 1280) >[ 35990.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35990.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35990.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46200] >[ 35990.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46200] width 1280 pitch 5120 (/4 1280) >[ 35993.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35993.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35993.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35993.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35994.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45970] >[ 35994.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45970] width 1280 pitch 5120 (/4 1280) >[ 35994.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35994.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35994.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 35994.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 35994.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35994.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35995.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 35995.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 35995.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35995.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35995.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35995.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35995.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 35995.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 35996.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35996.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35996.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35996.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35996.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35996.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35996.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35996.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35996.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35996.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35996.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35996.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35996.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35996.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35996.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5d0d0] >[ 35996.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5d0d0] width 1280 pitch 5120 (/4 1280) >[ 35996.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35996.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35996.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35996.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35997.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35997.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35997.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35997.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35997.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a33450] >[ 35997.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a33450] width 1280 pitch 5120 (/4 1280) >[ 35997.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35997.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35997.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5d030] >[ 35997.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5d030] width 1280 pitch 5120 (/4 1280) >[ 35997.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 35997.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 35997.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35997.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35997.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 35997.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 35997.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35997.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35997.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 35997.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 35997.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 35997.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 35997.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 35997.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 35997.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e3b40] >[ 35997.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e3b40] width 1280 pitch 5120 (/4 1280) >[ 35997.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e4cd0] >[ 35997.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e4cd0] width 1280 pitch 5120 (/4 1280) >[ 35998.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35998.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4140] >[ 35998.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4140] width 1280 pitch 5120 (/4 1280) >[ 35998.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4040] >[ 35998.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4040] width 1280 pitch 5120 (/4 1280) >[ 35999.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36000.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36000.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36000.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36000.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36000.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36000.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36000.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36000.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36000.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36001.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5650] >[ 36001.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5650] width 1280 pitch 5120 (/4 1280) >[ 36001.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36001.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36001.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36001.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36001.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5650] >[ 36001.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5650] width 1280 pitch 5120 (/4 1280) >[ 36001.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5650] >[ 36001.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5650] width 1280 pitch 5120 (/4 1280) >[ 36001.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36001.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36001.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36001.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36001.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36001.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36001.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5650] >[ 36001.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5650] width 1280 pitch 5120 (/4 1280) >[ 36002.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36002.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36002.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36002.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36002.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5650] >[ 36002.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5650] width 1280 pitch 5120 (/4 1280) >[ 36002.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36002.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36002.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36002.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36002.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36002.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36002.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36002.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36002.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36002.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36002.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36002.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36002.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36002.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36002.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36002.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36002.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36002.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36002.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36002.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36002.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36002.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36002.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36003.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36003.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36003.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36003.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36003.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36004.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36004.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36004.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36004.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36004.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36004.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36004.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36004.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36004.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36004.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36004.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36004.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36005.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36005.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36005.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36005.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36005.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36005.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36005.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36005.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36005.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2a010] >[ 36005.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2a010] width 1280 pitch 5120 (/4 1280) >[ 36005.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36005.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36005.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd150] >[ 36005.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd150] width 1280 pitch 5120 (/4 1280) >[ 36005.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328cf0] >[ 36005.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328cf0] width 1280 pitch 5120 (/4 1280) >[ 36005.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1937b90] >[ 36005.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1937b90] width 1280 pitch 5120 (/4 1280) >[ 36006.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c3b00] >[ 36006.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c3b00] width 1280 pitch 5120 (/4 1280) >[ 36006.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36006.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36006.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36006.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36006.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36006.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36006.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36006.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36006.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36006.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36006.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36006.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36006.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36006.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36006.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36006.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36006.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36006.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36006.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36006.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36006.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36006.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36006.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36006.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36006.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36006.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36006.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36006.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36006.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36006.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36006.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36006.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36006.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36006.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36006.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36006.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36006.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36006.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36006.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36006.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36006.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36006.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36007.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 36007.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 36007.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36007.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36007.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 36007.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 36007.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36007.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36007.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 36007.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 36007.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae6d60] >[ 36007.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae6d60] width 1280 pitch 5120 (/4 1280) >[ 36007.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0a20] >[ 36007.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0a20] width 1280 pitch 5120 (/4 1280) >[ 36007.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xfa5500] >[ 36007.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xfa5500] width 1280 pitch 5120 (/4 1280) >[ 36007.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0a20] >[ 36007.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0a20] width 1280 pitch 5120 (/4 1280) >[ 36007.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xfa5500] >[ 36007.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xfa5500] width 1280 pitch 5120 (/4 1280) >[ 36007.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36007.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36007.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xfa5500] >[ 36007.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xfa5500] width 1280 pitch 5120 (/4 1280) >[ 36007.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36007.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36007.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e030] >[ 36007.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e030] width 1280 pitch 5120 (/4 1280) >[ 36007.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36007.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36007.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e030] >[ 36007.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e030] width 1280 pitch 5120 (/4 1280) >[ 36007.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36007.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36007.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 36007.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 36007.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36007.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36007.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36007.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36007.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36007.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36007.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36007.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36007.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36007.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36007.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36007.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36007.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36007.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36007.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36007.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36007.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36008.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36008.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da910] >[ 36008.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da910] width 1280 pitch 5120 (/4 1280) >[ 36009.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36009.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36009.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 36009.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 36009.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36009.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36009.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36009.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36009.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36009.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36009.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36009.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36009.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36009.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36009.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114fcf0] >[ 36009.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114fcf0] width 1280 pitch 5120 (/4 1280) >[ 36010.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 36010.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 36010.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36010.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36010.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51520] >[ 36010.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51520] width 1280 pitch 5120 (/4 1280) >[ 36010.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b48bd0] >[ 36010.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b48bd0] width 1280 pitch 5120 (/4 1280) >[ 36012.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d15f0] >[ 36012.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d15f0] width 1280 pitch 5120 (/4 1280) >[ 36012.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51520] >[ 36012.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51520] width 1280 pitch 5120 (/4 1280) >[ 36012.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51520] >[ 36012.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51520] width 1280 pitch 5120 (/4 1280) >[ 36012.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36012.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36012.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36012.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36012.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36012.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36012.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36012.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36012.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d1450] >[ 36012.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d1450] width 1280 pitch 5120 (/4 1280) >[ 36012.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3e90] >[ 36012.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3e90] width 1280 pitch 5120 (/4 1280) >[ 36012.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d1450] >[ 36012.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d1450] width 1280 pitch 5120 (/4 1280) >[ 36012.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3e90] >[ 36012.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3e90] width 1280 pitch 5120 (/4 1280) >[ 36012.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36012.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36012.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36012.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36012.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36012.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36012.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3e90] >[ 36012.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3e90] width 1280 pitch 5120 (/4 1280) >[ 36012.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36012.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36012.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36012.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36012.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51520] >[ 36012.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51520] width 1280 pitch 5120 (/4 1280) >[ 36013.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51520] >[ 36013.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51520] width 1280 pitch 5120 (/4 1280) >[ 36013.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36013.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36013.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36013.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36013.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36013.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36013.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d1610] >[ 36013.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d1610] width 1280 pitch 5120 (/4 1280) >[ 36013.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484750] >[ 36013.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484750] width 1280 pitch 5120 (/4 1280) >[ 36013.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1306a30] >[ 36014.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1306a30] width 1280 pitch 5120 (/4 1280) >[ 36014.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484750] >[ 36014.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484750] width 1280 pitch 5120 (/4 1280) >[ 36014.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c980] >[ 36014.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c980] width 1280 pitch 5120 (/4 1280) >[ 36014.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484750] >[ 36014.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484750] width 1280 pitch 5120 (/4 1280) >[ 36014.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106c3e0] >[ 36014.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106c3e0] width 1280 pitch 5120 (/4 1280) >[ 36056.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef470] >[ 36056.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef470] width 1280 pitch 5120 (/4 1280) >[ 36056.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36056.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36056.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef470] >[ 36056.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef470] width 1280 pitch 5120 (/4 1280) >[ 36056.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36056.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36056.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef470] >[ 36057.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef470] width 1280 pitch 5120 (/4 1280) >[ 36057.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36057.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36057.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef470] >[ 36057.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef470] width 1280 pitch 5120 (/4 1280) >[ 36057.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36057.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36057.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef470] >[ 36057.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef470] width 1280 pitch 5120 (/4 1280) >[ 36057.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36057.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36057.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c7f0] >[ 36057.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c7f0] width 1280 pitch 5120 (/4 1280) >[ 36057.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[ 36057.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[ 36057.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196c7f0] >[ 36057.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196c7f0] width 1280 pitch 5120 (/4 1280) >[ 36077.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36077.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36077.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36077.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36077.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e80] >[ 36077.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e80] width 1280 pitch 5120 (/4 1280) >[ 36077.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36077.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36077.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36077.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36077.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e50] >[ 36077.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e50] width 1280 pitch 5120 (/4 1280) >[ 36077.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36077.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36077.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e80] >[ 36077.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e80] width 1280 pitch 5120 (/4 1280) >[ 36077.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e50] >[ 36077.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e50] width 1280 pitch 5120 (/4 1280) >[ 36077.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36077.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36077.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36077.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36077.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36077.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36077.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e50] >[ 36077.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e50] width 1280 pitch 5120 (/4 1280) >[ 36077.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da230] >[ 36077.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da230] width 1280 pitch 5120 (/4 1280) >[ 36077.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69e50] >[ 36077.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69e50] width 1280 pitch 5120 (/4 1280) >[ 36077.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36077.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36077.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36077.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36077.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69b10] >[ 36077.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69b10] width 1280 pitch 5120 (/4 1280) >[ 36077.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36077.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36077.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19da200] >[ 36078.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19da200] width 1280 pitch 5120 (/4 1280) >[ 36078.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36078.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36078.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c72250] >[ 36078.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c72250] width 1280 pitch 5120 (/4 1280) >[ 36078.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d69b10] >[ 36078.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d69b10] width 1280 pitch 5120 (/4 1280) >[ 36078.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36078.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36078.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 36078.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 36078.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9710] >[ 36078.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9710] width 1280 pitch 5120 (/4 1280) >[ 36078.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d9eb0] >[ 36078.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d9eb0] width 1280 pitch 5120 (/4 1280) >[ 36078.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44ac0] >[ 36078.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44ac0] width 1280 pitch 5120 (/4 1280) >[ 36078.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19d9e50] >[ 36078.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19d9e50] width 1280 pitch 5120 (/4 1280) >[ 36079.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19dd430] >[ 36079.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19dd430] width 1280 pitch 5120 (/4 1280) >[ 36079.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 36079.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 36079.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e030] >[ 36079.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e030] width 1280 pitch 5120 (/4 1280) >[ 36079.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36079.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36079.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e030] >[ 36079.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e030] width 1280 pitch 5120 (/4 1280) >[ 36079.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 36079.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 36079.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 36079.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 36079.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 36079.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 36079.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12516f0] >[ 36079.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12516f0] width 1280 pitch 5120 (/4 1280) >[ 36079.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 36079.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 36079.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36079.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36079.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 36079.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 36079.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36079.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36079.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36079.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36079.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36079.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36079.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36079.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36079.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19db310] >[ 36079.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19db310] width 1280 pitch 5120 (/4 1280) >[ 36080.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36080.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36080.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36080.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36080.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ad9a40] >[ 36080.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ad9a40] width 1280 pitch 5120 (/4 1280) >[ 36080.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 36080.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 36080.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36080.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36080.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 36080.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 36080.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae6d60] >[ 36080.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae6d60] width 1280 pitch 5120 (/4 1280) >[ 36080.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1daa0] >[ 36080.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1daa0] width 1280 pitch 5120 (/4 1280) >[ 36080.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36081.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36081.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36081.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36081.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x113b990] >[ 36081.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x113b990] width 1280 pitch 5120 (/4 1280) >[ 36081.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36081.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36081.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d68640] >[ 36081.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d68640] width 1280 pitch 5120 (/4 1280) >[ 36081.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a300b0] >[ 36081.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a300b0] width 1280 pitch 5120 (/4 1280) >[ 36081.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36081.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36081.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b5ed0] >[ 36081.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b5ed0] width 1280 pitch 5120 (/4 1280) >[ 36081.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36081.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36081.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1270a90] >[ 36081.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1270a90] width 1280 pitch 5120 (/4 1280) >[ 36081.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afec40] >[ 36081.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afec40] width 1280 pitch 5120 (/4 1280) >[ 36081.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36081.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36081.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e190] >[ 36081.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e190] width 1280 pitch 5120 (/4 1280) >[ 36081.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36081.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36081.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8600] >[ 36081.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8600] width 1280 pitch 5120 (/4 1280) >[ 36081.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12da830] >[ 36081.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12da830] width 1280 pitch 5120 (/4 1280) >[ 36081.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae6d60] >[ 36081.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae6d60] width 1280 pitch 5120 (/4 1280) >[ 36081.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0a20] >[ 36081.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0a20] width 1280 pitch 5120 (/4 1280) >[ 36081.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae6d60] >[ 36081.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae6d60] width 1280 pitch 5120 (/4 1280) >[ 36081.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196e030] >[ 36081.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196e030] width 1280 pitch 5120 (/4 1280) >[ 36083.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ac830] >[ 36083.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ac830] width 1280 pitch 5120 (/4 1280) >[ 36083.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ab50] >[ 36083.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ab50] width 1280 pitch 5120 (/4 1280) >[ 36089.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b427d0] >[ 36089.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b427d0] width 1280 pitch 5120 (/4 1280) >[ 36089.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x126c260] >[ 36089.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x126c260] width 1280 pitch 5120 (/4 1280) >[ 36091.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36091.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36091.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36091.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36091.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cda930] >[ 36091.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cda930] width 1280 pitch 5120 (/4 1280) >[ 36091.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2f400] >[ 36091.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2f400] width 1280 pitch 5120 (/4 1280) >[ 36091.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cda930] >[ 36091.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cda930] width 1280 pitch 5120 (/4 1280) >[ 36091.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2f400] >[ 36091.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2f400] width 1280 pitch 5120 (/4 1280) >[ 36091.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36091.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36091.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36091.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36091.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aecac0] >[ 36091.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aecac0] width 1280 pitch 5120 (/4 1280) >[ 36092.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36092.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36092.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36092.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36092.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aecac0] >[ 36092.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aecac0] width 1280 pitch 5120 (/4 1280) >[ 36093.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36093.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36093.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36093.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36093.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127f7c0] >[ 36093.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127f7c0] width 1280 pitch 5120 (/4 1280) >[ 36093.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aecac0] >[ 36093.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aecac0] width 1280 pitch 5120 (/4 1280) >[ 36093.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aecac0] >[ 36093.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aecac0] width 1280 pitch 5120 (/4 1280) >[ 36093.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36093.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36093.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b47f40] >[ 36093.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b47f40] width 1280 pitch 5120 (/4 1280) >[ 36093.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36093.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36093.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36093.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36093.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1263440] >[ 36093.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1263440] width 1280 pitch 5120 (/4 1280) >[ 36095.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c9a90] >[ 36095.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c9a90] width 1280 pitch 5120 (/4 1280) >[ 36095.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127f7c0] >[ 36095.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127f7c0] width 1280 pitch 5120 (/4 1280) >[ 36095.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c76ff0] >[ 36095.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c76ff0] width 1280 pitch 5120 (/4 1280) >[ 36095.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127f7c0] >[ 36095.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127f7c0] width 1280 pitch 5120 (/4 1280) >[ 36095.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b47f40] >[ 36095.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b47f40] width 1280 pitch 5120 (/4 1280) >[ 36095.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127f7c0] >[ 36095.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127f7c0] width 1280 pitch 5120 (/4 1280) >[ 36125.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36125.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36125.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36125.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36125.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36125.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36125.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36125.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36125.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44a60] >[ 36125.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44a60] width 1280 pitch 5120 (/4 1280) >[ 36125.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36125.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36125.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44a60] >[ 36125.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44a60] width 1280 pitch 5120 (/4 1280) >[ 36125.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36125.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36125.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44a60] >[ 36125.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44a60] width 1280 pitch 5120 (/4 1280) >[ 36125.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36125.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36125.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36125.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36125.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36125.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36125.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36125.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36126.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36126.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36126.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36126.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36126.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36126.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36126.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44a60] >[ 36126.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44a60] width 1280 pitch 5120 (/4 1280) >[ 36126.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36126.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36126.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36126.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36126.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36126.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36126.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36126.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36126.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36126.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36126.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36126.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36126.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36126.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36126.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36126.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36126.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36126.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36126.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36126.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36126.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5fad0] >[ 36126.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5fad0] width 1280 pitch 5120 (/4 1280) >[ 36127.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a600] >[ 36127.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a600] width 1280 pitch 5120 (/4 1280) >[ 36127.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b04460] >[ 36127.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b04460] width 1280 pitch 5120 (/4 1280) >[ 36127.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1492c90] >[ 36127.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1492c90] width 1280 pitch 5120 (/4 1280) >[ 36127.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5c330] >[ 36127.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5c330] width 1280 pitch 5120 (/4 1280) >[ 36127.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36127.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36127.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a600] >[ 36127.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a600] width 1280 pitch 5120 (/4 1280) >[ 36127.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36127.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36127.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36127.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36127.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36127.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36127.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144bff0] >[ 36127.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144bff0] width 1280 pitch 5120 (/4 1280) >[ 36127.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36127.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36127.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36127.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36127.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adff10] >[ 36127.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adff10] width 1280 pitch 5120 (/4 1280) >[ 36128.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8210] >[ 36128.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8210] width 1280 pitch 5120 (/4 1280) >[ 36128.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e340] >[ 36128.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e340] width 1280 pitch 5120 (/4 1280) >[ 36128.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ea80] >[ 36128.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ea80] width 1280 pitch 5120 (/4 1280) >[ 36128.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e980] >[ 36128.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e980] width 1280 pitch 5120 (/4 1280) >[ 36128.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ea80] >[ 36128.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ea80] width 1280 pitch 5120 (/4 1280) >[ 36128.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5e980] >[ 36128.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5e980] width 1280 pitch 5120 (/4 1280) >[ 36128.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ea80] >[ 36128.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ea80] width 1280 pitch 5120 (/4 1280) >[ 36128.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8430] >[ 36128.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8430] width 1280 pitch 5120 (/4 1280) >[ 36128.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8430] >[ 36128.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8430] width 1280 pitch 5120 (/4 1280) >[ 36128.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22aa0] >[ 36128.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22aa0] width 1280 pitch 5120 (/4 1280) >[ 36128.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60b80] >[ 36128.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60b80] width 1280 pitch 5120 (/4 1280) >[ 36128.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ea80] >[ 36128.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ea80] width 1280 pitch 5120 (/4 1280) >[ 36128.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c229d0] >[ 36128.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c229d0] width 1280 pitch 5120 (/4 1280) >[ 36128.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ea80] >[ 36129.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ea80] width 1280 pitch 5120 (/4 1280) >[ 36132.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36132.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36133.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36133.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36133.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36133.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36135.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36135.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36135.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36135.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36135.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36135.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36135.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9c090] >[ 36135.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9c090] width 1280 pitch 5120 (/4 1280) >[ 36135.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36135.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36136.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36136.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36136.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36136.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36136.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36136.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36136.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36136.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36136.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36136.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36137.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36137.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36137.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36137.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36138.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36138.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36138.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36138.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36138.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36138.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36138.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36138.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36138.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36138.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36138.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36138.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36138.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36138.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36139.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36139.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36139.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36139.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36139.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36139.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36139.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36139.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36139.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36139.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36139.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36139.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36139.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36139.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36139.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36139.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36139.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36139.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36139.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36139.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36139.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36140.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36140.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36140.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36140.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36140.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36140.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36140.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36140.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36140.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36140.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36140.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36140.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36140.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36140.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36140.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36140.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36140.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36140.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36140.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36140.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36140.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36140.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36140.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36140.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36140.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36140.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36140.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36140.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36141.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36141.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36141.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36141.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36141.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36141.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36141.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36141.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36141.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36141.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36141.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36141.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36141.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36141.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36141.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36141.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36141.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36141.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36141.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36141.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36141.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36141.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36141.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36141.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36142.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36142.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36142.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36142.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36142.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36142.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36142.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36142.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36142.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36142.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36142.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36142.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36142.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44580] >[ 36142.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44580] width 1280 pitch 5120 (/4 1280) >[ 36142.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36142.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36143.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36143.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36143.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36143.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36143.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5eb00] >[ 36144.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5eb00] width 1280 pitch 5120 (/4 1280) >[ 36145.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36145.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36145.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36145.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36146.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36146.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36146.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af8470] >[ 36146.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af8470] width 1280 pitch 5120 (/4 1280) >[ 36146.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36146.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36146.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36146.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36146.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36146.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36146.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36146.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36146.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5f860] >[ 36146.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5f860] width 1280 pitch 5120 (/4 1280) >[ 36146.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36146.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36146.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36146.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36146.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c257f0] >[ 36146.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c257f0] width 1280 pitch 5120 (/4 1280) >[ 36146.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1adfe90] >[ 36146.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1adfe90] width 1280 pitch 5120 (/4 1280) >[ 36167.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da25a0] >[ 36167.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da25a0] width 1280 pitch 5120 (/4 1280) >[ 36170.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11614c0] >[ 36170.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11614c0] width 1280 pitch 5120 (/4 1280) >[ 36170.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e258d0] >[ 36170.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e258d0] width 1280 pitch 5120 (/4 1280) >[ 36191.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d732f0] >[ 36191.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d732f0] width 1280 pitch 5120 (/4 1280) >[ 36203.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11649d0] >[ 36203.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11649d0] width 1280 pitch 5120 (/4 1280) >[ 36203.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c7030] >[ 36203.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c7030] width 1280 pitch 5120 (/4 1280) >[ 36203.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36203.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36203.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36203.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36203.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36203.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36203.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36203.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36203.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36203.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36203.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36203.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36203.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36203.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36203.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36203.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36203.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36203.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36203.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36203.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36203.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36203.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36203.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36204.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11649d0] >[ 36204.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11649d0] width 1280 pitch 5120 (/4 1280) >[ 36204.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c7030] >[ 36204.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c7030] width 1280 pitch 5120 (/4 1280) >[ 36204.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11649d0] >[ 36204.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11649d0] width 1280 pitch 5120 (/4 1280) >[ 36204.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36204.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36204.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36204.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36204.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36204.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36204.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1169cd0] >[ 36204.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1169cd0] width 1280 pitch 5120 (/4 1280) >[ 36204.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36204.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36204.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36204.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36204.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36204.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36204.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36204.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36204.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abc20] >[ 36204.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abc20] width 1280 pitch 5120 (/4 1280) >[ 36204.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36204.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36204.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36204.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36204.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11724d0] >[ 36204.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11724d0] width 1280 pitch 5120 (/4 1280) >[ 36204.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c7030] >[ 36204.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c7030] width 1280 pitch 5120 (/4 1280) >[ 36204.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c7030] >[ 36204.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c7030] width 1280 pitch 5120 (/4 1280) >[ 36204.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1177d80] >[ 36204.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1177d80] width 1280 pitch 5120 (/4 1280) >[ 36204.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c7030] >[ 36204.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c7030] width 1280 pitch 5120 (/4 1280) >[ 36266.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36266.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36266.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36266.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36266.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36266.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36266.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36266.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36266.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36266.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36266.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36266.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36266.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36266.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36266.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36266.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36266.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36266.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36266.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36266.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36266.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36266.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36266.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36266.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36266.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36266.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36266.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36266.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36266.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36266.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36266.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36266.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36266.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36267.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36267.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36267.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36267.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36267.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36267.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36267.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36267.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36267.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36267.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36267.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36267.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36267.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36267.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36267.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36267.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36267.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36267.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36267.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36267.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36268.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36268.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36268.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36268.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36268.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36268.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36268.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36268.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36268.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1996520] >[ 36268.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1996520] width 1280 pitch 5120 (/4 1280) >[ 36268.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36268.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36268.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36268.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36268.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12abcf0] >[ 36268.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12abcf0] width 1280 pitch 5120 (/4 1280) >[ 36269.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36269.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36270.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36270.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36270.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a9930] >[ 36270.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a9930] width 1280 pitch 5120 (/4 1280) >[ 36270.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36270.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36273.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36273.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36273.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36273.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36273.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36273.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36273.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1174030] >[ 36273.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1174030] width 1280 pitch 5120 (/4 1280) >[ 36273.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199a350] >[ 36273.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199a350] width 1280 pitch 5120 (/4 1280) >[ 36280.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2c820] >[ 36280.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2c820] width 1280 pitch 5120 (/4 1280) >[ 36281.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1164580] >[ 36281.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1164580] width 1280 pitch 5120 (/4 1280) >[ 36319.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e441a0] >[ 36319.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e441a0] width 1280 pitch 5120 (/4 1280) >[ 36319.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e48260] >[ 36319.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e48260] width 1280 pitch 5120 (/4 1280) >[ 36319.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e441a0] >[ 36319.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e441a0] width 1280 pitch 5120 (/4 1280) >[ 36319.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e46d40] >[ 36319.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e46d40] width 1280 pitch 5120 (/4 1280) >[ 36319.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e43f30] >[ 36319.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e43f30] width 1280 pitch 5120 (/4 1280) >[ 36319.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9c890] >[ 36319.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9c890] width 1280 pitch 5120 (/4 1280) >[ 36319.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e43f30] >[ 36319.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e43f30] width 1280 pitch 5120 (/4 1280) >[ 36319.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14650a0] >[ 36319.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14650a0] width 1280 pitch 5120 (/4 1280) >[ 36319.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9c890] >[ 36319.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9c890] width 1280 pitch 5120 (/4 1280) >[ 36319.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14650a0] >[ 36319.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14650a0] width 1280 pitch 5120 (/4 1280) >[ 36319.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9c890] >[ 36319.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9c890] width 1280 pitch 5120 (/4 1280) >[ 36319.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eff470] >[ 36319.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eff470] width 1280 pitch 5120 (/4 1280) >[ 36319.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e43f30] >[ 36319.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e43f30] width 1280 pitch 5120 (/4 1280) >[ 36321.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4a9d0] >[ 36321.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4a9d0] width 1280 pitch 5120 (/4 1280) >[ 36321.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d320] >[ 36321.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d320] width 1280 pitch 5120 (/4 1280) >[ 36321.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed0660] >[ 36321.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed0660] width 1280 pitch 5120 (/4 1280) >[ 36323.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17cf0] >[ 36323.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17cf0] width 1280 pitch 5120 (/4 1280) >[ 36323.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b620] >[ 36323.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b620] width 1280 pitch 5120 (/4 1280) >[ 36323.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b680] >[ 36323.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b680] width 1280 pitch 5120 (/4 1280) >[ 36323.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17460] >[ 36323.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17460] width 1280 pitch 5120 (/4 1280) >[ 36323.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b4f0] >[ 36323.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b4f0] width 1280 pitch 5120 (/4 1280) >[ 36323.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17ea0] >[ 36323.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17ea0] width 1280 pitch 5120 (/4 1280) >[ 36323.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a18380] >[ 36323.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a18380] width 1280 pitch 5120 (/4 1280) >[ 36323.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b490] >[ 36323.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b490] width 1280 pitch 5120 (/4 1280) >[ 36323.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17cf0] >[ 36323.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17cf0] width 1280 pitch 5120 (/4 1280) >[ 36323.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36323.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36323.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a18810] >[ 36323.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a18810] width 1280 pitch 5120 (/4 1280) >[ 36323.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36323.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36323.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf8920] >[ 36323.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf8920] width 1280 pitch 5120 (/4 1280) >[ 36323.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a18cc0] >[ 36323.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a18cc0] width 1280 pitch 5120 (/4 1280) >[ 36324.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17e40] >[ 36324.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17e40] width 1280 pitch 5120 (/4 1280) >[ 36324.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17cf0] >[ 36325.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17cf0] width 1280 pitch 5120 (/4 1280) >[ 36325.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a18cc0] >[ 36325.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a18cc0] width 1280 pitch 5120 (/4 1280) >[ 36325.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17ea0] >[ 36325.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17ea0] width 1280 pitch 5120 (/4 1280) >[ 36325.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17460] >[ 36325.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17460] width 1280 pitch 5120 (/4 1280) >[ 36325.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d92b20] >[ 36325.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d92b20] width 1280 pitch 5120 (/4 1280) >[ 36325.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d92b80] >[ 36325.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d92b80] width 1280 pitch 5120 (/4 1280) >[ 36325.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17e40] >[ 36325.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17e40] width 1280 pitch 5120 (/4 1280) >[ 36325.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d92b20] >[ 36325.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d92b20] width 1280 pitch 5120 (/4 1280) >[ 36325.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17e40] >[ 36325.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17e40] width 1280 pitch 5120 (/4 1280) >[ 36325.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d92b20] >[ 36325.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d92b20] width 1280 pitch 5120 (/4 1280) >[ 36325.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a18c90] >[ 36325.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a18c90] width 1280 pitch 5120 (/4 1280) >[ 36325.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d92b20] >[ 36325.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d92b20] width 1280 pitch 5120 (/4 1280) >[ 36325.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a17e70] >[ 36325.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a17e70] width 1280 pitch 5120 (/4 1280) >[ 36335.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1db70] >[ 36335.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1db70] width 1280 pitch 5120 (/4 1280) >[ 36335.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1db70] >[ 36335.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1db70] width 1280 pitch 5120 (/4 1280) >[ 36340.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36340.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36340.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36340.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36341.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36341.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36341.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36341.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36341.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36341.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36341.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36341.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36341.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36341.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36341.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36341.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36341.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36341.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36341.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36341.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36341.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36341.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36342.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 36342.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 36342.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36342.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36342.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36342.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36342.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36342.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36342.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36342.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36343.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36343.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36343.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36343.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36343.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36343.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36343.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36343.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36344.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36344.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36344.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36344.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36344.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36344.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36344.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36344.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36344.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36344.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36344.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36344.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36344.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36344.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36345.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36345.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36345.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36345.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36345.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36345.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36345.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36345.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36345.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36345.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36345.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36345.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36345.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36345.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36345.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36345.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36346.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36346.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36346.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36346.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36346.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36346.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36346.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36346.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36346.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36346.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36346.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36346.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36347.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462450] >[ 36347.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462450] width 1280 pitch 5120 (/4 1280) >[ 36347.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36347.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36348.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d8f0] >[ 36348.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d8f0] width 1280 pitch 5120 (/4 1280) >[ 36348.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a98a60] >[ 36348.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a98a60] width 1280 pitch 5120 (/4 1280) >[ 36348.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36348.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36348.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2b320] >[ 36348.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2b320] width 1280 pitch 5120 (/4 1280) >[ 36348.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36348.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36348.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2b320] >[ 36348.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2b320] width 1280 pitch 5120 (/4 1280) >[ 36348.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36348.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36348.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2b320] >[ 36348.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2b320] width 1280 pitch 5120 (/4 1280) >[ 36348.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2b320] >[ 36348.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2b320] width 1280 pitch 5120 (/4 1280) >[ 36348.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d850] >[ 36348.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d850] width 1280 pitch 5120 (/4 1280) >[ 36352.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3f820] >[ 36352.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3f820] width 1280 pitch 5120 (/4 1280) >[ 36352.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36352.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36386.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36386.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36386.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36386.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36386.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36386.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36386.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36386.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36386.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36386.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36386.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36386.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36386.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36386.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36386.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36386.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36386.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36386.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36386.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36386.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36386.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36386.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36386.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36386.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36386.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36386.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36386.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36386.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36387.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36387.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36387.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36387.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36387.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36387.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36387.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36387.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36387.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36387.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36387.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36387.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36387.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36387.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36387.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36387.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36387.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36387.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36387.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36387.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36387.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36387.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36394.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36394.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36394.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36394.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36394.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36394.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36394.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36394.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36394.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36394.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36394.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36394.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36394.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36394.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36394.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36394.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36394.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36394.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36394.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36394.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36394.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36394.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36394.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36394.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36394.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36394.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36394.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36394.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36394.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36394.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36394.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36394.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2381fd0] >[ 36394.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2381fd0] width 1280 pitch 5120 (/4 1280) >[ 36394.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36394.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36394.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36394.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36394.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a66f30] >[ 36394.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a66f30] width 1280 pitch 5120 (/4 1280) >[ 36394.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36394.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36394.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36394.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36394.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa5ca0] >[ 36394.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa5ca0] width 1280 pitch 5120 (/4 1280) >[ 36394.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1168bd0] >[ 36394.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1168bd0] width 1280 pitch 5120 (/4 1280) >[ 36394.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a187b0] >[ 36394.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a187b0] width 1280 pitch 5120 (/4 1280) >[ 36394.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3e080] >[ 36394.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3e080] width 1280 pitch 5120 (/4 1280) >[ 36580.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36580.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36580.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36580.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36580.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36580.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36580.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36580.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36580.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36580.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36580.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36580.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36580.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36580.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36580.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36580.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36580.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36580.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36580.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36580.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36580.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36580.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36580.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36580.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36580.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36580.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36581.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36581.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36581.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36581.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36581.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36581.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36581.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36581.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36581.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36581.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36581.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36581.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36581.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36581.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36581.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36581.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36581.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36581.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36581.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36581.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36581.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36581.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36581.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36581.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36581.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36581.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36581.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36581.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36581.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36581.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36583.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36583.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36583.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36583.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36583.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36583.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36583.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36583.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36583.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36583.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36583.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36583.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36583.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36583.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36583.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36583.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36583.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36583.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36583.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36583.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36583.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36583.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36583.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36583.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36583.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36583.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36583.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36583.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36583.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36583.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36583.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36583.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36583.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36584.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36584.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36584.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36584.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36584.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36584.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36584.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36584.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36584.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36584.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36584.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36584.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36584.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36584.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36584.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36584.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36584.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36584.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36584.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36584.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36584.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36584.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36584.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36584.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36584.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36584.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36584.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36584.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36584.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b5aaf0] >[ 36584.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b5aaf0] width 1280 pitch 5120 (/4 1280) >[ 36584.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36584.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36584.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36584.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36584.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36584.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36584.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36584.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36584.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36584.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36584.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36584.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36585.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36585.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36585.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36585.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36585.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36585.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36585.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36585.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36585.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b429c0] >[ 36585.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b429c0] width 1280 pitch 5120 (/4 1280) >[ 36585.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36585.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36585.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36585.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36585.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51820] >[ 36585.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51820] width 1280 pitch 5120 (/4 1280) >[ 36585.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36585.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36585.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36585.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36585.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36585.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36585.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36585.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36585.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a77540] >[ 36585.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a77540] width 1280 pitch 5120 (/4 1280) >[ 36585.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b429c0] >[ 36585.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b429c0] width 1280 pitch 5120 (/4 1280) >[ 36585.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67110] >[ 36585.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67110] width 1280 pitch 5120 (/4 1280) >[ 36585.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36585.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36585.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67110] >[ 36585.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67110] width 1280 pitch 5120 (/4 1280) >[ 36585.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36585.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36585.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e870b0] >[ 36585.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e870b0] width 1280 pitch 5120 (/4 1280) >[ 36585.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51820] >[ 36585.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51820] width 1280 pitch 5120 (/4 1280) >[ 36585.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36585.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36586.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e919d0] >[ 36586.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e919d0] width 1280 pitch 5120 (/4 1280) >[ 36586.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36586.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36586.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36586.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36586.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b429c0] >[ 36586.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b429c0] width 1280 pitch 5120 (/4 1280) >[ 36586.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71540] >[ 36586.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71540] width 1280 pitch 5120 (/4 1280) >[ 36586.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67110] >[ 36586.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67110] width 1280 pitch 5120 (/4 1280) >[ 36586.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36586.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36586.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51820] >[ 36586.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51820] width 1280 pitch 5120 (/4 1280) >[ 36586.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36586.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36586.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51820] >[ 36586.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51820] width 1280 pitch 5120 (/4 1280) >[ 36586.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e54d0] >[ 36586.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e54d0] width 1280 pitch 5120 (/4 1280) >[ 36601.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36601.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36601.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36601.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36601.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36601.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36601.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36601.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36601.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36601.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36601.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36601.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36601.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36601.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36601.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36601.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36601.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36602.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36602.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36602.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36602.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36602.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36602.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36602.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36602.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36602.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36602.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36602.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36602.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36602.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36602.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36602.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36602.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36602.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36602.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36602.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36602.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36602.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36602.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36602.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36602.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36602.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36602.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36603.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36603.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36603.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36603.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36603.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36603.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36603.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36603.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36603.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36603.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36603.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36603.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36604.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36604.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36604.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36604.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36604.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36604.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36604.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36604.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36605.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36605.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36605.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7ce40] >[ 36605.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7ce40] width 1280 pitch 5120 (/4 1280) >[ 36605.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36605.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36605.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36605.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36605.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36605.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36605.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36605.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36605.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44630] >[ 36605.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44630] width 1280 pitch 5120 (/4 1280) >[ 36605.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98f40] >[ 36605.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98f40] width 1280 pitch 5120 (/4 1280) >[ 36605.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9aaf0] >[ 36605.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9aaf0] width 1280 pitch 5120 (/4 1280) >[ 36606.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e94e50] >[ 36606.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e94e50] width 1280 pitch 5120 (/4 1280) >[ 36606.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e94e50] >[ 36606.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e94e50] width 1280 pitch 5120 (/4 1280) >[ 36606.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e445b0] >[ 36606.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e445b0] width 1280 pitch 5120 (/4 1280) >[ 36606.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36607.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36607.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36607.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36607.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36607.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36607.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36607.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36607.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36607.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36607.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36607.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36608.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36608.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36608.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36608.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36608.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36608.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36608.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36608.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36608.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36608.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36608.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36608.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36609.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36609.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36609.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36609.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36609.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36609.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36610.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36610.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36610.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36610.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36610.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36610.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36610.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36610.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36610.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36610.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36610.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7d000] >[ 36610.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7d000] width 1280 pitch 5120 (/4 1280) >[ 36610.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36610.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36616.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36616.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36616.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36616.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36616.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36616.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36617.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36617.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36617.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36617.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36617.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36617.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36617.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36617.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36617.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36617.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36617.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36617.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36618.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36618.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36621.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36621.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36621.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36621.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36621.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36621.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36621.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36621.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36621.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36621.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36621.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36621.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36621.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36622.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36622.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36622.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36622.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36622.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36622.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36622.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36622.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36622.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36622.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36622.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36622.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36622.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36623.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36623.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36623.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36623.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36623.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36623.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36623.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36623.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36626.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9df40] >[ 36626.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9df40] width 1280 pitch 5120 (/4 1280) >[ 36626.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36626.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36626.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[ 36626.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[ 36626.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36626.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36627.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36627.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36627.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98780] >[ 36627.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98780] width 1280 pitch 5120 (/4 1280) >[ 36627.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36627.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36627.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dd80] >[ 36627.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dd80] width 1280 pitch 5120 (/4 1280) >[ 36683.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36683.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36683.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36683.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36683.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36683.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36683.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36684.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36684.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36684.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36684.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36686.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36686.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36686.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36686.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36686.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36686.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36687.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36687.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36687.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36687.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36687.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36687.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36687.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36687.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36687.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36687.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36687.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36687.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36688.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36688.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36688.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36688.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36689.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36689.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36689.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36689.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36689.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36689.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36689.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36689.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36690.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36690.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36690.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36690.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36690.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36690.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36690.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36690.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36691.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36691.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36691.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36691.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36693.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36693.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36693.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36693.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36693.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36693.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36693.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36693.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36693.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36693.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36693.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36693.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36693.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36693.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36693.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36693.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36693.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36693.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36693.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36693.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131ee90] >[ 36694.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131ee90] width 1280 pitch 5120 (/4 1280) >[ 36694.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a36a0] >[ 36694.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a36a0] width 1280 pitch 5120 (/4 1280) >[ 36694.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36694.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36694.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36694.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36694.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36695.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36695.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36695.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36695.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36697.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36697.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36697.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36697.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36697.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36697.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36697.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36697.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36697.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36697.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36697.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36697.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36697.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36697.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36697.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36697.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36698.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36698.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36698.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36698.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36698.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36698.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36698.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36698.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36699.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36699.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36699.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36699.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36699.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36699.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36699.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36699.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36699.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36699.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36699.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36699.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36699.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36699.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d9330] >[ 36700.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d9330] width 1280 pitch 5120 (/4 1280) >[ 36700.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea1f30] >[ 36700.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea1f30] width 1280 pitch 5120 (/4 1280) >[ 36700.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d281e0] >[ 36700.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d281e0] width 1280 pitch 5120 (/4 1280) >[ 36700.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36700.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36700.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d28370] >[ 36700.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d28370] width 1280 pitch 5120 (/4 1280) >[ 36700.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eacb00] >[ 36700.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eacb00] width 1280 pitch 5120 (/4 1280) >[ 36700.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d28200] >[ 36700.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d28200] width 1280 pitch 5120 (/4 1280) >[ 36701.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac310] >[ 36701.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac310] width 1280 pitch 5120 (/4 1280) >[ 36701.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d281a0] >[ 36701.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d281a0] width 1280 pitch 5120 (/4 1280) >[ 36701.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac6e0] >[ 36701.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac6e0] width 1280 pitch 5120 (/4 1280) >[ 36701.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac090] >[ 36701.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac090] width 1280 pitch 5120 (/4 1280) >[ 36701.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36701.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36701.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36701.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36701.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36701.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36701.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac6e0] >[ 36701.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac6e0] width 1280 pitch 5120 (/4 1280) >[ 36701.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36701.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36701.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac6e0] >[ 36701.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac6e0] width 1280 pitch 5120 (/4 1280) >[ 36701.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36701.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36702.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36702.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36702.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9a1d0] >[ 36702.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9a1d0] width 1280 pitch 5120 (/4 1280) >[ 36702.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36702.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36703.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36703.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36703.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36703.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36703.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36703.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36703.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e55a0] >[ 36703.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e55a0] width 1280 pitch 5120 (/4 1280) >[ 36703.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36703.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36703.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac6e0] >[ 36703.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac6e0] width 1280 pitch 5120 (/4 1280) >[ 36703.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44360] >[ 36703.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44360] width 1280 pitch 5120 (/4 1280) >[ 36703.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9a1d0] >[ 36703.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9a1d0] width 1280 pitch 5120 (/4 1280) >[ 36704.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36704.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36704.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36704.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36705.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac6e0] >[ 36705.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac6e0] width 1280 pitch 5120 (/4 1280) >[ 36705.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36705.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36705.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36705.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36705.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36705.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36705.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 36706.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 36706.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9dfc0] >[ 36706.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9dfc0] width 1280 pitch 5120 (/4 1280) >[ 36706.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d90d0] >[ 36706.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d90d0] width 1280 pitch 5120 (/4 1280) >[ 36708.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36708.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36708.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36708.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36708.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36708.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36708.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36708.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36708.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36708.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36708.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36708.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36708.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36708.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36708.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36708.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36708.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36708.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36708.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36708.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36709.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36709.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36709.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36709.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36710.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36710.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36710.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36710.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36710.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36710.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36710.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36710.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36710.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36710.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36710.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36710.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36710.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36710.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36710.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36711.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36711.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36711.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36711.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36711.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36711.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36711.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36711.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36711.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36711.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36711.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36711.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36712.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36712.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36712.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14b4f60] >[ 36712.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14b4f60] width 1280 pitch 5120 (/4 1280) >[ 36712.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36712.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36712.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19de0b0] >[ 36712.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19de0b0] width 1280 pitch 5120 (/4 1280) >[ 36712.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36712.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36712.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19de0b0] >[ 36712.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19de0b0] width 1280 pitch 5120 (/4 1280) >[ 36712.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36712.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36712.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19de0b0] >[ 36712.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19de0b0] width 1280 pitch 5120 (/4 1280) >[ 36712.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 36712.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 36713.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d2e00] >[ 36713.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d2e00] width 1280 pitch 5120 (/4 1280) >[ 36713.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 36713.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 36713.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12de370] >[ 36713.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12de370] width 1280 pitch 5120 (/4 1280) >[ 36713.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 36713.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 36713.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 36713.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 36713.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 36713.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 36713.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 36713.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 36713.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5a20] >[ 36713.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5a20] width 1280 pitch 5120 (/4 1280) >[ 36713.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36713.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36713.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144f930] >[ 36713.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144f930] width 1280 pitch 5120 (/4 1280) >[ 36713.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36713.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36713.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36713.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36713.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36713.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36714.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1230510] >[ 36714.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1230510] width 1280 pitch 5120 (/4 1280) >[ 36714.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36714.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36714.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36714.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36714.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114bab0] >[ 36714.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114bab0] width 1280 pitch 5120 (/4 1280) >[ 36714.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1309510] >[ 36714.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1309510] width 1280 pitch 5120 (/4 1280) >[ 36714.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147eb0] >[ 36714.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147eb0] width 1280 pitch 5120 (/4 1280) >[ 36714.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1309510] >[ 36714.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1309510] width 1280 pitch 5120 (/4 1280) >[ 36714.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147eb0] >[ 36714.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147eb0] width 1280 pitch 5120 (/4 1280) >[ 36714.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36714.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36714.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36714.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36714.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19de0b0] >[ 36714.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19de0b0] width 1280 pitch 5120 (/4 1280) >[ 36714.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36714.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36714.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 36714.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 36714.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36714.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36714.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 36714.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 36714.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36714.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36715.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 36715.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 36715.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1993110] >[ 36715.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1993110] width 1280 pitch 5120 (/4 1280) >[ 36715.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36715.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36715.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9ae10] >[ 36715.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9ae10] width 1280 pitch 5120 (/4 1280) >[ 36715.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1309510] >[ 36715.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1309510] width 1280 pitch 5120 (/4 1280) >[ 36715.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1230510] >[ 36715.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1230510] width 1280 pitch 5120 (/4 1280) >[ 36715.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1316ef0] >[ 36715.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1316ef0] width 1280 pitch 5120 (/4 1280) >[ 36715.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36715.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36715.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x144f930] >[ 36715.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x144f930] width 1280 pitch 5120 (/4 1280) >[ 36715.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6f640] >[ 36715.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6f640] width 1280 pitch 5120 (/4 1280) >[ 36715.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[ 36715.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[ 36715.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c8d30] >[ 36716.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c8d30] width 1280 pitch 5120 (/4 1280) >[ 36716.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9f0e0] >[ 36716.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9f0e0] width 1280 pitch 5120 (/4 1280) >[ 36716.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114bab0] >[ 36716.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114bab0] width 1280 pitch 5120 (/4 1280) >[ 36716.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a9ae10] >[ 36716.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a9ae10] width 1280 pitch 5120 (/4 1280) >[ 36716.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1147eb0] >[ 36716.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1147eb0] width 1280 pitch 5120 (/4 1280) >[ 36716.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[ 36716.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[ 36717.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1309510] >[ 36717.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1309510] width 1280 pitch 5120 (/4 1280) >[ 36717.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c5aa0] >[ 36717.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c5aa0] width 1280 pitch 5120 (/4 1280) >[ 36729.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7cf30] >[ 36729.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7cf30] width 1280 pitch 5120 (/4 1280) >[ 36748.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450ed0] >[ 36748.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450ed0] width 1280 pitch 5120 (/4 1280) >[ 36755.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1471b70] >[ 36755.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1471b70] width 1280 pitch 5120 (/4 1280) >[ 36755.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x139b2a0] >[ 36755.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x139b2a0] width 1280 pitch 5120 (/4 1280) >[ 36756.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baea0] >[ 36756.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baea0] width 1280 pitch 5120 (/4 1280) >[ 36775.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bafa0] >[ 36775.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bafa0] width 1280 pitch 5120 (/4 1280) >[ 36777.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146b710] >[ 36777.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146b710] width 1280 pitch 5120 (/4 1280) >[ 36801.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fde90] >[ 36801.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fde90] width 1280 pitch 5120 (/4 1280) >[ 36803.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 36803.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 36803.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36803.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36803.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36803.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36803.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36803.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36803.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36803.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36803.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36803.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36803.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36803.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36803.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36803.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36803.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36803.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36803.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36804.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36804.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36804.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36804.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36804.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36804.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36804.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36804.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36804.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36804.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36804.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36804.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36804.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36804.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36804.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36804.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 36804.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 36804.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1450d40] >[ 36804.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1450d40] width 1280 pitch 5120 (/4 1280) >[ 36804.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36804.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36804.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36804.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36804.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0f80] >[ 36804.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0f80] width 1280 pitch 5120 (/4 1280) >[ 36804.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36804.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36804.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36804.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36804.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36805.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36805.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36805.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36805.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36805.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36805.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36805.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36805.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36805.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36805.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14503b0] >[ 36805.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14503b0] width 1280 pitch 5120 (/4 1280) >[ 36805.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14baf00] >[ 36805.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14baf00] width 1280 pitch 5120 (/4 1280) >[ 36834.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c30] >[ 36834.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c30] width 1280 pitch 5120 (/4 1280) >[ 36834.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36834.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36834.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36834.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36834.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36834.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36834.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36834.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36834.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36834.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36834.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36835.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 36835.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 36835.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e965a0] >[ 36835.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e965a0] width 1280 pitch 5120 (/4 1280) >[ 36835.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36835.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36835.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36835.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36835.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36835.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36835.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36835.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36835.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36835.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36835.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36836.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36836.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36836.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36836.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36836.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36836.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b1720] >[ 36836.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b1720] width 1280 pitch 5120 (/4 1280) >[ 36836.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36836.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36836.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 36836.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 36836.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36836.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36836.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 36836.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 36836.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 36836.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 36844.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236a140] >[ 36844.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236a140] width 1280 pitch 5120 (/4 1280) >[ 36845.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bd2c0] >[ 36845.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bd2c0] width 1280 pitch 5120 (/4 1280) >[ 36845.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bd2c0] >[ 36845.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bd2c0] width 1280 pitch 5120 (/4 1280) >[ 36845.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c87f0] >[ 36845.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c87f0] width 1280 pitch 5120 (/4 1280) >[ 36848.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14b67d0] >[ 36848.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14b67d0] width 1280 pitch 5120 (/4 1280) >[ 36850.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14711c0] >[ 36850.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14711c0] width 1280 pitch 5120 (/4 1280) >[ 36856.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db6440] >[ 36856.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db6440] width 1280 pitch 5120 (/4 1280) >[ 36865.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbbd70] >[ 36865.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbbd70] width 1280 pitch 5120 (/4 1280) >[ 36882.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10039d0] >[ 36882.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10039d0] width 1280 pitch 5120 (/4 1280) >[ 36882.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc1c20] >[ 36882.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc1c20] width 1280 pitch 5120 (/4 1280) >[ 36882.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aec50] >[ 36882.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aec50] width 1280 pitch 5120 (/4 1280) >[ 36882.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc0020] >[ 36882.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc0020] width 1280 pitch 5120 (/4 1280) >[ 36882.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236a1a0] >[ 36882.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236a1a0] width 1280 pitch 5120 (/4 1280) >[ 36882.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372e70] >[ 36882.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372e70] width 1280 pitch 5120 (/4 1280) >[ 36882.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b5c0] >[ 36882.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b5c0] width 1280 pitch 5120 (/4 1280) >[ 36882.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aec50] >[ 36882.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aec50] width 1280 pitch 5120 (/4 1280) >[ 36882.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc1c20] >[ 36882.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc1c20] width 1280 pitch 5120 (/4 1280) >[ 36882.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aec50] >[ 36882.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aec50] width 1280 pitch 5120 (/4 1280) >[ 36882.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc1c20] >[ 36882.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc1c20] width 1280 pitch 5120 (/4 1280) >[ 36882.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aebf0] >[ 36882.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aebf0] width 1280 pitch 5120 (/4 1280) >[ 36882.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x130e310] >[ 36882.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x130e310] width 1280 pitch 5120 (/4 1280) >[ 36882.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aebf0] >[ 36882.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aebf0] width 1280 pitch 5120 (/4 1280) >[ 37274.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4530] >[ 37275.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4530] width 1280 pitch 5120 (/4 1280) >[ 37275.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37275.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37294.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 37294.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 37294.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b92b0] >[ 37294.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b92b0] width 1280 pitch 5120 (/4 1280) >[ 37294.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c3e80] >[ 37294.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c3e80] width 1280 pitch 5120 (/4 1280) >[ 37294.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504880] >[ 37294.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504880] width 1280 pitch 5120 (/4 1280) >[ 37294.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c5a30] >[ 37294.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c5a30] width 1280 pitch 5120 (/4 1280) >[ 37294.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c16b0] >[ 37294.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c16b0] width 1280 pitch 5120 (/4 1280) >[ 37294.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149adc0] >[ 37294.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149adc0] width 1280 pitch 5120 (/4 1280) >[ 37294.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c99d0] >[ 37294.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c99d0] width 1280 pitch 5120 (/4 1280) >[ 37294.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235e2e0] >[ 37294.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235e2e0] width 1280 pitch 5120 (/4 1280) >[ 37294.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149b300] >[ 37294.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149b300] width 1280 pitch 5120 (/4 1280) >[ 37294.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0280] >[ 37294.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0280] width 1280 pitch 5120 (/4 1280) >[ 37294.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 37294.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 37294.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37294.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37294.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 37294.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 37294.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37294.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37294.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 37294.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 37294.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbf770] >[ 37294.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbf770] width 1280 pitch 5120 (/4 1280) >[ 37294.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b5560] >[ 37294.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b5560] width 1280 pitch 5120 (/4 1280) >[ 37294.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbf770] >[ 37294.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbf770] width 1280 pitch 5120 (/4 1280) >[ 37295.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x139b030] >[ 37295.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x139b030] width 1280 pitch 5120 (/4 1280) >[ 37295.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1396710] >[ 37295.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1396710] width 1280 pitch 5120 (/4 1280) >[ 37295.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1395870] >[ 37295.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1395870] width 1280 pitch 5120 (/4 1280) >[ 37295.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c87f0] >[ 37295.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c87f0] width 1280 pitch 5120 (/4 1280) >[ 37295.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1395870] >[ 37295.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1395870] width 1280 pitch 5120 (/4 1280) >[ 37295.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c87f0] >[ 37295.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c87f0] width 1280 pitch 5120 (/4 1280) >[ 37295.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bfe60] >[ 37295.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bfe60] width 1280 pitch 5120 (/4 1280) >[ 37295.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c87f0] >[ 37295.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c87f0] width 1280 pitch 5120 (/4 1280) >[ 37295.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbceb0] >[ 37295.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbceb0] width 1280 pitch 5120 (/4 1280) >[ 37295.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399b50] >[ 37295.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399b50] width 1280 pitch 5120 (/4 1280) >[ 37296.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504970] >[ 37296.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504970] width 1280 pitch 5120 (/4 1280) >[ 37296.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bed20] >[ 37296.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bed20] width 1280 pitch 5120 (/4 1280) >[ 37296.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b9220] >[ 37296.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b9220] width 1280 pitch 5120 (/4 1280) >[ 37296.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ca600] >[ 37296.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ca600] width 1280 pitch 5120 (/4 1280) >[ 37296.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c77a0] >[ 37296.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c77a0] width 1280 pitch 5120 (/4 1280) >[ 37296.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ca600] >[ 37296.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ca600] width 1280 pitch 5120 (/4 1280) >[ 37296.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c77a0] >[ 37296.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c77a0] width 1280 pitch 5120 (/4 1280) >[ 37296.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ca600] >[ 37296.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ca600] width 1280 pitch 5120 (/4 1280) >[ 37296.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 37296.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 37296.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23715e0] >[ 37296.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23715e0] width 1280 pitch 5120 (/4 1280) >[ 37296.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ccf00] >[ 37296.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ccf00] width 1280 pitch 5120 (/4 1280) >[ 37296.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23715e0] >[ 37296.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23715e0] width 1280 pitch 5120 (/4 1280) >[ 37296.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a4420] >[ 37296.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a4420] width 1280 pitch 5120 (/4 1280) >[ 37296.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b47c0] >[ 37296.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b47c0] width 1280 pitch 5120 (/4 1280) >[ 37296.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b92b0] >[ 37296.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b92b0] width 1280 pitch 5120 (/4 1280) >[ 37296.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b47c0] >[ 37296.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b47c0] width 1280 pitch 5120 (/4 1280) >[ 37296.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c3e80] >[ 37296.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c3e80] width 1280 pitch 5120 (/4 1280) >[ 37296.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1499ab0] >[ 37296.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1499ab0] width 1280 pitch 5120 (/4 1280) >[ 37297.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c49d0] >[ 37297.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c49d0] width 1280 pitch 5120 (/4 1280) >[ 37297.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1396520] >[ 37297.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1396520] width 1280 pitch 5120 (/4 1280) >[ 37297.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149ba70] >[ 37297.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149ba70] width 1280 pitch 5120 (/4 1280) >[ 37297.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1396520] >[ 37297.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1396520] width 1280 pitch 5120 (/4 1280) >[ 37297.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235e2e0] >[ 37297.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235e2e0] width 1280 pitch 5120 (/4 1280) >[ 37297.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c99d0] >[ 37297.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c99d0] width 1280 pitch 5120 (/4 1280) >[ 37298.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c29a0] >[ 37298.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c29a0] width 1280 pitch 5120 (/4 1280) >[ 37298.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c29a0] >[ 37298.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c29a0] width 1280 pitch 5120 (/4 1280) >[ 37298.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 37298.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 37298.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14951e0] >[ 37298.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14951e0] width 1280 pitch 5120 (/4 1280) >[ 37298.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37298.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37298.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37298.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37298.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1495570] >[ 37298.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1495570] width 1280 pitch 5120 (/4 1280) >[ 37298.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37298.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37299.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbf770] >[ 37299.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbf770] width 1280 pitch 5120 (/4 1280) >[ 37299.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae6c0] >[ 37299.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae6c0] width 1280 pitch 5120 (/4 1280) >[ 37299.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1396710] >[ 37299.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1396710] width 1280 pitch 5120 (/4 1280) >[ 37299.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1395870] >[ 37299.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1395870] width 1280 pitch 5120 (/4 1280) >[ 37299.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bfe60] >[ 37299.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bfe60] width 1280 pitch 5120 (/4 1280) >[ 37299.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea0b40] >[ 37299.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea0b40] width 1280 pitch 5120 (/4 1280) >[ 37299.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7370] >[ 37299.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7370] width 1280 pitch 5120 (/4 1280) >[ 37299.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x139b030] >[ 37299.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x139b030] width 1280 pitch 5120 (/4 1280) >[ 37299.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236b070] >[ 37299.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236b070] width 1280 pitch 5120 (/4 1280) >[ 37299.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2359fa0] >[ 37299.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2359fa0] width 1280 pitch 5120 (/4 1280) >[ 37299.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e70b20] >[ 37299.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e70b20] width 1280 pitch 5120 (/4 1280) >[ 37303.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ad580] >[ 37303.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ad580] width 1280 pitch 5120 (/4 1280) >[ 37303.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b660] >[ 37303.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b660] width 1280 pitch 5120 (/4 1280) >[ 37304.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37304.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37304.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b660] >[ 37304.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b660] width 1280 pitch 5120 (/4 1280) >[ 37305.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aca70] >[ 37305.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aca70] width 1280 pitch 5120 (/4 1280) >[ 37305.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ac6d0] >[ 37305.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ac6d0] width 1280 pitch 5120 (/4 1280) >[ 37305.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ac6d0] >[ 37305.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ac6d0] width 1280 pitch 5120 (/4 1280) >[ 37305.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ac6d0] >[ 37305.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ac6d0] width 1280 pitch 5120 (/4 1280) >[ 37305.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aca70] >[ 37305.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aca70] width 1280 pitch 5120 (/4 1280) >[ 37305.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ac6d0] >[ 37305.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ac6d0] width 1280 pitch 5120 (/4 1280) >[ 37305.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ac6d0] >[ 37305.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ac6d0] width 1280 pitch 5120 (/4 1280) >[ 37305.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37305.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19cb370] >[ 37305.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19cb370] width 1280 pitch 5120 (/4 1280) >[ 37305.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37305.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37306.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d86370] >[ 37306.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d86370] width 1280 pitch 5120 (/4 1280) >[ 37540.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14fa130] >[ 37540.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14fa130] width 1280 pitch 5120 (/4 1280) >[ 37540.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1261580] >[ 37540.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1261580] width 1280 pitch 5120 (/4 1280) >[ 37540.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14fa130] >[ 37540.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14fa130] width 1280 pitch 5120 (/4 1280) >[ 37540.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1261580] >[ 37540.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1261580] width 1280 pitch 5120 (/4 1280) >[ 37540.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14fa130] >[ 37540.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14fa130] width 1280 pitch 5120 (/4 1280) >[ 37540.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1261580] >[ 37540.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1261580] width 1280 pitch 5120 (/4 1280) >[ 37540.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 37540.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 37541.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f6d00] >[ 37541.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f6d00] width 1280 pitch 5120 (/4 1280) >[ 37541.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 37542.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 37542.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f6d00] >[ 37542.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f6d00] width 1280 pitch 5120 (/4 1280) >[ 37542.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f85c0] >[ 37542.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f85c0] width 1280 pitch 5120 (/4 1280) >[ 37543.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147a100] >[ 37543.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147a100] width 1280 pitch 5120 (/4 1280) >[ 37543.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147a100] >[ 37543.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147a100] width 1280 pitch 5120 (/4 1280) >[ 37543.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc7e90] >[ 37543.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc7e90] width 1280 pitch 5120 (/4 1280) >[ 37543.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d7510] >[ 37543.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d7510] width 1280 pitch 5120 (/4 1280) >[ 37543.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc7e90] >[ 37543.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc7e90] width 1280 pitch 5120 (/4 1280) >[ 37543.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d7510] >[ 37543.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d7510] width 1280 pitch 5120 (/4 1280) >[ 37544.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147a100] >[ 37544.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147a100] width 1280 pitch 5120 (/4 1280) >[ 37545.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e0350] >[ 37545.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e0350] width 1280 pitch 5120 (/4 1280) >[ 37545.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f6d00] >[ 37545.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f6d00] width 1280 pitch 5120 (/4 1280) >[ 37733.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d7780] >[ 37733.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d7780] width 1280 pitch 5120 (/4 1280) >[ 37733.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a9fe0] >[ 37733.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a9fe0] width 1280 pitch 5120 (/4 1280) >[ 37733.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d7780] >[ 37733.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d7780] width 1280 pitch 5120 (/4 1280) >[ 37734.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1d40] >[ 37734.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1d40] width 1280 pitch 5120 (/4 1280) >[ 37734.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[ 37734.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[ 37734.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef4a0] >[ 37734.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef4a0] width 1280 pitch 5120 (/4 1280) >[ 37734.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[ 37734.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[ 37734.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef4a0] >[ 37735.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef4a0] width 1280 pitch 5120 (/4 1280) >[ 37735.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[ 37735.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[ 37735.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef4a0] >[ 37735.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef4a0] width 1280 pitch 5120 (/4 1280) >[ 37735.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[ 37735.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[ 37736.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef4a0] >[ 37736.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef4a0] width 1280 pitch 5120 (/4 1280) >[ 37736.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[ 37736.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[ 37736.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147a100] >[ 37736.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147a100] width 1280 pitch 5120 (/4 1280) >[ 37736.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1175ad0] >[ 37736.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1175ad0] width 1280 pitch 5120 (/4 1280) >[ 37736.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf1210] >[ 37736.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf1210] width 1280 pitch 5120 (/4 1280) >[ 37736.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1175ad0] >[ 37736.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1175ad0] width 1280 pitch 5120 (/4 1280) >[ 37736.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf1210] >[ 37736.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf1210] width 1280 pitch 5120 (/4 1280) >[ 37736.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1992cf0] >[ 37736.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1992cf0] width 1280 pitch 5120 (/4 1280) >[ 37737.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14776e0] >[ 37737.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14776e0] width 1280 pitch 5120 (/4 1280) >[ 37737.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a3400] >[ 37737.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a3400] width 1280 pitch 5120 (/4 1280) >[ 37737.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e48a90] >[ 37737.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e48a90] width 1280 pitch 5120 (/4 1280) >[ 37737.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e48b70] >[ 37737.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e48b70] width 1280 pitch 5120 (/4 1280) >[ 37737.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 37738.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 37738.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e48b70] >[ 37738.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e48b70] width 1280 pitch 5120 (/4 1280) >[ 37738.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 37738.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 37738.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e48b70] >[ 37738.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e48b70] width 1280 pitch 5120 (/4 1280) >[ 37738.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c83780] >[ 37738.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c83780] width 1280 pitch 5120 (/4 1280) >[ 37738.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f00cc0] >[ 37738.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f00cc0] width 1280 pitch 5120 (/4 1280) >[ 37739.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a9d70] >[ 37739.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a9d70] width 1280 pitch 5120 (/4 1280) >[ 37739.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a9d70] >[ 37739.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a9d70] width 1280 pitch 5120 (/4 1280) >[ 37739.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1452a50] >[ 37739.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1452a50] width 1280 pitch 5120 (/4 1280) >[ 37739.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a9d70] >[ 37739.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a9d70] width 1280 pitch 5120 (/4 1280) >[ 37739.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1452a50] >[ 37739.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1452a50] width 1280 pitch 5120 (/4 1280) >[ 37742.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1476be0] >[ 37742.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1476be0] width 1280 pitch 5120 (/4 1280) >[ 37742.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9900] >[ 37742.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9900] width 1280 pitch 5120 (/4 1280) >[ 37742.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1476be0] >[ 37742.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1476be0] width 1280 pitch 5120 (/4 1280) >[ 37742.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9900] >[ 37742.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9900] width 1280 pitch 5120 (/4 1280) >[ 37742.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1476be0] >[ 37742.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1476be0] width 1280 pitch 5120 (/4 1280) >[ 37742.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d42d80] >[ 37742.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d42d80] width 1280 pitch 5120 (/4 1280) >[ 37744.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5b400] >[ 37744.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5b400] width 1280 pitch 5120 (/4 1280) >[ 37744.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abe710] >[ 37744.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abe710] width 1280 pitch 5120 (/4 1280) >[ 37744.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5b300] >[ 37744.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5b300] width 1280 pitch 5120 (/4 1280) >[ 37744.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abe6f0] >[ 37744.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abe6f0] width 1280 pitch 5120 (/4 1280) >[ 37744.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240e5c0] >[ 37744.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240e5c0] width 1280 pitch 5120 (/4 1280) >[ 37744.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98100] >[ 37744.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98100] width 1280 pitch 5120 (/4 1280) >[ 37744.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abe6f0] >[ 37744.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abe6f0] width 1280 pitch 5120 (/4 1280) >[ 37744.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5b450] >[ 37744.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5b450] width 1280 pitch 5120 (/4 1280) >[ 37744.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abe6f0] >[ 37744.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abe6f0] width 1280 pitch 5120 (/4 1280) >[ 37744.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502a30] >[ 37744.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502a30] width 1280 pitch 5120 (/4 1280) >[ 37744.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24572a0] >[ 37744.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24572a0] width 1280 pitch 5120 (/4 1280) >[ 37744.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502a30] >[ 37744.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502a30] width 1280 pitch 5120 (/4 1280) >[ 37749.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a6c30] >[ 37749.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a6c30] width 1280 pitch 5120 (/4 1280) >[ 37749.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37749.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37749.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1505aa0] >[ 37749.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1505aa0] width 1280 pitch 5120 (/4 1280) >[ 37749.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1424c90] >[ 37749.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1424c90] width 1280 pitch 5120 (/4 1280) >[ 37749.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461100] >[ 37749.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461100] width 1280 pitch 5120 (/4 1280) >[ 37749.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13485d0] >[ 37749.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13485d0] width 1280 pitch 5120 (/4 1280) >[ 37749.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7f920] >[ 37749.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7f920] width 1280 pitch 5120 (/4 1280) >[ 37749.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131f880] >[ 37749.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131f880] width 1280 pitch 5120 (/4 1280) >[ 37749.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502a30] >[ 37749.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502a30] width 1280 pitch 5120 (/4 1280) >[ 37749.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1333cd0] >[ 37749.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1333cd0] width 1280 pitch 5120 (/4 1280) >[ 37749.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a6c30] >[ 37749.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a6c30] width 1280 pitch 5120 (/4 1280) >[ 37749.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37749.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37749.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea1030] >[ 37749.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea1030] width 1280 pitch 5120 (/4 1280) >[ 37749.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac250] >[ 37749.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac250] width 1280 pitch 5120 (/4 1280) >[ 37750.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37750.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37750.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 37750.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 37750.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 37751.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 37826.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23814c0] >[ 37826.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23814c0] width 1280 pitch 5120 (/4 1280) >[ 37826.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23814c0] >[ 37826.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23814c0] width 1280 pitch 5120 (/4 1280) >[ 37967.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484610] >[ 37967.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484610] width 1280 pitch 5120 (/4 1280) >[ 37967.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9d220] >[ 37967.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9d220] width 1280 pitch 5120 (/4 1280) >[ 37975.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9d220] >[ 37975.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9d220] width 1280 pitch 5120 (/4 1280) >[ 37975.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea8060] >[ 37975.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea8060] width 1280 pitch 5120 (/4 1280) >[ 37975.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1367a10] >[ 37975.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1367a10] width 1280 pitch 5120 (/4 1280) >[ 37975.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea8060] >[ 37975.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea8060] width 1280 pitch 5120 (/4 1280) >[ 37975.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1367a10] >[ 37975.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1367a10] width 1280 pitch 5120 (/4 1280) >[ 37976.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a26000] >[ 37976.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a26000] width 1280 pitch 5120 (/4 1280) >[ 37978.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa67c0] >[ 37978.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa67c0] width 1280 pitch 5120 (/4 1280) >[ 38578.250] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 38578.250] (II) RADEON(0): Printing DDC gathered Modelines: >[ 38578.250] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 38668.888] (II) RADEON(0): RADEONSaveScreen(2) >[ 38668.888] (II) RADEON(0): RADEONSaveScreen(0) >[ 38840.153] (II) RADEON(0): RADEONSaveScreen(1) >[ 38845.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0e420] >[ 38845.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0e420] width 1280 pitch 5120 (/4 1280) >[ 38846.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38846.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38848.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d019c0] >[ 38848.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d019c0] width 1280 pitch 5120 (/4 1280) >[ 38848.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1368ee0] >[ 38848.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1368ee0] width 1280 pitch 5120 (/4 1280) >[ 38848.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13bce60] >[ 38848.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13bce60] width 1280 pitch 5120 (/4 1280) >[ 38864.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240fa00] >[ 38864.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240fa00] width 1280 pitch 5120 (/4 1280) >[ 38864.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240fa00] >[ 38864.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240fa00] width 1280 pitch 5120 (/4 1280) >[ 38864.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1163bf0] >[ 38864.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1163bf0] width 1280 pitch 5120 (/4 1280) >[ 38864.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x150f600] >[ 38864.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x150f600] width 1280 pitch 5120 (/4 1280) >[ 38865.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 38865.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 38868.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38868.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38868.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44910] >[ 38868.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44910] width 1280 pitch 5120 (/4 1280) >[ 38868.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240fa00] >[ 38868.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240fa00] width 1280 pitch 5120 (/4 1280) >[ 38869.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 38869.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 38869.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 38869.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 38869.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea1030] >[ 38869.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea1030] width 1280 pitch 5120 (/4 1280) >[ 38869.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2364e80] >[ 38869.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2364e80] width 1280 pitch 5120 (/4 1280) >[ 38869.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11398b0] >[ 38869.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11398b0] width 1280 pitch 5120 (/4 1280) >[ 38905.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38905.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38905.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e64eb0] >[ 38905.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e64eb0] width 1280 pitch 5120 (/4 1280) >[ 38905.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38905.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38905.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e64eb0] >[ 38905.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e64eb0] width 1280 pitch 5120 (/4 1280) >[ 38905.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38905.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38905.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e64eb0] >[ 38905.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e64eb0] width 1280 pitch 5120 (/4 1280) >[ 38905.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38905.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38905.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e64eb0] >[ 38905.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e64eb0] width 1280 pitch 5120 (/4 1280) >[ 38905.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38905.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38906.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead410] >[ 38906.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead410] width 1280 pitch 5120 (/4 1280) >[ 38906.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484610] >[ 38906.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484610] width 1280 pitch 5120 (/4 1280) >[ 38906.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1484610] >[ 38906.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1484610] width 1280 pitch 5120 (/4 1280) >[ 38906.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240e6c0] >[ 38906.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240e6c0] width 1280 pitch 5120 (/4 1280) >[ 38906.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240e6c0] >[ 38906.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240e6c0] width 1280 pitch 5120 (/4 1280) >[ 38906.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240e6c0] >[ 38906.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240e6c0] width 1280 pitch 5120 (/4 1280) >[ 38906.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38906.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240e6c0] >[ 38906.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240e6c0] width 1280 pitch 5120 (/4 1280) >[ 38906.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[ 38906.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[ 38907.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38907.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38907.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38907.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125aee0] >[ 38907.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125aee0] width 1280 pitch 5120 (/4 1280) >[ 38908.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1989c30] >[ 38908.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1989c30] width 1280 pitch 5120 (/4 1280) >[ 38908.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2467df0] >[ 38908.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2467df0] width 1280 pitch 5120 (/4 1280) >[ 38908.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38908.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38908.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38908.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38908.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38908.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38908.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38908.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38908.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38909.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38909.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38909.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38909.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38913.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5c30] >[ 38913.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5c30] width 1280 pitch 5120 (/4 1280) >[ 38913.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11398b0] >[ 38913.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11398b0] width 1280 pitch 5120 (/4 1280) >[ 38913.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5c30] >[ 38914.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5c30] width 1280 pitch 5120 (/4 1280) >[ 38914.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11398b0] >[ 38914.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11398b0] width 1280 pitch 5120 (/4 1280) >[ 38914.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1367ee0] >[ 38914.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1367ee0] width 1280 pitch 5120 (/4 1280) >[ 38915.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea8060] >[ 38915.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea8060] width 1280 pitch 5120 (/4 1280) >[ 38915.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38915.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38915.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38915.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38915.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38916.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38916.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38916.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38916.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38916.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38916.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f490] >[ 38916.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f490] width 1280 pitch 5120 (/4 1280) >[ 38916.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38916.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38926.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 38926.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 38926.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea8060] >[ 38926.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea8060] width 1280 pitch 5120 (/4 1280) >[ 38927.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14aa7a0] >[ 38927.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14aa7a0] width 1280 pitch 5120 (/4 1280) >[ 38927.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 38927.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 38927.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14aa7a0] >[ 38927.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14aa7a0] width 1280 pitch 5120 (/4 1280) >[ 38927.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 38927.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 38927.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14aa7a0] >[ 38927.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14aa7a0] width 1280 pitch 5120 (/4 1280) >[ 38927.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 38927.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 38927.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14aa7a0] >[ 38928.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14aa7a0] width 1280 pitch 5120 (/4 1280) >[ 38928.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 38928.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 38928.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[ 38928.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[ 38928.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 38928.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 38929.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 38929.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 38929.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7f920] >[ 38929.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7f920] width 1280 pitch 5120 (/4 1280) >[ 38929.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e41240] >[ 38929.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e41240] width 1280 pitch 5120 (/4 1280) >[ 38929.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7f920] >[ 38929.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7f920] width 1280 pitch 5120 (/4 1280) >[ 38929.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e41240] >[ 38929.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e41240] width 1280 pitch 5120 (/4 1280) >[ 38929.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7f920] >[ 38929.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7f920] width 1280 pitch 5120 (/4 1280) >[ 38929.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4b7a0] >[ 38929.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4b7a0] width 1280 pitch 5120 (/4 1280) >[ 38950.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[ 38950.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[ 38950.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 38950.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 38950.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[ 38950.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[ 38950.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 38950.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 38950.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[ 38950.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[ 38950.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 38950.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 38950.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[ 38950.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[ 38950.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 38950.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 38950.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[ 38950.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[ 38950.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b305a0] >[ 38950.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b305a0] width 1280 pitch 5120 (/4 1280) >[ 38950.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1d70] >[ 38950.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1d70] width 1280 pitch 5120 (/4 1280) >[ 38950.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38950.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38950.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1d70] >[ 38950.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1d70] width 1280 pitch 5120 (/4 1280) >[ 38950.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3b30] >[ 38950.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3b30] width 1280 pitch 5120 (/4 1280) >[ 38951.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a4ab0] >[ 38951.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a4ab0] width 1280 pitch 5120 (/4 1280) >[ 38951.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1263950] >[ 38951.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1263950] width 1280 pitch 5120 (/4 1280) >[ 38951.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c922b0] >[ 38951.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c922b0] width 1280 pitch 5120 (/4 1280) >[ 38951.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e5d50] >[ 38951.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e5d50] width 1280 pitch 5120 (/4 1280) >[ 38951.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a29f30] >[ 38951.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a29f30] width 1280 pitch 5120 (/4 1280) >[ 38951.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a7f920] >[ 38951.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a7f920] width 1280 pitch 5120 (/4 1280) >[ 38951.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131aee0] >[ 38951.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131aee0] width 1280 pitch 5120 (/4 1280) >[ 38951.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38951.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38951.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131aee0] >[ 38951.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131aee0] width 1280 pitch 5120 (/4 1280) >[ 38951.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38951.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38951.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131aee0] >[ 38951.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131aee0] width 1280 pitch 5120 (/4 1280) >[ 38951.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38951.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38951.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13134e0] >[ 38951.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13134e0] width 1280 pitch 5120 (/4 1280) >[ 38951.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38952.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38952.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13134e0] >[ 38952.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13134e0] width 1280 pitch 5120 (/4 1280) >[ 38952.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38952.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38952.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13134e0] >[ 38952.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13134e0] width 1280 pitch 5120 (/4 1280) >[ 38952.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142f540] >[ 38952.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142f540] width 1280 pitch 5120 (/4 1280) >[ 38952.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38952.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38952.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38952.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38952.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38952.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2468a50] >[ 38952.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2468a50] width 1280 pitch 5120 (/4 1280) >[ 38952.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[ 38952.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[ 38953.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b46c10] >[ 38953.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b46c10] width 1280 pitch 5120 (/4 1280) >[ 38953.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9ffa0] >[ 38953.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9ffa0] width 1280 pitch 5120 (/4 1280) >[ 38954.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9ffa0] >[ 38954.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9ffa0] width 1280 pitch 5120 (/4 1280) >[ 38954.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9ffa0] >[ 38954.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9ffa0] width 1280 pitch 5120 (/4 1280) >[ 38954.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afdde0] >[ 38954.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afdde0] width 1280 pitch 5120 (/4 1280) >[ 38954.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afdca0] >[ 38954.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afdca0] width 1280 pitch 5120 (/4 1280) >[ 38954.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afdca0] >[ 38954.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afdca0] width 1280 pitch 5120 (/4 1280) >[ 38954.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b468c0] >[ 38954.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b468c0] width 1280 pitch 5120 (/4 1280) >[ 38954.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afdde0] >[ 38954.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afdde0] width 1280 pitch 5120 (/4 1280) >[ 38954.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b468c0] >[ 38954.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b468c0] width 1280 pitch 5120 (/4 1280) >[ 38954.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24739b0] >[ 38954.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24739b0] width 1280 pitch 5120 (/4 1280) >[ 38954.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1494e40] >[ 38954.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1494e40] width 1280 pitch 5120 (/4 1280) >[ 38954.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38954.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38954.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1494e40] >[ 38955.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1494e40] width 1280 pitch 5120 (/4 1280) >[ 38957.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149a350] >[ 38957.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149a350] width 1280 pitch 5120 (/4 1280) >[ 38957.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 38957.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 38957.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149a350] >[ 38957.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149a350] width 1280 pitch 5120 (/4 1280) >[ 38957.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eedf0] >[ 38957.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eedf0] width 1280 pitch 5120 (/4 1280) >[ 38958.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3f380] >[ 38958.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3f380] width 1280 pitch 5120 (/4 1280) >[ 38995.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc80] >[ 38995.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc80] width 1280 pitch 5120 (/4 1280) >[ 38995.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234fa40] >[ 38995.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234fa40] width 1280 pitch 5120 (/4 1280) >[ 38995.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc80] >[ 38995.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc80] width 1280 pitch 5120 (/4 1280) >[ 38995.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234fa40] >[ 38995.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234fa40] width 1280 pitch 5120 (/4 1280) >[ 38995.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc80] >[ 38995.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc80] width 1280 pitch 5120 (/4 1280) >[ 38995.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234fa40] >[ 38995.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234fa40] width 1280 pitch 5120 (/4 1280) >[ 38995.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc80] >[ 38995.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc80] width 1280 pitch 5120 (/4 1280) >[ 38995.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234fa40] >[ 38995.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234fa40] width 1280 pitch 5120 (/4 1280) >[ 38995.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38995.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38995.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38995.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38995.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38996.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38996.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6e60] >[ 38996.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6e60] width 1280 pitch 5120 (/4 1280) >[ 38996.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38996.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38996.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ac1e0] >[ 38996.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ac1e0] width 1280 pitch 5120 (/4 1280) >[ 38996.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38996.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38996.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ac1e0] >[ 38996.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ac1e0] width 1280 pitch 5120 (/4 1280) >[ 38996.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38996.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38996.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ac1e0] >[ 38996.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ac1e0] width 1280 pitch 5120 (/4 1280) >[ 38996.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 38996.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 38996.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234fa40] >[ 38996.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234fa40] width 1280 pitch 5120 (/4 1280) >[ 39097.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfe1a0] >[ 39097.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfe1a0] width 1280 pitch 5120 (/4 1280) >[ 39097.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c6f60] >[ 39097.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c6f60] width 1280 pitch 5120 (/4 1280) >[ 39097.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfe1a0] >[ 39097.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfe1a0] width 1280 pitch 5120 (/4 1280) >[ 39097.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c6f60] >[ 39097.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c6f60] width 1280 pitch 5120 (/4 1280) >[ 39097.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfe1a0] >[ 39097.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfe1a0] width 1280 pitch 5120 (/4 1280) >[ 39097.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c6f60] >[ 39097.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c6f60] width 1280 pitch 5120 (/4 1280) >[ 39097.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 39097.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 39097.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2469030] >[ 39097.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2469030] width 1280 pitch 5120 (/4 1280) >[ 39097.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39097.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39097.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1509a70] >[ 39097.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1509a70] width 1280 pitch 5120 (/4 1280) >[ 39098.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 39098.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 39098.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 39098.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 39098.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 39098.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 39098.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 39098.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 39098.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 39098.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 39098.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 39098.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 39098.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 39098.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 39098.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b9d90] >[ 39098.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b9d90] width 1280 pitch 5120 (/4 1280) >[ 39098.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5ee70] >[ 39098.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5ee70] width 1280 pitch 5120 (/4 1280) >[ 39099.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39099.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39099.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e0ac0] >[ 39099.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e0ac0] width 1280 pitch 5120 (/4 1280) >[ 39099.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39099.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39099.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e0ac0] >[ 39099.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e0ac0] width 1280 pitch 5120 (/4 1280) >[ 39099.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39099.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39099.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e0ac0] >[ 39099.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e0ac0] width 1280 pitch 5120 (/4 1280) >[ 39099.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39099.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39099.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e0ac0] >[ 39099.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e0ac0] width 1280 pitch 5120 (/4 1280) >[ 39099.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478240] >[ 39099.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478240] width 1280 pitch 5120 (/4 1280) >[ 39099.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfe1a0] >[ 39099.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfe1a0] width 1280 pitch 5120 (/4 1280) >[ 39099.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1509a70] >[ 39099.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1509a70] width 1280 pitch 5120 (/4 1280) >[ 39100.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19443f0] >[ 39100.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19443f0] width 1280 pitch 5120 (/4 1280) >[ 39100.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2469030] >[ 39100.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2469030] width 1280 pitch 5120 (/4 1280) >[ 39100.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3ca70] >[ 39100.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3ca70] width 1280 pitch 5120 (/4 1280) >[ 39100.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfe370] >[ 39100.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfe370] width 1280 pitch 5120 (/4 1280) >[ 39100.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19443f0] >[ 39100.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19443f0] width 1280 pitch 5120 (/4 1280) >[ 39100.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12c50e0] >[ 39100.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12c50e0] width 1280 pitch 5120 (/4 1280) >[ 39100.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1367a10] >[ 39100.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1367a10] width 1280 pitch 5120 (/4 1280) >[ 39100.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13badc0] >[ 39100.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13badc0] width 1280 pitch 5120 (/4 1280) >[ 39100.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0f70] >[ 39100.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0f70] width 1280 pitch 5120 (/4 1280) >[ 39100.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13badc0] >[ 39100.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13badc0] width 1280 pitch 5120 (/4 1280) >[ 39100.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 39100.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 39100.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 39100.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 39100.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 39100.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 39100.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 39100.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 39100.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b44340] >[ 39101.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b44340] width 1280 pitch 5120 (/4 1280) >[ 39101.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffb10] >[ 39101.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffb10] width 1280 pitch 5120 (/4 1280) >[ 39101.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39101.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39101.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131e900] >[ 39101.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131e900] width 1280 pitch 5120 (/4 1280) >[ 39101.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39101.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39101.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131e900] >[ 39101.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131e900] width 1280 pitch 5120 (/4 1280) >[ 39101.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39101.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39101.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39101.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9b480] >[ 39106.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9b480] width 1280 pitch 5120 (/4 1280) >[ 39106.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9b480] >[ 39106.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9b480] width 1280 pitch 5120 (/4 1280) >[ 39106.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9b480] >[ 39106.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9b480] width 1280 pitch 5120 (/4 1280) >[ 39106.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d12b0] >[ 39106.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d12b0] width 1280 pitch 5120 (/4 1280) >[ 39106.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aed0] >[ 39106.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aed0] width 1280 pitch 5120 (/4 1280) >[ 39106.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aed0] >[ 39106.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aed0] width 1280 pitch 5120 (/4 1280) >[ 39106.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39106.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39106.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39106.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39106.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39106.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39106.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39106.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39106.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39106.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39106.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39106.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39106.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aed0] >[ 39107.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aed0] width 1280 pitch 5120 (/4 1280) >[ 39107.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39107.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39107.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39107.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39107.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39107.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39107.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39107.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39107.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc780] >[ 39107.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc780] width 1280 pitch 5120 (/4 1280) >[ 39107.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d12b0] >[ 39107.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d12b0] width 1280 pitch 5120 (/4 1280) >[ 39107.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aed0] >[ 39107.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aed0] width 1280 pitch 5120 (/4 1280) >[ 39107.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d12b0] >[ 39107.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d12b0] width 1280 pitch 5120 (/4 1280) >[ 39108.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9b480] >[ 39108.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9b480] width 1280 pitch 5120 (/4 1280) >[ 39108.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39108.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39108.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a1db0] >[ 39108.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a1db0] width 1280 pitch 5120 (/4 1280) >[ 39108.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fb580] >[ 39108.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fb580] width 1280 pitch 5120 (/4 1280) >[ 39108.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aa5b0] >[ 39108.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aa5b0] width 1280 pitch 5120 (/4 1280) >[ 39108.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fb580] >[ 39108.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fb580] width 1280 pitch 5120 (/4 1280) >[ 39108.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aa5b0] >[ 39108.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aa5b0] width 1280 pitch 5120 (/4 1280) >[ 39108.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fb580] >[ 39108.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fb580] width 1280 pitch 5120 (/4 1280) >[ 39108.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aa5b0] >[ 39108.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aa5b0] width 1280 pitch 5120 (/4 1280) >[ 39108.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fb580] >[ 39108.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fb580] width 1280 pitch 5120 (/4 1280) >[ 39108.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aa5b0] >[ 39108.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aa5b0] width 1280 pitch 5120 (/4 1280) >[ 39108.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39108.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39108.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134a9b0] >[ 39108.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134a9b0] width 1280 pitch 5120 (/4 1280) >[ 39108.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39108.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39108.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134a9b0] >[ 39108.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134a9b0] width 1280 pitch 5120 (/4 1280) >[ 39108.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39108.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39108.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134a9b0] >[ 39108.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134a9b0] width 1280 pitch 5120 (/4 1280) >[ 39109.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134a9b0] >[ 39109.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134a9b0] width 1280 pitch 5120 (/4 1280) >[ 39109.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39109.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39109.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39109.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39109.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39109.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39109.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39109.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0980] >[ 39109.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0980] width 1280 pitch 5120 (/4 1280) >[ 39119.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44e00] >[ 39119.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44e00] width 1280 pitch 5120 (/4 1280) >[ 39338.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c8b80] >[ 39338.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c8b80] width 1280 pitch 5120 (/4 1280) >[ 39338.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1333d50] >[ 39338.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1333d50] width 1280 pitch 5120 (/4 1280) >[ 39339.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c8b80] >[ 39339.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c8b80] width 1280 pitch 5120 (/4 1280) >[ 39339.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a52680] >[ 39339.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a52680] width 1280 pitch 5120 (/4 1280) >[ 39339.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9b480] >[ 39339.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9b480] width 1280 pitch 5120 (/4 1280) >[ 39339.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1333d50] >[ 39339.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1333d50] width 1280 pitch 5120 (/4 1280) >[ 39339.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d32ab0] >[ 39339.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d32ab0] width 1280 pitch 5120 (/4 1280) >[ 39340.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f23d0] >[ 39340.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f23d0] width 1280 pitch 5120 (/4 1280) >[ 39340.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecc870] >[ 39340.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecc870] width 1280 pitch 5120 (/4 1280) >[ 39340.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c71300] >[ 39340.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c71300] width 1280 pitch 5120 (/4 1280) >[ 39346.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f23d0] >[ 39346.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f23d0] width 1280 pitch 5120 (/4 1280) >[ 39346.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10661b0] >[ 39346.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10661b0] width 1280 pitch 5120 (/4 1280) >[ 39347.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ddd60] >[ 39347.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ddd60] width 1280 pitch 5120 (/4 1280) >[ 39347.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f5730] >[ 39347.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f5730] width 1280 pitch 5120 (/4 1280) >[ 39351.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127eee0] >[ 39351.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127eee0] width 1280 pitch 5120 (/4 1280) >[ 39351.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d00130] >[ 39351.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d00130] width 1280 pitch 5120 (/4 1280) >[ 39352.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[ 39352.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[ 39352.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8760] >[ 39352.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8760] width 1280 pitch 5120 (/4 1280) >[ 39354.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[ 39354.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[ 39355.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246ecc0] >[ 39355.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246ecc0] width 1280 pitch 5120 (/4 1280) >[ 39358.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af94f0] >[ 39358.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af94f0] width 1280 pitch 5120 (/4 1280) >[ 39358.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39358.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39358.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39358.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39358.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39358.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39358.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd3f0] >[ 39359.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd3f0] width 1280 pitch 5120 (/4 1280) >[ 39385.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b1710] >[ 39385.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b1710] width 1280 pitch 5120 (/4 1280) >[ 39385.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b1710] >[ 39385.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b1710] width 1280 pitch 5120 (/4 1280) >[ 39385.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2363d50] >[ 39385.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2363d50] width 1280 pitch 5120 (/4 1280) >[ 39385.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2363d50] >[ 39385.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2363d50] width 1280 pitch 5120 (/4 1280) >[ 39390.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260dd10] >[ 39390.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260dd10] width 1280 pitch 5120 (/4 1280) >[ 39390.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e69440] >[ 39390.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e69440] width 1280 pitch 5120 (/4 1280) >[ 39390.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a480] >[ 39390.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a480] width 1280 pitch 5120 (/4 1280) >[ 39390.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 39390.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 39395.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a480] >[ 39395.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a480] width 1280 pitch 5120 (/4 1280) >[ 39395.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b51640] >[ 39395.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b51640] width 1280 pitch 5120 (/4 1280) >[ 39395.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b51640] >[ 39395.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b51640] width 1280 pitch 5120 (/4 1280) >[ 39395.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b528f0] >[ 39395.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b528f0] width 1280 pitch 5120 (/4 1280) >[ 39400.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aab260] >[ 39400.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aab260] width 1280 pitch 5120 (/4 1280) >[ 39461.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1941e70] >[ 39461.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1941e70] width 1280 pitch 5120 (/4 1280) >[ 39461.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d8430] >[ 39461.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d8430] width 1280 pitch 5120 (/4 1280) >[ 39461.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b51920] >[ 39461.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b51920] width 1280 pitch 5120 (/4 1280) >[ 39461.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1941e70] >[ 39461.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1941e70] width 1280 pitch 5120 (/4 1280) >[ 39462.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246ff10] >[ 39462.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246ff10] width 1280 pitch 5120 (/4 1280) >[ 39462.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39462.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39462.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246ff10] >[ 39462.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246ff10] width 1280 pitch 5120 (/4 1280) >[ 39462.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 39462.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 39470.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f2e0] >[ 39470.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f2e0] width 1280 pitch 5120 (/4 1280) >[ 39470.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328120] >[ 39470.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328120] width 1280 pitch 5120 (/4 1280) >[ 39470.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aebb80] >[ 39470.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aebb80] width 1280 pitch 5120 (/4 1280) >[ 39470.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b51920] >[ 39470.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b51920] width 1280 pitch 5120 (/4 1280) >[ 39471.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1328120] >[ 39471.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1328120] width 1280 pitch 5120 (/4 1280) >[ 39471.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71190] >[ 39471.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71190] width 1280 pitch 5120 (/4 1280) >[ 39471.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b51920] >[ 39471.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b51920] width 1280 pitch 5120 (/4 1280) >[ 39471.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1278da0] >[ 39471.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1278da0] width 1280 pitch 5120 (/4 1280) >[ 39471.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 39471.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 39471.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b52890] >[ 39471.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b52890] width 1280 pitch 5120 (/4 1280) >[ 39471.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39471.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39471.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24571d0] >[ 39471.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24571d0] width 1280 pitch 5120 (/4 1280) >[ 39474.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaba90] >[ 39474.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaba90] width 1280 pitch 5120 (/4 1280) >[ 39474.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ebdf0] >[ 39474.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ebdf0] width 1280 pitch 5120 (/4 1280) >[ 39474.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aabe80] >[ 39474.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aabe80] width 1280 pitch 5120 (/4 1280) >[ 39474.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 39474.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 39474.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f2e0] >[ 39474.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f2e0] width 1280 pitch 5120 (/4 1280) >[ 39474.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39474.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39474.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ebdf0] >[ 39474.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ebdf0] width 1280 pitch 5120 (/4 1280) >[ 39474.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39474.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39474.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ebdf0] >[ 39474.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ebdf0] width 1280 pitch 5120 (/4 1280) >[ 39474.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aabe80] >[ 39474.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aabe80] width 1280 pitch 5120 (/4 1280) >[ 39474.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39474.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39474.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f2e0] >[ 39474.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f2e0] width 1280 pitch 5120 (/4 1280) >[ 39474.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ebdf0] >[ 39474.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ebdf0] width 1280 pitch 5120 (/4 1280) >[ 39474.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da6360] >[ 39474.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da6360] width 1280 pitch 5120 (/4 1280) >[ 39474.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13139f0] >[ 39474.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13139f0] width 1280 pitch 5120 (/4 1280) >[ 39474.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bde40] >[ 39474.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bde40] width 1280 pitch 5120 (/4 1280) >[ 39476.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f2e0] >[ 39476.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f2e0] width 1280 pitch 5120 (/4 1280) >[ 39476.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501f60] >[ 39476.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501f60] width 1280 pitch 5120 (/4 1280) >[ 39476.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14def30] >[ 39476.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14def30] width 1280 pitch 5120 (/4 1280) >[ 39476.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cce50] >[ 39476.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cce50] width 1280 pitch 5120 (/4 1280) >[ 39477.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f81e0] >[ 39477.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f81e0] width 1280 pitch 5120 (/4 1280) >[ 39477.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1660] >[ 39477.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1660] width 1280 pitch 5120 (/4 1280) >[ 39481.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1505aa0] >[ 39481.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1505aa0] width 1280 pitch 5120 (/4 1280) >[ 39481.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa9cc0] >[ 39481.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa9cc0] width 1280 pitch 5120 (/4 1280) >[ 39482.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 39482.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 39483.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14def50] >[ 39483.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14def50] width 1280 pitch 5120 (/4 1280) >[ 39483.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128b3f0] >[ 39483.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128b3f0] width 1280 pitch 5120 (/4 1280) >[ 39483.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147f2e0] >[ 39483.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147f2e0] width 1280 pitch 5120 (/4 1280) >[ 39484.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19b4730] >[ 39484.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19b4730] width 1280 pitch 5120 (/4 1280) >[ 39485.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 39485.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 39485.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a99f0] >[ 39485.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a99f0] width 1280 pitch 5120 (/4 1280) >[ 39485.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a99f0] >[ 39485.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a99f0] width 1280 pitch 5120 (/4 1280) >[ 39985.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1237000] >[ 39985.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1237000] width 1280 pitch 5120 (/4 1280) >[ 39987.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1970fe0] >[ 39987.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1970fe0] width 1280 pitch 5120 (/4 1280) >[ 39987.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127b460] >[ 39987.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127b460] width 1280 pitch 5120 (/4 1280) >[ 39987.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3ab10] >[ 39987.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3ab10] width 1280 pitch 5120 (/4 1280) >[ 39987.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1237000] >[ 39987.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1237000] width 1280 pitch 5120 (/4 1280) >[ 39989.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231450] >[ 39989.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231450] width 1280 pitch 5120 (/4 1280) >[ 39989.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24571d0] >[ 39989.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24571d0] width 1280 pitch 5120 (/4 1280) >[ 39989.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3ab10] >[ 39989.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3ab10] width 1280 pitch 5120 (/4 1280) >[ 40001.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246b560] >[ 40001.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246b560] width 1280 pitch 5120 (/4 1280) >[ 40003.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312650] >[ 40003.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312650] width 1280 pitch 5120 (/4 1280) >[ 40003.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b52890] >[ 40003.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b52890] width 1280 pitch 5120 (/4 1280) >[ 40005.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1516170] >[ 40005.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1516170] width 1280 pitch 5120 (/4 1280) >[ 40015.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151da70] >[ 40015.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151da70] width 1280 pitch 5120 (/4 1280) >[ 40016.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1515fa0] >[ 40016.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1515fa0] width 1280 pitch 5120 (/4 1280) >[ 40016.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b52330] >[ 40016.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b52330] width 1280 pitch 5120 (/4 1280) >[ 40016.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x133e420] >[ 40016.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x133e420] width 1280 pitch 5120 (/4 1280) >[ 40046.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343800] >[ 40046.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343800] width 1280 pitch 5120 (/4 1280) >[ 40046.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e98100] >[ 40046.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e98100] width 1280 pitch 5120 (/4 1280) >[ 40046.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15022a0] >[ 40046.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15022a0] width 1280 pitch 5120 (/4 1280) >[ 40046.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147eb90] >[ 40046.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147eb90] width 1280 pitch 5120 (/4 1280) >[ 40047.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15022a0] >[ 40047.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15022a0] width 1280 pitch 5120 (/4 1280) >[ 40047.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13244f0] >[ 40047.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13244f0] width 1280 pitch 5120 (/4 1280) >[ 40047.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13244f0] >[ 40047.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13244f0] width 1280 pitch 5120 (/4 1280) >[ 40047.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501790] >[ 40047.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501790] width 1280 pitch 5120 (/4 1280) >[ 40047.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147e230] >[ 40047.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147e230] width 1280 pitch 5120 (/4 1280) >[ 40048.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352fb0] >[ 40048.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352fb0] width 1280 pitch 5120 (/4 1280) >[ 40048.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec89e0] >[ 40048.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec89e0] width 1280 pitch 5120 (/4 1280) >[ 40048.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13517e0] >[ 40048.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13517e0] width 1280 pitch 5120 (/4 1280) >[ 40049.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15022a0] >[ 40049.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15022a0] width 1280 pitch 5120 (/4 1280) >[ 40049.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13517e0] >[ 40049.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13517e0] width 1280 pitch 5120 (/4 1280) >[ 40049.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352fb0] >[ 40049.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352fb0] width 1280 pitch 5120 (/4 1280) >[ 40049.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec89e0] >[ 40049.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec89e0] width 1280 pitch 5120 (/4 1280) >[ 40102.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352190] >[ 40102.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352190] width 1280 pitch 5120 (/4 1280) >[ 40102.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b4c20] >[ 40102.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b4c20] width 1280 pitch 5120 (/4 1280) >[ 40105.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40105.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40105.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9af00] >[ 40105.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9af00] width 1280 pitch 5120 (/4 1280) >[ 40105.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40105.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40105.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9af00] >[ 40105.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9af00] width 1280 pitch 5120 (/4 1280) >[ 40105.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40105.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40105.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9af00] >[ 40105.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9af00] width 1280 pitch 5120 (/4 1280) >[ 40105.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40105.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40105.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b4c20] >[ 40105.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b4c20] width 1280 pitch 5120 (/4 1280) >[ 40105.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40105.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40105.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b4c20] >[ 40105.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b4c20] width 1280 pitch 5120 (/4 1280) >[ 40105.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352190] >[ 40105.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352190] width 1280 pitch 5120 (/4 1280) >[ 40105.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1227540] >[ 40105.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1227540] width 1280 pitch 5120 (/4 1280) >[ 40105.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e1d90] >[ 40105.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e1d90] width 1280 pitch 5120 (/4 1280) >[ 40105.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1227540] >[ 40105.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1227540] width 1280 pitch 5120 (/4 1280) >[ 40105.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352190] >[ 40105.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352190] width 1280 pitch 5120 (/4 1280) >[ 40105.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71190] >[ 40105.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71190] width 1280 pitch 5120 (/4 1280) >[ 40105.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b06a70] >[ 40105.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b06a70] width 1280 pitch 5120 (/4 1280) >[ 40105.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40105.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40105.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9af00] >[ 40105.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9af00] width 1280 pitch 5120 (/4 1280) >[ 40105.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352190] >[ 40105.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352190] width 1280 pitch 5120 (/4 1280) >[ 40105.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1227540] >[ 40105.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1227540] width 1280 pitch 5120 (/4 1280) >[ 40105.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352190] >[ 40105.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352190] width 1280 pitch 5120 (/4 1280) >[ 40105.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1227540] >[ 40105.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1227540] width 1280 pitch 5120 (/4 1280) >[ 40112.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1333d50] >[ 40112.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1333d50] width 1280 pitch 5120 (/4 1280) >[ 40112.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa9cc0] >[ 40112.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa9cc0] width 1280 pitch 5120 (/4 1280) >[ 40122.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40122.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40122.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40122.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40122.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40122.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40122.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40122.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40122.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40122.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40122.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40122.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40122.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40122.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40122.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40122.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40122.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40122.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40123.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13517e0] >[ 40123.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13517e0] width 1280 pitch 5120 (/4 1280) >[ 40123.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15022a0] >[ 40123.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15022a0] width 1280 pitch 5120 (/4 1280) >[ 40123.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40123.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40123.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40123.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40123.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40123.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40123.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1220] >[ 40123.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1220] width 1280 pitch 5120 (/4 1280) >[ 40123.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343800] >[ 40123.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343800] width 1280 pitch 5120 (/4 1280) >[ 40123.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b06a70] >[ 40123.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b06a70] width 1280 pitch 5120 (/4 1280) >[ 40123.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71190] >[ 40123.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71190] width 1280 pitch 5120 (/4 1280) >[ 40123.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134ea50] >[ 40123.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134ea50] width 1280 pitch 5120 (/4 1280) >[ 40123.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aac30] >[ 40123.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aac30] width 1280 pitch 5120 (/4 1280) >[ 40123.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40123.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40123.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1424c90] >[ 40123.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1424c90] width 1280 pitch 5120 (/4 1280) >[ 40123.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[ 40124.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[ 40124.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b06a70] >[ 40124.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b06a70] width 1280 pitch 5120 (/4 1280) >[ 40124.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343800] >[ 40124.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343800] width 1280 pitch 5120 (/4 1280) >[ 40124.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b06a70] >[ 40124.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b06a70] width 1280 pitch 5120 (/4 1280) >[ 40124.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x133e420] >[ 40124.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x133e420] width 1280 pitch 5120 (/4 1280) >[ 40124.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40124.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40124.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40124.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40124.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40124.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40124.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1284740] >[ 40124.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1284740] width 1280 pitch 5120 (/4 1280) >[ 40124.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40124.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40124.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40124.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40124.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2473390] >[ 40124.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2473390] width 1280 pitch 5120 (/4 1280) >[ 40124.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40124.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40124.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2473390] >[ 40124.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2473390] width 1280 pitch 5120 (/4 1280) >[ 40124.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1220] >[ 40124.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1220] width 1280 pitch 5120 (/4 1280) >[ 40124.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71190] >[ 40124.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71190] width 1280 pitch 5120 (/4 1280) >[ 40124.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13517e0] >[ 40124.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13517e0] width 1280 pitch 5120 (/4 1280) >[ 40124.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71190] >[ 40124.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71190] width 1280 pitch 5120 (/4 1280) >[ 40124.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13517e0] >[ 40124.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13517e0] width 1280 pitch 5120 (/4 1280) >[ 40124.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343800] >[ 40124.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343800] width 1280 pitch 5120 (/4 1280) >[ 40125.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343800] >[ 40125.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343800] width 1280 pitch 5120 (/4 1280) >[ 40125.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b760] >[ 40125.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b760] width 1280 pitch 5120 (/4 1280) >[ 40125.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40125.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40125.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40125.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40135.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129c3e0] >[ 40135.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129c3e0] width 1280 pitch 5120 (/4 1280) >[ 40135.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1424c90] >[ 40135.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1424c90] width 1280 pitch 5120 (/4 1280) >[ 40135.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129c3e0] >[ 40135.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129c3e0] width 1280 pitch 5120 (/4 1280) >[ 40136.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40136.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40136.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134ea50] >[ 40136.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134ea50] width 1280 pitch 5120 (/4 1280) >[ 40136.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40136.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40136.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40136.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40136.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x133e420] >[ 40136.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x133e420] width 1280 pitch 5120 (/4 1280) >[ 40136.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40136.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40136.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134ea50] >[ 40137.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134ea50] width 1280 pitch 5120 (/4 1280) >[ 40137.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15022a0] >[ 40137.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15022a0] width 1280 pitch 5120 (/4 1280) >[ 40137.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5730] >[ 40137.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5730] width 1280 pitch 5120 (/4 1280) >[ 40137.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134ea50] >[ 40138.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134ea50] width 1280 pitch 5120 (/4 1280) >[ 40138.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b50de0] >[ 40138.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b50de0] width 1280 pitch 5120 (/4 1280) >[ 40138.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40138.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40138.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2473390] >[ 40138.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2473390] width 1280 pitch 5120 (/4 1280) >[ 40138.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bb910] >[ 40138.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bb910] width 1280 pitch 5120 (/4 1280) >[ 40138.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2363d90] >[ 40138.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2363d90] width 1280 pitch 5120 (/4 1280) >[ 40202.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13244f0] >[ 40202.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13244f0] width 1280 pitch 5120 (/4 1280) >[ 40202.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40202.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40213.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1a780] >[ 40213.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1a780] width 1280 pitch 5120 (/4 1280) >[ 40243.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9ab10] >[ 40243.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9ab10] width 1280 pitch 5120 (/4 1280) >[ 40243.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[ 40243.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[ 40285.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1227540] >[ 40285.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1227540] width 1280 pitch 5120 (/4 1280) >[ 40285.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40285.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40285.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1265fb0] >[ 40285.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1265fb0] width 1280 pitch 5120 (/4 1280) >[ 40285.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40285.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40641.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40641.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40641.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d31410] >[ 40641.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d31410] width 1280 pitch 5120 (/4 1280) >[ 40641.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40641.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40641.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40641.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40641.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40641.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40641.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40641.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40641.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40641.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40642.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40642.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40642.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf0c0] >[ 40642.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf0c0] width 1280 pitch 5120 (/4 1280) >[ 40642.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40642.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aac30] >[ 40642.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aac30] width 1280 pitch 5120 (/4 1280) >[ 40642.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40642.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1333d50] >[ 40642.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1333d50] width 1280 pitch 5120 (/4 1280) >[ 40642.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40642.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269e60] >[ 40642.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269e60] width 1280 pitch 5120 (/4 1280) >[ 40642.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d549b0] >[ 40642.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d549b0] width 1280 pitch 5120 (/4 1280) >[ 40642.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40642.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40642.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40642.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40642.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40642.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x135e970] >[ 40642.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x135e970] width 1280 pitch 5120 (/4 1280) >[ 40642.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ed430] >[ 40642.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ed430] width 1280 pitch 5120 (/4 1280) >[ 40644.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1265d40] >[ 40644.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1265d40] width 1280 pitch 5120 (/4 1280) >[ 40644.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40644.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40644.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40644.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40644.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1461730] >[ 40645.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1461730] width 1280 pitch 5120 (/4 1280) >[ 40645.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40645.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40645.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1128eb0] >[ 40645.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1128eb0] width 1280 pitch 5120 (/4 1280) >[ 40645.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40645.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40645.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1128eb0] >[ 40645.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1128eb0] width 1280 pitch 5120 (/4 1280) >[ 40645.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40645.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40646.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1128eb0] >[ 40646.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1128eb0] width 1280 pitch 5120 (/4 1280) >[ 40646.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40646.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40646.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1128eb0] >[ 40646.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1128eb0] width 1280 pitch 5120 (/4 1280) >[ 40646.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40646.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40647.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1128eb0] >[ 40647.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1128eb0] width 1280 pitch 5120 (/4 1280) >[ 40647.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40647.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40647.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aac30] >[ 40647.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aac30] width 1280 pitch 5120 (/4 1280) >[ 40647.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40647.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40647.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aac30] >[ 40647.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aac30] width 1280 pitch 5120 (/4 1280) >[ 40647.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc6850] >[ 40647.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc6850] width 1280 pitch 5120 (/4 1280) >[ 40647.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40647.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40648.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ad70] >[ 40648.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ad70] width 1280 pitch 5120 (/4 1280) >[ 40648.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1265fb0] >[ 40648.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1265fb0] width 1280 pitch 5120 (/4 1280) >[ 40699.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 40699.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 40700.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14cae40] >[ 40700.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14cae40] width 1280 pitch 5120 (/4 1280) >[ 40719.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13995b0] >[ 40719.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13995b0] width 1280 pitch 5120 (/4 1280) >[ 40719.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1359550] >[ 40719.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1359550] width 1280 pitch 5120 (/4 1280) >[ 40839.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40839.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40839.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1423910] >[ 40839.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1423910] width 1280 pitch 5120 (/4 1280) >[ 40849.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1474010] >[ 40849.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1474010] width 1280 pitch 5120 (/4 1280) >[ 40849.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1515750] >[ 40849.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1515750] width 1280 pitch 5120 (/4 1280) >[ 40939.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ced0] >[ 40939.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ced0] width 1280 pitch 5120 (/4 1280) >[ 40939.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14742b0] >[ 40939.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14742b0] width 1280 pitch 5120 (/4 1280) >[ 41002.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1312210] >[ 41002.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1312210] width 1280 pitch 5120 (/4 1280) >[ 41005.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1508e40] >[ 41005.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1508e40] width 1280 pitch 5120 (/4 1280) >[ 41091.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cfc8b0] >[ 41091.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cfc8b0] width 1280 pitch 5120 (/4 1280) >[ 41091.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6e4b0] >[ 41091.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6e4b0] width 1280 pitch 5120 (/4 1280) >[ 41198.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b1c20] >[ 41198.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b1c20] width 1280 pitch 5120 (/4 1280) >[ 41198.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b4da0] >[ 41198.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b4da0] width 1280 pitch 5120 (/4 1280) >[ 41203.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13af220] >[ 41203.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13af220] width 1280 pitch 5120 (/4 1280) >[ 41203.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d970] >[ 41203.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d970] width 1280 pitch 5120 (/4 1280) >[ 41384.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234d780] >[ 41384.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234d780] width 1280 pitch 5120 (/4 1280) >[ 41384.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234d500] >[ 41384.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234d500] width 1280 pitch 5120 (/4 1280) >[ 41484.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c78050] >[ 41484.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c78050] width 1280 pitch 5120 (/4 1280) >[ 41509.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240af00] >[ 41509.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240af00] width 1280 pitch 5120 (/4 1280) >[ 41509.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2493690] >[ 41509.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2493690] width 1280 pitch 5120 (/4 1280) >[ 41527.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240ad40] >[ 41527.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240ad40] width 1280 pitch 5120 (/4 1280) >[ 41527.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x234c750] >[ 41527.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x234c750] width 1280 pitch 5120 (/4 1280) >[ 41557.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240a000] >[ 41557.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240a000] width 1280 pitch 5120 (/4 1280) >[ 41559.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23441b0] >[ 41559.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23441b0] width 1280 pitch 5120 (/4 1280) >[ 41559.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26087f0] >[ 41559.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26087f0] width 1280 pitch 5120 (/4 1280) >[ 41582.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41582.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41582.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24077e0] >[ 41582.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24077e0] width 1280 pitch 5120 (/4 1280) >[ 41601.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240ad40] >[ 41601.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240ad40] width 1280 pitch 5120 (/4 1280) >[ 41601.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26088c0] >[ 41601.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26088c0] width 1280 pitch 5120 (/4 1280) >[ 41601.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41601.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41601.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41601.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41601.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41601.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41601.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41601.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41602.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41602.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41602.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41602.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41602.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41602.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41602.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41602.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41602.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41602.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41603.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41603.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41603.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41603.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41603.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41603.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41603.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41603.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41603.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f01b0] >[ 41603.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f01b0] width 1280 pitch 5120 (/4 1280) >[ 41603.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480d00] >[ 41603.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480d00] width 1280 pitch 5120 (/4 1280) >[ 41682.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0a400] >[ 41682.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0a400] width 1280 pitch 5120 (/4 1280) >[ 41682.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2409390] >[ 41682.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2409390] width 1280 pitch 5120 (/4 1280) >[ 41682.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2409390] >[ 41682.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2409390] width 1280 pitch 5120 (/4 1280) >[ 41682.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2409390] >[ 41682.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2409390] width 1280 pitch 5120 (/4 1280) >[ 41683.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f4530] >[ 41683.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f4530] width 1280 pitch 5120 (/4 1280) >[ 41683.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f4530] >[ 41683.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f4530] width 1280 pitch 5120 (/4 1280) >[ 41756.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f5ad0] >[ 41756.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f5ad0] width 1280 pitch 5120 (/4 1280) >[ 41756.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199c290] >[ 41756.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199c290] width 1280 pitch 5120 (/4 1280) >[ 42455.241] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 42455.241] (II) RADEON(0): Printing DDC gathered Modelines: >[ 42455.241] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 42545.890] (II) RADEON(0): RADEONSaveScreen(2) >[ 42545.890] (II) RADEON(0): RADEONSaveScreen(0) >[ 43047.742] (II) RADEON(0): RADEONSaveScreen(1) >[ 43053.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43053.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43053.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43053.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43053.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43056.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43056.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43056.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43056.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43056.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43056.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43056.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43056.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43057.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43057.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43057.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43057.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43058.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43058.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43060.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43060.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43061.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43061.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43061.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43061.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43062.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43062.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43062.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43062.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43062.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43062.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43062.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43062.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43063.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43063.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43064.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43064.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43066.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43066.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43067.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43067.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43067.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43067.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43067.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43067.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43067.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43067.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43067.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43067.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43067.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43067.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43067.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43067.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43067.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43067.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43067.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43067.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43067.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248ac90] >[ 43067.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248ac90] width 1280 pitch 5120 (/4 1280) >[ 43067.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cffea0] >[ 43067.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cffea0] width 1280 pitch 5120 (/4 1280) >[ 43073.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43073.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43073.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2455fa0] >[ 43073.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2455fa0] width 1280 pitch 5120 (/4 1280) >[ 43076.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f2d00] >[ 43076.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f2d00] width 1280 pitch 5120 (/4 1280) >[ 43076.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2347670] >[ 43076.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2347670] width 1280 pitch 5120 (/4 1280) >[ 43077.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10add10] >[ 43077.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10add10] width 1280 pitch 5120 (/4 1280) >[ 43077.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43077.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43077.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10add10] >[ 43077.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10add10] width 1280 pitch 5120 (/4 1280) >[ 43077.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199c160] >[ 43077.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199c160] width 1280 pitch 5120 (/4 1280) >[ 43077.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43077.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43077.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199c160] >[ 43077.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199c160] width 1280 pitch 5120 (/4 1280) >[ 43077.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199c160] >[ 43077.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199c160] width 1280 pitch 5120 (/4 1280) >[ 43077.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10add10] >[ 43077.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10add10] width 1280 pitch 5120 (/4 1280) >[ 43077.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43077.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43077.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43077.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43077.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10add10] >[ 43077.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10add10] width 1280 pitch 5120 (/4 1280) >[ 43077.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199c160] >[ 43077.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199c160] width 1280 pitch 5120 (/4 1280) >[ 43077.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2401ab0] >[ 43077.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2401ab0] width 1280 pitch 5120 (/4 1280) >[ 43077.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43077.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43079.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43079.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43082.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43082.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43082.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43082.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43082.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43082.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43088.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43088.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43089.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43089.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43089.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43090.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43090.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd38f0] >[ 43090.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd38f0] width 1280 pitch 5120 (/4 1280) >[ 43090.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43090.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43090.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd38f0] >[ 43090.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd38f0] width 1280 pitch 5120 (/4 1280) >[ 43091.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43091.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43095.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43095.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43096.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43096.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43099.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43099.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43099.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e0f60] >[ 43099.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e0f60] width 1280 pitch 5120 (/4 1280) >[ 43099.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d416f0] >[ 43099.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d416f0] width 1280 pitch 5120 (/4 1280) >[ 43099.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43099.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43099.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d416f0] >[ 43099.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d416f0] width 1280 pitch 5120 (/4 1280) >[ 43100.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43100.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43100.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43100.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43101.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43101.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43104.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43104.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43113.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43113.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43113.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43113.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43113.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43113.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43113.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43113.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43113.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43113.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43114.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43114.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43114.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43114.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43114.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43114.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43114.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43114.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43114.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43114.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43114.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43114.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43125.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43125.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43127.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43127.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43128.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43128.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43128.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43128.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43128.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43128.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43129.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43129.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43130.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43130.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43130.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43130.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43131.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43131.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43131.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43131.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43131.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43131.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43132.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43132.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43132.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43132.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43132.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43132.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43132.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43132.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43132.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43132.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43132.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43132.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43133.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43133.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43133.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43133.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43133.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43133.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43133.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43133.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43134.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43134.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43134.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43134.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43135.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43136.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43136.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43136.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43136.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43137.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43137.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43137.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43137.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43137.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43137.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43137.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43137.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43137.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43137.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43137.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43137.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43137.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43137.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43138.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43138.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43138.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43138.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43138.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43138.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43138.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43138.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43138.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43138.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43138.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43138.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43138.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43138.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43139.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43139.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43139.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43139.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43139.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43139.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43139.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43139.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43139.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43139.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43139.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43139.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43139.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43139.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43139.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43139.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43139.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43139.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43140.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43140.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43140.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43140.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43140.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43140.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43140.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43140.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43140.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43140.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43140.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43140.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43141.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43141.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43141.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43141.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43141.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43141.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43141.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43141.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43141.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43141.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43141.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43141.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43141.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43141.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43141.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43141.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43142.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43142.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43142.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43142.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43142.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43142.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43147.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43147.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43147.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43147.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43147.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43147.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43147.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43147.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43147.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43147.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43152.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43152.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43152.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43152.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43152.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43152.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43152.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43152.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43152.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43152.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43153.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43153.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43153.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43153.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43153.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43153.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43153.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43153.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43153.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43153.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43153.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43153.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43153.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43153.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43153.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43153.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43153.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43153.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43153.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43153.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43155.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43155.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43156.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43156.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43156.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43156.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43157.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43157.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43157.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43157.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43157.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43157.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43157.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43157.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43157.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43157.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43157.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43157.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43157.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43157.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43158.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43158.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43159.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43159.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43159.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43159.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43159.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43160.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43160.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43160.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43160.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43160.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43160.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43160.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43160.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43160.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43160.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43160.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43160.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43160.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43160.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43160.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43160.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247caf0] >[ 43160.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247caf0] width 1280 pitch 5120 (/4 1280) >[ 43160.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43160.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43160.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1136130] >[ 43160.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1136130] width 1280 pitch 5120 (/4 1280) >[ 43160.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244cd80] >[ 43160.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244cd80] width 1280 pitch 5120 (/4 1280) >[ 43174.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23fefc0] >[ 43174.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23fefc0] width 1280 pitch 5120 (/4 1280) >[ 43187.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43187.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43187.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43187.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43187.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43187.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43187.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43187.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43187.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43187.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43187.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43187.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43188.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43188.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43188.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43188.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43188.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43188.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43188.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498bc0] >[ 43188.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498bc0] width 1280 pitch 5120 (/4 1280) >[ 43188.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43188.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43188.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43188.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43188.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43188.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43188.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43188.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43188.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498bc0] >[ 43188.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498bc0] width 1280 pitch 5120 (/4 1280) >[ 43188.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43188.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43189.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43189.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43189.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43189.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43189.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43189.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43189.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43189.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43189.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43189.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43189.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43189.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43189.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43189.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43189.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498bc0] >[ 43189.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498bc0] width 1280 pitch 5120 (/4 1280) >[ 43189.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f21b0] >[ 43189.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f21b0] width 1280 pitch 5120 (/4 1280) >[ 43190.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43190.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43190.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43190.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43190.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43190.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43190.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43190.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43190.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43190.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43190.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1350c80] >[ 43190.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1350c80] width 1280 pitch 5120 (/4 1280) >[ 43190.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f9930] >[ 43190.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f9930] width 1280 pitch 5120 (/4 1280) >[ 43190.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25002e0] >[ 43190.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25002e0] width 1280 pitch 5120 (/4 1280) >[ 43190.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43190.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43190.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498bc0] >[ 43190.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498bc0] width 1280 pitch 5120 (/4 1280) >[ 43190.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f21b0] >[ 43190.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f21b0] width 1280 pitch 5120 (/4 1280) >[ 43190.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ffde0] >[ 43190.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ffde0] width 1280 pitch 5120 (/4 1280) >[ 43258.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d5910] >[ 43258.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d5910] width 1280 pitch 5120 (/4 1280) >[ 43258.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b8e700] >[ 43258.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b8e700] width 1280 pitch 5120 (/4 1280) >[ 43258.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23da780] >[ 43258.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23da780] width 1280 pitch 5120 (/4 1280) >[ 43258.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402e20] >[ 43258.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402e20] width 1280 pitch 5120 (/4 1280) >[ 43259.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d9ef0] >[ 43259.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d9ef0] width 1280 pitch 5120 (/4 1280) >[ 43259.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23da780] >[ 43259.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23da780] width 1280 pitch 5120 (/4 1280) >[ 43259.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402e20] >[ 43259.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402e20] width 1280 pitch 5120 (/4 1280) >[ 43260.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d9ef0] >[ 43260.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d9ef0] width 1280 pitch 5120 (/4 1280) >[ 43260.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402cc0] >[ 43260.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402cc0] width 1280 pitch 5120 (/4 1280) >[ 43260.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23da780] >[ 43260.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23da780] width 1280 pitch 5120 (/4 1280) >[ 43260.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402e20] >[ 43260.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402e20] width 1280 pitch 5120 (/4 1280) >[ 43260.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402cc0] >[ 43260.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402cc0] width 1280 pitch 5120 (/4 1280) >[ 43260.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402cc0] >[ 43260.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402cc0] width 1280 pitch 5120 (/4 1280) >[ 43260.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24030e0] >[ 43260.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24030e0] width 1280 pitch 5120 (/4 1280) >[ 43260.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24030e0] >[ 43260.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24030e0] width 1280 pitch 5120 (/4 1280) >[ 43260.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2403140] >[ 43260.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2403140] width 1280 pitch 5120 (/4 1280) >[ 43260.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2402b20] >[ 43260.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2402b20] width 1280 pitch 5120 (/4 1280) >[ 43263.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492ca0] >[ 43263.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492ca0] width 1280 pitch 5120 (/4 1280) >[ 43264.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d8270] >[ 43264.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d8270] width 1280 pitch 5120 (/4 1280) >[ 43264.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d26d0] >[ 43264.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d26d0] width 1280 pitch 5120 (/4 1280) >[ 43264.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ffc50] >[ 43264.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ffc50] width 1280 pitch 5120 (/4 1280) >[ 43264.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d6840] >[ 43264.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d6840] width 1280 pitch 5120 (/4 1280) >[ 43264.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ffc50] >[ 43264.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ffc50] width 1280 pitch 5120 (/4 1280) >[ 43264.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d26d0] >[ 43264.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d26d0] width 1280 pitch 5120 (/4 1280) >[ 43264.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d8270] >[ 43264.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d8270] width 1280 pitch 5120 (/4 1280) >[ 43264.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492ca0] >[ 43264.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492ca0] width 1280 pitch 5120 (/4 1280) >[ 43268.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492ca0] >[ 43268.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492ca0] width 1280 pitch 5120 (/4 1280) >[ 43268.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d8270] >[ 43268.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d8270] width 1280 pitch 5120 (/4 1280) >[ 43268.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d26d0] >[ 43268.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d26d0] width 1280 pitch 5120 (/4 1280) >[ 43268.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ffc50] >[ 43268.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ffc50] width 1280 pitch 5120 (/4 1280) >[ 43268.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d6840] >[ 43268.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d6840] width 1280 pitch 5120 (/4 1280) >[ 43268.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492ca0] >[ 43268.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492ca0] width 1280 pitch 5120 (/4 1280) >[ 43268.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d8270] >[ 43268.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d8270] width 1280 pitch 5120 (/4 1280) >[ 43268.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492ca0] >[ 43268.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492ca0] width 1280 pitch 5120 (/4 1280) >[ 43268.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d6840] >[ 43268.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d6840] width 1280 pitch 5120 (/4 1280) >[ 43268.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ffc50] >[ 43268.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ffc50] width 1280 pitch 5120 (/4 1280) >[ 43269.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d8270] >[ 43269.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d8270] width 1280 pitch 5120 (/4 1280) >[ 43269.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ffc50] >[ 43269.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ffc50] width 1280 pitch 5120 (/4 1280) >[ 43305.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f8180] >[ 43305.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f8180] width 1280 pitch 5120 (/4 1280) >[ 43410.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1066630] >[ 43410.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1066630] width 1280 pitch 5120 (/4 1280) >[ 43410.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43410.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43410.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43410.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43410.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43410.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43410.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 43410.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 43410.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26de230] >[ 43410.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26de230] width 1280 pitch 5120 (/4 1280) >[ 43410.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26de230] >[ 43410.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26de230] width 1280 pitch 5120 (/4 1280) >[ 43410.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43410.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43410.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26de230] >[ 43410.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26de230] width 1280 pitch 5120 (/4 1280) >[ 43410.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43410.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43410.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26de230] >[ 43410.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26de230] width 1280 pitch 5120 (/4 1280) >[ 43414.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43414.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43414.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43414.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43414.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 43414.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 43414.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43414.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43414.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26de230] >[ 43414.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26de230] width 1280 pitch 5120 (/4 1280) >[ 43414.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43414.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43414.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43414.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43414.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43414.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43414.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43414.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43414.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1066630] >[ 43414.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1066630] width 1280 pitch 5120 (/4 1280) >[ 43414.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43414.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43414.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 43414.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 43414.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43414.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43438.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43438.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43449.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43449.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43474.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43474.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 43594.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43594.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43622.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43622.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43742.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 43742.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 43770.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 43770.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 43890.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 43890.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 43919.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 43919.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44039.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 44039.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 44053.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 44053.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 44053.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44053.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44053.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 44053.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 44053.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44053.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44053.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44053.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44053.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44053.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44053.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 44053.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 44053.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 44053.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 44053.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 44053.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 44053.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44053.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44053.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44053.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44054.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d4e60] >[ 44054.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d4e60] width 1280 pitch 5120 (/4 1280) >[ 44054.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1066630] >[ 44054.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1066630] width 1280 pitch 5120 (/4 1280) >[ 44054.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 44054.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 44054.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1066630] >[ 44054.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1066630] width 1280 pitch 5120 (/4 1280) >[ 44054.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44054.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44054.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44054.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44054.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fcca0] >[ 44054.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fcca0] width 1280 pitch 5120 (/4 1280) >[ 44054.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1066630] >[ 44054.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1066630] width 1280 pitch 5120 (/4 1280) >[ 44067.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d7d10] >[ 44067.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d7d10] width 1280 pitch 5120 (/4 1280) >[ 44121.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44121.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44124.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44124.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44126.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91a0] >[ 44126.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91a0] width 1280 pitch 5120 (/4 1280) >[ 44129.238] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 44129.238] (II) RADEON(0): Printing DDC gathered Modelines: >[ 44129.238] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 44133.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1389140] >[ 44133.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1389140] width 1280 pitch 5120 (/4 1280) >[ 44137.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44137.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44139.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44139.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44139.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44139.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44139.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44139.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44139.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44139.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44139.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44139.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44139.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44139.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44139.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44139.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44139.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44139.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44139.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44139.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44139.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44139.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44139.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44139.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44139.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44139.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44139.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44139.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44140.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44140.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44141.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44141.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44141.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44141.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44141.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44141.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44141.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44141.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44142.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44142.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44142.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44142.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44142.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44142.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44142.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44142.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44142.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44142.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44148.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44148.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44148.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44148.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44148.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44148.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44148.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44148.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44148.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44148.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44148.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44148.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44148.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44148.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44148.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44148.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44148.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44148.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44148.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44148.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44148.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44148.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44148.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44148.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44148.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44148.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44148.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44148.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44148.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44148.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44148.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44148.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44152.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44152.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44152.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44152.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44152.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44152.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44152.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44152.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44152.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44152.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44152.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44152.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44152.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44152.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44152.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44152.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44152.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44152.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44152.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44152.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44153.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44153.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44153.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44153.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44153.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44153.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44153.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44153.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44153.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44153.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44153.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44153.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44154.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44154.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44154.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44154.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44154.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44154.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44155.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44155.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44155.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44155.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44155.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44155.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44155.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44155.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44155.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44155.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44155.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44155.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44155.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44155.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44155.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44155.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44155.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44155.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44155.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44155.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44155.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44155.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44155.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44155.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44159.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44159.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44159.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44159.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44159.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44159.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44159.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44159.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44159.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44159.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44159.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44159.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44159.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44159.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44159.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44159.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44159.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44159.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44159.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44159.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44159.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44159.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44159.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44159.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44159.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44159.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44166.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44166.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44166.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44166.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44166.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44166.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44166.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44166.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44170.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44170.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44170.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44170.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44170.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44170.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44170.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44170.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44170.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44170.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44170.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44170.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44170.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44170.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44170.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44170.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44170.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44170.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44170.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44170.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44171.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44171.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44171.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44171.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44171.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44171.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44171.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44171.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44171.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44171.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44171.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44171.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44171.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44171.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44171.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44171.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44172.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44172.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44172.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44172.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44172.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44172.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44172.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44172.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44172.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44172.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44172.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44172.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44172.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44172.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44172.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44172.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44172.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44172.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44172.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44172.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44173.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44173.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44173.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44173.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44173.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44173.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44173.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44173.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44173.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44173.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44173.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44173.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44173.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44173.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44173.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44173.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44173.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44173.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44173.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44173.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44173.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44173.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44173.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44173.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44173.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44173.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44173.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44173.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44174.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44174.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44174.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44174.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44174.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44174.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44174.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44174.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44174.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44174.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44174.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44174.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44174.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44174.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44174.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44174.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44174.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44174.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44174.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44174.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44174.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44174.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44175.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44175.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44175.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44175.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44175.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44175.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44175.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44175.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44175.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44175.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44175.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44175.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44175.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44175.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44175.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44175.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44175.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44175.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44175.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44175.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44175.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44175.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44176.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44176.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44176.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44176.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44176.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44176.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44176.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44176.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44176.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44176.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44176.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44176.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44176.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44176.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44176.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44176.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44176.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44176.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44176.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44176.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44176.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44176.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44177.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44177.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44177.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44177.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44177.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44177.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44177.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44177.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44177.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44177.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44177.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44177.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44177.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44177.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44177.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44177.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44177.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44177.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44177.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44177.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44177.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44177.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44177.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44177.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44178.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44178.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44178.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44178.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44178.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44178.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44178.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44178.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44178.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44178.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44178.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44178.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44178.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44178.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44178.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44178.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44178.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44178.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44178.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44178.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44178.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44178.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44178.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44178.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44179.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44179.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44179.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44179.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44179.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44179.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44179.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44179.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44179.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44179.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44179.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44179.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44179.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44179.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44179.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44179.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44179.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44179.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44179.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44179.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44179.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44179.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44179.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44179.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44180.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44180.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44180.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44180.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44180.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44180.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44180.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44180.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44180.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44180.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44180.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44180.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44180.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44180.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44180.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44180.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44180.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44180.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44180.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44180.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44180.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44180.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44180.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44180.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44181.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44181.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44181.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44181.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44181.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44181.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44181.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44181.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44181.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44181.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44181.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44181.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44181.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44181.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44181.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44181.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44181.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44181.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44181.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44181.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44181.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44181.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44181.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44181.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44182.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44182.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44182.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44182.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44182.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44182.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44182.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44182.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44182.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44182.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44182.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44182.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44182.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44182.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44182.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44182.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44182.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44182.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44182.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44182.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44182.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44182.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44182.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44182.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44183.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44183.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44183.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44183.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44183.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44183.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44183.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44183.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44183.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44183.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44183.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44183.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44183.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44183.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44183.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44183.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44183.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44183.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44183.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44183.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44183.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44183.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44183.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44183.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44184.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44184.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44184.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44184.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44184.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44184.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44184.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44184.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44184.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44184.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44184.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44184.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44184.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44184.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44184.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44184.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44184.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44184.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44184.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44184.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44184.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44184.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44184.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44184.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44185.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44185.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44185.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44185.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44185.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44185.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44185.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44185.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44185.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44185.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44185.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44185.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44185.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44185.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44185.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44185.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44185.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44185.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44185.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44185.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44185.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44185.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44185.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44186.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44186.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44186.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44186.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44186.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44186.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44186.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44186.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44186.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44186.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44186.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44186.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44186.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44186.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44186.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44186.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44186.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44186.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44186.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44186.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44186.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44186.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44186.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44187.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44187.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44187.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44187.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44187.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44187.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44187.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44187.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44187.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44187.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44187.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44187.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44187.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44187.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44187.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44187.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44187.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44187.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44187.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44187.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44187.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44187.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44187.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44187.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44192.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44192.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44192.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44192.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44192.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44192.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44192.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44192.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44192.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44192.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44192.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44192.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44192.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44192.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44192.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44192.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44192.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44192.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44192.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44192.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44193.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44193.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44193.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44193.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44193.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44193.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44193.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44193.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44193.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44193.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44193.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44193.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44193.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44193.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44193.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44193.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44193.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44193.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44193.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44193.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44193.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44193.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44193.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44193.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44193.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44193.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44193.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44194.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44194.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44194.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44194.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44194.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44194.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44194.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44194.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44194.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44194.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44194.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44194.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44194.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44194.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44194.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44194.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44194.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44194.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44194.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44194.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44194.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44194.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44194.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44194.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44194.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44194.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44194.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44194.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44194.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44194.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44195.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44195.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44195.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44195.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44195.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44195.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44195.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44195.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44195.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44195.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44195.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44205.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44205.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44205.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44205.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44205.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44205.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44205.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44205.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44205.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44205.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44206.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44206.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44206.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44206.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44206.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44206.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44206.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44206.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44206.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44206.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44206.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44206.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44206.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44206.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44206.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44206.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44206.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44206.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44206.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44206.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44206.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44206.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44206.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44206.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44207.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44207.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44207.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44207.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44207.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44207.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44207.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44207.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44207.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44207.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44207.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44207.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44231.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44231.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44239.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44239.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44239.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44239.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44239.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44239.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44239.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44239.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44239.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44239.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44239.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44239.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44239.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44239.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44239.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44239.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44239.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44239.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44240.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44240.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44240.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44240.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44240.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44240.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44240.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44240.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44240.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44240.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44240.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44240.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44240.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44240.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44240.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44240.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44247.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44247.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44247.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44247.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44247.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44247.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44247.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44247.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44247.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44247.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44247.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44247.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44247.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44247.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44247.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44247.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44247.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44247.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44247.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44247.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44247.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44247.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44247.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44247.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44247.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44247.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44247.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44247.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44247.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44248.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44248.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44248.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44248.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44248.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44248.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44248.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44248.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44248.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44248.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44248.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44248.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44248.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44248.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44248.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44248.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44248.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44248.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44248.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44248.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44248.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44248.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44248.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44248.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44248.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44248.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44248.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44248.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44248.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44248.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44248.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44248.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44248.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44249.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44249.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44249.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44249.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44249.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44249.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44249.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44249.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44249.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44249.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44249.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44249.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44250.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44250.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44250.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44250.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44250.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ece740] >[ 44250.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ece740] width 1280 pitch 5120 (/4 1280) >[ 44250.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44250.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44250.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44250.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44250.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44250.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44250.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44250.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44250.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44250.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44250.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44250.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44250.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44250.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44250.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44250.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44250.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44250.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44250.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44250.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44250.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44250.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44251.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44251.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44251.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44251.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44251.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44251.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44251.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44251.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44251.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44251.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44251.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44251.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44251.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44251.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44257.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44257.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44257.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44257.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44257.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44257.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44257.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44257.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44257.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44257.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44257.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44257.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44257.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44257.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44257.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44257.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44258.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44258.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44258.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44258.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44258.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44258.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44258.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44258.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44258.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44258.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44258.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44258.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44262.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44262.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44262.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44262.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44262.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44262.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44262.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44262.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44262.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44262.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44262.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44262.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44262.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44262.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44262.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44262.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44262.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44262.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44262.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44262.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44262.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44262.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44262.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44262.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44262.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44262.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44262.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44262.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44262.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44262.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44262.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44263.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44263.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44263.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44263.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44263.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44263.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44263.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44263.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44263.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44263.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44263.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44263.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44263.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44263.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44263.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44263.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44263.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44263.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44263.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44263.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44263.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44263.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44263.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44263.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44263.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44264.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44264.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44264.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44264.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44264.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44264.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44264.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44264.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44264.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44264.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44264.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44264.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44264.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44264.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44264.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44264.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44264.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44264.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44264.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44264.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44264.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44264.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44264.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44264.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44264.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44264.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44264.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44264.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44264.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44264.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44265.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44265.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44265.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44265.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44265.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44265.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44265.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44265.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44265.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44265.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44265.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44265.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44265.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44265.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44265.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44265.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44265.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44265.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44265.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44265.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44265.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44265.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44265.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44265.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44266.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44266.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44266.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44266.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44266.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44266.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44266.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44266.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44266.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44266.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44266.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44266.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44266.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44266.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44266.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44266.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44266.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44266.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44266.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44266.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44266.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44266.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44266.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44266.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44267.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44267.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44267.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44267.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44267.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44267.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44267.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44267.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44267.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44267.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44267.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44267.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44267.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44267.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44267.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44267.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44268.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44268.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44268.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44268.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44268.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44268.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44268.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44268.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44268.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44268.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44268.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44268.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44268.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44268.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44268.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44268.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44268.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44268.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44268.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44268.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44268.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44268.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44268.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44268.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44268.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44268.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44268.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44268.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44269.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44269.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44269.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44269.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44269.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44269.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44269.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44269.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44269.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44269.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44269.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44269.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44269.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44269.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44269.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44269.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44269.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44269.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44269.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44269.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44269.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44269.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44269.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44270.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44270.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44270.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44270.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44270.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44270.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44270.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44270.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44270.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44270.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44270.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44270.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44270.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44270.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44270.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44270.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44270.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44270.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44270.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44270.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 44270.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 44270.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44270.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44270.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44271.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44271.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbce40] >[ 44271.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbce40] width 1280 pitch 5120 (/4 1280) >[ 44271.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44271.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44271.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44271.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44271.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44271.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44271.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44271.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44271.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44271.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44271.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44271.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44271.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44271.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44271.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 44271.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 44271.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44271.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44271.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44271.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44271.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44271.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44271.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44271.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44271.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44271.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44271.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 44271.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 44277.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eae3d0] >[ 44277.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eae3d0] width 1280 pitch 5120 (/4 1280) >[ 44277.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c2270] >[ 44277.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c2270] width 1280 pitch 5120 (/4 1280) >[ 44294.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf6e0] >[ 44294.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf6e0] width 1280 pitch 5120 (/4 1280) >[ 44294.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44294.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44294.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44295.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44295.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44295.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44295.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44295.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44295.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44295.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44295.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44295.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44295.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44295.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44295.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44295.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 44295.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 44295.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5af40] >[ 44295.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5af40] width 1280 pitch 5120 (/4 1280) >[ 44908.766] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 44908.766] (II) RADEON(0): Printing DDC gathered Modelines: >[ 44908.766] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 44998.886] (II) RADEON(0): RADEONSaveScreen(2) >[ 44998.886] (II) RADEON(0): RADEONSaveScreen(0) >[ 47768.230] (II) RADEON(0): RADEONSaveScreen(1) >[ 47772.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478720] >[ 47772.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478720] width 1280 pitch 5120 (/4 1280) >[ 47777.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 47777.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 47778.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 47778.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 47778.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bae20] >[ 47778.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bae20] width 1280 pitch 5120 (/4 1280) >[ 47778.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 47778.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 47787.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xf3da10] >[ 47787.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xf3da10] width 1280 pitch 5120 (/4 1280) >[ 47787.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ecf00] >[ 47787.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ecf00] width 1280 pitch 5120 (/4 1280) >[ 47787.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d38830] >[ 47787.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d38830] width 1280 pitch 5120 (/4 1280) >[ 47787.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ecf00] >[ 47787.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ecf00] width 1280 pitch 5120 (/4 1280) >[ 47787.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d38830] >[ 47787.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d38830] width 1280 pitch 5120 (/4 1280) >[ 47787.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ecf00] >[ 47787.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ecf00] width 1280 pitch 5120 (/4 1280) >[ 47787.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d38830] >[ 47787.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d38830] width 1280 pitch 5120 (/4 1280) >[ 47788.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ecf00] >[ 47788.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ecf00] width 1280 pitch 5120 (/4 1280) >[ 47788.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d38830] >[ 47788.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d38830] width 1280 pitch 5120 (/4 1280) >[ 47788.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24afb20] >[ 47788.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24afb20] width 1280 pitch 5120 (/4 1280) >[ 47788.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478720] >[ 47788.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478720] width 1280 pitch 5120 (/4 1280) >[ 47788.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bae20] >[ 47788.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bae20] width 1280 pitch 5120 (/4 1280) >[ 47788.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478720] >[ 47788.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478720] width 1280 pitch 5120 (/4 1280) >[ 47788.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b5d0] >[ 47788.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b5d0] width 1280 pitch 5120 (/4 1280) >[ 47788.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1478720] >[ 47788.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1478720] width 1280 pitch 5120 (/4 1280) >[ 47844.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9760] >[ 47844.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9760] width 1280 pitch 5120 (/4 1280) >[ 47845.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec0900] >[ 47845.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec0900] width 1280 pitch 5120 (/4 1280) >[ 47871.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3b40] >[ 47871.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3b40] width 1280 pitch 5120 (/4 1280) >[ 47871.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11342a0] >[ 47871.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11342a0] width 1280 pitch 5120 (/4 1280) >[ 47985.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b35ff0] >[ 47985.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b35ff0] width 1280 pitch 5120 (/4 1280) >[ 47986.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3890] >[ 47986.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3890] width 1280 pitch 5120 (/4 1280) >[ 47987.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b35ff0] >[ 47987.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b35ff0] width 1280 pitch 5120 (/4 1280) >[ 47987.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3890] >[ 47987.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3890] width 1280 pitch 5120 (/4 1280) >[ 48025.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11cdb00] >[ 48025.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11cdb00] width 1280 pitch 5120 (/4 1280) >[ 48025.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11342a0] >[ 48025.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11342a0] width 1280 pitch 5120 (/4 1280) >[ 48337.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a3e0] >[ 48337.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a3e0] width 1280 pitch 5120 (/4 1280) >[ 48337.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a3e0] >[ 48337.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a3e0] width 1280 pitch 5120 (/4 1280) >[ 48337.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a3e0] >[ 48337.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a3e0] width 1280 pitch 5120 (/4 1280) >[ 48337.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a3e0] >[ 48337.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a3e0] width 1280 pitch 5120 (/4 1280) >[ 48337.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48337.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48337.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48337.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48337.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48337.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48337.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48337.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48337.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48337.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48337.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48337.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48337.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48337.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95ab0] >[ 48338.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48338.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48338.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48338.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48338.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48339.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48339.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48339.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48339.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48339.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48339.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48339.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48339.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48339.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48339.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48339.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48339.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48339.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48339.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48339.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48339.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48340.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48340.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48340.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48340.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1342490] >[ 48341.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1342490] width 1280 pitch 5120 (/4 1280) >[ 48341.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48341.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48341.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48341.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48341.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48341.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48341.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48341.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48341.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48341.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48341.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48341.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48341.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48341.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48341.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48341.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48341.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48341.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48341.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c20e0] >[ 48341.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c20e0] width 1280 pitch 5120 (/4 1280) >[ 48342.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248b9e0] >[ 48342.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248b9e0] width 1280 pitch 5120 (/4 1280) >[ 48342.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48342.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48342.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48342.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48342.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48344.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48344.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48344.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48344.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48346.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48346.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48346.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48346.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48347.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48347.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48347.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48347.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48348.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48348.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48348.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48348.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48348.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48348.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48348.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48348.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48348.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48348.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48348.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48348.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48349.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48349.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48349.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48349.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48349.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f6ab0] >[ 48349.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f6ab0] width 1280 pitch 5120 (/4 1280) >[ 48349.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c20e0] >[ 48349.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c20e0] width 1280 pitch 5120 (/4 1280) >[ 48350.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48350.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48350.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c20e0] >[ 48350.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c20e0] width 1280 pitch 5120 (/4 1280) >[ 48350.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48350.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48350.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c20e0] >[ 48350.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c20e0] width 1280 pitch 5120 (/4 1280) >[ 48350.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a3c30] >[ 48350.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a3c30] width 1280 pitch 5120 (/4 1280) >[ 48381.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2424a50] >[ 48381.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2424a50] width 1280 pitch 5120 (/4 1280) >[ 48417.892] [mi] Increasing EQ size to 512 to prevent dropped events. >[ 49040.735] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 49040.735] (II) RADEON(0): Printing DDC gathered Modelines: >[ 49040.735] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 49130.886] (II) RADEON(0): RADEONSaveScreen(2) >[ 49130.887] (II) RADEON(0): RADEONSaveScreen(0) >[ 49785.386] (II) RADEON(0): RADEONSaveScreen(1) >[ 49792.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14c20e0] >[ 49792.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14c20e0] width 1280 pitch 5120 (/4 1280) >[ 49856.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[ 49856.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[ 49908.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[ 49908.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[ 49908.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23185d0] >[ 49908.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23185d0] width 1280 pitch 5120 (/4 1280) >[ 50051.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d88740] >[ 50051.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d88740] width 1280 pitch 5120 (/4 1280) >[ 50056.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x116dd00] >[ 50056.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x116dd00] width 1280 pitch 5120 (/4 1280) >[ 50184.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2597ac0] >[ 50184.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2597ac0] width 1280 pitch 5120 (/4 1280) >[ 50215.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c2280] >[ 50215.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c2280] width 1280 pitch 5120 (/4 1280) >[ 50215.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2597ac0] >[ 50215.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2597ac0] width 1280 pitch 5120 (/4 1280) >[ 50215.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26be790] >[ 50215.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26be790] width 1280 pitch 5120 (/4 1280) >[ 50217.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2597ac0] >[ 50217.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2597ac0] width 1280 pitch 5120 (/4 1280) >[ 50277.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3a20] >[ 50277.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3a20] width 1280 pitch 5120 (/4 1280) >[ 50363.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231d980] >[ 50363.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231d980] width 1280 pitch 5120 (/4 1280) >[ 50364.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d52fc0] >[ 50364.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d52fc0] width 1280 pitch 5120 (/4 1280) >[ 50483.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8850] >[ 50483.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8850] width 1280 pitch 5120 (/4 1280) >[ 50483.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4af0] >[ 50483.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4af0] width 1280 pitch 5120 (/4 1280) >[ 50909.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x232aac0] >[ 50909.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x232aac0] width 1280 pitch 5120 (/4 1280) >[ 50909.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x232acd0] >[ 50909.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x232acd0] width 1280 pitch 5120 (/4 1280) >[ 51353.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1265050] >[ 51353.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1265050] width 1280 pitch 5120 (/4 1280) >[ 51353.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2595900] >[ 51353.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2595900] width 1280 pitch 5120 (/4 1280) >[ 51457.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2479350] >[ 51457.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2479350] width 1280 pitch 5120 (/4 1280) >[ 51457.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22f2690] >[ 51457.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22f2690] width 1280 pitch 5120 (/4 1280) >[ 51470.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x125d680] >[ 51470.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x125d680] width 1280 pitch 5120 (/4 1280) >[ 51470.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51470.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51474.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51474.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51474.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51474.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51475.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51475.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f600] >[ 51475.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f600] width 1280 pitch 5120 (/4 1280) >[ 51475.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x116d890] >[ 51475.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x116d890] width 1280 pitch 5120 (/4 1280) >[ 51475.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51475.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22e9400] >[ 51475.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22e9400] width 1280 pitch 5120 (/4 1280) >[ 51475.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51475.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51488.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51488.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51488.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[ 51488.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[ 51488.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25099e0] >[ 51488.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25099e0] width 1280 pitch 5120 (/4 1280) >[ 51488.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51488.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51511.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e2e00] >[ 51511.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e2e00] width 1280 pitch 5120 (/4 1280) >[ 51511.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1243ff0] >[ 51511.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1243ff0] width 1280 pitch 5120 (/4 1280) >[ 51521.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11eaea0] >[ 51521.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11eaea0] width 1280 pitch 5120 (/4 1280) >[ 51531.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26969e0] >[ 51531.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26969e0] width 1280 pitch 5120 (/4 1280) >[ 51566.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265f710] >[ 51566.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265f710] width 1280 pitch 5120 (/4 1280) >[ 51567.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2697510] >[ 51567.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2697510] width 1280 pitch 5120 (/4 1280) >[ 51598.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a600] >[ 51598.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a600] width 1280 pitch 5120 (/4 1280) >[ 51598.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699210] >[ 51598.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699210] width 1280 pitch 5120 (/4 1280) >[ 51601.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699ba0] >[ 51601.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699ba0] width 1280 pitch 5120 (/4 1280) >[ 51601.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2697140] >[ 51601.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2697140] width 1280 pitch 5120 (/4 1280) >[ 51639.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699ba0] >[ 51639.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699ba0] width 1280 pitch 5120 (/4 1280) >[ 51639.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d04f10] >[ 51639.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d04f10] width 1280 pitch 5120 (/4 1280) >[ 51771.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2334370] >[ 51771.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2334370] width 1280 pitch 5120 (/4 1280) >[ 51779.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2334370] >[ 51779.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2334370] width 1280 pitch 5120 (/4 1280) >[ 51789.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbbcc0] >[ 51789.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbbcc0] width 1280 pitch 5120 (/4 1280) >[ 51941.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23fdc80] >[ 51941.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23fdc80] width 1280 pitch 5120 (/4 1280) >[ 51941.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b97e70] >[ 51941.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b97e70] width 1280 pitch 5120 (/4 1280) >[ 52153.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1500] >[ 52153.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1500] width 1280 pitch 5120 (/4 1280) >[ 52230.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52230.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52231.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52231.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52232.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dba80] >[ 52232.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dba80] width 1280 pitch 5120 (/4 1280) >[ 52232.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52232.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52236.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52236.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52429.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52429.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b66e0] >[ 52429.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b66e0] width 1280 pitch 5120 (/4 1280) >[ 52429.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52429.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52429.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52429.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52429.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52429.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52429.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52429.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52429.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52430.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52430.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52430.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52430.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52430.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52430.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52430.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52430.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52430.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c8b0d0] >[ 52430.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c8b0d0] width 1280 pitch 5120 (/4 1280) >[ 52430.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52430.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52431.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a200] >[ 52431.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a200] width 1280 pitch 5120 (/4 1280) >[ 52432.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14b1070] >[ 52432.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14b1070] width 1280 pitch 5120 (/4 1280) >[ 52432.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a200] >[ 52432.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a200] width 1280 pitch 5120 (/4 1280) >[ 52432.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 52432.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 52432.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52432.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52432.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52432.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52432.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52432.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52433.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2687000] >[ 52433.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2687000] width 1280 pitch 5120 (/4 1280) >[ 52433.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52433.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52433.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52433.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52433.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52433.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52433.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52433.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52433.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52439.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52439.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52439.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52439.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52440.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52440.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52440.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52440.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52440.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52440.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52440.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52440.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52440.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52440.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52440.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52440.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52440.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52440.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52441.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52441.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52441.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52441.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52441.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52441.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52441.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52441.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52441.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52441.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52442.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a080] >[ 52442.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a080] width 1280 pitch 5120 (/4 1280) >[ 52442.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed230] >[ 52442.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed230] width 1280 pitch 5120 (/4 1280) >[ 52443.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52443.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52443.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2687000] >[ 52443.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2687000] width 1280 pitch 5120 (/4 1280) >[ 52443.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52443.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52443.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2687000] >[ 52444.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2687000] width 1280 pitch 5120 (/4 1280) >[ 52444.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52444.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52444.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2687000] >[ 52444.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2687000] width 1280 pitch 5120 (/4 1280) >[ 52444.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52444.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52444.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af9430] >[ 52444.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af9430] width 1280 pitch 5120 (/4 1280) >[ 52583.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52583.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52583.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52584.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52584.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52584.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52584.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52584.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52584.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52584.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52584.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52584.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52584.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a200] >[ 52584.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a200] width 1280 pitch 5120 (/4 1280) >[ 52584.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x142a200] >[ 52584.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x142a200] width 1280 pitch 5120 (/4 1280) >[ 52584.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52584.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52584.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52584.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52584.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52584.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52584.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52584.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52584.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52584.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52584.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52584.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52584.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52584.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52584.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52584.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52584.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2570] >[ 52584.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2570] width 1280 pitch 5120 (/4 1280) >[ 52584.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52584.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52584.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2570] >[ 52584.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2570] width 1280 pitch 5120 (/4 1280) >[ 52584.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52584.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52584.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2570] >[ 52584.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2570] width 1280 pitch 5120 (/4 1280) >[ 52587.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52587.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52587.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52587.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267aa00] >[ 52587.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267aa00] width 1280 pitch 5120 (/4 1280) >[ 52589.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52589.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52589.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49c30] >[ 52589.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49c30] width 1280 pitch 5120 (/4 1280) >[ 52589.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52589.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52589.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49c30] >[ 52589.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49c30] width 1280 pitch 5120 (/4 1280) >[ 52589.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52589.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52589.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49c30] >[ 52589.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49c30] width 1280 pitch 5120 (/4 1280) >[ 52589.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52589.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52589.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49c30] >[ 52589.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49c30] width 1280 pitch 5120 (/4 1280) >[ 52589.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bf630] >[ 52589.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bf630] width 1280 pitch 5120 (/4 1280) >[ 52589.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49c30] >[ 52589.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49c30] width 1280 pitch 5120 (/4 1280) >[ 52590.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22f7e40] >[ 52590.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22f7e40] width 1280 pitch 5120 (/4 1280) >[ 52590.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f403b0] >[ 52590.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f403b0] width 1280 pitch 5120 (/4 1280) >[ 52590.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52590.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52590.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2570] >[ 52590.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2570] width 1280 pitch 5120 (/4 1280) >[ 52590.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52591.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52591.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 52591.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 52591.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ddef0] >[ 52591.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ddef0] width 1280 pitch 5120 (/4 1280) >[ 52591.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 52591.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 52591.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52591.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52591.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da0200] >[ 52591.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da0200] width 1280 pitch 5120 (/4 1280) >[ 52591.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52591.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52591.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191b710] >[ 52591.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191b710] width 1280 pitch 5120 (/4 1280) >[ 52591.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26caaf0] >[ 52591.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26caaf0] width 1280 pitch 5120 (/4 1280) >[ 52592.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 52592.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 52592.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52592.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52592.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52592.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52592.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52592.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52592.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52592.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52592.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52592.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52592.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268a810] >[ 52592.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268a810] width 1280 pitch 5120 (/4 1280) >[ 52592.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ef0b0] >[ 52592.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ef0b0] width 1280 pitch 5120 (/4 1280) >[ 52592.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2654fb0] >[ 52592.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2654fb0] width 1280 pitch 5120 (/4 1280) >[ 52592.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca5e0] >[ 52592.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca5e0] width 1280 pitch 5120 (/4 1280) >[ 52592.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266c4c0] >[ 52592.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266c4c0] width 1280 pitch 5120 (/4 1280) >[ 52592.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26caaf0] >[ 52592.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26caaf0] width 1280 pitch 5120 (/4 1280) >[ 52592.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52592.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2656cc0] >[ 52592.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2656cc0] width 1280 pitch 5120 (/4 1280) >[ 52592.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12b2680] >[ 52592.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12b2680] width 1280 pitch 5120 (/4 1280) >[ 52610.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f12b70] >[ 52610.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f12b70] width 1280 pitch 5120 (/4 1280) >[ 52626.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260dc70] >[ 52626.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260dc70] width 1280 pitch 5120 (/4 1280) >[ 52637.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52637.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52659.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9590] >[ 52659.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9590] width 1280 pitch 5120 (/4 1280) >[ 52660.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52660.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52660.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f86870] >[ 52660.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f86870] width 1280 pitch 5120 (/4 1280) >[ 52660.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52660.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52661.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2051c00] >[ 52661.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2051c00] width 1280 pitch 5120 (/4 1280) >[ 52661.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20528f0] >[ 52661.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20528f0] width 1280 pitch 5120 (/4 1280) >[ 52663.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52663.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52663.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52663.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52663.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20528f0] >[ 52664.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20528f0] width 1280 pitch 5120 (/4 1280) >[ 52664.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2051dc0] >[ 52664.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2051dc0] width 1280 pitch 5120 (/4 1280) >[ 52664.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266e710] >[ 52664.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266e710] width 1280 pitch 5120 (/4 1280) >[ 52664.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52664.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52664.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266e710] >[ 52664.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266e710] width 1280 pitch 5120 (/4 1280) >[ 52664.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266e710] >[ 52664.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266e710] width 1280 pitch 5120 (/4 1280) >[ 52664.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52664.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52664.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20528f0] >[ 52664.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20528f0] width 1280 pitch 5120 (/4 1280) >[ 52664.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f87750] >[ 52664.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f87750] width 1280 pitch 5120 (/4 1280) >[ 52664.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138b510] >[ 52664.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138b510] width 1280 pitch 5120 (/4 1280) >[ 52664.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa9ac0] >[ 52664.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa9ac0] width 1280 pitch 5120 (/4 1280) >[ 52669.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2051dc0] >[ 52669.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2051dc0] width 1280 pitch 5120 (/4 1280) >[ 52700.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f19500] >[ 52700.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f19500] width 1280 pitch 5120 (/4 1280) >[ 52700.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a50d0] >[ 52700.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a50d0] width 1280 pitch 5120 (/4 1280) >[ 52700.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a5450] >[ 52700.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a5450] width 1280 pitch 5120 (/4 1280) >[ 52700.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb7060] >[ 52700.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb7060] width 1280 pitch 5120 (/4 1280) >[ 52700.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 52700.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 52710.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbab20] >[ 52710.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbab20] width 1280 pitch 5120 (/4 1280) >[ 52744.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb1d40] >[ 52744.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb1d40] width 1280 pitch 5120 (/4 1280) >[ 52744.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 52744.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 52744.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 52744.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 52744.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 52744.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 52744.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 52744.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 52744.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209e370] >[ 52744.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209e370] width 1280 pitch 5120 (/4 1280) >[ 52744.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209e370] >[ 52744.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209e370] width 1280 pitch 5120 (/4 1280) >[ 52744.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 52744.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209e370] >[ 52744.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209e370] width 1280 pitch 5120 (/4 1280) >[ 52744.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8230] >[ 52744.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8230] width 1280 pitch 5120 (/4 1280) >[ 53344.404] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 53344.404] (II) RADEON(0): Printing DDC gathered Modelines: >[ 53344.404] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 53434.886] (II) RADEON(0): RADEONSaveScreen(2) >[ 53434.886] (II) RADEON(0): RADEONSaveScreen(0) >[ 58434.108] (II) RADEON(0): RADEONSaveScreen(1) >[ 58441.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58441.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58443.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58443.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58443.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58443.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58443.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58443.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58443.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58443.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58443.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58443.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58443.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58443.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58443.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58443.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58443.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58443.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58443.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58443.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58444.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58444.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58444.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58444.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58444.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311820] >[ 58444.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311820] width 1280 pitch 5120 (/4 1280) >[ 58444.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58444.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58445.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209e900] >[ 58445.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209e900] width 1280 pitch 5120 (/4 1280) >[ 58445.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58445.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58446.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58446.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58446.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 58446.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 58446.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209fc30] >[ 58446.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209fc30] width 1280 pitch 5120 (/4 1280) >[ 58446.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f835c0] >[ 58446.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f835c0] width 1280 pitch 5120 (/4 1280) >[ 58446.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58446.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58446.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311820] >[ 58446.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311820] width 1280 pitch 5120 (/4 1280) >[ 58446.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58446.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58446.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311820] >[ 58446.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311820] width 1280 pitch 5120 (/4 1280) >[ 58446.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58446.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58446.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209fc30] >[ 58447.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209fc30] width 1280 pitch 5120 (/4 1280) >[ 58447.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 58447.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 58447.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2378050] >[ 58447.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2378050] width 1280 pitch 5120 (/4 1280) >[ 58447.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311820] >[ 58447.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311820] width 1280 pitch 5120 (/4 1280) >[ 58447.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58447.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58447.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f14ad0] >[ 58447.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f14ad0] width 1280 pitch 5120 (/4 1280) >[ 58447.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da1580] >[ 58447.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da1580] width 1280 pitch 5120 (/4 1280) >[ 58447.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x209fc30] >[ 58447.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x209fc30] width 1280 pitch 5120 (/4 1280) >[ 58447.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 58447.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 58447.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2378050] >[ 58447.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2378050] width 1280 pitch 5120 (/4 1280) >[ 58447.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58447.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58447.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58447.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58447.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311820] >[ 58447.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311820] width 1280 pitch 5120 (/4 1280) >[ 58447.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58447.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58447.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2378050] >[ 58447.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2378050] width 1280 pitch 5120 (/4 1280) >[ 58448.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 58448.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 58448.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2378050] >[ 58448.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2378050] width 1280 pitch 5120 (/4 1280) >[ 58448.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 58448.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 58448.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 58448.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 58448.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58448.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58448.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58448.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58448.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 58448.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 58448.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58449.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58449.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58449.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58449.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 58449.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 58449.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 58449.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 58449.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194f770] >[ 58449.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194f770] width 1280 pitch 5120 (/4 1280) >[ 58463.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679a00] >[ 58463.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679a00] width 1280 pitch 5120 (/4 1280) >[ 58516.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38820] >[ 58516.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38820] width 1280 pitch 5120 (/4 1280) >[ 58516.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2675c20] >[ 58516.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2675c20] width 1280 pitch 5120 (/4 1280) >[ 58522.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38e20] >[ 58522.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38e20] width 1280 pitch 5120 (/4 1280) >[ 58549.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f381e0] >[ 58549.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f381e0] width 1280 pitch 5120 (/4 1280) >[ 59179.305] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 59179.305] (II) RADEON(0): Printing DDC gathered Modelines: >[ 59179.305] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 59269.906] (II) RADEON(0): RADEONSaveScreen(2) >[ 59269.906] (II) RADEON(0): RADEONSaveScreen(0) >[ 59328.527] (II) RADEON(0): RADEONSaveScreen(1) >[ 59339.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267a100] >[ 59339.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267a100] width 1280 pitch 5120 (/4 1280) >[ 59354.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e35e0] >[ 59354.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e35e0] width 1280 pitch 5120 (/4 1280) >[ 59354.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249ab50] >[ 59354.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249ab50] width 1280 pitch 5120 (/4 1280) >[ 59354.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59354.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59354.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ad120] >[ 59354.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ad120] width 1280 pitch 5120 (/4 1280) >[ 59354.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59354.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59354.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ad120] >[ 59354.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ad120] width 1280 pitch 5120 (/4 1280) >[ 59354.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59354.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59354.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ad120] >[ 59354.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ad120] width 1280 pitch 5120 (/4 1280) >[ 59354.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59354.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59354.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ad120] >[ 59354.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ad120] width 1280 pitch 5120 (/4 1280) >[ 59354.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59354.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59354.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13ad120] >[ 59354.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13ad120] width 1280 pitch 5120 (/4 1280) >[ 59363.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f14ad0] >[ 59363.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f14ad0] width 1280 pitch 5120 (/4 1280) >[ 59363.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38e20] >[ 59363.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38e20] width 1280 pitch 5120 (/4 1280) >[ 59363.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59363.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59363.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38e20] >[ 59363.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38e20] width 1280 pitch 5120 (/4 1280) >[ 59363.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59363.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59363.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38e20] >[ 59363.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38e20] width 1280 pitch 5120 (/4 1280) >[ 59363.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59363.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59363.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f38e20] >[ 59363.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f38e20] width 1280 pitch 5120 (/4 1280) >[ 59363.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59363.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59363.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 59363.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 59363.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f76390] >[ 59363.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f76390] width 1280 pitch 5120 (/4 1280) >[ 59363.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb28a0] >[ 59363.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb28a0] width 1280 pitch 5120 (/4 1280) >[ 59363.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59363.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1f2b0] >[ 59363.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1f2b0] width 1280 pitch 5120 (/4 1280) >[ 59363.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb2c30] >[ 59363.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb2c30] width 1280 pitch 5120 (/4 1280) >[ 59659.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1c10] >[ 59659.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1c10] width 1280 pitch 5120 (/4 1280) >[ 59659.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1308220] >[ 59659.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1308220] width 1280 pitch 5120 (/4 1280) >[ 59660.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1c10] >[ 59660.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1c10] width 1280 pitch 5120 (/4 1280) >[ 59660.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1c10] >[ 59660.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1c10] width 1280 pitch 5120 (/4 1280) >[ 59853.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26713e0] >[ 59853.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26713e0] width 1280 pitch 5120 (/4 1280) >[ 59853.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d98c60] >[ 59853.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d98c60] width 1280 pitch 5120 (/4 1280) >[ 59859.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3a930] >[ 59859.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3a930] width 1280 pitch 5120 (/4 1280) >[ 59859.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2054c30] >[ 59859.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2054c30] width 1280 pitch 5120 (/4 1280) >[ 60001.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60001.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60001.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60001.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60001.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60001.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60001.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60001.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60001.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60001.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60001.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60001.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60001.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60001.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60001.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60001.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60001.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60001.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60001.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60001.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60003.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60003.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60003.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60003.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60020.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[ 60020.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[ 60020.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ab5f0] >[ 60020.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ab5f0] width 1280 pitch 5120 (/4 1280) >[ 60057.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f30bd0] >[ 60057.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f30bd0] width 1280 pitch 5120 (/4 1280) >[ 60057.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f303b0] >[ 60057.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f303b0] width 1280 pitch 5120 (/4 1280) >[ 60070.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2692090] >[ 60070.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2692090] width 1280 pitch 5120 (/4 1280) >[ 60070.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22dd0f0] >[ 60070.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22dd0f0] width 1280 pitch 5120 (/4 1280) >[ 60078.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f85a10] >[ 60078.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f85a10] width 1280 pitch 5120 (/4 1280) >[ 60081.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13423a0] >[ 60081.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13423a0] width 1280 pitch 5120 (/4 1280) >[ 60093.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60093.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60094.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2670da0] >[ 60094.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2670da0] width 1280 pitch 5120 (/4 1280) >[ 60094.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60094.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60094.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2670da0] >[ 60094.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2670da0] width 1280 pitch 5120 (/4 1280) >[ 60094.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60094.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60094.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2670da0] >[ 60094.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2670da0] width 1280 pitch 5120 (/4 1280) >[ 60094.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60094.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60094.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2670da0] >[ 60094.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2670da0] width 1280 pitch 5120 (/4 1280) >[ 60094.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60094.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60094.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2670da0] >[ 60094.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2670da0] width 1280 pitch 5120 (/4 1280) >[ 60095.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1439db0] >[ 60095.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1439db0] width 1280 pitch 5120 (/4 1280) >[ 60095.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a8ba0] >[ 60095.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a8ba0] width 1280 pitch 5120 (/4 1280) >[ 60095.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1190] >[ 60095.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1190] width 1280 pitch 5120 (/4 1280) >[ 60095.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f43690] >[ 60095.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f43690] width 1280 pitch 5120 (/4 1280) >[ 60095.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1190] >[ 60095.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1190] width 1280 pitch 5120 (/4 1280) >[ 60095.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f43690] >[ 60095.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f43690] width 1280 pitch 5120 (/4 1280) >[ 60095.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1190] >[ 60095.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1190] width 1280 pitch 5120 (/4 1280) >[ 60095.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a9b0] >[ 60095.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a9b0] width 1280 pitch 5120 (/4 1280) >[ 60100.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a9b0] >[ 60100.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a9b0] width 1280 pitch 5120 (/4 1280) >[ 60100.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a9b0] >[ 60100.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a9b0] width 1280 pitch 5120 (/4 1280) >[ 60189.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f296f0] >[ 60189.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f296f0] width 1280 pitch 5120 (/4 1280) >[ 60189.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f296f0] >[ 60189.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f296f0] width 1280 pitch 5120 (/4 1280) >[ 60189.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26667e0] >[ 60189.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26667e0] width 1280 pitch 5120 (/4 1280) >[ 60189.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60189.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60189.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f296f0] >[ 60189.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f296f0] width 1280 pitch 5120 (/4 1280) >[ 60189.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22dd0f0] >[ 60189.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22dd0f0] width 1280 pitch 5120 (/4 1280) >[ 60189.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f296f0] >[ 60189.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f296f0] width 1280 pitch 5120 (/4 1280) >[ 60189.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60189.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60189.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26667e0] >[ 60189.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26667e0] width 1280 pitch 5120 (/4 1280) >[ 60189.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60189.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60189.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b530] >[ 60189.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b530] width 1280 pitch 5120 (/4 1280) >[ 60189.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26667e0] >[ 60189.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26667e0] width 1280 pitch 5120 (/4 1280) >[ 60189.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f296f0] >[ 60189.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f296f0] width 1280 pitch 5120 (/4 1280) >[ 60189.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60189.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60189.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60189.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60189.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26667e0] >[ 60189.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26667e0] width 1280 pitch 5120 (/4 1280) >[ 60189.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60189.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b530] >[ 60190.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b530] width 1280 pitch 5120 (/4 1280) >[ 60190.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26667e0] >[ 60190.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26667e0] width 1280 pitch 5120 (/4 1280) >[ 60190.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60190.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60190.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60190.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60190.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60190.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60190.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60191.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60191.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f22b20] >[ 60191.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f22b20] width 1280 pitch 5120 (/4 1280) >[ 60191.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60191.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60191.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60191.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60191.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60191.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60191.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60191.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60192.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60192.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60192.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60192.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60192.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60192.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60192.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60192.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60192.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60192.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60192.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60192.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60199.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60199.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60199.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60199.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60199.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60199.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60199.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60199.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60199.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60199.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60199.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60199.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60199.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60199.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60200.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60200.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60200.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60200.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60200.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60200.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60200.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60200.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60200.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60200.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60200.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60200.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60200.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60200.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60200.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60200.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60200.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60200.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60201.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60201.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60201.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60201.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60201.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60201.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60201.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60201.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60201.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60201.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60201.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60201.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60201.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60201.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60202.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60202.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60203.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60203.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60203.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f25ed0] >[ 60203.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f25ed0] width 1280 pitch 5120 (/4 1280) >[ 60203.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60203.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60203.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f25ed0] >[ 60203.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f25ed0] width 1280 pitch 5120 (/4 1280) >[ 60203.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60203.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60203.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60203.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60203.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60203.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60203.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60203.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60204.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60204.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60204.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5de60] >[ 60204.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5de60] width 1280 pitch 5120 (/4 1280) >[ 60204.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f25ed0] >[ 60204.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f25ed0] width 1280 pitch 5120 (/4 1280) >[ 60204.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60204.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60205.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60205.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60205.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29ca0] >[ 60205.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29ca0] width 1280 pitch 5120 (/4 1280) >[ 60205.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129ccf0] >[ 60205.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129ccf0] width 1280 pitch 5120 (/4 1280) >[ 60205.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3d680] >[ 60205.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3d680] width 1280 pitch 5120 (/4 1280) >[ 60294.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f63c10] >[ 60294.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f63c10] width 1280 pitch 5120 (/4 1280) >[ 60294.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f63c10] >[ 60294.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f63c10] width 1280 pitch 5120 (/4 1280) >[ 60365.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199e270] >[ 60365.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199e270] width 1280 pitch 5120 (/4 1280) >[ 60365.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x199e270] >[ 60365.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x199e270] width 1280 pitch 5120 (/4 1280) >[ 60421.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20a32a0] >[ 60421.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20a32a0] width 1280 pitch 5120 (/4 1280) >[ 60478.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f68490] >[ 60478.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f68490] width 1280 pitch 5120 (/4 1280) >[ 60566.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60566.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60566.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60566.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60566.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60566.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60566.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60566.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60566.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60566.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60566.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60566.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60566.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60566.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60567.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60567.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60567.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60567.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60567.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60567.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60567.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60567.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60567.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60567.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60567.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60567.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60567.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60567.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60597.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x193e8b0] >[ 60597.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x193e8b0] width 1280 pitch 5120 (/4 1280) >[ 60597.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2059010] >[ 60597.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2059010] width 1280 pitch 5120 (/4 1280) >[ 60597.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f60620] >[ 60597.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f60620] width 1280 pitch 5120 (/4 1280) >[ 60597.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a7f0] >[ 60597.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a7f0] width 1280 pitch 5120 (/4 1280) >[ 60597.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60597.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60597.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a7f0] >[ 60597.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a7f0] width 1280 pitch 5120 (/4 1280) >[ 60597.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60597.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60598.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a7f0] >[ 60598.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a7f0] width 1280 pitch 5120 (/4 1280) >[ 60598.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60598.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60598.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a7f0] >[ 60598.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a7f0] width 1280 pitch 5120 (/4 1280) >[ 60599.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f517d0] >[ 60599.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f517d0] width 1280 pitch 5120 (/4 1280) >[ 60599.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e3a7f0] >[ 60599.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e3a7f0] width 1280 pitch 5120 (/4 1280) >[ 60599.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4e380] >[ 60599.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4e380] width 1280 pitch 5120 (/4 1280) >[ 60599.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7ee0] >[ 60599.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7ee0] width 1280 pitch 5120 (/4 1280) >[ 60599.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f655b0] >[ 60599.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f655b0] width 1280 pitch 5120 (/4 1280) >[ 60599.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7ee0] >[ 60599.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7ee0] width 1280 pitch 5120 (/4 1280) >[ 60599.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f655b0] >[ 60599.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f655b0] width 1280 pitch 5120 (/4 1280) >[ 60599.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7ee0] >[ 60599.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7ee0] width 1280 pitch 5120 (/4 1280) >[ 60599.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f655b0] >[ 60599.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f655b0] width 1280 pitch 5120 (/4 1280) >[ 60734.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f55470] >[ 60734.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f55470] width 1280 pitch 5120 (/4 1280) >[ 60734.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5da70] >[ 60734.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5da70] width 1280 pitch 5120 (/4 1280) >[ 60747.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60747.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d030] >[ 60747.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d030] width 1280 pitch 5120 (/4 1280) >[ 60747.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20499f0] >[ 60747.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20499f0] width 1280 pitch 5120 (/4 1280) >[ 60941.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f50cd0] >[ 60941.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f50cd0] width 1280 pitch 5120 (/4 1280) >[ 60941.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6aa80] >[ 60941.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6aa80] width 1280 pitch 5120 (/4 1280) >[ 61025.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61025.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61025.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61025.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61025.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61026.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61026.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61026.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61026.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61027.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61027.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61027.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61027.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61027.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61027.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61027.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61027.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61027.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61027.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61027.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61027.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61027.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61027.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61027.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61027.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61027.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6ffa0] >[ 61027.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6ffa0] width 1280 pitch 5120 (/4 1280) >[ 61027.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11d3660] >[ 61027.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11d3660] width 1280 pitch 5120 (/4 1280) >[ 61028.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5d5f0] >[ 61028.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5d5f0] width 1280 pitch 5120 (/4 1280) >[ 61029.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f51360] >[ 61029.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f51360] width 1280 pitch 5120 (/4 1280) >[ 61029.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200ace0] >[ 61029.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200ace0] width 1280 pitch 5120 (/4 1280) >[ 61029.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2069c10] >[ 61029.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2069c10] width 1280 pitch 5120 (/4 1280) >[ 61029.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4f760] >[ 61029.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4f760] width 1280 pitch 5120 (/4 1280) >[ 61029.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a570] >[ 61029.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a570] width 1280 pitch 5120 (/4 1280) >[ 61029.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5d5f0] >[ 61029.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5d5f0] width 1280 pitch 5120 (/4 1280) >[ 61029.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20463b0] >[ 61029.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20463b0] width 1280 pitch 5120 (/4 1280) >[ 61029.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20463b0] >[ 61029.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20463b0] width 1280 pitch 5120 (/4 1280) >[ 61029.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20463b0] >[ 61029.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20463b0] width 1280 pitch 5120 (/4 1280) >[ 61029.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20463b0] >[ 61029.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20463b0] width 1280 pitch 5120 (/4 1280) >[ 61029.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20463b0] >[ 61029.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20463b0] width 1280 pitch 5120 (/4 1280) >[ 61029.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2046960] >[ 61029.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2046960] width 1280 pitch 5120 (/4 1280) >[ 61029.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2046960] >[ 61029.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2046960] width 1280 pitch 5120 (/4 1280) >[ 61029.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2046960] >[ 61029.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2046960] width 1280 pitch 5120 (/4 1280) >[ 61029.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2046960] >[ 61029.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2046960] width 1280 pitch 5120 (/4 1280) >[ 61029.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61029.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2046960] >[ 61029.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2046960] width 1280 pitch 5120 (/4 1280) >[ 61029.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61029.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266a570] >[ 61057.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266a570] width 1280 pitch 5120 (/4 1280) >[ 61057.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61057.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61057.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61057.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61057.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4f760] >[ 61058.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4f760] width 1280 pitch 5120 (/4 1280) >[ 61058.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4f760] >[ 61058.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4f760] width 1280 pitch 5120 (/4 1280) >[ 61058.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61058.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61058.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61058.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61058.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61058.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61058.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61058.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61058.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61058.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61058.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61058.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61058.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61058.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61058.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61058.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61059.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61059.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61059.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61059.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61059.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61059.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61059.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61059.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61059.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61059.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61059.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61059.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61059.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61059.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61059.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61059.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61059.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61059.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61059.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61059.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61060.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4fc20] >[ 61060.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4fc20] width 1280 pitch 5120 (/4 1280) >[ 61060.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200a3b0] >[ 61060.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200a3b0] width 1280 pitch 5120 (/4 1280) >[ 61060.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2009740] >[ 61060.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2009740] width 1280 pitch 5120 (/4 1280) >[ 61060.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61060.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61060.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2009740] >[ 61060.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2009740] width 1280 pitch 5120 (/4 1280) >[ 61060.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 61060.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 61060.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2009740] >[ 61060.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2009740] width 1280 pitch 5120 (/4 1280) >[ 61089.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e2c0] >[ 61089.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e2c0] width 1280 pitch 5120 (/4 1280) >[ 61089.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61089.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61089.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e2c0] >[ 61089.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e2c0] width 1280 pitch 5120 (/4 1280) >[ 61089.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bda0] >[ 61089.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bda0] width 1280 pitch 5120 (/4 1280) >[ 61196.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61196.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61196.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61196.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61196.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61196.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61196.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61196.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61196.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61196.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61196.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61196.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61196.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61196.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61196.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61196.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61197.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61197.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61197.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61197.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61197.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61197.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61198.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61198.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61198.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61198.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61198.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61198.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61198.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bcd0] >[ 61198.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bcd0] width 1280 pitch 5120 (/4 1280) >[ 61198.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61198.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61198.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bcd0] >[ 61198.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bcd0] width 1280 pitch 5120 (/4 1280) >[ 61198.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61199.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61199.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bcd0] >[ 61199.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bcd0] width 1280 pitch 5120 (/4 1280) >[ 61199.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61199.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61199.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bcd0] >[ 61199.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bcd0] width 1280 pitch 5120 (/4 1280) >[ 61199.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61199.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61200.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206bcd0] >[ 61200.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206bcd0] width 1280 pitch 5120 (/4 1280) >[ 61200.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2075920] >[ 61200.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2075920] width 1280 pitch 5120 (/4 1280) >[ 61200.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61200.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61200.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2075920] >[ 61200.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2075920] width 1280 pitch 5120 (/4 1280) >[ 61200.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61200.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61200.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61200.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61200.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f65510] >[ 61200.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f65510] width 1280 pitch 5120 (/4 1280) >[ 61201.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61201.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61201.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61201.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61202.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x203a1d0] >[ 61202.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x203a1d0] width 1280 pitch 5120 (/4 1280) >[ 61206.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x203a1d0] >[ 61206.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x203a1d0] width 1280 pitch 5120 (/4 1280) >[ 61206.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61206.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61206.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61206.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61206.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61206.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61206.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61206.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61206.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61206.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61206.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61206.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61206.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61206.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61208.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2027e30] >[ 61208.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2027e30] width 1280 pitch 5120 (/4 1280) >[ 61216.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2027e30] >[ 61216.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2027e30] width 1280 pitch 5120 (/4 1280) >[ 61278.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20222e0] >[ 61278.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20222e0] width 1280 pitch 5120 (/4 1280) >[ 61278.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61278.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2016250] >[ 61278.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2016250] width 1280 pitch 5120 (/4 1280) >[ 61278.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61278.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61280.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61280.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61280.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c0c0] >[ 61280.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c0c0] width 1280 pitch 5120 (/4 1280) >[ 61280.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61280.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61280.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c0c0] >[ 61280.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c0c0] width 1280 pitch 5120 (/4 1280) >[ 61280.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200b590] >[ 61280.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200b590] width 1280 pitch 5120 (/4 1280) >[ 61296.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202fc40] >[ 61296.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202fc40] width 1280 pitch 5120 (/4 1280) >[ 61297.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61297.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61297.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202fc40] >[ 61297.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202fc40] width 1280 pitch 5120 (/4 1280) >[ 61297.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61297.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61297.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202fc40] >[ 61297.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202fc40] width 1280 pitch 5120 (/4 1280) >[ 61297.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61297.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61297.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202fc40] >[ 61297.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202fc40] width 1280 pitch 5120 (/4 1280) >[ 61297.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61297.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61298.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202fc40] >[ 61298.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202fc40] width 1280 pitch 5120 (/4 1280) >[ 61298.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1971a00] >[ 61298.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1971a00] width 1280 pitch 5120 (/4 1280) >[ 61298.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c461a0] >[ 61298.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c461a0] width 1280 pitch 5120 (/4 1280) >[ 61298.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61298.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61298.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c461a0] >[ 61298.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c461a0] width 1280 pitch 5120 (/4 1280) >[ 61298.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20633b0] >[ 61298.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20633b0] width 1280 pitch 5120 (/4 1280) >[ 61298.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61298.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61298.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4bcd0] >[ 61298.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4bcd0] width 1280 pitch 5120 (/4 1280) >[ 61305.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1971a00] >[ 61305.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1971a00] width 1280 pitch 5120 (/4 1280) >[ 61305.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1971a00] >[ 61305.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1971a00] width 1280 pitch 5120 (/4 1280) >[ 61315.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e20390] >[ 61315.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e20390] width 1280 pitch 5120 (/4 1280) >[ 61315.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20753e0] >[ 61315.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20753e0] width 1280 pitch 5120 (/4 1280) >[ 61315.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b2c0] >[ 61315.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b2c0] width 1280 pitch 5120 (/4 1280) >[ 61315.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1a400] >[ 61315.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1a400] width 1280 pitch 5120 (/4 1280) >[ 61316.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bdc10] >[ 61316.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bdc10] width 1280 pitch 5120 (/4 1280) >[ 61319.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1b2c0] >[ 61319.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1b2c0] width 1280 pitch 5120 (/4 1280) >[ 61319.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14b9470] >[ 61319.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14b9470] width 1280 pitch 5120 (/4 1280) >[ 61319.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x110da50] >[ 61319.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x110da50] width 1280 pitch 5120 (/4 1280) >[ 61409.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe670] >[ 61409.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe670] width 1280 pitch 5120 (/4 1280) >[ 61410.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61410.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61411.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f714b0] >[ 61411.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f714b0] width 1280 pitch 5120 (/4 1280) >[ 61411.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f714b0] >[ 61411.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f714b0] width 1280 pitch 5120 (/4 1280) >[ 61411.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61411.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61413.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61413.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61413.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f7ca40] >[ 61413.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f7ca40] width 1280 pitch 5120 (/4 1280) >[ 61457.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4cab0] >[ 61457.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4cab0] width 1280 pitch 5120 (/4 1280) >[ 61457.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4cab0] >[ 61457.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4cab0] width 1280 pitch 5120 (/4 1280) >[ 61457.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4cab0] >[ 61457.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4cab0] width 1280 pitch 5120 (/4 1280) >[ 61457.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4cab0] >[ 61457.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4cab0] width 1280 pitch 5120 (/4 1280) >[ 61457.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61457.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61457.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61457.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61457.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61458.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61458.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61458.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61458.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61458.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4cab0] >[ 61458.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4cab0] width 1280 pitch 5120 (/4 1280) >[ 61458.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61458.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61458.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206fdd0] >[ 61458.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206fdd0] width 1280 pitch 5120 (/4 1280) >[ 61458.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61458.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61458.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61458.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61458.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61458.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61459.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61459.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61459.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61459.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61459.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61459.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2012890] >[ 61459.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2012890] width 1280 pitch 5120 (/4 1280) >[ 61459.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2012890] >[ 61459.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2012890] width 1280 pitch 5120 (/4 1280) >[ 61459.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2012890] >[ 61459.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2012890] width 1280 pitch 5120 (/4 1280) >[ 61459.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1269220] >[ 61459.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1269220] width 1280 pitch 5120 (/4 1280) >[ 61459.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2012890] >[ 61459.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2012890] width 1280 pitch 5120 (/4 1280) >[ 61459.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2012890] >[ 61459.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2012890] width 1280 pitch 5120 (/4 1280) >[ 61459.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61459.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61459.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61462.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61462.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61478.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61478.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61478.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61478.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61478.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2146dc0] >[ 61478.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2146dc0] width 1280 pitch 5120 (/4 1280) >[ 61478.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61478.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61478.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61478.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61478.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2039d40] >[ 61478.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2039d40] width 1280 pitch 5120 (/4 1280) >[ 61478.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61478.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61478.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61478.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61478.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2039d40] >[ 61478.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2039d40] width 1280 pitch 5120 (/4 1280) >[ 61478.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2146dc0] >[ 61478.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2146dc0] width 1280 pitch 5120 (/4 1280) >[ 61478.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61478.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61478.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61479.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61479.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61479.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61479.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2041940] >[ 61479.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2041940] width 1280 pitch 5120 (/4 1280) >[ 61479.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146da20] >[ 61479.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146da20] width 1280 pitch 5120 (/4 1280) >[ 61479.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61479.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61479.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2041940] >[ 61479.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2041940] width 1280 pitch 5120 (/4 1280) >[ 61479.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146da20] >[ 61479.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146da20] width 1280 pitch 5120 (/4 1280) >[ 61479.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61479.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61479.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61479.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61479.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa4700] >[ 61479.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa4700] width 1280 pitch 5120 (/4 1280) >[ 61479.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2146dc0] >[ 61479.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2146dc0] width 1280 pitch 5120 (/4 1280) >[ 61479.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2039d40] >[ 61479.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2039d40] width 1280 pitch 5120 (/4 1280) >[ 61479.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b83aa0] >[ 61479.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b83aa0] width 1280 pitch 5120 (/4 1280) >[ 61480.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61480.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61480.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2039d40] >[ 61480.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2039d40] width 1280 pitch 5120 (/4 1280) >[ 61480.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61480.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61480.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2146dc0] >[ 61480.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2146dc0] width 1280 pitch 5120 (/4 1280) >[ 61480.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146da20] >[ 61480.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146da20] width 1280 pitch 5120 (/4 1280) >[ 61480.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2146dc0] >[ 61480.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2146dc0] width 1280 pitch 5120 (/4 1280) >[ 61481.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61481.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61481.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146da20] >[ 61481.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146da20] width 1280 pitch 5120 (/4 1280) >[ 61481.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe5c0] >[ 61481.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe5c0] width 1280 pitch 5120 (/4 1280) >[ 61481.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa4700] >[ 61481.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa4700] width 1280 pitch 5120 (/4 1280) >[ 61481.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146da20] >[ 61481.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146da20] width 1280 pitch 5120 (/4 1280) >[ 61481.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2041940] >[ 61481.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2041940] width 1280 pitch 5120 (/4 1280) >[ 61481.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61481.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61482.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b83aa0] >[ 61482.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b83aa0] width 1280 pitch 5120 (/4 1280) >[ 61482.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d6e0] >[ 61482.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d6e0] width 1280 pitch 5120 (/4 1280) >[ 61482.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b83aa0] >[ 61482.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b83aa0] width 1280 pitch 5120 (/4 1280) >[ 61483.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f59fa0] >[ 61483.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f59fa0] width 1280 pitch 5120 (/4 1280) >[ 61483.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x110cd10] >[ 61483.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x110cd10] width 1280 pitch 5120 (/4 1280) >[ 61483.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61483.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61483.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe8d0] >[ 61483.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe8d0] width 1280 pitch 5120 (/4 1280) >[ 61483.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61483.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61483.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61483.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61483.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26917b0] >[ 61483.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26917b0] width 1280 pitch 5120 (/4 1280) >[ 61486.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61486.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61486.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61486.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61486.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61486.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61486.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61487.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61487.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61487.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61487.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61487.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61487.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61488.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61488.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61488.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61488.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61488.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61488.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61488.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61488.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61488.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61488.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61489.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61489.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61491.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d3c70] >[ 61491.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d3c70] width 1280 pitch 5120 (/4 1280) >[ 61491.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61491.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61491.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe7a0] >[ 61491.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe7a0] width 1280 pitch 5120 (/4 1280) >[ 61491.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61491.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61491.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61491.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61491.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61491.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61492.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61492.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61492.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61492.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61492.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61492.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61492.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61492.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61492.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe7a0] >[ 61492.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe7a0] width 1280 pitch 5120 (/4 1280) >[ 61492.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61492.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61493.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61493.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61494.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61494.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61494.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61494.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61494.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61494.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61494.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61494.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61494.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61494.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61494.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe7a0] >[ 61495.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe7a0] width 1280 pitch 5120 (/4 1280) >[ 61495.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61495.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61495.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe7a0] >[ 61495.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe7a0] width 1280 pitch 5120 (/4 1280) >[ 61495.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fef40] >[ 61495.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fef40] width 1280 pitch 5120 (/4 1280) >[ 61512.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fe7a0] >[ 61512.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fe7a0] width 1280 pitch 5120 (/4 1280) >[ 61512.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61512.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61513.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61513.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61513.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61513.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61513.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61513.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2017c60] >[ 61513.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2017c60] width 1280 pitch 5120 (/4 1280) >[ 61513.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c0410] >[ 61513.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c0410] width 1280 pitch 5120 (/4 1280) >[ 61558.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x201aa90] >[ 61558.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x201aa90] width 1280 pitch 5120 (/4 1280) >[ 61558.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2019a20] >[ 61558.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2019a20] width 1280 pitch 5120 (/4 1280) >[ 61558.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2004150] >[ 61558.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2004150] width 1280 pitch 5120 (/4 1280) >[ 61558.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2004150] >[ 61558.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2004150] width 1280 pitch 5120 (/4 1280) >[ 61558.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x201aa90] >[ 61558.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x201aa90] width 1280 pitch 5120 (/4 1280) >[ 61558.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2004150] >[ 61558.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2004150] width 1280 pitch 5120 (/4 1280) >[ 61558.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2004150] >[ 61558.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2004150] width 1280 pitch 5120 (/4 1280) >[ 61566.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001430] >[ 61566.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001430] width 1280 pitch 5120 (/4 1280) >[ 61566.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001430] >[ 61567.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001430] width 1280 pitch 5120 (/4 1280) >[ 61567.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ff2d0] >[ 61567.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ff2d0] width 1280 pitch 5120 (/4 1280) >[ 61567.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2034c00] >[ 61567.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2034c00] width 1280 pitch 5120 (/4 1280) >[ 61567.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001430] >[ 61567.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001430] width 1280 pitch 5120 (/4 1280) >[ 61567.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11091d0] >[ 61567.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11091d0] width 1280 pitch 5120 (/4 1280) >[ 61567.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2034c00] >[ 61567.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2034c00] width 1280 pitch 5120 (/4 1280) >[ 61567.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b83fc0] >[ 61567.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b83fc0] width 1280 pitch 5120 (/4 1280) >[ 61610.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fca240] >[ 61610.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fca240] width 1280 pitch 5120 (/4 1280) >[ 61610.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84bd0] >[ 61610.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84bd0] width 1280 pitch 5120 (/4 1280) >[ 61611.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2042730] >[ 61611.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2042730] width 1280 pitch 5120 (/4 1280) >[ 61611.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fca240] >[ 61611.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fca240] width 1280 pitch 5120 (/4 1280) >[ 61612.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd3220] >[ 61612.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd3220] width 1280 pitch 5120 (/4 1280) >[ 61612.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61612.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61612.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd3220] >[ 61612.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd3220] width 1280 pitch 5120 (/4 1280) >[ 61614.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fca240] >[ 61614.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fca240] width 1280 pitch 5120 (/4 1280) >[ 61615.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61615.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61615.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84bd0] >[ 61615.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84bd0] width 1280 pitch 5120 (/4 1280) >[ 61615.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2042730] >[ 61615.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2042730] width 1280 pitch 5120 (/4 1280) >[ 61615.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61615.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61615.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61615.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61617.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2042730] >[ 61617.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2042730] width 1280 pitch 5120 (/4 1280) >[ 61617.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fca240] >[ 61617.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fca240] width 1280 pitch 5120 (/4 1280) >[ 61619.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84bd0] >[ 61619.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84bd0] width 1280 pitch 5120 (/4 1280) >[ 61621.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61621.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61621.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84bd0] >[ 61621.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84bd0] width 1280 pitch 5120 (/4 1280) >[ 61621.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61621.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61628.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61628.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61628.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b9640] >[ 61628.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b9640] width 1280 pitch 5120 (/4 1280) >[ 61628.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25091a0] >[ 61628.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25091a0] width 1280 pitch 5120 (/4 1280) >[ 61629.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x110a990] >[ 61629.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x110a990] width 1280 pitch 5120 (/4 1280) >[ 61633.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f1b310] >[ 61633.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f1b310] width 1280 pitch 5120 (/4 1280) >[ 61633.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb0300] >[ 61633.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb0300] width 1280 pitch 5120 (/4 1280) >[ 61634.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131c290] >[ 61634.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131c290] width 1280 pitch 5120 (/4 1280) >[ 61634.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115f670] >[ 61634.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115f670] width 1280 pitch 5120 (/4 1280) >[ 61634.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2097680] >[ 61634.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2097680] width 1280 pitch 5120 (/4 1280) >[ 61634.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84bd0] >[ 61634.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84bd0] width 1280 pitch 5120 (/4 1280) >[ 61634.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x116b040] >[ 61634.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x116b040] width 1280 pitch 5120 (/4 1280) >[ 61634.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb0300] >[ 61634.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb0300] width 1280 pitch 5120 (/4 1280) >[ 61635.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fca240] >[ 61635.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fca240] width 1280 pitch 5120 (/4 1280) >[ 61635.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131c290] >[ 61635.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131c290] width 1280 pitch 5120 (/4 1280) >[ 61635.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1971a00] >[ 61635.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1971a00] width 1280 pitch 5120 (/4 1280) >[ 61635.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11050d0] >[ 61635.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11050d0] width 1280 pitch 5120 (/4 1280) >[ 62066.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62066.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62066.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62066.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62066.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62066.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62066.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62066.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62066.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265b6a0] >[ 62066.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265b6a0] width 1280 pitch 5120 (/4 1280) >[ 62066.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62066.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62066.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ed90] >[ 62066.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ed90] width 1280 pitch 5120 (/4 1280) >[ 62066.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2419c90] >[ 62066.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2419c90] width 1280 pitch 5120 (/4 1280) >[ 62066.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2659fc0] >[ 62066.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2659fc0] width 1280 pitch 5120 (/4 1280) >[ 62066.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20925c0] >[ 62066.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20925c0] width 1280 pitch 5120 (/4 1280) >[ 62066.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2659fc0] >[ 62066.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2659fc0] width 1280 pitch 5120 (/4 1280) >[ 62066.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62066.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62066.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62066.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62066.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62066.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62066.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62066.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62066.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62066.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62066.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62066.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62067.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62067.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62067.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 62067.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 62067.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62067.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62067.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265b6a0] >[ 62067.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265b6a0] width 1280 pitch 5120 (/4 1280) >[ 62067.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62067.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62067.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2419c90] >[ 62067.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2419c90] width 1280 pitch 5120 (/4 1280) >[ 62067.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62067.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62067.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ed90] >[ 62067.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ed90] width 1280 pitch 5120 (/4 1280) >[ 62067.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62067.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62067.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2659fc0] >[ 62067.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2659fc0] width 1280 pitch 5120 (/4 1280) >[ 62067.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20925c0] >[ 62067.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20925c0] width 1280 pitch 5120 (/4 1280) >[ 62068.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[ 62068.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[ 62068.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1425720] >[ 62068.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1425720] width 1280 pitch 5120 (/4 1280) >[ 62068.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62068.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62068.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62068.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62068.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62068.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62068.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 62068.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 62068.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62068.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62068.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 62068.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 62068.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62068.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62068.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265b6a0] >[ 62068.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265b6a0] width 1280 pitch 5120 (/4 1280) >[ 62068.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62068.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62068.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265b6a0] >[ 62068.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265b6a0] width 1280 pitch 5120 (/4 1280) >[ 62068.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc0d40] >[ 62068.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc0d40] width 1280 pitch 5120 (/4 1280) >[ 62068.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[ 62068.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[ 62068.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62068.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62068.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[ 62068.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[ 62068.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ed90] >[ 62068.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ed90] width 1280 pitch 5120 (/4 1280) >[ 62068.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62068.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62068.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62068.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62068.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62068.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62068.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffa020] >[ 62068.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffa020] width 1280 pitch 5120 (/4 1280) >[ 62068.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62068.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62068.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62069.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62069.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62069.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62069.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62069.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62069.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62069.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62069.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62069.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62069.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62069.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62069.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2011db0] >[ 62069.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2011db0] width 1280 pitch 5120 (/4 1280) >[ 62069.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62069.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62069.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[ 62069.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[ 62069.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f5e1c0] >[ 62069.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f5e1c0] width 1280 pitch 5120 (/4 1280) >[ 62069.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[ 62069.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[ 62072.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20517d0] >[ 62072.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20517d0] width 1280 pitch 5120 (/4 1280) >[ 62074.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 62074.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 62074.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62074.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62074.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 62074.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 62075.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 62075.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 62075.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62075.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62075.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62075.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62075.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62075.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62075.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62075.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62075.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62075.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62075.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62075.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62075.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62075.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62075.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62075.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62075.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62075.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62075.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f050] >[ 62075.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f050] width 1280 pitch 5120 (/4 1280) >[ 62076.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 62076.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 62076.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62076.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62076.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62076.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62076.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62076.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62077.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62077.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62077.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62077.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62077.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62077.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62078.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0190] >[ 62078.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0190] width 1280 pitch 5120 (/4 1280) >[ 62078.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x196b1d0] >[ 62078.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x196b1d0] width 1280 pitch 5120 (/4 1280) >[ 62087.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f6d710] >[ 62087.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f6d710] width 1280 pitch 5120 (/4 1280) >[ 62087.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dbc90] >[ 62087.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dbc90] width 1280 pitch 5120 (/4 1280) >[ 62280.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11de0e0] >[ 62280.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11de0e0] width 1280 pitch 5120 (/4 1280) >[ 62280.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3010] >[ 62280.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3010] width 1280 pitch 5120 (/4 1280) >[ 62449.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2089340] >[ 62449.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2089340] width 1280 pitch 5120 (/4 1280) >[ 62450.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1337100] >[ 62450.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1337100] width 1280 pitch 5120 (/4 1280) >[ 62459.163] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 62459.163] (II) RADEON(0): Printing DDC gathered Modelines: >[ 62459.163] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 63059.167] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 63059.167] (II) RADEON(0): Printing DDC gathered Modelines: >[ 63059.167] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 63149.893] (II) RADEON(0): RADEONSaveScreen(2) >[ 63149.893] (II) RADEON(0): RADEONSaveScreen(0) >[ 90353.036] (II) RADEON(0): RADEONSaveScreen(1) >[ 90367.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0cca0] >[ 90367.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0cca0] width 1280 pitch 5120 (/4 1280) >[ 90367.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90367.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90367.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0cca0] >[ 90367.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0cca0] width 1280 pitch 5120 (/4 1280) >[ 90367.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90367.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90367.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0cca0] >[ 90367.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0cca0] width 1280 pitch 5120 (/4 1280) >[ 90368.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90368.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90368.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0cca0] >[ 90368.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0cca0] width 1280 pitch 5120 (/4 1280) >[ 90368.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90368.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90383.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90383.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90383.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90383.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90383.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90383.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90383.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90383.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90383.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90383.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90383.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90383.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90383.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90383.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90383.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90383.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90383.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90383.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90384.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90384.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90384.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90384.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90384.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90384.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90384.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90384.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90384.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90384.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90386.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90386.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90386.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90386.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90386.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90386.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90386.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90386.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90386.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90386.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90386.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90386.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90386.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90386.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90386.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90386.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90386.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90386.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90387.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90387.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90387.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90387.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90387.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90387.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90387.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90387.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90387.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90387.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90387.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90387.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90387.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90387.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90387.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90387.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90387.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90387.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90387.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90387.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90387.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90387.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90387.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90387.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90436.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90436.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90436.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90436.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90436.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90436.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90436.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90436.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90436.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90436.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90436.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90436.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90436.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90436.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90436.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90436.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90437.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90437.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90437.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90437.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90437.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90437.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90437.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90437.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90437.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90437.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90437.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90437.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90437.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90437.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90437.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90437.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90437.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90437.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90437.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90438.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90438.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90438.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90438.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90438.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90438.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90438.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90438.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90438.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90438.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90438.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90438.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90438.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90438.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90438.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90438.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90438.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90438.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90438.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90438.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90438.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90438.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90438.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90438.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90439.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90439.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90439.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90439.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90439.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90439.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90439.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90439.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90439.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90439.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90439.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bfd0b0] >[ 90439.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bfd0b0] width 1280 pitch 5120 (/4 1280) >[ 90450.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90450.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90450.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90450.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90450.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0bd80] >[ 90450.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0bd80] width 1280 pitch 5120 (/4 1280) >[ 90450.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90450.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90450.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0ca80] >[ 90450.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0ca80] width 1280 pitch 5120 (/4 1280) >[ 90450.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff22f0] >[ 90450.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff22f0] width 1280 pitch 5120 (/4 1280) >[ 90610.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2081c80] >[ 90610.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2081c80] width 1280 pitch 5120 (/4 1280) >[ 90610.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1de10] >[ 90610.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1de10] width 1280 pitch 5120 (/4 1280) >[ 90681.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a6690] >[ 90681.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a6690] width 1280 pitch 5120 (/4 1280) >[ 90681.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1e990] >[ 90681.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1e990] width 1280 pitch 5120 (/4 1280) >[ 90841.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 90841.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 90841.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 90841.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 90841.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 90841.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 90841.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 90841.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 90841.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 90841.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 90841.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 90841.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 90841.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 90841.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 90841.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 90841.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 90841.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 90841.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 90841.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 90841.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 90841.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 90841.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 90841.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 90841.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 90841.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 90841.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91113.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 91113.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 91113.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91113.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91113.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91113.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91113.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91113.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91113.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91113.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91113.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91113.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91113.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91113.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91113.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91113.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91113.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91113.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91113.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91113.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91113.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91113.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91113.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227a1d0] >[ 91113.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227a1d0] width 1280 pitch 5120 (/4 1280) >[ 91113.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91113.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91113.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91113.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91113.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91113.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91114.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91114.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91114.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91114.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91114.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91114.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91114.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 91114.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 91114.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91114.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91114.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91114.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91114.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91114.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91114.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91114.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91114.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91114.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91114.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91114.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91114.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91114.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91114.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91114.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91114.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91114.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91114.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 91114.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 91114.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91114.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91114.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91114.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91120.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91120.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91120.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91120.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91120.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91120.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91120.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227a1d0] >[ 91120.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227a1d0] width 1280 pitch 5120 (/4 1280) >[ 91120.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91120.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91120.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91120.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91120.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91120.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91120.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91120.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91120.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91120.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91120.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91120.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91120.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91120.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91120.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91120.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91120.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91120.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91120.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91120.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91120.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91120.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91120.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91120.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91120.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91120.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91120.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91121.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91121.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227a1d0] >[ 91121.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227a1d0] width 1280 pitch 5120 (/4 1280) >[ 91121.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91121.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91121.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91121.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91121.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91121.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91121.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91121.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91121.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227a1d0] >[ 91121.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227a1d0] width 1280 pitch 5120 (/4 1280) >[ 91121.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91121.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91121.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91121.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91121.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91121.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91121.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91121.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91121.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91121.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91121.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2276c50] >[ 91121.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2276c50] width 1280 pitch 5120 (/4 1280) >[ 91121.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91121.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91121.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91121.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91121.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 91121.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 91121.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91121.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91121.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91121.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91121.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225d930] >[ 91121.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225d930] width 1280 pitch 5120 (/4 1280) >[ 91121.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273ae0] >[ 91121.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273ae0] width 1280 pitch 5120 (/4 1280) >[ 91121.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227a1d0] >[ 91121.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227a1d0] width 1280 pitch 5120 (/4 1280) >[ 91121.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2273f10] >[ 91121.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2273f10] width 1280 pitch 5120 (/4 1280) >[ 91121.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91121.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91121.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91121.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91121.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343490] >[ 91121.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343490] width 1280 pitch 5120 (/4 1280) >[ 91121.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22781b0] >[ 91121.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22781b0] width 1280 pitch 5120 (/4 1280) >[ 91242.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22891d0] >[ 91242.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22891d0] width 1280 pitch 5120 (/4 1280) >[ 91242.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22835a0] >[ 91242.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22835a0] width 1280 pitch 5120 (/4 1280) >[ 91273.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22891d0] >[ 91273.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22891d0] width 1280 pitch 5120 (/4 1280) >[ 91273.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c04280] >[ 91273.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c04280] width 1280 pitch 5120 (/4 1280) >[ 91605.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91605.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91605.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91605.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91605.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d51e0] >[ 91605.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d51e0] width 1280 pitch 5120 (/4 1280) >[ 91605.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91605.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91605.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[ 91605.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[ 91605.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91605.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91606.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91606.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91606.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d51e0] >[ 91606.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d51e0] width 1280 pitch 5120 (/4 1280) >[ 91606.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[ 91606.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[ 91607.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91607.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91607.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91607.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91607.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91607.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91607.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d51e0] >[ 91607.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d51e0] width 1280 pitch 5120 (/4 1280) >[ 91607.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91607.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91622.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91622.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91622.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d71c0] >[ 91622.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d71c0] width 1280 pitch 5120 (/4 1280) >[ 91622.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91622.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91624.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa320] >[ 91624.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa320] width 1280 pitch 5120 (/4 1280) >[ 91624.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa2c0] >[ 91624.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa320] >[ 91624.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa320] width 1280 pitch 5120 (/4 1280) >[ 91624.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa2c0] >[ 91624.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa320] >[ 91624.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa320] width 1280 pitch 5120 (/4 1280) >[ 91624.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa2c0] >[ 91624.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a9b80] >[ 91624.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a9b80] width 1280 pitch 5120 (/4 1280) >[ 91624.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa2c0] >[ 91624.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4e2c0] >[ 91624.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4e2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa2c0] >[ 91624.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4e2c0] >[ 91624.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4e2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91624.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91624.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4e2c0] >[ 91624.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4e2c0] width 1280 pitch 5120 (/4 1280) >[ 91624.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225c070] >[ 91624.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225c070] width 1280 pitch 5120 (/4 1280) >[ 91625.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab070] >[ 91625.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab070] width 1280 pitch 5120 (/4 1280) >[ 91625.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab070] >[ 91625.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab070] width 1280 pitch 5120 (/4 1280) >[ 91625.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab070] >[ 91625.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab070] width 1280 pitch 5120 (/4 1280) >[ 91625.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab070] >[ 91625.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab070] width 1280 pitch 5120 (/4 1280) >[ 91625.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab070] >[ 91625.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab070] width 1280 pitch 5120 (/4 1280) >[ 91625.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f2c0] >[ 91625.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f2c0] width 1280 pitch 5120 (/4 1280) >[ 91625.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e60e0] >[ 91625.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e60e0] width 1280 pitch 5120 (/4 1280) >[ 91625.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21dcf60] >[ 91625.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21dcf60] width 1280 pitch 5120 (/4 1280) >[ 91630.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ac0b0] >[ 91630.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ac0b0] width 1280 pitch 5120 (/4 1280) >[ 91630.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91630.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91630.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ac0b0] >[ 91630.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ac0b0] width 1280 pitch 5120 (/4 1280) >[ 91630.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91630.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91630.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ac0b0] >[ 91630.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ac0b0] width 1280 pitch 5120 (/4 1280) >[ 91630.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91630.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91630.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ac0b0] >[ 91630.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ac0b0] width 1280 pitch 5120 (/4 1280) >[ 91630.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91630.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91630.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ac0b0] >[ 91630.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ac0b0] width 1280 pitch 5120 (/4 1280) >[ 91630.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91630.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91631.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91631.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91631.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa510] >[ 91631.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa510] width 1280 pitch 5120 (/4 1280) >[ 91631.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91631.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91631.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aaff0] >[ 91631.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aaff0] width 1280 pitch 5120 (/4 1280) >[ 91631.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aaff0] >[ 91631.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aaff0] width 1280 pitch 5120 (/4 1280) >[ 91631.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa510] >[ 91631.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa510] width 1280 pitch 5120 (/4 1280) >[ 91631.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aaff0] >[ 91631.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aaff0] width 1280 pitch 5120 (/4 1280) >[ 91631.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa510] >[ 91631.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa510] width 1280 pitch 5120 (/4 1280) >[ 91631.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91631.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91631.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aa510] >[ 91631.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aa510] width 1280 pitch 5120 (/4 1280) >[ 91631.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f390] >[ 91631.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f390] width 1280 pitch 5120 (/4 1280) >[ 91632.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91632.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91633.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d71c0] >[ 91633.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d71c0] width 1280 pitch 5120 (/4 1280) >[ 91633.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d51e0] >[ 91634.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d51e0] width 1280 pitch 5120 (/4 1280) >[ 91634.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[ 91634.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[ 91634.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91634.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91634.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[ 91634.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[ 91634.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91634.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91634.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91634.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91634.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[ 91634.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[ 91634.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91634.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91634.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2278690] >[ 91634.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2278690] width 1280 pitch 5120 (/4 1280) >[ 91634.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91634.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91634.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d71c0] >[ 91634.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d71c0] width 1280 pitch 5120 (/4 1280) >[ 91634.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91634.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91634.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d71c0] >[ 91634.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d71c0] width 1280 pitch 5120 (/4 1280) >[ 91634.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91634.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91670.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[ 91670.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[ 91670.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e9b40] >[ 91670.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e9b40] width 1280 pitch 5120 (/4 1280) >[ 91670.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d7500] >[ 91670.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d7500] width 1280 pitch 5120 (/4 1280) >[ 91670.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91670.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91670.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2253f60] >[ 91670.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2253f60] width 1280 pitch 5120 (/4 1280) >[ 91670.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2255410] >[ 91670.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2255410] width 1280 pitch 5120 (/4 1280) >[ 91670.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224ed60] >[ 91670.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224ed60] width 1280 pitch 5120 (/4 1280) >[ 91670.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2253f60] >[ 91670.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2253f60] width 1280 pitch 5120 (/4 1280) >[ 91671.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224f770] >[ 91671.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224f770] width 1280 pitch 5120 (/4 1280) >[ 91671.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91672.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91672.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224f770] >[ 91672.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224f770] width 1280 pitch 5120 (/4 1280) >[ 91672.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91672.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91672.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224f770] >[ 91672.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224f770] width 1280 pitch 5120 (/4 1280) >[ 91672.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91672.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91672.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224f770] >[ 91672.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224f770] width 1280 pitch 5120 (/4 1280) >[ 91672.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91672.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91672.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e2880] >[ 91672.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e2880] width 1280 pitch 5120 (/4 1280) >[ 91672.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2236fb0] >[ 91672.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2236fb0] width 1280 pitch 5120 (/4 1280) >[ 91672.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e2880] >[ 91672.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e2880] width 1280 pitch 5120 (/4 1280) >[ 91672.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e2880] >[ 91672.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e2880] width 1280 pitch 5120 (/4 1280) >[ 91672.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224f770] >[ 91672.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224f770] width 1280 pitch 5120 (/4 1280) >[ 91690.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff6990] >[ 91690.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff6990] width 1280 pitch 5120 (/4 1280) >[ 91695.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91695.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91695.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1faee90] >[ 91695.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1faee90] width 1280 pitch 5120 (/4 1280) >[ 91695.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117dd70] >[ 91695.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117dd70] width 1280 pitch 5120 (/4 1280) >[ 91695.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff6990] >[ 91695.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff6990] width 1280 pitch 5120 (/4 1280) >[ 91695.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ce2c0] >[ 91695.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ce2c0] width 1280 pitch 5120 (/4 1280) >[ 91695.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117e370] >[ 91695.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117e370] width 1280 pitch 5120 (/4 1280) >[ 91695.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91695.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91695.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117dd70] >[ 91695.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117dd70] width 1280 pitch 5120 (/4 1280) >[ 91695.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1faee90] >[ 91695.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1faee90] width 1280 pitch 5120 (/4 1280) >[ 91695.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff6990] >[ 91695.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff6990] width 1280 pitch 5120 (/4 1280) >[ 91695.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ce2c0] >[ 91695.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ce2c0] width 1280 pitch 5120 (/4 1280) >[ 91696.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91696.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91696.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ce2c0] >[ 91696.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ce2c0] width 1280 pitch 5120 (/4 1280) >[ 91696.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff6990] >[ 91696.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff6990] width 1280 pitch 5120 (/4 1280) >[ 91696.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117e370] >[ 91696.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117e370] width 1280 pitch 5120 (/4 1280) >[ 91696.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91696.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91697.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1faee90] >[ 91697.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1faee90] width 1280 pitch 5120 (/4 1280) >[ 91697.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ce2c0] >[ 91697.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ce2c0] width 1280 pitch 5120 (/4 1280) >[ 91697.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91697.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91697.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1faee90] >[ 91697.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1faee90] width 1280 pitch 5120 (/4 1280) >[ 91697.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117dd70] >[ 91697.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117dd70] width 1280 pitch 5120 (/4 1280) >[ 91697.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff6990] >[ 91697.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff6990] width 1280 pitch 5120 (/4 1280) >[ 91697.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ce2c0] >[ 91697.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ce2c0] width 1280 pitch 5120 (/4 1280) >[ 91697.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a173a0] >[ 91697.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a173a0] width 1280 pitch 5120 (/4 1280) >[ 91924.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2200a40] >[ 91924.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2200a40] width 1280 pitch 5120 (/4 1280) >[ 91924.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2200a40] >[ 91924.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2200a40] width 1280 pitch 5120 (/4 1280) >[ 91958.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f9590] >[ 91958.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f9590] width 1280 pitch 5120 (/4 1280) >[ 91958.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 91958.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92130.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92130.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92131.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92131.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92131.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f5780] >[ 92131.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f5780] width 1280 pitch 5120 (/4 1280) >[ 92131.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92131.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92132.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92132.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92132.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92132.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92132.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92132.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92132.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92132.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92132.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92132.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92132.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92132.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92132.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92132.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92141.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92141.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92142.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f5780] >[ 92142.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f5780] width 1280 pitch 5120 (/4 1280) >[ 92142.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6c210] >[ 92142.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6c210] width 1280 pitch 5120 (/4 1280) >[ 92142.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92142.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92142.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92142.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92142.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92142.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92142.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92142.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92143.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92143.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92144.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92144.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92144.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92144.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92145.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92145.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92145.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92145.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92145.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22111d0] >[ 92145.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22111d0] width 1280 pitch 5120 (/4 1280) >[ 92145.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92145.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92145.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22111d0] >[ 92145.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22111d0] width 1280 pitch 5120 (/4 1280) >[ 92145.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92145.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92167.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92167.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92167.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92167.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92167.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92167.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92167.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fd4a0] >[ 92167.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fd4a0] width 1280 pitch 5120 (/4 1280) >[ 92167.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92167.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92167.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f5780] >[ 92167.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f5780] width 1280 pitch 5120 (/4 1280) >[ 92167.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92167.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92167.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92167.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92167.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92167.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92167.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2213660] >[ 92167.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2213660] width 1280 pitch 5120 (/4 1280) >[ 92167.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92167.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92167.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92167.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92167.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92167.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92167.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92167.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92168.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6c210] >[ 92168.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6c210] width 1280 pitch 5120 (/4 1280) >[ 92169.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92169.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92169.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fd4a0] >[ 92169.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fd4a0] width 1280 pitch 5120 (/4 1280) >[ 92169.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92169.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92170.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92170.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92170.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92170.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92170.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f5780] >[ 92170.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f5780] width 1280 pitch 5120 (/4 1280) >[ 92170.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92170.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92170.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6c210] >[ 92170.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6c210] width 1280 pitch 5120 (/4 1280) >[ 92170.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92170.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92170.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2213660] >[ 92170.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2213660] width 1280 pitch 5120 (/4 1280) >[ 92196.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92196.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92196.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92196.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92299.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92299.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92299.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92299.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92299.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92299.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92299.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92299.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92299.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92299.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92299.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92299.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92299.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92299.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92299.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92299.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92299.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92299.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92300.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92300.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92300.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92300.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92300.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92300.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92300.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92300.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92301.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92301.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92301.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92301.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92301.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[ 92301.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[ 92301.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92301.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92301.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92301.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92301.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92301.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92301.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc640] >[ 92301.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc640] width 1280 pitch 5120 (/4 1280) >[ 92301.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92301.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92303.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92303.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92303.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92303.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92303.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92303.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92303.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92303.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92303.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0a080] >[ 92303.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0a080] width 1280 pitch 5120 (/4 1280) >[ 92303.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92303.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92303.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0a080] >[ 92303.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0a080] width 1280 pitch 5120 (/4 1280) >[ 92303.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92303.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92303.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92303.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92304.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15ef0] >[ 92304.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15ef0] width 1280 pitch 5120 (/4 1280) >[ 92304.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92304.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92304.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92304.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92304.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92304.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92304.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92304.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92304.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92304.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92304.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92304.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92304.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2211f00] >[ 92304.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2211f00] width 1280 pitch 5120 (/4 1280) >[ 92304.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92304.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92304.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2211f00] >[ 92304.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2211f00] width 1280 pitch 5120 (/4 1280) >[ 92304.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92305.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92305.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92305.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92305.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92305.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92305.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92305.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92305.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92305.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92305.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92305.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92305.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92305.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92305.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21faf80] >[ 92305.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21faf80] width 1280 pitch 5120 (/4 1280) >[ 92305.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92305.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92305.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf990] >[ 92305.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf990] width 1280 pitch 5120 (/4 1280) >[ 92305.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15ef0] >[ 92305.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15ef0] width 1280 pitch 5120 (/4 1280) >[ 92305.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227de70] >[ 92305.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227de70] width 1280 pitch 5120 (/4 1280) >[ 92305.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15ef0] >[ 92305.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15ef0] width 1280 pitch 5120 (/4 1280) >[ 92306.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[ 92306.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[ 92309.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92309.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92309.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2211f00] >[ 92309.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2211f00] width 1280 pitch 5120 (/4 1280) >[ 92309.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92309.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92309.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92309.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92309.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92309.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92309.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92309.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92309.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92310.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8590] >[ 92310.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8590] width 1280 pitch 5120 (/4 1280) >[ 92310.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92310.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92310.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92310.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92310.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92310.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92310.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92310.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92310.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92310.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92310.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92310.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92310.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92310.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92310.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92310.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92310.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92310.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92310.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224fc40] >[ 92310.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224fc40] width 1280 pitch 5120 (/4 1280) >[ 92311.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d4de0] >[ 92311.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d4de0] width 1280 pitch 5120 (/4 1280) >[ 92311.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92311.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92311.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d4de0] >[ 92311.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d4de0] width 1280 pitch 5120 (/4 1280) >[ 92311.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92311.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92311.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f2b70] >[ 92311.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f2b70] width 1280 pitch 5120 (/4 1280) >[ 92311.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d4de0] >[ 92311.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d4de0] width 1280 pitch 5120 (/4 1280) >[ 92311.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2211f00] >[ 92311.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2211f00] width 1280 pitch 5120 (/4 1280) >[ 92311.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92311.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92311.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e7500] >[ 92311.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e7500] width 1280 pitch 5120 (/4 1280) >[ 92311.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fae340] >[ 92311.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fae340] width 1280 pitch 5120 (/4 1280) >[ 92311.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92311.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92311.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92311.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92311.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250a60] >[ 92311.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250a60] width 1280 pitch 5120 (/4 1280) >[ 92311.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92311.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ffa0] >[ 92311.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ffa0] width 1280 pitch 5120 (/4 1280) >[ 92311.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e04f40] >[ 92311.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e04f40] width 1280 pitch 5120 (/4 1280) >[ 92316.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92316.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92537.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92537.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92537.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92537.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92537.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92538.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de4320] >[ 92538.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de4320] width 1280 pitch 5120 (/4 1280) >[ 92538.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92538.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92538.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de4320] >[ 92538.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de4320] width 1280 pitch 5120 (/4 1280) >[ 92538.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92538.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92538.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92538.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92538.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de4320] >[ 92538.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de4320] width 1280 pitch 5120 (/4 1280) >[ 92538.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92538.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92538.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de94a0] >[ 92538.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de94a0] width 1280 pitch 5120 (/4 1280) >[ 92538.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92538.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92538.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92538.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92538.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92538.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92538.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92538.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92538.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92538.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92538.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92538.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92538.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92538.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2212080] >[ 92538.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2212080] width 1280 pitch 5120 (/4 1280) >[ 92538.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 92538.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 92752.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92752.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92752.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92752.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92874.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92874.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92876.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acfe10] >[ 92876.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acfe10] width 1280 pitch 5120 (/4 1280) >[ 92876.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b10] >[ 92876.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b10] width 1280 pitch 5120 (/4 1280) >[ 92877.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92877.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92877.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acfe10] >[ 92877.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acfe10] width 1280 pitch 5120 (/4 1280) >[ 92877.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92877.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92877.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acfe10] >[ 92877.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acfe10] width 1280 pitch 5120 (/4 1280) >[ 92877.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92877.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92877.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92877.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92878.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92878.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92879.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92879.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92879.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92879.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92879.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92879.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92880.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dff6d0] >[ 92880.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dff6d0] width 1280 pitch 5120 (/4 1280) >[ 92880.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dff6d0] >[ 92880.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dff6d0] width 1280 pitch 5120 (/4 1280) >[ 92880.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dff6d0] >[ 92880.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dff6d0] width 1280 pitch 5120 (/4 1280) >[ 92880.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df4a90] >[ 92880.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df4a90] width 1280 pitch 5120 (/4 1280) >[ 92880.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dff6d0] >[ 92880.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dff6d0] width 1280 pitch 5120 (/4 1280) >[ 92880.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df4a90] >[ 92880.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df4a90] width 1280 pitch 5120 (/4 1280) >[ 92895.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92895.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92895.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92895.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92895.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0e430] >[ 92896.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0e430] width 1280 pitch 5120 (/4 1280) >[ 92896.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92896.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1deaa20] >[ 92896.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1deaa20] width 1280 pitch 5120 (/4 1280) >[ 92896.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 92896.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 92897.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92897.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92897.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92898.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92898.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae04e0] >[ 92898.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae04e0] width 1280 pitch 5120 (/4 1280) >[ 92898.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae0420] >[ 92898.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae0420] width 1280 pitch 5120 (/4 1280) >[ 92898.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae04e0] >[ 92898.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae04e0] width 1280 pitch 5120 (/4 1280) >[ 92898.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae0420] >[ 92898.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae0420] width 1280 pitch 5120 (/4 1280) >[ 92898.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae0420] >[ 92898.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae0420] width 1280 pitch 5120 (/4 1280) >[ 92898.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ae0420] >[ 92898.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ae0420] width 1280 pitch 5120 (/4 1280) >[ 92898.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21ece10] >[ 92898.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21ece10] width 1280 pitch 5120 (/4 1280) >[ 92898.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21ece10] >[ 92898.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21ece10] width 1280 pitch 5120 (/4 1280) >[ 92898.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238000] >[ 92898.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238000] width 1280 pitch 5120 (/4 1280) >[ 92898.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21ece10] >[ 92898.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21ece10] width 1280 pitch 5120 (/4 1280) >[ 92902.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92902.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92902.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92902.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92902.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92902.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92902.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92902.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92902.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92902.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92902.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92902.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92902.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92902.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92902.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92902.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92902.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92902.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92903.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92903.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92903.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acc570] >[ 92903.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acc570] width 1280 pitch 5120 (/4 1280) >[ 92905.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92905.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92907.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df72a0] >[ 92907.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df72a0] width 1280 pitch 5120 (/4 1280) >[ 92907.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92907.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92907.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df72a0] >[ 92907.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df72a0] width 1280 pitch 5120 (/4 1280) >[ 92907.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92907.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92907.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df72a0] >[ 92907.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df72a0] width 1280 pitch 5120 (/4 1280) >[ 92907.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0930] >[ 92907.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0930] width 1280 pitch 5120 (/4 1280) >[ 92907.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df72a0] >[ 92907.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df72a0] width 1280 pitch 5120 (/4 1280) >[ 92910.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf7f0] >[ 92910.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf7f0] width 1280 pitch 5120 (/4 1280) >[ 92910.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ad81a0] >[ 92910.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ad81a0] width 1280 pitch 5120 (/4 1280) >[ 92910.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf7f0] >[ 92910.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf7f0] width 1280 pitch 5120 (/4 1280) >[ 92910.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ad81a0] >[ 92910.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ad81a0] width 1280 pitch 5120 (/4 1280) >[ 92910.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf7f0] >[ 92910.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf7f0] width 1280 pitch 5120 (/4 1280) >[ 92910.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf6a0] >[ 92910.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf6a0] width 1280 pitch 5120 (/4 1280) >[ 93095.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93095.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93095.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf6e0] >[ 93095.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf6e0] width 1280 pitch 5120 (/4 1280) >[ 93095.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93095.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93095.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93095.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93096.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93096.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93096.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93096.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93096.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93096.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93096.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ad8140] >[ 93096.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ad8140] width 1280 pitch 5120 (/4 1280) >[ 93096.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93096.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93096.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93096.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93096.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf6e0] >[ 93096.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf6e0] width 1280 pitch 5120 (/4 1280) >[ 93096.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223b3b0] >[ 93096.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223b3b0] width 1280 pitch 5120 (/4 1280) >[ 93097.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93097.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93098.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2adf6e0] >[ 93098.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2adf6e0] width 1280 pitch 5120 (/4 1280) >[ 93098.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93098.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93098.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93098.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93103.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93103.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93103.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93103.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93103.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e1a440] >[ 93103.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e1a440] width 1280 pitch 5120 (/4 1280) >[ 93103.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e1a440] >[ 93103.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e1a440] width 1280 pitch 5120 (/4 1280) >[ 93104.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e1a440] >[ 93104.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e1a440] width 1280 pitch 5120 (/4 1280) >[ 93104.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93104.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93104.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93104.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93104.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93104.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93114.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e1d9b0] >[ 93114.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e1d9b0] width 1280 pitch 5120 (/4 1280) >[ 93114.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223b3b0] >[ 93114.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223b3b0] width 1280 pitch 5120 (/4 1280) >[ 93114.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223b3b0] >[ 93114.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223b3b0] width 1280 pitch 5120 (/4 1280) >[ 93114.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93114.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93114.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[ 93114.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[ 93114.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e1d9b0] >[ 93114.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e1d9b0] width 1280 pitch 5120 (/4 1280) >[ 93114.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93114.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93114.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223b3b0] >[ 93115.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223b3b0] width 1280 pitch 5120 (/4 1280) >[ 93115.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23caa10] >[ 93115.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23caa10] width 1280 pitch 5120 (/4 1280) >[ 93116.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93116.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93116.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93116.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93116.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93116.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93116.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93116.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93116.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22887d0] >[ 93116.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22887d0] width 1280 pitch 5120 (/4 1280) >[ 93116.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93116.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93370.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223ab80] >[ 93370.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223ab80] width 1280 pitch 5120 (/4 1280) >[ 93370.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93370.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93373.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93373.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93373.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93373.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93373.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93373.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93374.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93374.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93374.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93374.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93374.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93374.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93374.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93374.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93374.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93374.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93374.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93374.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e22030] >[ 93374.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e22030] width 1280 pitch 5120 (/4 1280) >[ 93374.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93374.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93374.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93374.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93374.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93374.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93374.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[ 93374.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[ 93374.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93374.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93375.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[ 93375.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[ 93375.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93375.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93375.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24fb0] >[ 93375.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24fb0] width 1280 pitch 5120 (/4 1280) >[ 93375.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93375.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93375.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24fb0] >[ 93375.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24fb0] width 1280 pitch 5120 (/4 1280) >[ 93375.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93375.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93375.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24fb0] >[ 93375.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24fb0] width 1280 pitch 5120 (/4 1280) >[ 93375.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93375.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93375.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93375.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93375.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93375.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93375.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93375.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93375.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93375.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93375.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93375.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93375.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93376.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93376.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93376.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93376.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93376.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93376.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93376.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93376.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93376.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93376.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[ 93376.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[ 93376.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93376.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93376.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93376.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93376.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93376.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93376.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93377.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93377.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e24620] >[ 93377.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e24620] width 1280 pitch 5120 (/4 1280) >[ 93377.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[ 93377.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[ 93377.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[ 93377.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[ 93377.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[ 93377.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[ 93377.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[ 93377.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[ 93377.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[ 93377.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[ 93377.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93377.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93377.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1a540] >[ 93377.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1a540] width 1280 pitch 5120 (/4 1280) >[ 93377.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9050] >[ 93377.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9050] width 1280 pitch 5120 (/4 1280) >[ 93377.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2cc40] >[ 93377.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2cc40] width 1280 pitch 5120 (/4 1280) >[ 93377.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 93377.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 93377.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[ 93377.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[ 93377.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 93377.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 93377.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[ 93377.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[ 93377.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[ 93377.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[ 93377.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[ 93377.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[ 93500.231] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 93500.231] (II) RADEON(0): Printing DDC gathered Modelines: >[ 93500.231] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 94100.204] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[ 94100.204] (II) RADEON(0): Printing DDC gathered Modelines: >[ 94100.204] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[ 94190.888] (II) RADEON(0): RADEONSaveScreen(2) >[ 94190.888] (II) RADEON(0): RADEONSaveScreen(0) >[110069.505] (II) RADEON(0): RADEONSaveScreen(1) >[110075.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2df0c00] >[110075.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2df0c00] width 1280 pitch 5120 (/4 1280) >[110076.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110076.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6cfe0] >[110076.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6cfe0] width 1280 pitch 5120 (/4 1280) >[110076.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[110076.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[110100.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2df0c00] >[110101.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2df0c00] width 1280 pitch 5120 (/4 1280) >[110101.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2eb80] >[110101.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2eb80] width 1280 pitch 5120 (/4 1280) >[110101.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b5a1d0] >[110101.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b5a1d0] width 1280 pitch 5120 (/4 1280) >[110101.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d5d100] >[110101.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d5d100] width 1280 pitch 5120 (/4 1280) >[110101.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22134a0] >[110101.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22134a0] width 1280 pitch 5120 (/4 1280) >[110101.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d5d100] >[110101.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d5d100] width 1280 pitch 5120 (/4 1280) >[110101.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229b040] >[110101.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229b040] width 1280 pitch 5120 (/4 1280) >[110101.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d5d100] >[110101.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d5d100] width 1280 pitch 5120 (/4 1280) >[110101.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b400] >[110101.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b400] width 1280 pitch 5120 (/4 1280) >[110101.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d5d100] >[110101.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d5d100] width 1280 pitch 5120 (/4 1280) >[110101.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d66c0] >[110101.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d66c0] width 1280 pitch 5120 (/4 1280) >[110102.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2acfe10] >[110102.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2acfe10] width 1280 pitch 5120 (/4 1280) >[110102.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c92640] >[110103.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c92640] width 1280 pitch 5120 (/4 1280) >[110103.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be4220] >[110103.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be4220] width 1280 pitch 5120 (/4 1280) >[110103.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6e530] >[110103.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6e530] width 1280 pitch 5120 (/4 1280) >[110103.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be4220] >[110103.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be4220] width 1280 pitch 5120 (/4 1280) >[110103.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b18bb0] >[110103.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b18bb0] width 1280 pitch 5120 (/4 1280) >[110103.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be4220] >[110103.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be4220] width 1280 pitch 5120 (/4 1280) >[110103.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d21980] >[110103.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d21980] width 1280 pitch 5120 (/4 1280) >[110103.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e8ec50] >[110103.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e8ec50] width 1280 pitch 5120 (/4 1280) >[110103.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc53f0] >[110103.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc53f0] width 1280 pitch 5120 (/4 1280) >[110103.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d01270] >[110103.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d01270] width 1280 pitch 5120 (/4 1280) >[110103.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebc860] >[110103.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebc860] width 1280 pitch 5120 (/4 1280) >[110104.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c92640] >[110104.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c92640] width 1280 pitch 5120 (/4 1280) >[110104.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df3690] >[110105.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df3690] width 1280 pitch 5120 (/4 1280) >[110105.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110105.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110105.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8b1f0] >[110105.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8b1f0] width 1280 pitch 5120 (/4 1280) >[110118.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f7c0] >[110118.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f7c0] width 1280 pitch 5120 (/4 1280) >[110342.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c85dd0] >[110342.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c85dd0] width 1280 pitch 5120 (/4 1280) >[110465.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[110465.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[110465.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[110465.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[110465.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[110465.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[110465.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[110465.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[110465.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e585e0] >[110465.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e585e0] width 1280 pitch 5120 (/4 1280) >[110465.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9d4f0] >[110465.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9d4f0] width 1280 pitch 5120 (/4 1280) >[110465.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8b1f0] >[110465.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8b1f0] width 1280 pitch 5120 (/4 1280) >[110466.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d04e00] >[110466.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d04e00] width 1280 pitch 5120 (/4 1280) >[110467.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b18860] >[110467.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b18860] width 1280 pitch 5120 (/4 1280) >[110467.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b400] >[110467.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b400] width 1280 pitch 5120 (/4 1280) >[110467.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c68f20] >[110467.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c68f20] width 1280 pitch 5120 (/4 1280) >[110467.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2effd20] >[110467.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2effd20] width 1280 pitch 5120 (/4 1280) >[110467.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e0850] >[110467.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e0850] width 1280 pitch 5120 (/4 1280) >[110467.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117bfa0] >[110467.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117bfa0] width 1280 pitch 5120 (/4 1280) >[110467.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc53f0] >[110467.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc53f0] width 1280 pitch 5120 (/4 1280) >[110467.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e53180] >[110467.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e53180] width 1280 pitch 5120 (/4 1280) >[110467.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2df0c00] >[110467.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2df0c00] width 1280 pitch 5120 (/4 1280) >[110467.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23caa10] >[110467.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23caa10] width 1280 pitch 5120 (/4 1280) >[110467.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15b00] >[110467.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15b00] width 1280 pitch 5120 (/4 1280) >[110467.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c17020] >[110467.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c17020] width 1280 pitch 5120 (/4 1280) >[110467.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d04e00] >[110467.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d04e00] width 1280 pitch 5120 (/4 1280) >[110468.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22134a0] >[110468.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22134a0] width 1280 pitch 5120 (/4 1280) >[110468.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[110468.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[110468.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f01ec0] >[110468.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f01ec0] width 1280 pitch 5120 (/4 1280) >[110468.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b400] >[110468.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b400] width 1280 pitch 5120 (/4 1280) >[110468.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3b50] >[110468.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3b50] width 1280 pitch 5120 (/4 1280) >[110468.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f7c0] >[110468.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f7c0] width 1280 pitch 5120 (/4 1280) >[110468.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3b50] >[110468.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3b50] width 1280 pitch 5120 (/4 1280) >[110468.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[110468.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[110468.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e18900] >[110468.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e18900] width 1280 pitch 5120 (/4 1280) >[110468.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d2da90] >[110468.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d2da90] width 1280 pitch 5120 (/4 1280) >[110469.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d4ff0] >[110469.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d4ff0] width 1280 pitch 5120 (/4 1280) >[110469.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e53180] >[110469.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e53180] width 1280 pitch 5120 (/4 1280) >[110469.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2df0c00] >[110469.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2df0c00] width 1280 pitch 5120 (/4 1280) >[110470.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3b50] >[110470.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3b50] width 1280 pitch 5120 (/4 1280) >[110470.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[110470.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[110505.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d82600] >[110505.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d82600] width 1280 pitch 5120 (/4 1280) >[110506.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e25c70] >[110506.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e25c70] width 1280 pitch 5120 (/4 1280) >[110703.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae490] >[110703.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae490] width 1280 pitch 5120 (/4 1280) >[110703.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb04d0] >[110703.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb04d0] width 1280 pitch 5120 (/4 1280) >[110703.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cda290] >[110703.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cda290] width 1280 pitch 5120 (/4 1280) >[110703.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f05100] >[110703.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f05100] width 1280 pitch 5120 (/4 1280) >[110703.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cda290] >[110703.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cda290] width 1280 pitch 5120 (/4 1280) >[110703.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1245db0] >[110703.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1245db0] width 1280 pitch 5120 (/4 1280) >[110703.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[110703.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[110703.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3b50] >[110703.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3b50] width 1280 pitch 5120 (/4 1280) >[110823.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf9200] >[110823.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf9200] width 1280 pitch 5120 (/4 1280) >[110823.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d2cda0] >[110823.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d2cda0] width 1280 pitch 5120 (/4 1280) >[110994.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d2da90] >[110994.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d2da90] width 1280 pitch 5120 (/4 1280) >[110995.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b18860] >[110995.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b18860] width 1280 pitch 5120 (/4 1280) >[111645.345] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[111645.345] (II) RADEON(0): Printing DDC gathered Modelines: >[111645.345] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[111735.892] (II) RADEON(0): RADEONSaveScreen(2) >[111735.892] (II) RADEON(0): RADEONSaveScreen(0) >[125632.176] (II) RADEON(0): RADEONSaveScreen(1) >[125637.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[125637.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[125693.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4abe0] >[125693.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4abe0] width 1280 pitch 5120 (/4 1280) >[125693.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cecf40] >[125693.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cecf40] width 1280 pitch 5120 (/4 1280) >[125738.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e7fb0] >[125738.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e7fb0] width 1280 pitch 5120 (/4 1280) >[125738.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4b100] >[125738.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4b100] width 1280 pitch 5120 (/4 1280) >[125741.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bed010] >[125741.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bed010] width 1280 pitch 5120 (/4 1280) >[125741.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ff2d0] >[125741.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ff2d0] width 1280 pitch 5120 (/4 1280) >[125746.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2effd20] >[125746.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2effd20] width 1280 pitch 5120 (/4 1280) >[125746.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x131c360] >[125746.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x131c360] width 1280 pitch 5120 (/4 1280) >[125770.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f89880] >[125770.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f89880] width 1280 pitch 5120 (/4 1280) >[125770.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229b040] >[125770.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229b040] width 1280 pitch 5120 (/4 1280) >[125796.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fdaf40] >[125796.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fdaf40] width 1280 pitch 5120 (/4 1280) >[125797.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be7450] >[125797.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be7450] width 1280 pitch 5120 (/4 1280) >[125797.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[125797.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[125797.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be7450] >[125797.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be7450] width 1280 pitch 5120 (/4 1280) >[125797.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[125797.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[125797.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be7450] >[125797.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be7450] width 1280 pitch 5120 (/4 1280) >[125797.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[125797.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[125797.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be7450] >[125797.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be7450] width 1280 pitch 5120 (/4 1280) >[125798.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[125798.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[125799.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27060] >[125799.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27060] width 1280 pitch 5120 (/4 1280) >[125895.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[125895.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[125895.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bebce0] >[125895.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bebce0] width 1280 pitch 5120 (/4 1280) >[125895.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[125896.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[125896.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bebce0] >[125896.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bebce0] width 1280 pitch 5120 (/4 1280) >[125896.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30381e0] >[125896.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30381e0] width 1280 pitch 5120 (/4 1280) >[125896.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bebce0] >[125896.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bebce0] width 1280 pitch 5120 (/4 1280) >[125896.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30381e0] >[125896.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30381e0] width 1280 pitch 5120 (/4 1280) >[125896.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbf930] >[125896.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbf930] width 1280 pitch 5120 (/4 1280) >[125896.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[125896.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[125896.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbf930] >[125896.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbf930] width 1280 pitch 5120 (/4 1280) >[125896.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[125896.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[125896.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbf930] >[125896.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbf930] width 1280 pitch 5120 (/4 1280) >[125896.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e23be0] >[125896.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e23be0] width 1280 pitch 5120 (/4 1280) >[125897.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1245db0] >[125897.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1245db0] width 1280 pitch 5120 (/4 1280) >[125897.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f07380] >[125897.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f07380] width 1280 pitch 5120 (/4 1280) >[125897.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d8b8b0] >[125897.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d8b8b0] width 1280 pitch 5120 (/4 1280) >[125897.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e9040] >[125897.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e9040] width 1280 pitch 5120 (/4 1280) >[125897.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e8ec50] >[125897.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e8ec50] width 1280 pitch 5120 (/4 1280) >[125897.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035330] >[125897.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035330] width 1280 pitch 5120 (/4 1280) >[125897.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e8ec50] >[125897.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e8ec50] width 1280 pitch 5120 (/4 1280) >[125897.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035330] >[125897.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035330] width 1280 pitch 5120 (/4 1280) >[125897.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b4c0] >[125897.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b4c0] width 1280 pitch 5120 (/4 1280) >[125897.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035330] >[125897.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035330] width 1280 pitch 5120 (/4 1280) >[125897.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b4c0] >[125897.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b4c0] width 1280 pitch 5120 (/4 1280) >[125897.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035330] >[125897.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035330] width 1280 pitch 5120 (/4 1280) >[125898.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d2da90] >[125898.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d2da90] width 1280 pitch 5120 (/4 1280) >[125898.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e81d0] >[125898.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e81d0] width 1280 pitch 5120 (/4 1280) >[125898.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e81d0] >[125898.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e81d0] width 1280 pitch 5120 (/4 1280) >[125898.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee420] >[125898.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee420] width 1280 pitch 5120 (/4 1280) >[125898.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee420] >[125898.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee420] width 1280 pitch 5120 (/4 1280) >[125898.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4b30] >[125898.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4b30] width 1280 pitch 5120 (/4 1280) >[125898.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4b30] >[125898.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4b30] width 1280 pitch 5120 (/4 1280) >[125898.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125898.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125898.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4b30] >[125898.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4b30] width 1280 pitch 5120 (/4 1280) >[125898.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fadf70] >[125898.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fadf70] width 1280 pitch 5120 (/4 1280) >[125898.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4b30] >[125898.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4b30] width 1280 pitch 5120 (/4 1280) >[125898.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fadf70] >[125898.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fadf70] width 1280 pitch 5120 (/4 1280) >[125898.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4b30] >[125898.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4b30] width 1280 pitch 5120 (/4 1280) >[125917.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4e930] >[125917.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4e930] width 1280 pitch 5120 (/4 1280) >[125918.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e27bd0] >[125918.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e27bd0] width 1280 pitch 5120 (/4 1280) >[125918.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f500e0] >[125918.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f500e0] width 1280 pitch 5120 (/4 1280) >[125998.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[125998.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[125998.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb03c0] >[125998.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb03c0] width 1280 pitch 5120 (/4 1280) >[125998.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[125998.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[125998.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da2b30] >[125998.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da2b30] width 1280 pitch 5120 (/4 1280) >[125998.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[125998.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[125998.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[125998.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[125998.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[125998.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[126129.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e57680] >[126129.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e57680] width 1280 pitch 5120 (/4 1280) >[126129.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f534b0] >[126129.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f534b0] width 1280 pitch 5120 (/4 1280) >[126131.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222e120] >[126131.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222e120] width 1280 pitch 5120 (/4 1280) >[126132.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0a8d0] >[126132.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0a8d0] width 1280 pitch 5120 (/4 1280) >[126132.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec6a20] >[126132.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec6a20] width 1280 pitch 5120 (/4 1280) >[126132.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea93b0] >[126132.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea93b0] width 1280 pitch 5120 (/4 1280) >[126132.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbf930] >[126132.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbf930] width 1280 pitch 5120 (/4 1280) >[126132.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da39d0] >[126132.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da39d0] width 1280 pitch 5120 (/4 1280) >[126132.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[126132.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[126132.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b4c0] >[126132.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b4c0] width 1280 pitch 5120 (/4 1280) >[126132.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1ec0] >[126132.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1ec0] width 1280 pitch 5120 (/4 1280) >[126210.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d04e00] >[126210.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d04e00] width 1280 pitch 5120 (/4 1280) >[126210.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2072540] >[126210.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2072540] width 1280 pitch 5120 (/4 1280) >[126790.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126790.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[126800.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[126800.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[126825.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da29a0] >[126825.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da29a0] width 1280 pitch 5120 (/4 1280) >[126826.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126826.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[126826.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[126826.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[126826.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126826.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[126826.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[126826.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[126826.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126826.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[126826.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[126826.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[126826.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126826.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[126826.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[126826.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[126826.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[126826.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[127428.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132c5e0] >[127428.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132c5e0] width 1280 pitch 5120 (/4 1280) >[127428.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[127428.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[127428.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[127428.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[127428.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[127428.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[127428.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da44e0] >[127428.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da44e0] width 1280 pitch 5120 (/4 1280) >[127428.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[127428.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[127428.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132c5e0] >[127428.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132c5e0] width 1280 pitch 5120 (/4 1280) >[127428.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[127428.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[127428.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127428.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127428.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[127428.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[127428.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0a080] >[127428.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0a080] width 1280 pitch 5120 (/4 1280) >[127428.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132c5e0] >[127428.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132c5e0] width 1280 pitch 5120 (/4 1280) >[127428.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127428.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127428.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[127428.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[127428.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0a080] >[127428.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0a080] width 1280 pitch 5120 (/4 1280) >[127428.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x132c5e0] >[127428.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x132c5e0] width 1280 pitch 5120 (/4 1280) >[127429.146] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[127429.146] (II) RADEON(0): Printing DDC gathered Modelines: >[127429.146] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[127431.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127431.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127517.892] (II) RADEON(0): RADEONSaveScreen(2) >[127517.892] (II) RADEON(0): RADEONSaveScreen(0) >[127795.563] (II) RADEON(0): RADEONSaveScreen(1) >[127804.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[127804.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[127805.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127805.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127805.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127805.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127805.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127805.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127805.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127805.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127805.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127805.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127806.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127806.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127806.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127806.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127806.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127806.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127806.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127806.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[127806.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127806.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127806.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[127807.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[127807.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[127807.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[127807.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[127807.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[127807.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[127807.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[127807.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[127807.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[127807.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[127807.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[127820.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1beaac0] >[127820.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1beaac0] width 1280 pitch 5120 (/4 1280) >[128026.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0a8d0] >[128026.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0a8d0] width 1280 pitch 5120 (/4 1280) >[128184.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20b6fc0] >[128184.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20b6fc0] width 1280 pitch 5120 (/4 1280) >[128185.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128185.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128185.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128185.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128185.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128185.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128185.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128185.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128186.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fddf30] >[128186.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fddf30] width 1280 pitch 5120 (/4 1280) >[128205.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[128205.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[128205.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128205.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128205.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[128205.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[128206.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128206.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128206.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[128206.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[128206.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128206.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128206.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245bb10] >[128206.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245bb10] width 1280 pitch 5120 (/4 1280) >[128206.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128206.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128206.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0a080] >[128206.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0a080] width 1280 pitch 5120 (/4 1280) >[128207.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128207.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128207.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fddf30] >[128207.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fddf30] width 1280 pitch 5120 (/4 1280) >[128207.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fddf30] >[128207.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fddf30] width 1280 pitch 5120 (/4 1280) >[128207.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245bb10] >[128207.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245bb10] width 1280 pitch 5120 (/4 1280) >[128207.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fddf30] >[128207.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fddf30] width 1280 pitch 5120 (/4 1280) >[128207.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245bb10] >[128207.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245bb10] width 1280 pitch 5120 (/4 1280) >[128207.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dedba0] >[128207.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dedba0] width 1280 pitch 5120 (/4 1280) >[128220.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208a4d0] >[128220.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208a4d0] width 1280 pitch 5120 (/4 1280) >[128260.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d883a0] >[128260.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d883a0] width 1280 pitch 5120 (/4 1280) >[128260.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351530] >[128260.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351530] width 1280 pitch 5120 (/4 1280) >[128260.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15310] >[128260.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15310] width 1280 pitch 5120 (/4 1280) >[128260.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351530] >[128260.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351530] width 1280 pitch 5120 (/4 1280) >[128278.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d88330] >[128278.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d88330] width 1280 pitch 5120 (/4 1280) >[128278.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d86590] >[128278.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d86590] width 1280 pitch 5120 (/4 1280) >[128278.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81c80] >[128278.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81c80] width 1280 pitch 5120 (/4 1280) >[128278.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20258b0] >[128278.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20258b0] width 1280 pitch 5120 (/4 1280) >[128280.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9900] >[128280.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9900] width 1280 pitch 5120 (/4 1280) >[128280.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dad2d0] >[128280.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dad2d0] width 1280 pitch 5120 (/4 1280) >[128280.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dad2d0] >[128280.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dad2d0] width 1280 pitch 5120 (/4 1280) >[128280.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128280.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128285.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dad2d0] >[128285.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dad2d0] width 1280 pitch 5120 (/4 1280) >[128286.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128286.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128286.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128286.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128286.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128286.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128301.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128301.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128301.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128301.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128301.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128301.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128301.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128301.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128301.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128301.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128301.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128301.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128302.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128302.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128302.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128302.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128302.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb3a0] >[128351.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb3a0] width 1280 pitch 5120 (/4 1280) >[128351.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128351.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128351.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128351.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128351.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128352.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128352.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128352.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128352.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128352.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128352.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128352.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128352.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1450] >[128352.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1450] width 1280 pitch 5120 (/4 1280) >[128352.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fad3f0] >[128352.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fad3f0] width 1280 pitch 5120 (/4 1280) >[128467.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[128467.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[128509.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128509.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128509.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128509.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128509.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128509.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128509.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128509.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128509.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128509.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128509.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128509.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128509.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128509.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128509.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128509.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128509.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128509.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128509.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128509.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128509.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128509.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128509.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128510.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128510.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128510.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128510.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128510.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128510.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128510.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128510.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128511.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[128511.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[128511.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128511.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128511.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128511.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128511.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128511.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128511.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128511.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128511.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128511.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128511.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128511.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128511.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128511.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128511.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128511.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128511.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128511.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128511.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128511.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128511.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128511.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128511.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128511.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128511.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128511.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128511.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128511.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128511.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[128511.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[128511.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128511.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128511.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128511.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128511.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128511.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128511.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128511.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128511.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf4c0] >[128511.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf4c0] width 1280 pitch 5120 (/4 1280) >[128511.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128511.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128511.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128511.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128511.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23414c0] >[128511.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23414c0] width 1280 pitch 5120 (/4 1280) >[128513.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd5520] >[128513.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd5520] width 1280 pitch 5120 (/4 1280) >[128517.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128517.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128518.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128518.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128518.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128518.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128518.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128518.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128518.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128518.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128518.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128518.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128518.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128518.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128518.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128518.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128518.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128518.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128518.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x133add0] >[128518.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x133add0] width 1280 pitch 5120 (/4 1280) >[128518.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128518.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128518.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128518.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128518.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23414c0] >[128518.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23414c0] width 1280 pitch 5120 (/4 1280) >[128518.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128518.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128518.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128518.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128518.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[128518.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[128518.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128518.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128518.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[128519.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[128519.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128519.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128519.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[128519.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[128519.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128519.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128519.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[128519.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[128519.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128519.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128519.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128519.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128519.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128519.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128519.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[128519.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[128519.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128519.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128519.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128519.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128519.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128519.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128519.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[128519.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[128519.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128519.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128519.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128519.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128519.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128519.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128519.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[128519.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[128519.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[128520.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[128520.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23414c0] >[128520.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23414c0] width 1280 pitch 5120 (/4 1280) >[128521.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd5520] >[128521.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd5520] width 1280 pitch 5120 (/4 1280) >[128521.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[128521.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[128521.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128521.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128521.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[128521.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[128521.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30431e0] >[128521.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30431e0] width 1280 pitch 5120 (/4 1280) >[128521.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[128521.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[128521.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[128521.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b531e0] >[128521.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b531e0] width 1280 pitch 5120 (/4 1280) >[129006.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129006.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129006.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129006.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129006.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[129006.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[129006.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129006.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129006.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[129006.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[129006.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129006.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129006.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[129006.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[129006.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129006.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129007.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129007.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129007.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129007.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129007.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129007.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129007.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129007.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129007.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129007.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129007.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129007.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129007.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129007.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129007.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129007.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129007.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129007.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129007.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129007.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129017.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129017.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129017.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129017.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129017.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129017.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129017.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129017.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129017.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129017.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129017.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dae330] >[129017.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dae330] width 1280 pitch 5120 (/4 1280) >[129017.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129017.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129017.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[129017.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[129017.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129017.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129017.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[129017.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[129017.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129017.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129017.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f949a0] >[129017.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f949a0] width 1280 pitch 5120 (/4 1280) >[129017.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe1270] >[129017.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe1270] width 1280 pitch 5120 (/4 1280) >[129017.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[129017.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[129017.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30448c0] >[129017.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30448c0] width 1280 pitch 5120 (/4 1280) >[129017.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x133add0] >[129017.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x133add0] width 1280 pitch 5120 (/4 1280) >[129017.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[129017.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[129018.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129018.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129018.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129018.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf3710] >[129018.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf3710] width 1280 pitch 5120 (/4 1280) >[129019.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129019.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129019.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e930] >[129019.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e930] width 1280 pitch 5120 (/4 1280) >[129019.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129019.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129019.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e930] >[129019.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e930] width 1280 pitch 5120 (/4 1280) >[129019.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129019.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129019.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e930] >[129019.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e930] width 1280 pitch 5120 (/4 1280) >[129020.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129020.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129020.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacf40] >[129020.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacf40] width 1280 pitch 5120 (/4 1280) >[129051.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478080] >[129051.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478080] width 1280 pitch 5120 (/4 1280) >[129051.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30340b0] >[129051.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30340b0] width 1280 pitch 5120 (/4 1280) >[129051.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e930] >[129051.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e930] width 1280 pitch 5120 (/4 1280) >[129051.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3c20] >[129051.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3c20] width 1280 pitch 5120 (/4 1280) >[129278.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacc80] >[129278.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacc80] width 1280 pitch 5120 (/4 1280) >[129278.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa1350] >[129278.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa1350] width 1280 pitch 5120 (/4 1280) >[129325.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129325.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129325.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0e360] >[129325.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0e360] width 1280 pitch 5120 (/4 1280) >[129325.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129325.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129325.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129325.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129325.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129325.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129325.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129325.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129325.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129325.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129325.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129325.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129325.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0e360] >[129325.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0e360] width 1280 pitch 5120 (/4 1280) >[129325.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0cd60] >[129325.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0cd60] width 1280 pitch 5120 (/4 1280) >[129325.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129325.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129325.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129325.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129325.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129325.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129325.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129326.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129326.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129326.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129326.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129326.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129326.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129326.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129326.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129326.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129326.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129326.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129326.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3016a20] >[129326.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3016a20] width 1280 pitch 5120 (/4 1280) >[129326.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129326.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129326.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129326.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129326.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129326.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129326.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129326.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129326.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129326.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129326.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129326.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129326.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129326.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129327.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129327.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129327.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129327.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129327.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129327.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129327.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129327.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129328.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129328.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129328.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129328.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129328.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129328.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129328.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129328.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129328.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129328.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129328.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129328.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129328.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129328.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129328.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129328.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129328.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129328.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129328.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129328.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129328.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129328.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3029b60] >[129328.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3029b60] width 1280 pitch 5120 (/4 1280) >[129328.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129328.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129328.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129328.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129328.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129328.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129328.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129328.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129328.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129328.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129328.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c378b0] >[129328.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c378b0] width 1280 pitch 5120 (/4 1280) >[129328.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129329.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129329.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129329.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129329.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129329.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129329.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129329.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129329.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129329.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129329.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129329.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129329.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129329.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129329.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129329.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0] >[129329.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1280 pitch 5120 (/4 1280) >[129329.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129329.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129337.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x191dd10] >[129337.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x191dd10] width 1280 pitch 5120 (/4 1280) >[129347.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129347.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129367.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129367.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129367.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129367.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129367.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129367.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129367.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129367.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129367.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129367.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129367.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129367.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129367.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129367.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129367.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129367.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129367.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129367.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129367.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129367.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129367.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129367.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129367.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129367.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129367.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129367.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129367.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129367.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129367.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129367.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129367.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129367.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129367.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129367.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129368.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129368.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129368.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129368.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129368.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129368.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129368.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129368.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129368.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129368.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129368.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129368.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129368.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129368.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129368.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129368.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129368.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129368.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129368.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129368.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129368.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129368.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129368.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129368.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129368.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129368.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129368.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129368.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129368.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129368.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129368.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129368.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129368.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129368.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129368.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129368.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129368.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129368.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129368.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129368.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129368.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129368.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129368.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129368.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129368.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129368.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129368.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129368.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129368.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129368.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129368.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129368.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129368.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129368.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129368.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129368.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129369.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129369.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129369.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129369.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129369.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129369.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129369.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129369.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129369.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129369.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129369.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129369.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129369.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129369.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129369.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129369.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129369.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129369.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129369.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ad40] >[129369.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ad40] width 1280 pitch 5120 (/4 1280) >[129369.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129369.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129369.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129369.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129369.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa9ca0] >[129369.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa9ca0] width 1280 pitch 5120 (/4 1280) >[129370.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129370.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129370.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129370.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129370.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129370.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129370.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129370.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129370.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129370.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129370.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129370.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129370.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129370.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129370.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129370.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129370.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129370.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129370.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129370.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129370.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129370.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129370.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129370.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129370.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129370.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129370.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129370.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129370.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301f0b0] >[129370.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301f0b0] width 1280 pitch 5120 (/4 1280) >[129370.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129370.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129370.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129370.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129370.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129370.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c368f0] >[129370.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c368f0] width 1280 pitch 5120 (/4 1280) >[129370.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129370.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129419.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129419.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129419.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129419.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129419.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129419.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129419.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129419.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129419.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129419.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129419.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129419.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129419.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129419.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129419.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129419.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129419.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129419.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129419.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129419.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129419.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129419.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129419.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129419.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa550] >[129419.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa550] width 1280 pitch 5120 (/4 1280) >[129419.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129419.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129419.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129419.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129419.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129419.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129420.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129420.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129420.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129420.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129420.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129420.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129420.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129420.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129420.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129420.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129420.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129420.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129420.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129420.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129420.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129420.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129420.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129420.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129420.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129420.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129420.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129420.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129420.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129420.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129420.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129420.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129420.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129420.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129420.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304a1d0] >[129420.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304a1d0] width 1280 pitch 5120 (/4 1280) >[129420.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129420.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129420.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129420.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129420.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129420.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129420.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129420.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129420.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129420.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129420.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129421.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129421.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129421.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129421.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129421.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129421.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129421.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129421.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129421.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129421.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c39350] >[129421.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c39350] width 1280 pitch 5120 (/4 1280) >[129421.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8650] >[129421.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8650] width 1280 pitch 5120 (/4 1280) >[129421.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129421.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129421.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129421.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129421.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129421.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb9170] >[129421.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb9170] width 1280 pitch 5120 (/4 1280) >[129421.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129421.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129547.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cbd80] >[129547.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cbd80] width 1280 pitch 5120 (/4 1280) >[129599.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b55ae0] >[129599.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b55ae0] width 1280 pitch 5120 (/4 1280) >[129601.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3033ed0] >[129601.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3033ed0] width 1280 pitch 5120 (/4 1280) >[129983.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129983.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129983.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129983.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129983.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129989.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129989.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129989.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129989.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129989.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129989.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129989.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a6ff0] >[129989.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a6ff0] width 1280 pitch 5120 (/4 1280) >[129990.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4fea0] >[129990.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4fea0] width 1280 pitch 5120 (/4 1280) >[129991.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbdea0] >[129991.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbdea0] width 1280 pitch 5120 (/4 1280) >[129991.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129991.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129991.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbdea0] >[129991.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbdea0] width 1280 pitch 5120 (/4 1280) >[129991.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129991.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129991.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399420] >[129991.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399420] width 1280 pitch 5120 (/4 1280) >[129991.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129991.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129991.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399420] >[129991.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399420] width 1280 pitch 5120 (/4 1280) >[129991.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[129991.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[129991.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399420] >[129991.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399420] width 1280 pitch 5120 (/4 1280) >[129991.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3076880] >[129991.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3076880] width 1280 pitch 5120 (/4 1280) >[129991.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399420] >[129991.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399420] width 1280 pitch 5120 (/4 1280) >[129991.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3076880] >[129991.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3076880] width 1280 pitch 5120 (/4 1280) >[129991.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1399420] >[129991.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1399420] width 1280 pitch 5120 (/4 1280) >[130013.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006040] >[130013.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006040] width 1280 pitch 5120 (/4 1280) >[130013.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4080] >[130013.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4080] width 1280 pitch 5120 (/4 1280) >[130028.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d04e00] >[130028.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d04e00] width 1280 pitch 5120 (/4 1280) >[130111.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fa440] >[130111.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fa440] width 1280 pitch 5120 (/4 1280) >[130172.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x116cd90] >[130172.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x116cd90] width 1280 pitch 5120 (/4 1280) >[130172.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f24c20] >[130172.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f24c20] width 1280 pitch 5120 (/4 1280) >[130196.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307a070] >[130196.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307a070] width 1280 pitch 5120 (/4 1280) >[130196.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30550c0] >[130196.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30550c0] width 1280 pitch 5120 (/4 1280) >[130392.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d47f0] >[130392.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d47f0] width 1280 pitch 5120 (/4 1280) >[130393.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309ef90] >[130393.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309ef90] width 1280 pitch 5120 (/4 1280) >[130396.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d47f0] >[130396.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d47f0] width 1280 pitch 5120 (/4 1280) >[130397.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309ef90] >[130397.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309ef90] width 1280 pitch 5120 (/4 1280) >[130401.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f859e0] >[130401.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f859e0] width 1280 pitch 5120 (/4 1280) >[130401.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d2d80] >[130401.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d2d80] width 1280 pitch 5120 (/4 1280) >[130455.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b4860] >[130455.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b4860] width 1280 pitch 5120 (/4 1280) >[130464.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312a9b0] >[130464.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312a9b0] width 1280 pitch 5120 (/4 1280) >[130520.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31347e0] >[130520.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31347e0] width 1280 pitch 5120 (/4 1280) >[130520.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31347e0] >[130521.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31347e0] width 1280 pitch 5120 (/4 1280) >[130562.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133b60] >[130562.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133b60] width 1280 pitch 5120 (/4 1280) >[130562.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30afc80] >[130562.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30afc80] width 1280 pitch 5120 (/4 1280) >[130774.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140f90] >[130774.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140f90] width 1280 pitch 5120 (/4 1280) >[130774.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3148340] >[130774.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3148340] width 1280 pitch 5120 (/4 1280) >[130780.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130780.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130780.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140f90] >[130780.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140f90] width 1280 pitch 5120 (/4 1280) >[130780.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130780.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130780.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140f90] >[130780.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140f90] width 1280 pitch 5120 (/4 1280) >[130780.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130780.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130780.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130780.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130780.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130780.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130780.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3147330] >[130780.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3147330] width 1280 pitch 5120 (/4 1280) >[130780.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3134e80] >[130780.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3134e80] width 1280 pitch 5120 (/4 1280) >[130780.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dc0c0] >[130780.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dc0c0] width 1280 pitch 5120 (/4 1280) >[130780.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130780.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130780.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140f90] >[130780.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140f90] width 1280 pitch 5120 (/4 1280) >[130780.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b4860] >[130780.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b4860] width 1280 pitch 5120 (/4 1280) >[130781.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31482a0] >[130781.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31482a0] width 1280 pitch 5120 (/4 1280) >[130781.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3134e80] >[130781.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3134e80] width 1280 pitch 5120 (/4 1280) >[130781.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c390] >[130781.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c390] width 1280 pitch 5120 (/4 1280) >[130781.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3147330] >[130781.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3147330] width 1280 pitch 5120 (/4 1280) >[130781.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3147330] >[130781.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3147330] width 1280 pitch 5120 (/4 1280) >[130781.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3147330] >[130781.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3147330] width 1280 pitch 5120 (/4 1280) >[130781.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130781.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3147330] >[130781.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3147330] width 1280 pitch 5120 (/4 1280) >[130781.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[130781.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[130910.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfef0] >[130910.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfef0] width 1280 pitch 5120 (/4 1280) >[131402.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31197e0] >[131402.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31197e0] width 1280 pitch 5120 (/4 1280) >[131604.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133280] >[131604.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133280] width 1280 pitch 5120 (/4 1280) >[131604.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3117770] >[131604.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3117770] width 1280 pitch 5120 (/4 1280) >[131629.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ce220] >[131629.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ce220] width 1280 pitch 5120 (/4 1280) >[131629.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133280] >[131629.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133280] width 1280 pitch 5120 (/4 1280) >[131629.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3145cc0] >[131629.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3145cc0] width 1280 pitch 5120 (/4 1280) >[131629.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3099eb0] >[131629.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3099eb0] width 1280 pitch 5120 (/4 1280) >[131677.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31197e0] >[131677.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31197e0] width 1280 pitch 5120 (/4 1280) >[131677.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133280] >[131677.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133280] width 1280 pitch 5120 (/4 1280) >[131751.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ce220] >[131751.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ce220] width 1280 pitch 5120 (/4 1280) >[131751.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131751.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131771.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131771.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131771.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157770] >[131771.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157770] width 1280 pitch 5120 (/4 1280) >[131782.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131782.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131782.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131782.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131782.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131786.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131786.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131786.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131786.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131787.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131787.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131787.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131787.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131787.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131787.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131787.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131787.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131787.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131787.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3073c60] >[131787.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3073c60] width 1280 pitch 5120 (/4 1280) >[131787.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157770] >[131787.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157770] width 1280 pitch 5120 (/4 1280) >[131789.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3120a80] >[131789.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3120a80] width 1280 pitch 5120 (/4 1280) >[131789.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131789.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131792.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131792.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131792.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131792.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131792.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131792.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131792.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131792.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131792.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131792.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131792.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131792.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131792.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131792.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131792.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131792.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131792.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131792.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131792.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131792.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131792.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131792.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131792.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131792.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131792.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131793.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131793.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131793.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131793.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131793.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131793.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131793.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131793.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131793.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131793.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131793.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131793.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131793.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131793.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131793.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131793.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131793.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131793.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131793.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131793.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131793.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131793.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131793.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131793.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131793.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131793.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131793.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131793.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131793.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131793.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131793.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131793.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131793.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131793.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131793.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131793.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310f970] >[131793.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310f970] width 1280 pitch 5120 (/4 1280) >[131793.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131793.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131793.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131793.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131795.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131795.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131795.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131795.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131795.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131795.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131795.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131795.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131795.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131795.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131795.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131795.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131795.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131795.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131795.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131795.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131795.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131795.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131795.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131796.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131796.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131796.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131796.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131796.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131796.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131796.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131805.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131805.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131805.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131805.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131861.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131861.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131861.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131861.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131861.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131862.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131862.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131862.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131862.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131862.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131862.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131862.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131862.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131862.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131862.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131862.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131862.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131862.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131862.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131862.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131862.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131862.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131862.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131862.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131862.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131863.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131863.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131863.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131863.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131863.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131863.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131863.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131863.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131863.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131863.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131863.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131863.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131863.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131863.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e68c0] >[131863.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e68c0] width 1280 pitch 5120 (/4 1280) >[131863.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131863.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131864.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015710] >[131864.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015710] width 1280 pitch 5120 (/4 1280) >[131864.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131864.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131864.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131864.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131864.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3132e40] >[131864.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3132e40] width 1280 pitch 5120 (/4 1280) >[131864.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131864.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131864.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131864.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131864.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131864.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131864.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3114be0] >[131864.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3114be0] width 1280 pitch 5120 (/4 1280) >[131864.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127ad0] >[131864.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127ad0] width 1280 pitch 5120 (/4 1280) >[131868.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131868.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131874.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131874.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131874.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131874.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131874.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131874.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131874.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131874.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131874.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131874.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131874.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131874.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131875.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131875.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131875.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131875.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131875.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131876.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131876.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171d20] >[131876.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171d20] width 1280 pitch 5120 (/4 1280) >[131876.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196030] >[131876.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196030] width 1280 pitch 5120 (/4 1280) >[131876.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131876.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131876.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131876.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131876.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3179460] >[131876.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3179460] width 1280 pitch 5120 (/4 1280) >[131884.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131885.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131885.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196030] >[131885.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196030] width 1280 pitch 5120 (/4 1280) >[131894.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171d20] >[131894.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171d20] width 1280 pitch 5120 (/4 1280) >[131894.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196030] >[131894.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196030] width 1280 pitch 5120 (/4 1280) >[131894.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131894.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131894.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196030] >[131894.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196030] width 1280 pitch 5120 (/4 1280) >[131894.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131894.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131894.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131894.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131894.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131894.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131894.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131894.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131895.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196030] >[131895.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196030] width 1280 pitch 5120 (/4 1280) >[131895.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3179460] >[131895.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3179460] width 1280 pitch 5120 (/4 1280) >[131895.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31799d0] >[131895.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31799d0] width 1280 pitch 5120 (/4 1280) >[131895.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174fe0] >[131895.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174fe0] width 1280 pitch 5120 (/4 1280) >[131895.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131895.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131895.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131895.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131895.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x302e8d0] >[131895.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x302e8d0] width 1280 pitch 5120 (/4 1280) >[131917.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131917.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131917.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3173b60] >[131917.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3173b60] width 1280 pitch 5120 (/4 1280) >[131922.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131922.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131922.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3173b60] >[131923.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3173b60] width 1280 pitch 5120 (/4 1280) >[131923.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131923.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131923.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131923.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131923.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131923.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131923.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131923.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131923.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131923.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131923.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131923.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131923.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131923.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131924.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131924.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131924.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131924.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131924.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131924.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131924.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131924.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131924.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3173b60] >[131924.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3173b60] width 1280 pitch 5120 (/4 1280) >[131924.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131924.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131924.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131924.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131924.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131924.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131924.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131924.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131925.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131925.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131925.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131925.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131925.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131925.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131925.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131925.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131925.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131925.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131925.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131925.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131925.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131925.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131925.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131925.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131925.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131925.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3197230] >[131925.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3197230] width 1280 pitch 5120 (/4 1280) >[131925.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131926.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131926.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131926.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131926.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131926.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131926.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3173b60] >[131926.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3173b60] width 1280 pitch 5120 (/4 1280) >[131926.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131926.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131926.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[131926.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[131926.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3197230] >[131926.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3197230] width 1280 pitch 5120 (/4 1280) >[131926.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3173b60] >[131926.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3173b60] width 1280 pitch 5120 (/4 1280) >[131926.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131926.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131926.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131926.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131926.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171b40] >[131926.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171b40] width 1280 pitch 5120 (/4 1280) >[131926.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131926.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131926.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131926.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131926.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131926.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131926.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131926.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131926.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131926.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131926.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131926.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131926.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131926.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131926.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131926.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131926.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131927.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131927.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131927.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131927.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dac9d0] >[131927.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dac9d0] width 1280 pitch 5120 (/4 1280) >[131927.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056c80] >[131927.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056c80] width 1280 pitch 5120 (/4 1280) >[131927.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dac9d0] >[131927.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dac9d0] width 1280 pitch 5120 (/4 1280) >[131927.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056c80] >[131927.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056c80] width 1280 pitch 5120 (/4 1280) >[131927.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dac9d0] >[131928.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dac9d0] width 1280 pitch 5120 (/4 1280) >[131936.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131936.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131936.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131936.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131936.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131936.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131937.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131937.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131937.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131937.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131937.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131937.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131937.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131937.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131937.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131937.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131937.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131937.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131937.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131937.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131937.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3171df0] >[131937.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3171df0] width 1280 pitch 5120 (/4 1280) >[131938.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131938.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131938.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131938.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131938.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131938.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131938.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131938.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131938.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[131938.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[131938.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[131938.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[131942.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312ea80] >[131942.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312ea80] width 1280 pitch 5120 (/4 1280) >[131942.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174310] >[131942.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174310] width 1280 pitch 5120 (/4 1280) >[131942.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312ea80] >[131942.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312ea80] width 1280 pitch 5120 (/4 1280) >[131942.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174310] >[131942.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174310] width 1280 pitch 5120 (/4 1280) >[131943.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312ea80] >[131943.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312ea80] width 1280 pitch 5120 (/4 1280) >[131943.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131943.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131943.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31963d0] >[131943.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31963d0] width 1280 pitch 5120 (/4 1280) >[131943.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131943.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131943.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31963d0] >[131943.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31963d0] width 1280 pitch 5120 (/4 1280) >[131943.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131943.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131943.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31963d0] >[131944.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31963d0] width 1280 pitch 5120 (/4 1280) >[131944.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131944.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131944.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31963d0] >[131944.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31963d0] width 1280 pitch 5120 (/4 1280) >[131944.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131944.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131944.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31963d0] >[131944.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31963d0] width 1280 pitch 5120 (/4 1280) >[131944.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351270] >[131944.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351270] width 1280 pitch 5120 (/4 1280) >[131944.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x124eb60] >[131944.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x124eb60] width 1280 pitch 5120 (/4 1280) >[131944.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131944.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131944.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x124eb60] >[131944.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x124eb60] width 1280 pitch 5120 (/4 1280) >[131944.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131944.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[131944.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x124eb60] >[131944.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x124eb60] width 1280 pitch 5120 (/4 1280) >[131944.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b890] >[131944.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b890] width 1280 pitch 5120 (/4 1280) >[132104.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132104.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132104.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132104.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132104.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132105.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132105.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132105.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132105.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132105.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4580] >[132105.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4580] width 1280 pitch 5120 (/4 1280) >[132105.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132105.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132105.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x311e9f0] >[132105.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x311e9f0] width 1280 pitch 5120 (/4 1280) >[132105.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x311e9f0] >[132105.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x311e9f0] width 1280 pitch 5120 (/4 1280) >[132105.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x311e9f0] >[132105.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x311e9f0] width 1280 pitch 5120 (/4 1280) >[132105.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192dd0] >[132105.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192dd0] width 1280 pitch 5120 (/4 1280) >[132105.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192dd0] >[132105.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192dd0] width 1280 pitch 5120 (/4 1280) >[132105.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192dd0] >[132105.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192dd0] width 1280 pitch 5120 (/4 1280) >[132105.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132105.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192dd0] >[132105.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192dd0] width 1280 pitch 5120 (/4 1280) >[132105.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309e1a0] >[132105.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309e1a0] width 1280 pitch 5120 (/4 1280) >[132106.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x318b210] >[132106.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x318b210] width 1280 pitch 5120 (/4 1280) >[132108.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132108.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132108.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[132108.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[132108.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132108.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132108.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132108.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132108.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132108.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132108.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132108.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132108.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132108.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132108.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132108.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132108.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132108.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132108.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132108.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132108.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132108.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132108.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132108.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132109.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3174f20] >[132109.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3174f20] width 1280 pitch 5120 (/4 1280) >[132109.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157de0] >[132109.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157de0] width 1280 pitch 5120 (/4 1280) >[132140.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132140.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132140.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132140.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132140.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132140.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132140.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132140.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132140.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132140.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132140.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132140.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132140.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132140.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132140.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132140.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132140.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c41d0] >[132140.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c41d0] width 1280 pitch 5120 (/4 1280) >[132141.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3194dd0] >[132141.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3194dd0] width 1280 pitch 5120 (/4 1280) >[132141.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c41d0] >[132141.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c41d0] width 1280 pitch 5120 (/4 1280) >[132141.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3194dd0] >[132141.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3194dd0] width 1280 pitch 5120 (/4 1280) >[132142.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c41d0] >[132142.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c41d0] width 1280 pitch 5120 (/4 1280) >[132142.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132142.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132142.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132142.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132142.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132142.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132142.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30679e0] >[132142.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30679e0] width 1280 pitch 5120 (/4 1280) >[132142.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2673530] >[132142.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2673530] width 1280 pitch 5120 (/4 1280) >[132142.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[132142.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[132272.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eea40] >[132272.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eea40] width 1280 pitch 5120 (/4 1280) >[132272.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eea40] >[132272.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eea40] width 1280 pitch 5120 (/4 1280) >[132295.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3162940] >[132295.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3162940] width 1280 pitch 5120 (/4 1280) >[132295.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[132295.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[132302.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b610] >[132302.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b610] width 1280 pitch 5120 (/4 1280) >[132302.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25352a0] >[132302.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25352a0] width 1280 pitch 5120 (/4 1280) >[132302.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23dc9a0] >[132302.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23dc9a0] width 1280 pitch 5120 (/4 1280) >[132302.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133410] >[132303.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133410] width 1280 pitch 5120 (/4 1280) >[132905.670] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[132905.670] (II) RADEON(0): Printing DDC gathered Modelines: >[132905.670] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[132995.904] (II) RADEON(0): RADEONSaveScreen(2) >[132995.905] (II) RADEON(0): RADEONSaveScreen(0) >[135316.176] (II) RADEON(0): RADEONSaveScreen(1) >[135323.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2458fa0] >[135323.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2458fa0] width 1280 pitch 5120 (/4 1280) >[135325.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135325.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135325.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135325.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135325.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135325.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135325.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135325.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135325.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135325.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135325.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135325.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135325.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135325.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135325.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151710] >[135326.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151710] width 1280 pitch 5120 (/4 1280) >[135326.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135326.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135326.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31527d0] >[135326.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31527d0] width 1280 pitch 5120 (/4 1280) >[135326.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135327.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135327.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135327.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177ee0] >[135327.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177ee0] width 1280 pitch 5120 (/4 1280) >[135328.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b3650] >[135328.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b3650] width 1280 pitch 5120 (/4 1280) >[135328.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135328.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135328.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ed0b0] >[135328.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ed0b0] width 1280 pitch 5120 (/4 1280) >[135328.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135328.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135328.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ed0b0] >[135328.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ed0b0] width 1280 pitch 5120 (/4 1280) >[135328.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c5b0] >[135328.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c5b0] width 1280 pitch 5120 (/4 1280) >[135328.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161840] >[135328.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161840] width 1280 pitch 5120 (/4 1280) >[135328.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3162940] >[135328.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3162940] width 1280 pitch 5120 (/4 1280) >[135368.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317c470] >[135368.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317c470] width 1280 pitch 5120 (/4 1280) >[135368.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3196660] >[135368.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3196660] width 1280 pitch 5120 (/4 1280) >[135449.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202e180] >[135449.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202e180] width 1280 pitch 5120 (/4 1280) >[135449.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202e180] >[135449.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202e180] width 1280 pitch 5120 (/4 1280) >[135449.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202e180] >[135449.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202e180] width 1280 pitch 5120 (/4 1280) >[135449.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202e180] >[135449.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202e180] width 1280 pitch 5120 (/4 1280) >[135449.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202e180] >[135449.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202e180] width 1280 pitch 5120 (/4 1280) >[135449.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135449.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135449.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135449.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135449.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135449.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135449.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135449.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135449.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135449.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135449.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135450.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aa7c0] >[135450.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aa7c0] width 1280 pitch 5120 (/4 1280) >[135450.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135450.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135451.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135451.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135451.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135451.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135452.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a4d50] >[135452.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a4d50] width 1280 pitch 5120 (/4 1280) >[135452.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135452.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135452.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c18c0] >[135452.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c18c0] width 1280 pitch 5120 (/4 1280) >[135452.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e5f30] >[135452.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e5f30] width 1280 pitch 5120 (/4 1280) >[135452.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135452.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135452.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e5f30] >[135452.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e5f30] width 1280 pitch 5120 (/4 1280) >[135452.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135452.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135452.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e5f30] >[135452.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e5f30] width 1280 pitch 5120 (/4 1280) >[135452.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135452.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135452.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c18c0] >[135452.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c18c0] width 1280 pitch 5120 (/4 1280) >[135453.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135453.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135453.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135453.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135453.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135454.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135454.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135454.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135454.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135455.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135455.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135455.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135455.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135455.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135455.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135455.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135455.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135455.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135455.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135455.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135455.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135455.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135455.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3164180] >[135455.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3164180] width 1280 pitch 5120 (/4 1280) >[135457.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1dff0] >[135457.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1dff0] width 1280 pitch 5120 (/4 1280) >[135457.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x318e570] >[135457.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x318e570] width 1280 pitch 5120 (/4 1280) >[135457.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3189870] >[135457.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3189870] width 1280 pitch 5120 (/4 1280) >[135457.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d323a0] >[135457.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d323a0] width 1280 pitch 5120 (/4 1280) >[135457.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1dff0] >[135457.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1dff0] width 1280 pitch 5120 (/4 1280) >[135457.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6340] >[135457.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6340] width 1280 pitch 5120 (/4 1280) >[135457.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135457.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135457.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x318e570] >[135457.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x318e570] width 1280 pitch 5120 (/4 1280) >[135457.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d323a0] >[135458.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d323a0] width 1280 pitch 5120 (/4 1280) >[135458.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1dff0] >[135458.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1dff0] width 1280 pitch 5120 (/4 1280) >[135458.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316b170] >[135458.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316b170] width 1280 pitch 5120 (/4 1280) >[135458.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135458.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135458.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135458.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135458.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135458.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135458.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135458.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135458.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135458.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135458.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135458.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135458.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135458.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135458.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135458.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135458.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316b170] >[135458.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316b170] width 1280 pitch 5120 (/4 1280) >[135458.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1dff0] >[135458.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1dff0] width 1280 pitch 5120 (/4 1280) >[135458.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d323a0] >[135458.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d323a0] width 1280 pitch 5120 (/4 1280) >[135458.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x318e570] >[135458.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x318e570] width 1280 pitch 5120 (/4 1280) >[135458.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3189870] >[135458.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3189870] width 1280 pitch 5120 (/4 1280) >[135458.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1febd90] >[135458.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1febd90] width 1280 pitch 5120 (/4 1280) >[135458.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154bc0] >[135458.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154bc0] width 1280 pitch 5120 (/4 1280) >[135473.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x318e570] >[135473.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x318e570] width 1280 pitch 5120 (/4 1280) >[135473.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d323a0] >[135473.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d323a0] width 1280 pitch 5120 (/4 1280) >[135474.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316b170] >[135474.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316b170] width 1280 pitch 5120 (/4 1280) >[135474.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3189870] >[135474.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3189870] width 1280 pitch 5120 (/4 1280) >[135474.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192ae0] >[135474.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192ae0] width 1280 pitch 5120 (/4 1280) >[135474.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de56e0] >[135474.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de56e0] width 1280 pitch 5120 (/4 1280) >[135474.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192ae0] >[135474.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192ae0] width 1280 pitch 5120 (/4 1280) >[135474.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de56e0] >[135474.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de56e0] width 1280 pitch 5120 (/4 1280) >[135474.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192ae0] >[135474.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192ae0] width 1280 pitch 5120 (/4 1280) >[135474.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de56e0] >[135474.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de56e0] width 1280 pitch 5120 (/4 1280) >[135475.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192ae0] >[135475.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192ae0] width 1280 pitch 5120 (/4 1280) >[135475.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316b170] >[135475.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316b170] width 1280 pitch 5120 (/4 1280) >[135475.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224ed60] >[135475.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224ed60] width 1280 pitch 5120 (/4 1280) >[135475.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135475.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135475.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224ed60] >[135475.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224ed60] width 1280 pitch 5120 (/4 1280) >[135475.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d370] >[135475.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d370] width 1280 pitch 5120 (/4 1280) >[135498.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[135498.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[135498.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2e50] >[135498.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2e50] width 1280 pitch 5120 (/4 1280) >[135554.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3175f90] >[135554.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3175f90] width 1280 pitch 5120 (/4 1280) >[135556.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31733c0] >[135556.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31733c0] width 1280 pitch 5120 (/4 1280) >[135557.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e9cc0] >[135557.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e9cc0] width 1280 pitch 5120 (/4 1280) >[135557.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31733c0] >[135557.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31733c0] width 1280 pitch 5120 (/4 1280) >[135704.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3180630] >[135704.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3180630] width 1280 pitch 5120 (/4 1280) >[135704.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322bfe0] >[135704.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322bfe0] width 1280 pitch 5120 (/4 1280) >[135739.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efa50] >[135739.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efa50] width 1280 pitch 5120 (/4 1280) >[135739.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a54e0] >[135739.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a54e0] width 1280 pitch 5120 (/4 1280) >[135809.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31faeb0] >[135809.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31faeb0] width 1280 pitch 5120 (/4 1280) >[135840.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31675b0] >[135840.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31675b0] width 1280 pitch 5120 (/4 1280) >[135878.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3090] >[135878.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3090] width 1280 pitch 5120 (/4 1280) >[135878.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fe630] >[135878.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fe630] width 1280 pitch 5120 (/4 1280) >[135878.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31675b0] >[135878.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31675b0] width 1280 pitch 5120 (/4 1280) >[135878.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fb8d0] >[135878.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fb8d0] width 1280 pitch 5120 (/4 1280) >[135930.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135930.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135930.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135930.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135930.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135931.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135931.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135931.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135931.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135931.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135931.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135931.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135931.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135931.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135931.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216170] >[135931.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216170] width 1280 pitch 5120 (/4 1280) >[135931.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216170] >[135931.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216170] width 1280 pitch 5120 (/4 1280) >[135931.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216170] >[135931.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216170] width 1280 pitch 5120 (/4 1280) >[135931.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216170] >[135931.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216170] width 1280 pitch 5120 (/4 1280) >[135931.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2535130] >[135931.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2535130] width 1280 pitch 5120 (/4 1280) >[135931.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216170] >[135931.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216170] width 1280 pitch 5120 (/4 1280) >[135932.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31aaf90] >[135932.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31aaf90] width 1280 pitch 5120 (/4 1280) >[135932.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3090] >[135932.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3090] width 1280 pitch 5120 (/4 1280) >[135932.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dda70] >[135932.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dda70] width 1280 pitch 5120 (/4 1280) >[135932.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3090] >[135932.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3090] width 1280 pitch 5120 (/4 1280) >[135932.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dda70] >[135932.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dda70] width 1280 pitch 5120 (/4 1280) >[135932.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3090] >[135932.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3090] width 1280 pitch 5120 (/4 1280) >[135932.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dfce0] >[135932.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dfce0] width 1280 pitch 5120 (/4 1280) >[135933.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e4c80] >[135933.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e4c80] width 1280 pitch 5120 (/4 1280) >[135934.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e4c80] >[135934.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e4c80] width 1280 pitch 5120 (/4 1280) >[136107.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136107.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136107.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226aa0] >[136107.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226aa0] width 1280 pitch 5120 (/4 1280) >[136107.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226aa0] >[136107.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226aa0] width 1280 pitch 5120 (/4 1280) >[136107.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136107.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136107.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226aa0] >[136107.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226aa0] width 1280 pitch 5120 (/4 1280) >[136108.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226aa0] >[136108.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226aa0] width 1280 pitch 5120 (/4 1280) >[136108.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136108.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136108.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136108.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[136108.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[136111.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32272a0] >[136112.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32272a0] width 1280 pitch 5120 (/4 1280) >[136113.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136113.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136113.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136113.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136113.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316c0f0] >[136113.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316c0f0] width 1280 pitch 5120 (/4 1280) >[136122.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136122.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136122.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc620] >[136122.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc620] width 1280 pitch 5120 (/4 1280) >[136122.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136122.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136123.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc620] >[136123.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc620] width 1280 pitch 5120 (/4 1280) >[136123.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136123.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136123.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc620] >[136123.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc620] width 1280 pitch 5120 (/4 1280) >[136123.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc620] >[136123.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc620] width 1280 pitch 5120 (/4 1280) >[136123.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1388600] >[136123.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1388600] width 1280 pitch 5120 (/4 1280) >[136130.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136130.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136130.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e53c80] >[136130.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e53c80] width 1280 pitch 5120 (/4 1280) >[136130.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd2ac0] >[136130.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd2ac0] width 1280 pitch 5120 (/4 1280) >[136130.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136130.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136130.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d97e0] >[136130.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d97e0] width 1280 pitch 5120 (/4 1280) >[136130.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc4c0] >[136130.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc4c0] width 1280 pitch 5120 (/4 1280) >[136168.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118ec0] >[136168.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118ec0] width 1280 pitch 5120 (/4 1280) >[136168.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136168.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136168.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd2ac0] >[136168.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd2ac0] width 1280 pitch 5120 (/4 1280) >[136169.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc620] >[136169.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc620] width 1280 pitch 5120 (/4 1280) >[136170.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136170.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136170.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd2ac0] >[136170.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd2ac0] width 1280 pitch 5120 (/4 1280) >[136170.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3187a30] >[136170.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3187a30] width 1280 pitch 5120 (/4 1280) >[136170.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3180630] >[136170.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3180630] width 1280 pitch 5120 (/4 1280) >[136170.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136170.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136170.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fe8e0] >[136170.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fe8e0] width 1280 pitch 5120 (/4 1280) >[136170.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136170.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136170.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dd620] >[136170.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dd620] width 1280 pitch 5120 (/4 1280) >[136172.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dd620] >[136172.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dd620] width 1280 pitch 5120 (/4 1280) >[136172.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136172.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136172.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dd620] >[136172.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dd620] width 1280 pitch 5120 (/4 1280) >[136173.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x152a650] >[136173.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x152a650] width 1280 pitch 5120 (/4 1280) >[136173.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dd620] >[136173.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dd620] width 1280 pitch 5120 (/4 1280) >[136173.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229a00] >[136173.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229a00] width 1280 pitch 5120 (/4 1280) >[136173.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dd620] >[136173.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dd620] width 1280 pitch 5120 (/4 1280) >[136262.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a113e0] >[136262.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a113e0] width 1280 pitch 5120 (/4 1280) >[136263.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[136263.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[136263.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216890] >[136263.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216890] width 1280 pitch 5120 (/4 1280) >[136263.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[136263.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[136274.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136274.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136274.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3df0] >[136274.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3df0] width 1280 pitch 5120 (/4 1280) >[136274.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3df0] >[136274.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3df0] width 1280 pitch 5120 (/4 1280) >[136274.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3df0] >[136275.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3df0] width 1280 pitch 5120 (/4 1280) >[136309.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[136309.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[136309.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x110f240] >[136309.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x110f240] width 1280 pitch 5120 (/4 1280) >[136309.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136309.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136309.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136309.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136310.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136310.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136310.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[136310.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[136310.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136310.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136310.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136310.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136311.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136311.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136311.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136311.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136311.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136311.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136311.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d9b20] >[136312.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d9b20] width 1280 pitch 5120 (/4 1280) >[136357.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136357.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136357.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136357.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136357.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136357.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136357.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136357.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136357.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136357.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136357.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136357.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136357.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136357.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136357.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136357.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136357.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136365.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136365.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136365.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136365.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136365.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136365.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136365.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136365.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136365.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136365.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12ad140] >[136366.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12ad140] width 1280 pitch 5120 (/4 1280) >[136393.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136393.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136393.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfa0] >[136393.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfa0] width 1280 pitch 5120 (/4 1280) >[136393.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[136393.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[136393.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7b30] >[136393.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7b30] width 1280 pitch 5120 (/4 1280) >[136393.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a9810] >[136393.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a9810] width 1280 pitch 5120 (/4 1280) >[136393.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1afc660] >[136393.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1afc660] width 1280 pitch 5120 (/4 1280) >[136397.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab0a0] >[136397.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab0a0] width 1280 pitch 5120 (/4 1280) >[136397.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136397.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136397.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136397.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136398.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136398.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136424.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c2be0] >[136424.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c2be0] width 1280 pitch 5120 (/4 1280) >[136424.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c2be0] >[136424.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c2be0] width 1280 pitch 5120 (/4 1280) >[136424.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136424.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136424.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a9810] >[136424.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a9810] width 1280 pitch 5120 (/4 1280) >[136432.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[136432.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[136432.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6840] >[136432.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6840] width 1280 pitch 5120 (/4 1280) >[136437.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7b30] >[136437.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7b30] width 1280 pitch 5120 (/4 1280) >[136437.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[136437.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[136462.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dc2d0] >[136462.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dc2d0] width 1280 pitch 5120 (/4 1280) >[136462.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227d30] >[136462.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227d30] width 1280 pitch 5120 (/4 1280) >[136462.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3223600] >[136462.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3223600] width 1280 pitch 5120 (/4 1280) >[136462.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dc2d0] >[136462.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dc2d0] width 1280 pitch 5120 (/4 1280) >[136463.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d6980] >[136463.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d6980] width 1280 pitch 5120 (/4 1280) >[136463.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6840] >[136463.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6840] width 1280 pitch 5120 (/4 1280) >[136463.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7260] >[136463.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7260] width 1280 pitch 5120 (/4 1280) >[136463.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c2be0] >[136463.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c2be0] width 1280 pitch 5120 (/4 1280) >[136463.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b610] >[136463.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b610] width 1280 pitch 5120 (/4 1280) >[136463.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dc2d0] >[136463.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dc2d0] width 1280 pitch 5120 (/4 1280) >[136463.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b4ab0] >[136463.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b4ab0] width 1280 pitch 5120 (/4 1280) >[136463.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c890] >[136463.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c890] width 1280 pitch 5120 (/4 1280) >[136463.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136463.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136463.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a5770] >[136463.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a5770] width 1280 pitch 5120 (/4 1280) >[136463.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6840] >[136463.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6840] width 1280 pitch 5120 (/4 1280) >[136563.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136563.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136563.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136563.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136563.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96e80] >[136563.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96e80] width 1280 pitch 5120 (/4 1280) >[136563.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b4ab0] >[136563.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b4ab0] width 1280 pitch 5120 (/4 1280) >[136563.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96e80] >[136563.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96e80] width 1280 pitch 5120 (/4 1280) >[136563.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7260] >[136563.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7260] width 1280 pitch 5120 (/4 1280) >[136564.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136564.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136564.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136564.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136564.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136564.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136564.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136564.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136564.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136564.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136564.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136564.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136564.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136564.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136564.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7260] >[136564.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7260] width 1280 pitch 5120 (/4 1280) >[136564.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136564.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136564.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136564.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136564.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136564.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136564.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136564.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3227dd0] >[136564.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3227dd0] width 1280 pitch 5120 (/4 1280) >[136564.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136564.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136584.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[136584.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[136584.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136584.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136610.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136610.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136610.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136610.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136610.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3a40] >[136610.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3a40] width 1280 pitch 5120 (/4 1280) >[136610.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[136611.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[136617.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[136617.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[136617.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136617.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136617.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[136617.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[136617.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[136617.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[136638.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b4ab0] >[136638.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b4ab0] width 1280 pitch 5120 (/4 1280) >[136638.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136638.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136638.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273c430] >[136638.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273c430] width 1280 pitch 5120 (/4 1280) >[136638.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[136639.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[136654.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136654.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136654.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[136654.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[136654.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32037f0] >[136654.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32037f0] width 1280 pitch 5120 (/4 1280) >[136654.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7260] >[136654.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7260] width 1280 pitch 5120 (/4 1280) >[136666.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3a40] >[136666.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3a40] width 1280 pitch 5120 (/4 1280) >[136666.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2775660] >[136666.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2775660] width 1280 pitch 5120 (/4 1280) >[136666.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[136666.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[136666.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b4ab0] >[136666.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b4ab0] width 1280 pitch 5120 (/4 1280) >[136671.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[136671.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[136671.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[136671.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[136671.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[136671.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[136671.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[136671.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[136671.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27427b0] >[136671.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27427b0] width 1280 pitch 5120 (/4 1280) >[136682.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136682.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136682.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[136682.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[136682.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[136682.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[136682.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[136682.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[136738.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3207250] >[136738.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3207250] width 1280 pitch 5120 (/4 1280) >[136738.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[136738.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[136744.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136744.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136744.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136744.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136744.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136744.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136744.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[136744.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[136771.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136771.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136771.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136771.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136771.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136771.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136771.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[136771.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[136771.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[136771.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[136771.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[136771.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[136771.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[136771.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[136771.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[136771.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[136771.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136771.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136771.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136771.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136771.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3a40] >[136771.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3a40] width 1280 pitch 5120 (/4 1280) >[136771.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fe950] >[136771.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fe950] width 1280 pitch 5120 (/4 1280) >[136771.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e3a40] >[136771.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e3a40] width 1280 pitch 5120 (/4 1280) >[136772.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136772.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136772.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136772.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136772.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136772.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136772.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136772.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136772.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136772.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136772.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136772.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136772.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136772.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136772.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136772.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136772.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136772.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136772.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136773.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136773.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32004e0] >[136773.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32004e0] width 1280 pitch 5120 (/4 1280) >[136773.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31659c0] >[136773.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31659c0] width 1280 pitch 5120 (/4 1280) >[136774.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[136774.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[136774.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136774.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[136774.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31659c0] >[136774.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31659c0] width 1280 pitch 5120 (/4 1280) >[136774.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[136774.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[136774.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3091000] >[136774.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3091000] width 1280 pitch 5120 (/4 1280) >[136774.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3091000] >[136774.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3091000] width 1280 pitch 5120 (/4 1280) >[136774.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[136774.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[136774.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3091000] >[136774.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3091000] width 1280 pitch 5120 (/4 1280) >[136774.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[136774.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[136777.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[136777.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[136790.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d5d0] >[136790.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d5d0] width 1280 pitch 5120 (/4 1280) >[136790.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136790.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136790.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136790.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136790.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[136790.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[136791.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3f30] >[136791.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3f30] width 1280 pitch 5120 (/4 1280) >[136800.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2779050] >[136800.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2779050] width 1280 pitch 5120 (/4 1280) >[136801.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136801.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136801.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136801.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136801.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31659c0] >[136801.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31659c0] width 1280 pitch 5120 (/4 1280) >[136801.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[136801.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[136801.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d5d0] >[136801.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d5d0] width 1280 pitch 5120 (/4 1280) >[136801.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[136801.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[136801.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31659c0] >[136801.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31659c0] width 1280 pitch 5120 (/4 1280) >[136806.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663830] >[136806.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663830] width 1280 pitch 5120 (/4 1280) >[136835.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[136835.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[136835.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[136835.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[136835.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[136835.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[136835.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663830] >[136835.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663830] width 1280 pitch 5120 (/4 1280) >[136835.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136835.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136835.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[136835.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[136835.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b540] >[136835.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b540] width 1280 pitch 5120 (/4 1280) >[136835.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[136835.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[136869.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b540] >[136869.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b540] width 1280 pitch 5120 (/4 1280) >[136869.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[136869.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[136869.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2779050] >[136869.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2779050] width 1280 pitch 5120 (/4 1280) >[136869.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff7e90] >[136869.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff7e90] width 1280 pitch 5120 (/4 1280) >[136870.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d7260] >[136870.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d7260] width 1280 pitch 5120 (/4 1280) >[136870.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[136870.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[136870.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c1eb0] >[136870.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c1eb0] width 1280 pitch 5120 (/4 1280) >[136870.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[136870.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137006.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3f30] >[137006.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3f30] width 1280 pitch 5120 (/4 1280) >[137006.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2779050] >[137006.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2779050] width 1280 pitch 5120 (/4 1280) >[137006.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137006.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137006.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[137006.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[137007.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137007.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137007.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137007.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137016.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663830] >[137016.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663830] width 1280 pitch 5120 (/4 1280) >[137016.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a11b50] >[137016.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a11b50] width 1280 pitch 5120 (/4 1280) >[137037.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137037.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137037.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[137037.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[137037.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d330] >[137037.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d330] width 1280 pitch 5120 (/4 1280) >[137037.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[137037.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[137044.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137044.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137044.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137044.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137044.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137044.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137044.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2779050] >[137044.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2779050] width 1280 pitch 5120 (/4 1280) >[137045.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3f30] >[137045.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3f30] width 1280 pitch 5120 (/4 1280) >[137045.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137045.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137046.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2763b80] >[137046.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2763b80] width 1280 pitch 5120 (/4 1280) >[137046.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[137046.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[137046.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e6d0] >[137046.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e6d0] width 1280 pitch 5120 (/4 1280) >[137046.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137046.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137073.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137073.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137073.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137073.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137073.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137073.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137073.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137073.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137073.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137073.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137073.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137073.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137073.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137073.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137074.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137074.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137074.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137074.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137074.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137074.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137074.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e6d0] >[137074.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e6d0] width 1280 pitch 5120 (/4 1280) >[137074.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e6d0] >[137074.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e6d0] width 1280 pitch 5120 (/4 1280) >[137074.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137074.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137074.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e6d0] >[137074.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e6d0] width 1280 pitch 5120 (/4 1280) >[137074.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137074.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137076.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137076.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137076.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229250] >[137076.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229250] width 1280 pitch 5120 (/4 1280) >[137076.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137076.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137080.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[137080.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[137080.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137080.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137080.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[137080.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[137081.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229250] >[137081.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229250] width 1280 pitch 5120 (/4 1280) >[137081.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663830] >[137081.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663830] width 1280 pitch 5120 (/4 1280) >[137081.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2763b80] >[137081.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2763b80] width 1280 pitch 5120 (/4 1280) >[137081.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2763b80] >[137081.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2763b80] width 1280 pitch 5120 (/4 1280) >[137081.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137081.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137082.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137082.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137082.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229250] >[137082.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229250] width 1280 pitch 5120 (/4 1280) >[137082.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f840] >[137082.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f840] width 1280 pitch 5120 (/4 1280) >[137089.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137089.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137089.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206c20] >[137089.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206c20] width 1280 pitch 5120 (/4 1280) >[137091.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137091.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137091.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137091.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137091.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea130] >[137091.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea130] width 1280 pitch 5120 (/4 1280) >[137092.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137092.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137092.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137092.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137092.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137092.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137108.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137108.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137108.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137108.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137108.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2763810] >[137108.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2763810] width 1280 pitch 5120 (/4 1280) >[137108.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0ccb0] >[137108.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0ccb0] width 1280 pitch 5120 (/4 1280) >[137138.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137138.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137138.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea130] >[137138.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea130] width 1280 pitch 5120 (/4 1280) >[137155.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137155.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137155.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137155.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137164.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137164.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137164.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137164.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137164.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137164.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137164.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137164.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137165.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c33a0] >[137165.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c33a0] width 1280 pitch 5120 (/4 1280) >[137165.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137165.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137165.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276fcd0] >[137165.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276fcd0] width 1280 pitch 5120 (/4 1280) >[137165.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1152bb0] >[137165.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1152bb0] width 1280 pitch 5120 (/4 1280) >[137165.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0ccb0] >[137165.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0ccb0] width 1280 pitch 5120 (/4 1280) >[137165.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[137165.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[137173.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137173.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137173.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137173.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137206.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0b5e0] >[137206.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0b5e0] width 1280 pitch 5120 (/4 1280) >[137206.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137206.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137207.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137207.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137207.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276fcd0] >[137207.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276fcd0] width 1280 pitch 5120 (/4 1280) >[137207.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137207.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137207.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137207.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137208.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137208.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137208.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137208.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137208.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137208.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137208.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137208.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137233.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137233.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137233.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0ccb0] >[137233.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0ccb0] width 1280 pitch 5120 (/4 1280) >[137237.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2701110] >[137237.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2701110] width 1280 pitch 5120 (/4 1280) >[137253.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ba900] >[137253.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ba900] width 1280 pitch 5120 (/4 1280) >[137253.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2721120] >[137253.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2721120] width 1280 pitch 5120 (/4 1280) >[137257.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27baf40] >[137257.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27baf40] width 1280 pitch 5120 (/4 1280) >[137257.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[137257.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[137257.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137257.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137257.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137257.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137257.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137257.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137257.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137257.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137257.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137257.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137257.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c3e0] >[137257.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c3e0] width 1280 pitch 5120 (/4 1280) >[137257.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137257.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137271.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[137271.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[137272.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c6f0] >[137272.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c6f0] width 1280 pitch 5120 (/4 1280) >[137272.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27baf40] >[137272.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27baf40] width 1280 pitch 5120 (/4 1280) >[137284.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27baf40] >[137284.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27baf40] width 1280 pitch 5120 (/4 1280) >[137284.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206c20] >[137284.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206c20] width 1280 pitch 5120 (/4 1280) >[137284.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3223b80] >[137284.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3223b80] width 1280 pitch 5120 (/4 1280) >[137284.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206c20] >[137284.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206c20] width 1280 pitch 5120 (/4 1280) >[137284.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276fcd0] >[137284.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276fcd0] width 1280 pitch 5120 (/4 1280) >[137284.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137284.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137285.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[137285.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[137285.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[137285.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[137285.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137286.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137286.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137286.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137286.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137286.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137286.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137286.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137288.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[137288.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[137288.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[137288.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[137288.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137288.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137288.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fd4d0] >[137288.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fd4d0] width 1280 pitch 5120 (/4 1280) >[137294.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[137294.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[137294.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703250] >[137294.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703250] width 1280 pitch 5120 (/4 1280) >[137301.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271e6a0] >[137301.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271e6a0] width 1280 pitch 5120 (/4 1280) >[137301.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[137301.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[137301.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137301.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137301.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137301.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137301.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137301.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137301.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137301.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137301.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137301.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137301.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137301.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137301.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137301.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137301.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137301.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137301.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137301.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137301.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137301.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137329.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137329.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137329.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[137329.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[137329.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137329.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137329.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a10530] >[137329.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a10530] width 1280 pitch 5120 (/4 1280) >[137329.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137329.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137329.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137329.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137329.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219ba0] >[137329.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219ba0] width 1280 pitch 5120 (/4 1280) >[137330.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32115c0] >[137330.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32115c0] width 1280 pitch 5120 (/4 1280) >[137408.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137408.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137408.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137408.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137408.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137408.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137408.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[137408.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[137408.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276fcd0] >[137408.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276fcd0] width 1280 pitch 5120 (/4 1280) >[137408.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137408.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137448.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137448.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137448.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c680] >[137448.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c680] width 1280 pitch 5120 (/4 1280) >[137448.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137448.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137448.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137448.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137448.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137448.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137449.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137449.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137449.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f730] >[137449.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f730] width 1280 pitch 5120 (/4 1280) >[137449.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137449.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137476.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137476.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137476.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[137476.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[137476.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[137476.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[137476.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ab40] >[137476.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ab40] width 1280 pitch 5120 (/4 1280) >[137476.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ab40] >[137476.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ab40] width 1280 pitch 5120 (/4 1280) >[137476.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137476.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137476.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[137476.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[137476.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137476.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137477.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137477.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137477.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ab40] >[137477.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ab40] width 1280 pitch 5120 (/4 1280) >[137477.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d330] >[137477.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d330] width 1280 pitch 5120 (/4 1280) >[137477.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137477.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137478.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703a50] >[137478.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703a50] width 1280 pitch 5120 (/4 1280) >[137478.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137478.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137478.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0b8f0] >[137478.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0b8f0] width 1280 pitch 5120 (/4 1280) >[137478.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137478.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137495.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d330] >[137495.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d330] width 1280 pitch 5120 (/4 1280) >[137495.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137495.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137495.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2701ae0] >[137495.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2701ae0] width 1280 pitch 5120 (/4 1280) >[137495.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274d090] >[137495.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274d090] width 1280 pitch 5120 (/4 1280) >[137496.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27342e0] >[137496.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27342e0] width 1280 pitch 5120 (/4 1280) >[137496.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273c630] >[137496.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273c630] width 1280 pitch 5120 (/4 1280) >[137496.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703300] >[137496.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703300] width 1280 pitch 5120 (/4 1280) >[137496.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[137496.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[137501.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137501.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137501.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137501.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137501.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2718550] >[137501.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2718550] width 1280 pitch 5120 (/4 1280) >[137501.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c0ea0] >[137501.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c0ea0] width 1280 pitch 5120 (/4 1280) >[137503.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b200] >[137503.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b200] width 1280 pitch 5120 (/4 1280) >[137503.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bbee0] >[137503.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bbee0] width 1280 pitch 5120 (/4 1280) >[137538.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[137538.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[137538.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270b1d0] >[137538.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270b1d0] width 1280 pitch 5120 (/4 1280) >[137538.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137538.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137538.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bbee0] >[137538.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bbee0] width 1280 pitch 5120 (/4 1280) >[137538.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137538.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137539.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bbee0] >[137539.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bbee0] width 1280 pitch 5120 (/4 1280) >[137539.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137539.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137539.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274f660] >[137539.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274f660] width 1280 pitch 5120 (/4 1280) >[137539.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c1eb0] >[137539.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c1eb0] width 1280 pitch 5120 (/4 1280) >[137539.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308d330] >[137539.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308d330] width 1280 pitch 5120 (/4 1280) >[137539.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137539.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137540.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[137540.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[137540.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a97b0] >[137540.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a97b0] width 1280 pitch 5120 (/4 1280) >[137540.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2742fa0] >[137540.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2742fa0] width 1280 pitch 5120 (/4 1280) >[137540.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bccb0] >[137540.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bccb0] width 1280 pitch 5120 (/4 1280) >[137540.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137540.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137577.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[137577.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[137577.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[137577.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[137577.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137577.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137578.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[137578.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[137588.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[137588.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[137588.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a01be0] >[137588.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a01be0] width 1280 pitch 5120 (/4 1280) >[137588.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27178f0] >[137588.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27178f0] width 1280 pitch 5120 (/4 1280) >[137588.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276aff0] >[137588.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276aff0] width 1280 pitch 5120 (/4 1280) >[137591.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a01ba0] >[137591.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a01ba0] width 1280 pitch 5120 (/4 1280) >[137591.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2717140] >[137591.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2717140] width 1280 pitch 5120 (/4 1280) >[137592.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[137592.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[137592.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137592.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137592.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137592.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137592.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137592.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137601.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137601.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137601.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703a50] >[137601.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703a50] width 1280 pitch 5120 (/4 1280) >[137601.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137601.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137601.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137601.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137601.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137601.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137601.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137601.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137601.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137601.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137601.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274c1d0] >[137601.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274c1d0] width 1280 pitch 5120 (/4 1280) >[137602.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137602.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137602.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137602.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137635.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2768b30] >[137635.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2768b30] width 1280 pitch 5120 (/4 1280) >[137635.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3165bd0] >[137635.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3165bd0] width 1280 pitch 5120 (/4 1280) >[137635.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[137635.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[137635.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137635.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137635.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137635.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137635.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137635.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137635.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137635.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137635.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137635.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137636.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765c80] >[137636.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765c80] width 1280 pitch 5120 (/4 1280) >[137637.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137637.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137637.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137637.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137637.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137637.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137637.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137637.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137638.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137638.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137638.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137638.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137638.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703300] >[137638.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703300] width 1280 pitch 5120 (/4 1280) >[137651.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2703300] >[137651.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2703300] width 1280 pitch 5120 (/4 1280) >[137651.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137651.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137651.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137651.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137652.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137652.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137652.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137652.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137652.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137652.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137652.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137652.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137652.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137652.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137655.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137655.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137655.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2720660] >[137655.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2720660] width 1280 pitch 5120 (/4 1280) >[137655.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137655.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137655.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137655.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137655.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137655.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137656.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137656.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137656.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[137656.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[137656.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137656.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137715.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[137715.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[137717.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137717.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137717.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[137717.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[137717.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137717.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137717.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[137717.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[137718.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2702820] >[137718.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2702820] width 1280 pitch 5120 (/4 1280) >[137718.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137718.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137718.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2722050] >[137718.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2722050] width 1280 pitch 5120 (/4 1280) >[137718.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2769580] >[137718.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2769580] width 1280 pitch 5120 (/4 1280) >[137718.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137718.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137718.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af270] >[137718.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af270] width 1280 pitch 5120 (/4 1280) >[137718.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[137718.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[137734.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[137734.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[137734.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2706c00] >[137734.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2706c00] width 1280 pitch 5120 (/4 1280) >[137734.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765c80] >[137734.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765c80] width 1280 pitch 5120 (/4 1280) >[137734.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[137734.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[137735.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137735.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137735.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137735.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137735.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137735.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137735.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765c80] >[137735.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765c80] width 1280 pitch 5120 (/4 1280) >[137759.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137759.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137759.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137759.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137759.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137759.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137759.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137759.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137760.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137760.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137760.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2722050] >[137760.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2722050] width 1280 pitch 5120 (/4 1280) >[137760.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[137760.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[137760.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137760.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137766.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2722050] >[137766.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2722050] width 1280 pitch 5120 (/4 1280) >[137766.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137766.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137766.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[137766.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[137766.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137766.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137767.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137767.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137767.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[137767.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[137767.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137767.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137767.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[137767.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[137782.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[137782.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[137782.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137782.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137782.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ff000] >[137782.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ff000] width 1280 pitch 5120 (/4 1280) >[137782.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137782.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137782.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2702d60] >[137782.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2702d60] width 1280 pitch 5120 (/4 1280) >[137783.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137783.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137783.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[137783.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[137783.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[137783.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[137818.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137818.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137818.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137818.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137818.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2759860] >[137818.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2759860] width 1280 pitch 5120 (/4 1280) >[137818.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[137818.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[137819.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137819.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137819.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[137819.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[137819.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2754db0] >[137819.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2754db0] width 1280 pitch 5120 (/4 1280) >[137819.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137819.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137821.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[137821.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[137821.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137821.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137821.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2759860] >[137821.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2759860] width 1280 pitch 5120 (/4 1280) >[137821.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137821.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137822.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[137822.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[137822.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137822.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137822.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137822.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137822.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[137822.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[137846.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137846.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137846.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137846.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137846.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137846.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137846.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137846.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137846.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137846.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137846.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137846.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137846.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137846.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137847.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137847.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137862.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[137862.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[137862.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137862.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137862.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3210790] >[137862.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3210790] width 1280 pitch 5120 (/4 1280) >[137862.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137862.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137863.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137863.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137863.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137863.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137863.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137863.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137863.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[137863.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[137866.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[137866.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[137866.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3820] >[137866.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3820] width 1280 pitch 5120 (/4 1280) >[137866.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[137866.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[137866.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[137866.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[137867.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[137867.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[137867.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137867.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137867.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137867.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137867.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2754db0] >[137867.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2754db0] width 1280 pitch 5120 (/4 1280) >[137868.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137868.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137868.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137868.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137868.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727fd0] >[137868.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727fd0] width 1280 pitch 5120 (/4 1280) >[137871.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137871.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137871.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2763b80] >[137871.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2763b80] width 1280 pitch 5120 (/4 1280) >[137871.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137871.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137871.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[137871.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[137872.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[137872.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[137872.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137872.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137872.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137872.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137872.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[137872.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[137873.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[137873.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[137873.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727fd0] >[137873.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727fd0] width 1280 pitch 5120 (/4 1280) >[137873.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137873.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137873.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[137873.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[137895.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[137895.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[137895.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137895.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137895.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[137895.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[137895.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ab7f0] >[137895.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ab7f0] width 1280 pitch 5120 (/4 1280) >[137897.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[137897.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[137898.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[137898.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[137898.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2768b30] >[137898.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2768b30] width 1280 pitch 5120 (/4 1280) >[137898.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137898.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137898.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137898.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137898.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[137898.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[137899.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[137900.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[137900.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[137900.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[137900.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270b640] >[137900.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270b640] width 1280 pitch 5120 (/4 1280) >[137901.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[137901.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[137912.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288dd60] >[137912.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288dd60] width 1280 pitch 5120 (/4 1280) >[137912.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27236b0] >[137912.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27236b0] width 1280 pitch 5120 (/4 1280) >[137922.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2895570] >[137922.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2895570] width 1280 pitch 5120 (/4 1280) >[137922.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137923.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137923.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d310] >[137923.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d310] width 1280 pitch 5120 (/4 1280) >[137923.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288da80] >[137923.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288da80] width 1280 pitch 5120 (/4 1280) >[137923.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137923.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137923.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2891ab0] >[137923.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2891ab0] width 1280 pitch 5120 (/4 1280) >[137923.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2890ee0] >[137923.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2890ee0] width 1280 pitch 5120 (/4 1280) >[137923.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277fc20] >[137923.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277fc20] width 1280 pitch 5120 (/4 1280) >[137927.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[137927.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[137927.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137928.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137928.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137928.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137928.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137928.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137928.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137928.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137929.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ac9a0] >[137929.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ac9a0] width 1280 pitch 5120 (/4 1280) >[137930.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27acec0] >[137930.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27acec0] width 1280 pitch 5120 (/4 1280) >[137930.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27acec0] >[137930.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27acec0] width 1280 pitch 5120 (/4 1280) >[137930.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137930.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137931.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137931.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137932.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288dbd0] >[137932.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288dbd0] width 1280 pitch 5120 (/4 1280) >[137932.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e7480] >[137933.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e7480] width 1280 pitch 5120 (/4 1280) >[137933.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[137933.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[137933.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2729de0] >[137933.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2729de0] width 1280 pitch 5120 (/4 1280) >[137933.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[137933.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[137934.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27abda0] >[137934.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27abda0] width 1280 pitch 5120 (/4 1280) >[137935.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27abda0] >[137935.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27abda0] width 1280 pitch 5120 (/4 1280) >[137935.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ad530] >[137935.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ad530] width 1280 pitch 5120 (/4 1280) >[137935.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ad430] >[137935.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ad430] width 1280 pitch 5120 (/4 1280) >[137945.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2889f40] >[137945.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2889f40] width 1280 pitch 5120 (/4 1280) >[137945.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137945.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137947.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[137947.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[137948.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2899cb0] >[137948.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2899cb0] width 1280 pitch 5120 (/4 1280) >[137949.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[137949.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[137949.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[137949.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[137951.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[137951.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[137951.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[137951.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[137951.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288cdd0] >[137951.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288cdd0] width 1280 pitch 5120 (/4 1280) >[137952.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[137952.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[137952.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137952.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137952.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[137952.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[137952.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137952.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137955.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137955.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137955.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dab10] >[137955.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dab10] width 1280 pitch 5120 (/4 1280) >[137955.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[137955.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[137955.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2895570] >[137955.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2895570] width 1280 pitch 5120 (/4 1280) >[137961.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2891d10] >[137961.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2891d10] width 1280 pitch 5120 (/4 1280) >[137961.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137961.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137961.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[137961.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[137961.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[137961.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[137982.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[137982.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[137983.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[137983.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[137983.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[137983.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[137983.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137983.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137984.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[137984.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[137984.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[137984.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[137984.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727e50] >[137984.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727e50] width 1280 pitch 5120 (/4 1280) >[137984.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[137984.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[137986.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277f220] >[137986.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277f220] width 1280 pitch 5120 (/4 1280) >[137986.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727e50] >[137986.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727e50] width 1280 pitch 5120 (/4 1280) >[137986.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[137986.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[137986.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[137986.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138012.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[138012.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[138012.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138012.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138012.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727e50] >[138012.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727e50] width 1280 pitch 5120 (/4 1280) >[138012.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138012.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138013.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138013.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138013.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277f220] >[138013.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277f220] width 1280 pitch 5120 (/4 1280) >[138030.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765440] >[138030.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765440] width 1280 pitch 5120 (/4 1280) >[138030.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727e50] >[138030.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727e50] width 1280 pitch 5120 (/4 1280) >[138030.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[138030.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[138030.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[138030.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[138031.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138031.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138031.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[138031.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[138032.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138032.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138032.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138032.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138032.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138032.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138032.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138032.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138032.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138032.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138032.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138032.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138032.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138032.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138032.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138032.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138032.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138032.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138032.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138033.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138086.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138086.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138086.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[138086.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[138086.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138086.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138086.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138086.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138092.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138092.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138092.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727e50] >[138092.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727e50] width 1280 pitch 5120 (/4 1280) >[138093.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138093.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138093.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138093.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138120.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138120.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138120.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138120.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138120.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138120.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138120.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138120.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138129.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[138129.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[138129.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138129.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138129.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138129.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138129.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138129.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138131.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138131.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138131.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138131.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138131.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751a60] >[138131.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751a60] width 1280 pitch 5120 (/4 1280) >[138131.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138131.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138132.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138132.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138132.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[138132.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[138132.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138132.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138132.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138132.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138133.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138133.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138134.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[138134.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[138134.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138134.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138134.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[138134.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[138134.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138134.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138159.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[138159.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[138159.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138159.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138159.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138159.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138159.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2702760] >[138159.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2702760] width 1280 pitch 5120 (/4 1280) >[138165.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138165.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138165.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[138165.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[138165.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138165.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138165.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138165.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138190.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138190.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138190.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138190.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138194.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[138194.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[138194.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fe210] >[138194.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fe210] width 1280 pitch 5120 (/4 1280) >[138194.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[138194.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[138194.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fe210] >[138195.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fe210] width 1280 pitch 5120 (/4 1280) >[138218.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138218.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138218.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96d50] >[138218.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96d50] width 1280 pitch 5120 (/4 1280) >[138218.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[138218.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[138218.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138218.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138218.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138218.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138218.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[138219.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[138225.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff9f0] >[138225.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff9f0] width 1280 pitch 5120 (/4 1280) >[138225.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2754db0] >[138225.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2754db0] width 1280 pitch 5120 (/4 1280) >[138225.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138225.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138225.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138225.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138228.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138228.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138228.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138228.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138228.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[138228.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[138228.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[138228.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[138233.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2753d50] >[138233.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2753d50] width 1280 pitch 5120 (/4 1280) >[138233.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138233.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138233.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27feec0] >[138233.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27feec0] width 1280 pitch 5120 (/4 1280) >[138233.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138233.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138254.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138254.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138254.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fe210] >[138254.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fe210] width 1280 pitch 5120 (/4 1280) >[138254.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138254.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138254.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2754420] >[138254.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2754420] width 1280 pitch 5120 (/4 1280) >[138255.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc5a0] >[138255.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc5a0] width 1280 pitch 5120 (/4 1280) >[138255.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2727fd0] >[138255.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2727fd0] width 1280 pitch 5120 (/4 1280) >[138255.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea330] >[138255.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea330] width 1280 pitch 5120 (/4 1280) >[138255.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2755680] >[138255.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2755680] width 1280 pitch 5120 (/4 1280) >[138256.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138256.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138256.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fe210] >[138256.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fe210] width 1280 pitch 5120 (/4 1280) >[138257.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288af20] >[138257.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288af20] width 1280 pitch 5120 (/4 1280) >[138257.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138257.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138257.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276f5f0] >[138257.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276f5f0] width 1280 pitch 5120 (/4 1280) >[138257.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e43d0] >[138257.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e43d0] width 1280 pitch 5120 (/4 1280) >[138317.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23efb60] >[138317.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23efb60] width 1280 pitch 5120 (/4 1280) >[138317.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827df0] >[138317.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827df0] width 1280 pitch 5120 (/4 1280) >[138329.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138329.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138329.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138329.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138329.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138329.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138329.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138329.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138329.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138329.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138354.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2751360] >[138354.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2751360] width 1280 pitch 5120 (/4 1280) >[138354.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b96f50] >[138354.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b96f50] width 1280 pitch 5120 (/4 1280) >[138354.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5110] >[138354.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5110] width 1280 pitch 5120 (/4 1280) >[138354.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138355.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138368.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5110] >[138368.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5110] width 1280 pitch 5120 (/4 1280) >[138368.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138368.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138369.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5110] >[138369.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5110] width 1280 pitch 5120 (/4 1280) >[138369.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138369.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138378.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5110] >[138379.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5110] width 1280 pitch 5120 (/4 1280) >[138379.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5110] >[138379.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5110] width 1280 pitch 5120 (/4 1280) >[138379.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b38a0] >[138379.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b38a0] width 1280 pitch 5120 (/4 1280) >[138379.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138379.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138380.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b38a0] >[138380.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b38a0] width 1280 pitch 5120 (/4 1280) >[138380.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138380.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138380.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138380.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138382.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138382.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138385.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28260b0] >[138385.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28260b0] width 1280 pitch 5120 (/4 1280) >[138385.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138385.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138385.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28260b0] >[138385.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28260b0] width 1280 pitch 5120 (/4 1280) >[138385.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28260b0] >[138385.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28260b0] width 1280 pitch 5120 (/4 1280) >[138386.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138386.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138387.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28260b0] >[138387.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28260b0] width 1280 pitch 5120 (/4 1280) >[138387.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28260b0] >[138387.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28260b0] width 1280 pitch 5120 (/4 1280) >[138387.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a1400] >[138387.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a1400] width 1280 pitch 5120 (/4 1280) >[138518.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138518.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138519.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138519.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138519.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138519.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138519.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138519.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138520.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[138520.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[138520.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[138520.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[138520.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138520.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138520.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898a20] >[138520.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898a20] width 1280 pitch 5120 (/4 1280) >[138520.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138520.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138520.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138520.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138520.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138520.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138520.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[138520.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[138521.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138521.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138521.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138521.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138521.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138521.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138521.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288e470] >[138521.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288e470] width 1280 pitch 5120 (/4 1280) >[138531.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6400] >[138531.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6400] width 1280 pitch 5120 (/4 1280) >[138531.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a5ab0] >[138531.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a5ab0] width 1280 pitch 5120 (/4 1280) >[138538.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f8a50] >[138538.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f8a50] width 1280 pitch 5120 (/4 1280) >[138602.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d860] >[138602.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d860] width 1280 pitch 5120 (/4 1280) >[138602.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d860] >[138602.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d860] width 1280 pitch 5120 (/4 1280) >[138602.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138602.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138602.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138602.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138602.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138603.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138603.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138603.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138603.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138603.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138603.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2768b30] >[138603.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2768b30] width 1280 pitch 5120 (/4 1280) >[138628.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288ccc0] >[138628.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288ccc0] width 1280 pitch 5120 (/4 1280) >[138628.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288ccc0] >[138628.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288ccc0] width 1280 pitch 5120 (/4 1280) >[138628.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138628.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138629.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138629.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138639.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138639.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138639.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138640.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138640.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[138640.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[138640.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138640.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138644.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138644.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138644.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138644.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138644.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138644.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138644.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138644.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138645.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138645.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138645.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138645.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138645.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138646.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138646.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[138646.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[138646.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[138646.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[138646.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138647.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138647.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[138647.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[138647.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138647.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138652.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138652.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138652.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138652.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138652.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138652.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138652.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[138652.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[138706.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[138706.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[138706.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138706.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138706.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138706.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138706.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138706.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138730.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288e710] >[138730.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288e710] width 1280 pitch 5120 (/4 1280) >[138730.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138730.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138730.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138730.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138730.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138730.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138730.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138730.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138730.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2729de0] >[138730.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2729de0] width 1280 pitch 5120 (/4 1280) >[138731.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138731.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138731.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2729de0] >[138731.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2729de0] width 1280 pitch 5120 (/4 1280) >[138731.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138731.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138731.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138731.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138731.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138731.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138731.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138731.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138731.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138731.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138731.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138731.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138731.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138731.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138731.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288e710] >[138731.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288e710] width 1280 pitch 5120 (/4 1280) >[138731.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138731.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138731.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288e710] >[138731.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288e710] width 1280 pitch 5120 (/4 1280) >[138731.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138731.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138731.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[138731.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[138731.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[138731.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[138731.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[138731.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[138731.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[138731.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[138731.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[138731.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[138731.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[138731.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[138731.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138731.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138731.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138731.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138731.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138731.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138731.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138731.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138732.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138732.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138732.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138732.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138732.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3214320] >[138732.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3214320] width 1280 pitch 5120 (/4 1280) >[138732.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138732.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138732.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288e710] >[138732.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288e710] width 1280 pitch 5120 (/4 1280) >[138733.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea190] >[138733.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea190] width 1280 pitch 5120 (/4 1280) >[138733.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138733.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138733.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138733.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138733.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288ccc0] >[138733.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288ccc0] width 1280 pitch 5120 (/4 1280) >[138736.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138736.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138736.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138736.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138736.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[138736.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[138736.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138736.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138750.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138750.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138752.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[138752.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[138819.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[138819.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[138819.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[138819.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[138819.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[138819.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[138819.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138819.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138821.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc8f0] >[138821.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc8f0] width 1280 pitch 5120 (/4 1280) >[138821.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc8f0] >[138821.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc8f0] width 1280 pitch 5120 (/4 1280) >[138821.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138821.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138821.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[138821.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[138821.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[138821.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[138821.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[138821.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[138822.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[138822.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[138822.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138822.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138822.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272fce0] >[138822.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272fce0] width 1280 pitch 5120 (/4 1280) >[138822.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138822.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138823.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[138823.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[138823.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[138823.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[138823.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138823.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138823.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138823.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138826.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[138826.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[138826.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[138826.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[138826.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[138826.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[138826.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31bfd80] >[138826.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31bfd80] width 1280 pitch 5120 (/4 1280) >[138826.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138826.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138826.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138826.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138826.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138826.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138827.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138827.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138828.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[138828.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[138828.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138828.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138828.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[138828.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[138828.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[138828.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[138878.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[138878.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[138878.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[138878.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[138878.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[138878.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[138878.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138878.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138878.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[138878.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[138878.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138878.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138878.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138878.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138878.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138878.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138889.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138889.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138890.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[138890.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[138893.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138893.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138893.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138893.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138893.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138893.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138895.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138895.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138895.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138895.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138895.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138895.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138895.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138895.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138895.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138895.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138896.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[138896.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[138897.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b2110] >[138897.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b2110] width 1280 pitch 5120 (/4 1280) >[138898.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[138898.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[138898.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[138898.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[138898.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320dfb0] >[138898.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320dfb0] width 1280 pitch 5120 (/4 1280) >[138900.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ea40] >[138900.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ea40] width 1280 pitch 5120 (/4 1280) >[138900.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138900.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138900.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[138900.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[138900.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[138900.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[138924.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2652ce0] >[138924.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2652ce0] width 1280 pitch 5120 (/4 1280) >[138924.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2652ce0] >[138924.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2652ce0] width 1280 pitch 5120 (/4 1280) >[138924.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[138924.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[138924.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[138924.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[138946.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[138946.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[138946.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[138946.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[138946.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[138946.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[138946.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138946.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138947.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[138947.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[138947.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[138947.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[138947.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[138947.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[138947.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138947.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138982.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288cdb0] >[138982.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288cdb0] width 1280 pitch 5120 (/4 1280) >[138982.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2084ae0] >[138982.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2084ae0] width 1280 pitch 5120 (/4 1280) >[138983.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd910] >[138983.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd910] width 1280 pitch 5120 (/4 1280) >[138983.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd910] >[138983.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd910] width 1280 pitch 5120 (/4 1280) >[138983.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288d0f0] >[138983.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288d0f0] width 1280 pitch 5120 (/4 1280) >[138983.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[138983.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[138984.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2729de0] >[138984.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2729de0] width 1280 pitch 5120 (/4 1280) >[138984.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2084ae0] >[138984.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2084ae0] width 1280 pitch 5120 (/4 1280) >[138984.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[138984.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[138984.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2084ae0] >[138984.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2084ae0] width 1280 pitch 5120 (/4 1280) >[139030.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2084ae0] >[139030.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2084ae0] width 1280 pitch 5120 (/4 1280) >[139030.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[139030.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[139030.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139030.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139030.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a090c0] >[139030.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a090c0] width 1280 pitch 5120 (/4 1280) >[139056.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139056.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139056.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2084ae0] >[139056.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2084ae0] width 1280 pitch 5120 (/4 1280) >[139056.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139056.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139056.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139056.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139058.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[139058.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[139058.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139058.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139058.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139058.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139058.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[139058.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[139059.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139059.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139059.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[139059.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[139059.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139059.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139059.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139059.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139120.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8ffa0] >[139120.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8ffa0] width 1280 pitch 5120 (/4 1280) >[139122.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139122.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139123.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[139123.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[139123.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139123.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139123.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[139123.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[139242.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[139242.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[139242.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[139242.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[139242.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139242.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139242.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[139242.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[139287.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289af10] >[139287.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289af10] width 1280 pitch 5120 (/4 1280) >[139287.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139287.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139287.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f7a0] >[139287.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f7a0] width 1280 pitch 5120 (/4 1280) >[139287.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139287.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139288.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[139288.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[139288.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[139288.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[139288.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139288.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139288.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5b70] >[139288.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5b70] width 1280 pitch 5120 (/4 1280) >[139365.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f2b50] >[139365.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f2b50] width 1280 pitch 5120 (/4 1280) >[139365.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ca0b0] >[139365.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ca0b0] width 1280 pitch 5120 (/4 1280) >[139365.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[139365.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[139365.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139365.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139365.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139365.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139365.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139365.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139365.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f2bd0] >[139365.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f2bd0] width 1280 pitch 5120 (/4 1280) >[139365.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139365.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139413.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139413.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139413.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[139413.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[139413.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139413.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139413.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139413.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139415.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27695a0] >[139415.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27695a0] width 1280 pitch 5120 (/4 1280) >[139415.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139415.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139415.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139415.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139418.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[139419.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[139419.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139419.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139419.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139419.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139419.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[139419.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[139421.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139421.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139421.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139421.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139421.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219380] >[139421.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219380] width 1280 pitch 5120 (/4 1280) >[139421.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1471bd0] >[139421.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1471bd0] width 1280 pitch 5120 (/4 1280) >[139422.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139422.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139422.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139422.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139424.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139424.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139424.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139424.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139424.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139424.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139425.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e38d50] >[139425.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e38d50] width 1280 pitch 5120 (/4 1280) >[139426.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2729510] >[139426.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2729510] width 1280 pitch 5120 (/4 1280) >[139427.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139427.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139431.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[139432.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[139433.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139433.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139433.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2766f10] >[139433.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2766f10] width 1280 pitch 5120 (/4 1280) >[139433.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139433.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139433.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139433.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139456.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139456.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139456.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139456.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139456.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8ffa0] >[139456.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8ffa0] width 1280 pitch 5120 (/4 1280) >[139456.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[139456.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[139458.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139458.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139458.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27695a0] >[139458.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27695a0] width 1280 pitch 5120 (/4 1280) >[139458.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[139458.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[139458.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139458.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139476.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139476.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139476.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139476.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139476.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27695a0] >[139476.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27695a0] width 1280 pitch 5120 (/4 1280) >[139476.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1471bd0] >[139476.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1471bd0] width 1280 pitch 5120 (/4 1280) >[139482.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139482.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139482.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[139482.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[139482.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2888cb0] >[139482.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2888cb0] width 1280 pitch 5120 (/4 1280) >[139482.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139482.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139489.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219380] >[139489.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219380] width 1280 pitch 5120 (/4 1280) >[139489.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274ee10] >[139489.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274ee10] width 1280 pitch 5120 (/4 1280) >[139489.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139489.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139489.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139489.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139490.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139490.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139490.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8ffa0] >[139490.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8ffa0] width 1280 pitch 5120 (/4 1280) >[139490.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc26d0] >[139490.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc26d0] width 1280 pitch 5120 (/4 1280) >[139490.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139490.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139496.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[139496.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[139496.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ca0b0] >[139496.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ca0b0] width 1280 pitch 5120 (/4 1280) >[139496.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1471bd0] >[139496.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1471bd0] width 1280 pitch 5120 (/4 1280) >[139496.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139496.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139497.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139497.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139497.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276ac10] >[139497.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276ac10] width 1280 pitch 5120 (/4 1280) >[139497.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[139497.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[139497.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ca0b0] >[139497.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ca0b0] width 1280 pitch 5120 (/4 1280) >[139508.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139508.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139508.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139508.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139508.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[139508.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[139508.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[139508.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[139511.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c260] >[139511.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c260] width 1280 pitch 5120 (/4 1280) >[139511.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139511.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139511.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[139511.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[139511.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139511.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139543.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[139543.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[139543.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[139543.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[139543.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139543.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139543.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139543.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139547.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139547.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139547.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139547.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139547.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139547.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139547.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1dc0] >[139547.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1dc0] width 1280 pitch 5120 (/4 1280) >[139549.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139549.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139550.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139550.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139550.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139550.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139550.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139550.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139550.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bbad0] >[139550.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bbad0] width 1280 pitch 5120 (/4 1280) >[139550.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276b830] >[139550.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276b830] width 1280 pitch 5120 (/4 1280) >[139550.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139550.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139550.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274ee10] >[139550.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274ee10] width 1280 pitch 5120 (/4 1280) >[139551.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139551.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139552.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139552.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139554.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1129860] >[139554.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1129860] width 1280 pitch 5120 (/4 1280) >[139554.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139554.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139555.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139555.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139556.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbb30] >[139556.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbb30] width 1280 pitch 5120 (/4 1280) >[139558.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139558.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139558.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274de60] >[139558.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274de60] width 1280 pitch 5120 (/4 1280) >[139558.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23759b0] >[139558.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23759b0] width 1280 pitch 5120 (/4 1280) >[139564.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139564.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139564.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[139564.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[139583.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cba60] >[139583.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cba60] width 1280 pitch 5120 (/4 1280) >[139590.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139590.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139590.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139590.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139590.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139590.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139590.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139590.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139590.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139590.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139598.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139598.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139598.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139598.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139598.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139598.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139598.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139598.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139608.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc26d0] >[139608.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc26d0] width 1280 pitch 5120 (/4 1280) >[139608.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274ee10] >[139608.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274ee10] width 1280 pitch 5120 (/4 1280) >[139608.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27695a0] >[139608.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27695a0] width 1280 pitch 5120 (/4 1280) >[139608.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139608.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139609.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139609.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139610.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139610.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139610.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27695a0] >[139610.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27695a0] width 1280 pitch 5120 (/4 1280) >[139610.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139610.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139612.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139612.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139613.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139613.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139613.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139613.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139613.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139613.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139613.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc26d0] >[139613.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc26d0] width 1280 pitch 5120 (/4 1280) >[139613.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[139613.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[139616.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139616.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139616.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139616.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139616.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139616.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139616.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139616.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139616.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139617.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139617.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139617.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139617.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139617.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139617.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e45ff0] >[139617.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e45ff0] width 1280 pitch 5120 (/4 1280) >[139617.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139617.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139618.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139618.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139618.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[139618.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[139618.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[139618.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[139618.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139618.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139618.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139618.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139618.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288c9c0] >[139618.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288c9c0] width 1280 pitch 5120 (/4 1280) >[139618.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[139618.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[139619.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139619.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139619.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139619.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139619.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139619.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139619.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139619.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139638.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139638.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139638.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139638.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139638.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139638.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139638.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[139638.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[139639.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2889940] >[139639.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2889940] width 1280 pitch 5120 (/4 1280) >[139640.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139640.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139640.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc26d0] >[139640.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc26d0] width 1280 pitch 5120 (/4 1280) >[139640.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139640.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139649.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139649.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139649.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139649.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139649.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139649.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139649.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31c7df0] >[139649.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31c7df0] width 1280 pitch 5120 (/4 1280) >[139650.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832880] >[139650.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832880] width 1280 pitch 5120 (/4 1280) >[139650.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139650.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139650.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139650.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139650.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139650.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139652.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139652.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139652.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139652.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139672.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1949840] >[139672.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1949840] width 1280 pitch 5120 (/4 1280) >[139698.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139698.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139698.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1949840] >[139698.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1949840] width 1280 pitch 5120 (/4 1280) >[139698.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc990] >[139698.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc990] width 1280 pitch 5120 (/4 1280) >[139698.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e45ff0] >[139698.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e45ff0] width 1280 pitch 5120 (/4 1280) >[139709.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139709.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139709.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320fe30] >[139709.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320fe30] width 1280 pitch 5120 (/4 1280) >[139709.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23efef0] >[139709.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23efef0] width 1280 pitch 5120 (/4 1280) >[139709.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139709.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139710.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139710.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139710.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27afc30] >[139710.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27afc30] width 1280 pitch 5120 (/4 1280) >[139710.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139710.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139710.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139710.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139710.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139710.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139710.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139710.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139738.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139738.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139738.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[139738.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[139738.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6d80] >[139738.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6d80] width 1280 pitch 5120 (/4 1280) >[139739.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fd1c0] >[139739.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fd1c0] width 1280 pitch 5120 (/4 1280) >[139739.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139739.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139739.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6d80] >[139739.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6d80] width 1280 pitch 5120 (/4 1280) >[139739.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139739.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139739.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6d80] >[139739.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6d80] width 1280 pitch 5120 (/4 1280) >[139740.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139740.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139742.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc420] >[139742.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc420] width 1280 pitch 5120 (/4 1280) >[139743.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ff4a0] >[139743.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ff4a0] width 1280 pitch 5120 (/4 1280) >[139745.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ff320] >[139745.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ff320] width 1280 pitch 5120 (/4 1280) >[139745.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139745.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139757.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32147b0] >[139757.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32147b0] width 1280 pitch 5120 (/4 1280) >[139788.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139788.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139822.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139822.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139822.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139822.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139822.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139822.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139822.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c7d0] >[139822.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c7d0] width 1280 pitch 5120 (/4 1280) >[139822.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139822.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139822.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[139822.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[139822.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139822.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139822.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139822.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139869.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3177cb0] >[139869.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3177cb0] width 1280 pitch 5120 (/4 1280) >[139869.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139869.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139883.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139883.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139883.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[139883.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[139884.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[139884.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[139884.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139884.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139884.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139884.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139884.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139884.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139898.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d4460] >[139898.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d4460] width 1280 pitch 5120 (/4 1280) >[139898.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139898.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139898.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139898.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139898.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[139898.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[139899.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[139899.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[139899.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139899.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139899.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c120] >[139899.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c120] width 1280 pitch 5120 (/4 1280) >[139900.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139900.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139954.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139954.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139954.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139955.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139955.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[139955.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[139955.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[139955.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[139955.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[139955.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[139955.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139955.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139955.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[139955.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[139956.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[139956.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[139975.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289ad60] >[139976.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289ad60] width 1280 pitch 5120 (/4 1280) >[139979.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[139979.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[139979.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fc6a0] >[139979.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fc6a0] width 1280 pitch 5120 (/4 1280) >[139979.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102730] >[139979.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102730] width 1280 pitch 5120 (/4 1280) >[139979.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[139979.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[139981.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139981.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fb1a0] >[139981.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fb1a0] width 1280 pitch 5120 (/4 1280) >[139981.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[139981.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[139999.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[139999.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140000.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[140000.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[140001.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[140001.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140001.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[140001.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[140002.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[140002.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[140003.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[140003.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140004.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[140004.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140004.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b4790] >[140004.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b4790] width 1280 pitch 5120 (/4 1280) >[140004.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dae8a0] >[140004.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dae8a0] width 1280 pitch 5120 (/4 1280) >[140029.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[140029.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[140029.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194ed90] >[140029.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194ed90] width 1280 pitch 5120 (/4 1280) >[140046.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[140046.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[140046.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[140046.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140046.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[140046.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[140046.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e1630] >[140046.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e1630] width 1280 pitch 5120 (/4 1280) >[140046.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[140046.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[140071.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aed10] >[140071.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aed10] width 1280 pitch 5120 (/4 1280) >[140072.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[140072.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[140073.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[140073.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[140073.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276f590] >[140073.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276f590] width 1280 pitch 5120 (/4 1280) >[140075.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2760cc0] >[140075.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2760cc0] width 1280 pitch 5120 (/4 1280) >[140076.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28986a0] >[140076.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28986a0] width 1280 pitch 5120 (/4 1280) >[140077.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c120] >[140077.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c120] width 1280 pitch 5120 (/4 1280) >[140077.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276f590] >[140077.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276f590] width 1280 pitch 5120 (/4 1280) >[140077.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c120] >[140077.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c120] width 1280 pitch 5120 (/4 1280) >[140131.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[140131.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[140131.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[140131.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[140131.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27282a0] >[140131.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27282a0] width 1280 pitch 5120 (/4 1280) >[140131.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[140131.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[140146.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834930] >[140146.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834930] width 1280 pitch 5120 (/4 1280) >[140146.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc420] >[140146.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc420] width 1280 pitch 5120 (/4 1280) >[140146.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275ede0] >[140146.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275ede0] width 1280 pitch 5120 (/4 1280) >[140146.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bc420] >[140146.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bc420] width 1280 pitch 5120 (/4 1280) >[140148.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a0e00] >[140148.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a0e00] width 1280 pitch 5120 (/4 1280) >[140148.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[140148.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[140148.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2358960] >[140148.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2358960] width 1280 pitch 5120 (/4 1280) >[140149.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723270] >[140149.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723270] width 1280 pitch 5120 (/4 1280) >[140149.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275d640] >[140149.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275d640] width 1280 pitch 5120 (/4 1280) >[140149.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765950] >[140149.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765950] width 1280 pitch 5120 (/4 1280) >[140171.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2504cd0] >[140171.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2504cd0] width 1280 pitch 5120 (/4 1280) >[140171.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275c8b0] >[140171.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275c8b0] width 1280 pitch 5120 (/4 1280) >[140193.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ba210] >[140193.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ba210] width 1280 pitch 5120 (/4 1280) >[140193.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12fd0] >[140193.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12fd0] width 1280 pitch 5120 (/4 1280) >[140193.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ea5c0] >[140193.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ea5c0] width 1280 pitch 5120 (/4 1280) >[140193.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12fd0] >[140193.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12fd0] width 1280 pitch 5120 (/4 1280) >[140203.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12fd0] >[140203.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12fd0] width 1280 pitch 5120 (/4 1280) >[140204.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273bca0] >[140204.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273bca0] width 1280 pitch 5120 (/4 1280) >[140204.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ba210] >[140204.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ba210] width 1280 pitch 5120 (/4 1280) >[140204.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223aaa0] >[140204.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223aaa0] width 1280 pitch 5120 (/4 1280) >[140204.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223aaa0] >[140204.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223aaa0] width 1280 pitch 5120 (/4 1280) >[140204.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x223aaa0] >[140204.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x223aaa0] width 1280 pitch 5120 (/4 1280) >[140204.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[140204.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[140204.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b4b30] >[140204.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b4b30] width 1280 pitch 5120 (/4 1280) >[140218.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[140218.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[140218.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12fd0] >[140218.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12fd0] width 1280 pitch 5120 (/4 1280) >[140218.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6010] >[140218.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6010] width 1280 pitch 5120 (/4 1280) >[140218.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12fd0] >[140218.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12fd0] width 1280 pitch 5120 (/4 1280) >[140219.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[140219.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[140220.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194e240] >[140220.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194e240] width 1280 pitch 5120 (/4 1280) >[140220.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194e240] >[140220.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194e240] width 1280 pitch 5120 (/4 1280) >[140220.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa7280] >[140220.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa7280] width 1280 pitch 5120 (/4 1280) >[140220.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6010] >[140220.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6010] width 1280 pitch 5120 (/4 1280) >[140220.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1948c60] >[140220.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1948c60] width 1280 pitch 5120 (/4 1280) >[140253.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[140253.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[140253.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b32c40] >[140253.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b32c40] width 1280 pitch 5120 (/4 1280) >[140282.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ea7d0] >[140282.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ea7d0] width 1280 pitch 5120 (/4 1280) >[140282.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ea7d0] >[140282.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ea7d0] width 1280 pitch 5120 (/4 1280) >[140282.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140282.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140282.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ea7d0] >[140282.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ea7d0] width 1280 pitch 5120 (/4 1280) >[140302.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140302.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140302.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140302.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140302.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ea9a0] >[140302.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ea9a0] width 1280 pitch 5120 (/4 1280) >[140302.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140302.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140320.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140320.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140320.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140320.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140320.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140320.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140320.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140320.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140320.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271f640] >[140320.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271f640] width 1280 pitch 5120 (/4 1280) >[140321.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140321.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140321.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140321.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140321.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140321.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140326.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140326.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140326.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140326.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140326.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140327.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140327.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140327.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140328.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140328.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140328.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140328.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140328.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140328.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140328.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140328.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140329.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140329.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140329.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726f50] >[140329.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726f50] width 1280 pitch 5120 (/4 1280) >[140329.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140329.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140329.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140329.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140329.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140329.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140329.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a7670] >[140329.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a7670] width 1280 pitch 5120 (/4 1280) >[140329.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726f50] >[140329.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726f50] width 1280 pitch 5120 (/4 1280) >[140329.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140329.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140371.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140371.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140371.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140371.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140371.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288b990] >[140371.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288b990] width 1280 pitch 5120 (/4 1280) >[140371.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288b990] >[140371.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288b990] width 1280 pitch 5120 (/4 1280) >[140372.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140372.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140372.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140372.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140372.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51480] >[140372.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51480] width 1280 pitch 5120 (/4 1280) >[140372.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140372.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140379.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aea10] >[140379.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aea10] width 1280 pitch 5120 (/4 1280) >[140379.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140379.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140385.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140385.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140385.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194be00] >[140385.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194be00] width 1280 pitch 5120 (/4 1280) >[140385.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aea10] >[140385.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aea10] width 1280 pitch 5120 (/4 1280) >[140385.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f9b30] >[140385.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f9b30] width 1280 pitch 5120 (/4 1280) >[140385.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140385.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140385.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140385.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140385.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140385.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140386.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f9b30] >[140386.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f9b30] width 1280 pitch 5120 (/4 1280) >[140386.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140386.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140386.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aea10] >[140386.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aea10] width 1280 pitch 5120 (/4 1280) >[140386.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aea10] >[140386.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aea10] width 1280 pitch 5120 (/4 1280) >[140386.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f9b30] >[140386.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f9b30] width 1280 pitch 5120 (/4 1280) >[140398.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28aea10] >[140398.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28aea10] width 1280 pitch 5120 (/4 1280) >[140404.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c180] >[140404.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c180] width 1280 pitch 5120 (/4 1280) >[140404.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ede0] >[140404.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ede0] width 1280 pitch 5120 (/4 1280) >[140404.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28894e0] >[140404.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28894e0] width 1280 pitch 5120 (/4 1280) >[140404.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f80] >[140404.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f80] width 1280 pitch 5120 (/4 1280) >[140404.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faaf0] >[140404.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faaf0] width 1280 pitch 5120 (/4 1280) >[140405.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faaf0] >[140405.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faaf0] width 1280 pitch 5120 (/4 1280) >[140405.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140405.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140405.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c610] >[140405.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c610] width 1280 pitch 5120 (/4 1280) >[140406.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140406.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140406.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c180] >[140406.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c180] width 1280 pitch 5120 (/4 1280) >[140406.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140406.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140406.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140407.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140407.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c180] >[140407.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c180] width 1280 pitch 5120 (/4 1280) >[140407.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288b990] >[140407.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288b990] width 1280 pitch 5120 (/4 1280) >[140407.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288b990] >[140407.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288b990] width 1280 pitch 5120 (/4 1280) >[140407.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837da0] >[140407.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837da0] width 1280 pitch 5120 (/4 1280) >[140457.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c180] >[140458.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c180] width 1280 pitch 5120 (/4 1280) >[140458.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140458.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140458.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cd10] >[140458.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cd10] width 1280 pitch 5120 (/4 1280) >[140458.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140458.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140458.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140458.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140458.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140458.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140458.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140459.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140459.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140459.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140476.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140476.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140478.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140478.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140479.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140479.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140479.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b6d80] >[140479.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b6d80] width 1280 pitch 5120 (/4 1280) >[140479.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140479.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140495.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140495.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140495.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b6d80] >[140495.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b6d80] width 1280 pitch 5120 (/4 1280) >[140495.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140495.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140495.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140495.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140496.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140496.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140496.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140496.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140496.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140496.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140496.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140496.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140506.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e4c940] >[140506.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e4c940] width 1280 pitch 5120 (/4 1280) >[140506.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140506.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140507.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140507.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140507.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140507.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140507.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140507.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140507.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839330] >[140507.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839330] width 1280 pitch 5120 (/4 1280) >[140526.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e990] >[140526.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e990] width 1280 pitch 5120 (/4 1280) >[140526.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140526.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140531.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963670] >[140531.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963670] width 1280 pitch 5120 (/4 1280) >[140531.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140531.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140531.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963670] >[140531.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963670] width 1280 pitch 5120 (/4 1280) >[140531.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140531.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140531.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726690] >[140531.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726690] width 1280 pitch 5120 (/4 1280) >[140535.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140535.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140535.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281de90] >[140535.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281de90] width 1280 pitch 5120 (/4 1280) >[140536.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140536.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140536.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140536.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140537.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140537.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140537.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726690] >[140537.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726690] width 1280 pitch 5120 (/4 1280) >[140537.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e990] >[140537.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e990] width 1280 pitch 5120 (/4 1280) >[140537.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140537.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140537.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140537.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140537.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140537.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140538.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140538.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140538.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140538.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140538.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140538.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140538.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281de90] >[140538.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281de90] width 1280 pitch 5120 (/4 1280) >[140546.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140546.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140547.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140547.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140547.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140547.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140547.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2725c70] >[140547.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2725c70] width 1280 pitch 5120 (/4 1280) >[140547.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140547.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140547.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140547.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140547.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140547.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140547.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140547.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140548.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f170] >[140548.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f170] width 1280 pitch 5120 (/4 1280) >[140548.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140548.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140549.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e990] >[140549.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e990] width 1280 pitch 5120 (/4 1280) >[140549.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e990] >[140549.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e990] width 1280 pitch 5120 (/4 1280) >[140549.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140549.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140550.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d510] >[140550.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d510] width 1280 pitch 5120 (/4 1280) >[140550.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140550.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140550.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140550.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140550.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140550.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140551.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140551.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140551.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d510] >[140551.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d510] width 1280 pitch 5120 (/4 1280) >[140551.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140551.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140551.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140551.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140565.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140565.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140565.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140565.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140565.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140565.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140565.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140566.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140566.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140566.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140566.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140566.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140566.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140566.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140566.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ceac10] >[140566.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ceac10] width 1280 pitch 5120 (/4 1280) >[140566.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140566.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140605.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140605.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140605.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ca80] >[140605.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ca80] width 1280 pitch 5120 (/4 1280) >[140605.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273cb20] >[140605.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273cb20] width 1280 pitch 5120 (/4 1280) >[140605.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140605.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140606.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140606.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140606.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140606.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140606.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140606.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140606.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140606.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140652.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140652.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140652.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140652.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140652.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14bd9f0] >[140652.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14bd9f0] width 1280 pitch 5120 (/4 1280) >[140652.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31013c0] >[140652.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31013c0] width 1280 pitch 5120 (/4 1280) >[140653.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140653.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140653.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140653.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140653.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b5630] >[140653.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b5630] width 1280 pitch 5120 (/4 1280) >[140653.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b5040] >[140653.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b5040] width 1280 pitch 5120 (/4 1280) >[140707.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140707.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140707.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bc3a0] >[140707.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bc3a0] width 1280 pitch 5120 (/4 1280) >[140707.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bc5f0] >[140707.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bc5f0] width 1280 pitch 5120 (/4 1280) >[140707.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f0900] >[140707.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f0900] width 1280 pitch 5120 (/4 1280) >[140707.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bc3a0] >[140707.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bc3a0] width 1280 pitch 5120 (/4 1280) >[140708.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140708.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140708.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140708.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140708.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289e850] >[140708.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289e850] width 1280 pitch 5120 (/4 1280) >[140709.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289e850] >[140709.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289e850] width 1280 pitch 5120 (/4 1280) >[140709.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[140709.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[140709.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c210] >[140709.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c210] width 1280 pitch 5120 (/4 1280) >[140709.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[140709.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[140710.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195c210] >[140710.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195c210] width 1280 pitch 5120 (/4 1280) >[140710.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a51210] >[140710.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a51210] width 1280 pitch 5120 (/4 1280) >[140710.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965930] >[140710.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965930] width 1280 pitch 5120 (/4 1280) >[140710.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faa00] >[140710.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faa00] width 1280 pitch 5120 (/4 1280) >[140713.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965930] >[140713.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965930] width 1280 pitch 5120 (/4 1280) >[140713.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194c9f0] >[140713.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194c9f0] width 1280 pitch 5120 (/4 1280) >[140713.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194c9f0] >[140713.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194c9f0] width 1280 pitch 5120 (/4 1280) >[140713.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273bca0] >[140713.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273bca0] width 1280 pitch 5120 (/4 1280) >[140713.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140713.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140713.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faa00] >[140713.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faa00] width 1280 pitch 5120 (/4 1280) >[140713.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140713.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140713.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1e7b0] >[140713.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1e7b0] width 1280 pitch 5120 (/4 1280) >[140716.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f2550] >[140716.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f2550] width 1280 pitch 5120 (/4 1280) >[140716.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289e470] >[140716.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289e470] width 1280 pitch 5120 (/4 1280) >[140716.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140716.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140716.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1e840] >[140716.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1e840] width 1280 pitch 5120 (/4 1280) >[140717.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140717.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140717.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140717.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140717.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3082820] >[140717.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3082820] width 1280 pitch 5120 (/4 1280) >[140717.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faa00] >[140717.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faa00] width 1280 pitch 5120 (/4 1280) >[140731.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bc5f0] >[140731.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bc5f0] width 1280 pitch 5120 (/4 1280) >[140731.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d340] >[140731.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d340] width 1280 pitch 5120 (/4 1280) >[140731.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d340] >[140731.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d340] width 1280 pitch 5120 (/4 1280) >[140731.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f24f0] >[140731.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f24f0] width 1280 pitch 5120 (/4 1280) >[140731.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d340] >[140731.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d340] width 1280 pitch 5120 (/4 1280) >[140731.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d340] >[140731.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d340] width 1280 pitch 5120 (/4 1280) >[140731.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140731.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140731.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3082820] >[140731.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3082820] width 1280 pitch 5120 (/4 1280) >[140732.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bc5f0] >[140732.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bc5f0] width 1280 pitch 5120 (/4 1280) >[140732.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a3630] >[140732.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a3630] width 1280 pitch 5120 (/4 1280) >[140732.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140732.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140732.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[140732.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[140732.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140732.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140732.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30faa00] >[140732.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30faa00] width 1280 pitch 5120 (/4 1280) >[140732.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140732.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140732.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140732.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140733.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140733.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140733.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964ee0] >[140733.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964ee0] width 1280 pitch 5120 (/4 1280) >[140733.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a3630] >[140733.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a3630] width 1280 pitch 5120 (/4 1280) >[140733.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964ee0] >[140733.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964ee0] width 1280 pitch 5120 (/4 1280) >[140734.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bd3a0] >[140734.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bd3a0] width 1280 pitch 5120 (/4 1280) >[140734.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140734.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140734.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d420] >[140734.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d420] width 1280 pitch 5120 (/4 1280) >[140734.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140734.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140735.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283d420] >[140735.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283d420] width 1280 pitch 5120 (/4 1280) >[140735.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140735.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140735.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140735.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140735.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823db0] >[140735.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823db0] width 1280 pitch 5120 (/4 1280) >[140735.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823db0] >[140735.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823db0] width 1280 pitch 5120 (/4 1280) >[140736.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965750] >[140736.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965750] width 1280 pitch 5120 (/4 1280) >[140736.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194c750] >[140736.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194c750] width 1280 pitch 5120 (/4 1280) >[140736.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140736.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140749.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140749.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140749.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194c750] >[140749.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194c750] width 1280 pitch 5120 (/4 1280) >[140750.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140750.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140750.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140750.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140750.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140750.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140750.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140750.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140800.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a8f0] >[140800.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a8f0] width 1280 pitch 5120 (/4 1280) >[140800.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e990] >[140800.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e990] width 1280 pitch 5120 (/4 1280) >[140809.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819470] >[140809.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819470] width 1280 pitch 5120 (/4 1280) >[140809.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[140809.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[140809.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965930] >[140809.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965930] width 1280 pitch 5120 (/4 1280) >[140809.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27261b0] >[140809.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27261b0] width 1280 pitch 5120 (/4 1280) >[140809.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2722510] >[140809.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2722510] width 1280 pitch 5120 (/4 1280) >[140849.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27261b0] >[140849.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27261b0] width 1280 pitch 5120 (/4 1280) >[140849.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819330] >[140849.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819330] width 1280 pitch 5120 (/4 1280) >[140849.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28973d0] >[140849.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28973d0] width 1280 pitch 5120 (/4 1280) >[140849.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819330] >[140849.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819330] width 1280 pitch 5120 (/4 1280) >[140849.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28973d0] >[140849.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28973d0] width 1280 pitch 5120 (/4 1280) >[140850.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819330] >[140850.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819330] width 1280 pitch 5120 (/4 1280) >[140850.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27261b0] >[140850.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27261b0] width 1280 pitch 5120 (/4 1280) >[140850.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281b180] >[140850.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281b180] width 1280 pitch 5120 (/4 1280) >[140857.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1962bf0] >[140857.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1962bf0] width 1280 pitch 5120 (/4 1280) >[140857.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819330] >[140857.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819330] width 1280 pitch 5120 (/4 1280) >[140864.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140864.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140864.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1962bf0] >[140864.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1962bf0] width 1280 pitch 5120 (/4 1280) >[140864.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c920] >[140865.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c920] width 1280 pitch 5120 (/4 1280) >[140865.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[140865.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[140865.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28973d0] >[140865.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28973d0] width 1280 pitch 5120 (/4 1280) >[140865.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c920] >[140865.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c920] width 1280 pitch 5120 (/4 1280) >[140865.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28973d0] >[140865.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28973d0] width 1280 pitch 5120 (/4 1280) >[140865.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c920] >[140865.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c920] width 1280 pitch 5120 (/4 1280) >[140889.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1962bf0] >[140889.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1962bf0] width 1280 pitch 5120 (/4 1280) >[140889.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[140889.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[140889.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289e500] >[140889.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289e500] width 1280 pitch 5120 (/4 1280) >[140889.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[140889.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[140890.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964300] >[140890.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964300] width 1280 pitch 5120 (/4 1280) >[140890.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140890.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140890.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140890.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140890.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1962bf0] >[140890.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1962bf0] width 1280 pitch 5120 (/4 1280) >[140891.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140891.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140891.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140891.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140892.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140892.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140893.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140893.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140893.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140893.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140893.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1962bf0] >[140894.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1962bf0] width 1280 pitch 5120 (/4 1280) >[140894.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140894.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140894.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140894.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140894.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140894.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140894.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964300] >[140894.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964300] width 1280 pitch 5120 (/4 1280) >[140894.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140894.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140894.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140895.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140895.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140895.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140898.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140898.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140898.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140898.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140918.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31020c0] >[140918.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31020c0] width 1280 pitch 5120 (/4 1280) >[140947.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140947.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140986.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140986.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140986.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140986.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140986.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140986.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140986.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140986.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140986.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[140986.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[140986.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140986.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140986.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140986.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140986.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140986.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140986.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140986.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140987.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140987.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140987.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140987.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14637d0] >[140988.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14637d0] width 1280 pitch 5120 (/4 1280) >[140988.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[140988.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[140988.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[140988.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[140988.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141005.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141005.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141005.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141005.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141005.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[141005.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[141005.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141005.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141006.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[141006.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[141006.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141006.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141006.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141006.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141006.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141006.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141006.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141006.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141007.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141007.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141007.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141007.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141007.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141007.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141010.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3105030] >[141010.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3105030] width 1280 pitch 5120 (/4 1280) >[141010.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdd90] >[141010.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdd90] width 1280 pitch 5120 (/4 1280) >[141025.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141025.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141025.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141025.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141025.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141025.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141025.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141025.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141025.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141025.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141034.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141034.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141034.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141034.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141034.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281df90] >[141034.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281df90] width 1280 pitch 5120 (/4 1280) >[141034.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2894d20] >[141034.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2894d20] width 1280 pitch 5120 (/4 1280) >[141034.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281df90] >[141034.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281df90] width 1280 pitch 5120 (/4 1280) >[141034.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2894d20] >[141034.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2894d20] width 1280 pitch 5120 (/4 1280) >[141034.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141034.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141034.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141034.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141035.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141035.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141035.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141035.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141035.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831d60] >[141035.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831d60] width 1280 pitch 5120 (/4 1280) >[141035.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141035.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141035.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892410] >[141035.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892410] width 1280 pitch 5120 (/4 1280) >[141035.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141035.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141049.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892410] >[141049.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892410] width 1280 pitch 5120 (/4 1280) >[141049.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2894d20] >[141049.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2894d20] width 1280 pitch 5120 (/4 1280) >[141053.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892410] >[141053.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892410] width 1280 pitch 5120 (/4 1280) >[141053.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c3b0] >[141053.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c3b0] width 1280 pitch 5120 (/4 1280) >[141053.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[141053.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[141053.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965940] >[141053.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965940] width 1280 pitch 5120 (/4 1280) >[141054.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281df90] >[141054.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281df90] width 1280 pitch 5120 (/4 1280) >[141054.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fef2c0] >[141054.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fef2c0] width 1280 pitch 5120 (/4 1280) >[141054.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28416f0] >[141054.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28416f0] width 1280 pitch 5120 (/4 1280) >[141054.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c3b0] >[141054.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c3b0] width 1280 pitch 5120 (/4 1280) >[141120.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281df90] >[141120.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281df90] width 1280 pitch 5120 (/4 1280) >[141120.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141120.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141120.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141120.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141120.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820770] >[141120.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820770] width 1280 pitch 5120 (/4 1280) >[141121.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141121.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141121.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141121.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141121.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820770] >[141121.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820770] width 1280 pitch 5120 (/4 1280) >[141121.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141121.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141128.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820770] >[141128.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820770] width 1280 pitch 5120 (/4 1280) >[141128.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141128.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141129.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892350] >[141129.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892350] width 1280 pitch 5120 (/4 1280) >[141129.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141129.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141129.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141129.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141129.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141129.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141129.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141129.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141129.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141129.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141129.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141129.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141129.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820770] >[141129.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820770] width 1280 pitch 5120 (/4 1280) >[141129.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[141129.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[141130.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462a30] >[141130.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462a30] width 1280 pitch 5120 (/4 1280) >[141130.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[141130.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[141130.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141130.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141130.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28932f0] >[141130.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28932f0] width 1280 pitch 5120 (/4 1280) >[141130.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ffac0] >[141130.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ffac0] width 1280 pitch 5120 (/4 1280) >[141131.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28932f0] >[141131.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28932f0] width 1280 pitch 5120 (/4 1280) >[141132.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141132.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141132.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141132.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141132.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141132.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141135.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1463800] >[141135.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1463800] width 1280 pitch 5120 (/4 1280) >[141135.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31040d0] >[141135.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31040d0] width 1280 pitch 5120 (/4 1280) >[141144.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799ab0] >[141144.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799ab0] width 1280 pitch 5120 (/4 1280) >[141144.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320aa40] >[141144.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320aa40] width 1280 pitch 5120 (/4 1280) >[141144.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320aa40] >[141144.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320aa40] width 1280 pitch 5120 (/4 1280) >[141144.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2844280] >[141144.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2844280] width 1280 pitch 5120 (/4 1280) >[141145.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320aa40] >[141145.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320aa40] width 1280 pitch 5120 (/4 1280) >[141145.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3104d90] >[141145.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3104d90] width 1280 pitch 5120 (/4 1280) >[141145.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3104d90] >[141145.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3104d90] width 1280 pitch 5120 (/4 1280) >[141145.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2795270] >[141145.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2795270] width 1280 pitch 5120 (/4 1280) >[141148.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fe330] >[141148.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fe330] width 1280 pitch 5120 (/4 1280) >[141148.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964980] >[141148.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964980] width 1280 pitch 5120 (/4 1280) >[141148.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141148.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141148.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1964980] >[141148.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1964980] width 1280 pitch 5120 (/4 1280) >[141148.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141148.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141152.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102e00] >[141152.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102e00] width 1280 pitch 5120 (/4 1280) >[141153.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141153.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141153.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141153.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141153.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141153.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141153.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102d20] >[141153.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102d20] width 1280 pitch 5120 (/4 1280) >[141154.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141154.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141154.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820770] >[141154.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820770] width 1280 pitch 5120 (/4 1280) >[141154.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320e8c0] >[141154.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320e8c0] width 1280 pitch 5120 (/4 1280) >[141204.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194c370] >[141204.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194c370] width 1280 pitch 5120 (/4 1280) >[141204.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141204.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141204.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141204.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141204.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27224a0] >[141204.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27224a0] width 1280 pitch 5120 (/4 1280) >[141204.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3101fd0] >[141204.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3101fd0] width 1280 pitch 5120 (/4 1280) >[141204.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195f6f0] >[141204.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195f6f0] width 1280 pitch 5120 (/4 1280) >[141204.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2891dd0] >[141204.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2891dd0] width 1280 pitch 5120 (/4 1280) >[141204.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102d20] >[141204.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102d20] width 1280 pitch 5120 (/4 1280) >[141208.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2891dd0] >[141208.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2891dd0] width 1280 pitch 5120 (/4 1280) >[141208.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102d20] >[141208.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102d20] width 1280 pitch 5120 (/4 1280) >[141208.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19609e0] >[141208.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19609e0] width 1280 pitch 5120 (/4 1280) >[141208.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141208.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141209.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102240] >[141209.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102240] width 1280 pitch 5120 (/4 1280) >[141209.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279dd10] >[141209.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279dd10] width 1280 pitch 5120 (/4 1280) >[141209.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a75d0] >[141209.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a75d0] width 1280 pitch 5120 (/4 1280) >[141209.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723ec0] >[141209.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723ec0] width 1280 pitch 5120 (/4 1280) >[141211.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28320f0] >[141211.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28320f0] width 1280 pitch 5120 (/4 1280) >[141211.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2723ec0] >[141211.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2723ec0] width 1280 pitch 5120 (/4 1280) >[141211.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892170] >[141211.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892170] width 1280 pitch 5120 (/4 1280) >[141211.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19609e0] >[141211.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19609e0] width 1280 pitch 5120 (/4 1280) >[141212.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892170] >[141212.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892170] width 1280 pitch 5120 (/4 1280) >[141212.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320d240] >[141212.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320d240] width 1280 pitch 5120 (/4 1280) >[141212.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28320f0] >[141212.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28320f0] width 1280 pitch 5120 (/4 1280) >[141212.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e8b0] >[141212.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e8b0] width 1280 pitch 5120 (/4 1280) >[141213.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28320f0] >[141213.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28320f0] width 1280 pitch 5120 (/4 1280) >[141213.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28320f0] >[141213.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28320f0] width 1280 pitch 5120 (/4 1280) >[141213.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462af0] >[141213.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462af0] width 1280 pitch 5120 (/4 1280) >[141213.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279dba0] >[141213.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279dba0] width 1280 pitch 5120 (/4 1280) >[141218.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462af0] >[141218.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462af0] width 1280 pitch 5120 (/4 1280) >[141220.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[141220.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[141220.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141220.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141220.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141220.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141220.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141221.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141221.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141221.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141221.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462af0] >[141221.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462af0] width 1280 pitch 5120 (/4 1280) >[141221.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3082820] >[141221.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3082820] width 1280 pitch 5120 (/4 1280) >[141221.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3102240] >[141221.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3102240] width 1280 pitch 5120 (/4 1280) >[141222.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3101fd0] >[141222.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3101fd0] width 1280 pitch 5120 (/4 1280) >[141222.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282be00] >[141222.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282be00] width 1280 pitch 5120 (/4 1280) >[141222.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141222.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141224.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279a7c0] >[141224.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279a7c0] width 1280 pitch 5120 (/4 1280) >[141225.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141225.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141225.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[141225.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[141225.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141225.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141226.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141226.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141226.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141226.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141226.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141226.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141226.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462b00] >[141226.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462b00] width 1280 pitch 5120 (/4 1280) >[141227.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1969690] >[141227.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1969690] width 1280 pitch 5120 (/4 1280) >[141228.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898300] >[141228.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898300] width 1280 pitch 5120 (/4 1280) >[141228.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462b00] >[141228.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462b00] width 1280 pitch 5120 (/4 1280) >[141228.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1462b00] >[141228.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1462b00] width 1280 pitch 5120 (/4 1280) >[141229.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[141229.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[141230.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af90] >[141230.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af90] width 1280 pitch 5120 (/4 1280) >[141230.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141230.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141230.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141230.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141230.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141230.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141230.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141230.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141230.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141230.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141230.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141230.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141230.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141230.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141230.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141230.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141231.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141231.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141231.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141231.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141231.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141231.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141231.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141231.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141231.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141231.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141231.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141231.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141231.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141231.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141231.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141231.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141231.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81320] >[141231.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81320] width 1280 pitch 5120 (/4 1280) >[141231.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81320] >[141231.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81320] width 1280 pitch 5120 (/4 1280) >[141231.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81320] >[141231.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81320] width 1280 pitch 5120 (/4 1280) >[141231.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141231.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141231.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81320] >[141232.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81320] width 1280 pitch 5120 (/4 1280) >[141232.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f81320] >[141232.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f81320] width 1280 pitch 5120 (/4 1280) >[141232.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1963000] >[141232.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1963000] width 1280 pitch 5120 (/4 1280) >[141232.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141232.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141232.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6590] >[141232.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6590] width 1280 pitch 5120 (/4 1280) >[141232.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141232.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141232.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141232.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141232.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141233.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141233.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141233.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141233.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141233.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141233.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141233.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141233.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141233.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141234.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141234.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141234.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141234.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898270] >[141234.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898270] width 1280 pitch 5120 (/4 1280) >[141234.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141234.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141234.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfc0] >[141234.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfc0] width 1280 pitch 5120 (/4 1280) >[141234.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141234.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141234.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfc0] >[141234.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfc0] width 1280 pitch 5120 (/4 1280) >[141234.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141234.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141234.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31dcfc0] >[141234.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31dcfc0] width 1280 pitch 5120 (/4 1280) >[141234.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fed0] >[141234.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fed0] width 1280 pitch 5120 (/4 1280) >[141236.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f42230] >[141236.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f42230] width 1280 pitch 5120 (/4 1280) >[141236.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f4960] >[141236.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f4960] width 1280 pitch 5120 (/4 1280) >[141236.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2844220] >[141236.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2844220] width 1280 pitch 5120 (/4 1280) >[141236.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f42230] >[141236.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f42230] width 1280 pitch 5120 (/4 1280) >[141236.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2844220] >[141236.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2844220] width 1280 pitch 5120 (/4 1280) >[141237.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27af690] >[141237.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27af690] width 1280 pitch 5120 (/4 1280) >[141238.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27af690] >[141238.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27af690] width 1280 pitch 5120 (/4 1280) >[141238.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c0f0] >[141238.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c0f0] width 1280 pitch 5120 (/4 1280) >[141238.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27af690] >[141238.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27af690] width 1280 pitch 5120 (/4 1280) >[141254.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141254.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141257.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141257.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141258.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31015e0] >[141258.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31015e0] width 1280 pitch 5120 (/4 1280) >[141258.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141258.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141258.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31015e0] >[141258.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31015e0] width 1280 pitch 5120 (/4 1280) >[141284.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141284.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141284.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141284.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141284.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288acc0] >[141284.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288acc0] width 1280 pitch 5120 (/4 1280) >[141284.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288acc0] >[141284.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288acc0] width 1280 pitch 5120 (/4 1280) >[141285.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141285.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141285.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281abb0] >[141285.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281abb0] width 1280 pitch 5120 (/4 1280) >[141285.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5d90] >[141285.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5d90] width 1280 pitch 5120 (/4 1280) >[141285.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5d90] >[141285.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5d90] width 1280 pitch 5120 (/4 1280) >[141285.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281abb0] >[141285.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281abb0] width 1280 pitch 5120 (/4 1280) >[141285.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5d90] >[141285.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5d90] width 1280 pitch 5120 (/4 1280) >[141316.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141316.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141316.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff7550] >[141316.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff7550] width 1280 pitch 5120 (/4 1280) >[141316.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141316.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141316.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141316.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141317.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141317.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141317.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141317.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141317.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141317.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141317.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141317.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141318.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141318.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141318.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d190] >[141318.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d190] width 1280 pitch 5120 (/4 1280) >[141318.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0ce80] >[141318.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0ce80] width 1280 pitch 5120 (/4 1280) >[141318.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141318.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141319.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141319.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141319.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442100] >[141319.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442100] width 1280 pitch 5120 (/4 1280) >[141319.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442100] >[141319.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442100] width 1280 pitch 5120 (/4 1280) >[141319.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307f3d0] >[141319.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307f3d0] width 1280 pitch 5120 (/4 1280) >[141329.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f6db0] >[141329.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f6db0] width 1280 pitch 5120 (/4 1280) >[141329.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f6f20] >[141330.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f6f20] width 1280 pitch 5120 (/4 1280) >[141330.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141330.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141330.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141330.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141330.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141330.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141330.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141330.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141330.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27604a0] >[141330.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27604a0] width 1280 pitch 5120 (/4 1280) >[141330.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141330.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141330.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839290] >[141330.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839290] width 1280 pitch 5120 (/4 1280) >[141331.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141331.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141331.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141331.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141331.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141331.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141333.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d1a0] >[141334.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d1a0] width 1280 pitch 5120 (/4 1280) >[141334.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141334.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141334.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141334.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141334.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d1a0] >[141334.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d1a0] width 1280 pitch 5120 (/4 1280) >[141335.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d1a0] >[141335.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d1a0] width 1280 pitch 5120 (/4 1280) >[141335.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f640] >[141335.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f640] width 1280 pitch 5120 (/4 1280) >[141335.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d1a0] >[141335.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d1a0] width 1280 pitch 5120 (/4 1280) >[141335.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141335.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141335.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141335.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141335.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141335.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141336.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141336.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141336.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19604e0] >[141336.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19604e0] width 1280 pitch 5120 (/4 1280) >[141336.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282aee0] >[141336.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282aee0] width 1280 pitch 5120 (/4 1280) >[141336.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141336.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141354.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445f20] >[141354.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445f20] width 1280 pitch 5120 (/4 1280) >[141354.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f7d90] >[141354.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f7d90] width 1280 pitch 5120 (/4 1280) >[141371.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444cb0] >[141371.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444cb0] width 1280 pitch 5120 (/4 1280) >[141371.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fb050] >[141371.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fb050] width 1280 pitch 5120 (/4 1280) >[141371.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3005400] >[141371.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3005400] width 1280 pitch 5120 (/4 1280) >[141371.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fb600] >[141371.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fb600] width 1280 pitch 5120 (/4 1280) >[141371.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892150] >[141371.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892150] width 1280 pitch 5120 (/4 1280) >[141378.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141378.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141378.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2892150] >[141378.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2892150] width 1280 pitch 5120 (/4 1280) >[141378.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x111a190] >[141378.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x111a190] width 1280 pitch 5120 (/4 1280) >[141378.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1960560] >[141378.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1960560] width 1280 pitch 5120 (/4 1280) >[141378.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839200] >[141378.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839200] width 1280 pitch 5120 (/4 1280) >[141379.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141379.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141379.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27993c0] >[141379.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27993c0] width 1280 pitch 5120 (/4 1280) >[141379.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141379.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141380.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fee150] >[141380.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fee150] width 1280 pitch 5120 (/4 1280) >[141380.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fea5f0] >[141380.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fea5f0] width 1280 pitch 5120 (/4 1280) >[141400.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe80c0] >[141400.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe80c0] width 1280 pitch 5120 (/4 1280) >[141404.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2260] >[141404.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2260] width 1280 pitch 5120 (/4 1280) >[141438.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27993c0] >[141438.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27993c0] width 1280 pitch 5120 (/4 1280) >[141439.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141439.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141439.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839150] >[141439.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839150] width 1280 pitch 5120 (/4 1280) >[141439.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799e50] >[141439.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799e50] width 1280 pitch 5120 (/4 1280) >[141483.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141483.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141483.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141483.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141483.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141483.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141484.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141484.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141484.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141484.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141484.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141484.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141484.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff6160] >[141484.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff6160] width 1280 pitch 5120 (/4 1280) >[141484.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141484.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141486.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141486.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141486.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141486.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141486.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141486.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141486.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141486.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141487.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141487.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141487.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141487.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141487.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141487.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141487.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141487.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141489.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141489.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141489.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141489.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141489.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141489.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141489.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141489.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141494.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141494.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141494.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141494.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141494.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141494.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141494.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141494.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141495.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141495.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141495.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141495.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141495.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141496.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141496.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2023540] >[141496.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2023540] width 1280 pitch 5120 (/4 1280) >[141500.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838740] >[141500.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838740] width 1280 pitch 5120 (/4 1280) >[141500.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1e960] >[141500.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1e960] width 1280 pitch 5120 (/4 1280) >[141501.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff6120] >[141501.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff6120] width 1280 pitch 5120 (/4 1280) >[141501.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fb6a0] >[141501.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fb6a0] width 1280 pitch 5120 (/4 1280) >[141501.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141501.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141501.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141501.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141517.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141517.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141517.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141517.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141517.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febd80] >[141517.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febd80] width 1280 pitch 5120 (/4 1280) >[141517.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141517.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141518.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f99d0] >[141518.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f99d0] width 1280 pitch 5120 (/4 1280) >[141518.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f4d50] >[141518.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f4d50] width 1280 pitch 5120 (/4 1280) >[141518.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141518.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141518.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff6c40] >[141518.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff6c40] width 1280 pitch 5120 (/4 1280) >[141523.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff6c40] >[141523.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff6c40] width 1280 pitch 5120 (/4 1280) >[141523.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141523.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141523.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8fd10] >[141523.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8fd10] width 1280 pitch 5120 (/4 1280) >[141523.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141523.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141524.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445020] >[141524.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445020] width 1280 pitch 5120 (/4 1280) >[141524.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444ec0] >[141524.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444ec0] width 1280 pitch 5120 (/4 1280) >[141524.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141524.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141524.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141524.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141524.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141525.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141525.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f97d0] >[141525.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f97d0] width 1280 pitch 5120 (/4 1280) >[141525.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797b50] >[141525.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797b50] width 1280 pitch 5120 (/4 1280) >[141525.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27991c0] >[141525.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27991c0] width 1280 pitch 5120 (/4 1280) >[141526.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e8b0] >[141526.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e8b0] width 1280 pitch 5120 (/4 1280) >[141526.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e8b0] >[141526.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e8b0] width 1280 pitch 5120 (/4 1280) >[141528.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a5f60] >[141528.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a5f60] width 1280 pitch 5120 (/4 1280) >[141528.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820b20] >[141528.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820b20] width 1280 pitch 5120 (/4 1280) >[141528.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff6c40] >[141528.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff6c40] width 1280 pitch 5120 (/4 1280) >[141528.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820b20] >[141528.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820b20] width 1280 pitch 5120 (/4 1280) >[141528.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141528.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141528.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141528.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141529.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb190] >[141529.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb190] width 1280 pitch 5120 (/4 1280) >[141529.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820a60] >[141529.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820a60] width 1280 pitch 5120 (/4 1280) >[141554.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa150] >[141554.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa150] width 1280 pitch 5120 (/4 1280) >[141554.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa150] >[141554.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa150] width 1280 pitch 5120 (/4 1280) >[141554.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa150] >[141554.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa150] width 1280 pitch 5120 (/4 1280) >[141554.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24451a0] >[141554.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24451a0] width 1280 pitch 5120 (/4 1280) >[141554.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24451a0] >[141554.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24451a0] width 1280 pitch 5120 (/4 1280) >[141554.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa150] >[141554.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa150] width 1280 pitch 5120 (/4 1280) >[141554.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004a40] >[141554.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004a40] width 1280 pitch 5120 (/4 1280) >[141554.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141554.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141556.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141556.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141556.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa150] >[141556.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa150] width 1280 pitch 5120 (/4 1280) >[141556.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141556.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141556.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141556.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141556.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141556.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141556.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141556.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141556.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fa870] >[141556.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fa870] width 1280 pitch 5120 (/4 1280) >[141556.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141556.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141558.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ec120] >[141558.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ec120] width 1280 pitch 5120 (/4 1280) >[141558.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141558.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141558.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fea180] >[141558.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fea180] width 1280 pitch 5120 (/4 1280) >[141558.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fa870] >[141558.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fa870] width 1280 pitch 5120 (/4 1280) >[141561.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff33d0] >[141561.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff33d0] width 1280 pitch 5120 (/4 1280) >[141561.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebc40] >[141561.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebc40] width 1280 pitch 5120 (/4 1280) >[141581.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fac70] >[141581.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fac70] width 1280 pitch 5120 (/4 1280) >[141589.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eaa80] >[141589.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eaa80] width 1280 pitch 5120 (/4 1280) >[141589.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebc70] >[141589.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebc70] width 1280 pitch 5120 (/4 1280) >[141589.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bf390] >[141589.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bf390] width 1280 pitch 5120 (/4 1280) >[141589.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141589.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141590.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141590.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141590.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141590.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141590.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f9900] >[141590.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f9900] width 1280 pitch 5120 (/4 1280) >[141590.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141590.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141595.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f9600] >[141595.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f9600] width 1280 pitch 5120 (/4 1280) >[141595.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f9600] >[141595.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f9600] width 1280 pitch 5120 (/4 1280) >[141595.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff3360] >[141595.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff3360] width 1280 pitch 5120 (/4 1280) >[141595.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30889c0] >[141595.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30889c0] width 1280 pitch 5120 (/4 1280) >[141596.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831720] >[141596.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831720] width 1280 pitch 5120 (/4 1280) >[141596.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fea180] >[141596.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fea180] width 1280 pitch 5120 (/4 1280) >[141596.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27240c0] >[141596.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27240c0] width 1280 pitch 5120 (/4 1280) >[141596.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27240c0] >[141596.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27240c0] width 1280 pitch 5120 (/4 1280) >[141596.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eb6f0] >[141596.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eb6f0] width 1280 pitch 5120 (/4 1280) >[141596.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff83e0] >[141596.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff83e0] width 1280 pitch 5120 (/4 1280) >[141631.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f05b0] >[141631.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f05b0] width 1280 pitch 5120 (/4 1280) >[141631.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2ef0] >[141631.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2ef0] width 1280 pitch 5120 (/4 1280) >[141631.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141631.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141631.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0bd0] >[141631.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0bd0] width 1280 pitch 5120 (/4 1280) >[141631.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0bd0] >[141631.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0bd0] width 1280 pitch 5120 (/4 1280) >[141631.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141632.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141632.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141632.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141632.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141632.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141636.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141636.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141636.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141636.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141636.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141636.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141636.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0bd0] >[141636.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0bd0] width 1280 pitch 5120 (/4 1280) >[141664.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0bd0] >[141664.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0bd0] width 1280 pitch 5120 (/4 1280) >[141665.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0bd0] >[141665.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0bd0] width 1280 pitch 5120 (/4 1280) >[141665.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[141665.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[141665.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141665.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141665.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2442d40] >[141665.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2442d40] width 1280 pitch 5120 (/4 1280) >[141665.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[141665.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[141665.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141665.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141665.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[141665.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[141694.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141694.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141698.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141698.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141699.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f09e0] >[141699.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f09e0] width 1280 pitch 5120 (/4 1280) >[141720.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797a30] >[141721.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797a30] width 1280 pitch 5120 (/4 1280) >[141721.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed3a0] >[141721.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed3a0] width 1280 pitch 5120 (/4 1280) >[141721.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed8d0] >[141721.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed8d0] width 1280 pitch 5120 (/4 1280) >[141721.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed3a0] >[141721.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed3a0] width 1280 pitch 5120 (/4 1280) >[141748.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445900] >[141748.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445900] width 1280 pitch 5120 (/4 1280) >[141748.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28389b0] >[141748.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28389b0] width 1280 pitch 5120 (/4 1280) >[141748.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[141748.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[141748.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fabf0] >[141748.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fabf0] width 1280 pitch 5120 (/4 1280) >[141749.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea50] >[141749.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea50] width 1280 pitch 5120 (/4 1280) >[141749.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141749.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141749.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b42a0] >[141749.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b42a0] width 1280 pitch 5120 (/4 1280) >[141749.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089b90] >[141749.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089b90] width 1280 pitch 5120 (/4 1280) >[141750.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141750.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141750.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141750.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141750.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2022fd0] >[141750.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2022fd0] width 1280 pitch 5120 (/4 1280) >[141750.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea50] >[141750.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea50] width 1280 pitch 5120 (/4 1280) >[141765.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed9a0] >[141765.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed9a0] width 1280 pitch 5120 (/4 1280) >[141765.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed9a0] >[141765.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed9a0] width 1280 pitch 5120 (/4 1280) >[141765.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[141765.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[141765.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed9a0] >[141765.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed9a0] width 1280 pitch 5120 (/4 1280) >[141778.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141778.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141778.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27008a0] >[141778.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27008a0] width 1280 pitch 5120 (/4 1280) >[141778.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141778.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141778.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27008a0] >[141778.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27008a0] width 1280 pitch 5120 (/4 1280) >[141778.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141778.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141778.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27008a0] >[141778.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27008a0] width 1280 pitch 5120 (/4 1280) >[141778.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141778.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141778.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27008a0] >[141778.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27008a0] width 1280 pitch 5120 (/4 1280) >[141779.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141779.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141779.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27008a0] >[141779.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27008a0] width 1280 pitch 5120 (/4 1280) >[141783.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24420a0] >[141783.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24420a0] width 1280 pitch 5120 (/4 1280) >[141783.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24420a0] >[141783.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24420a0] width 1280 pitch 5120 (/4 1280) >[141783.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141783.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141783.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141783.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141783.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141783.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141783.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141783.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141783.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141783.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141783.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141783.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141784.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141784.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141784.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141784.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141784.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7c30] >[141784.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7c30] width 1280 pitch 5120 (/4 1280) >[141784.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141784.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141784.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed840] >[141784.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed840] width 1280 pitch 5120 (/4 1280) >[141784.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c80f0] >[141784.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c80f0] width 1280 pitch 5120 (/4 1280) >[141784.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed840] >[141784.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed840] width 1280 pitch 5120 (/4 1280) >[141784.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7290] >[141784.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7290] width 1280 pitch 5120 (/4 1280) >[141784.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed840] >[141784.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed840] width 1280 pitch 5120 (/4 1280) >[141784.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7290] >[141784.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7290] width 1280 pitch 5120 (/4 1280) >[141784.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed840] >[141784.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed840] width 1280 pitch 5120 (/4 1280) >[141784.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141784.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141784.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed840] >[141784.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed840] width 1280 pitch 5120 (/4 1280) >[141784.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27affd0] >[141784.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27affd0] width 1280 pitch 5120 (/4 1280) >[141784.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700720] >[141784.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700720] width 1280 pitch 5120 (/4 1280) >[141784.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275e710] >[141784.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275e710] width 1280 pitch 5120 (/4 1280) >[141784.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700720] >[141785.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700720] width 1280 pitch 5120 (/4 1280) >[141785.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x275e710] >[141785.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x275e710] width 1280 pitch 5120 (/4 1280) >[141785.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c0f20] >[141785.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c0f20] width 1280 pitch 5120 (/4 1280) >[141785.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823d30] >[141785.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823d30] width 1280 pitch 5120 (/4 1280) >[141785.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c0ec0] >[141785.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c0ec0] width 1280 pitch 5120 (/4 1280) >[141785.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823d30] >[141785.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823d30] width 1280 pitch 5120 (/4 1280) >[141785.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c0ec0] >[141785.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c0ec0] width 1280 pitch 5120 (/4 1280) >[141785.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823d30] >[141785.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823d30] width 1280 pitch 5120 (/4 1280) >[141785.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c0ec0] >[141785.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c0ec0] width 1280 pitch 5120 (/4 1280) >[141785.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8450] >[141785.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8450] width 1280 pitch 5120 (/4 1280) >[141785.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27aff60] >[141785.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27aff60] width 1280 pitch 5120 (/4 1280) >[141785.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8450] >[141785.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8450] width 1280 pitch 5120 (/4 1280) >[141785.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27aff60] >[141785.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27aff60] width 1280 pitch 5120 (/4 1280) >[141785.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8450] >[141785.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8450] width 1280 pitch 5120 (/4 1280) >[141785.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27aff60] >[141786.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27aff60] width 1280 pitch 5120 (/4 1280) >[141786.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8450] >[141786.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8450] width 1280 pitch 5120 (/4 1280) >[141786.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27aff60] >[141786.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27aff60] width 1280 pitch 5120 (/4 1280) >[141786.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8450] >[141786.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8450] width 1280 pitch 5120 (/4 1280) >[141786.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823d30] >[141786.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823d30] width 1280 pitch 5120 (/4 1280) >[141786.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823d30] >[141786.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823d30] width 1280 pitch 5120 (/4 1280) >[141787.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c020] >[141787.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c020] width 1280 pitch 5120 (/4 1280) >[141787.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[141787.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[141787.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141787.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2220] >[141787.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2220] width 1280 pitch 5120 (/4 1280) >[141787.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b45a0] >[141787.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b45a0] width 1280 pitch 5120 (/4 1280) >[141789.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26faef0] >[141789.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26faef0] width 1280 pitch 5120 (/4 1280) >[141794.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a5ae0] >[141794.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a5ae0] width 1280 pitch 5120 (/4 1280) >[141794.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141794.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141794.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141794.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141794.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141794.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141794.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141794.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141794.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141794.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141794.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0860] >[141794.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0860] width 1280 pitch 5120 (/4 1280) >[141794.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141794.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0860] >[141794.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0860] width 1280 pitch 5120 (/4 1280) >[141794.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0800] >[141794.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0800] width 1280 pitch 5120 (/4 1280) >[141795.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a5ae0] >[141795.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a5ae0] width 1280 pitch 5120 (/4 1280) >[141795.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a5ae0] >[141795.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a5ae0] width 1280 pitch 5120 (/4 1280) >[141795.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141795.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141795.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141795.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141795.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141796.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141796.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141796.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141796.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141796.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141796.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141796.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141796.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141796.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141796.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141796.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141796.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141797.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141797.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141797.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141797.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141797.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141797.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141797.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141797.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141797.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa980] >[141798.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa980] width 1280 pitch 5120 (/4 1280) >[141798.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141798.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141798.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb100] >[141798.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb100] width 1280 pitch 5120 (/4 1280) >[141798.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb4490] >[141798.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb4490] width 1280 pitch 5120 (/4 1280) >[141798.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22de5b0] >[141798.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22de5b0] width 1280 pitch 5120 (/4 1280) >[141798.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb100] >[141798.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb100] width 1280 pitch 5120 (/4 1280) >[141798.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22de5b0] >[141798.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22de5b0] width 1280 pitch 5120 (/4 1280) >[141798.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb100] >[141798.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb100] width 1280 pitch 5120 (/4 1280) >[141798.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c090] >[141798.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c090] width 1280 pitch 5120 (/4 1280) >[141798.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb830] >[141798.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb830] width 1280 pitch 5120 (/4 1280) >[141798.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22de5b0] >[141798.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22de5b0] width 1280 pitch 5120 (/4 1280) >[141798.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1389480] >[141798.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1389480] width 1280 pitch 5120 (/4 1280) >[141798.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663d40] >[141798.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663d40] width 1280 pitch 5120 (/4 1280) >[141799.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb100] >[141799.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb100] width 1280 pitch 5120 (/4 1280) >[141799.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22de5f0] >[141799.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22de5f0] width 1280 pitch 5120 (/4 1280) >[141799.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb100] >[141799.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb100] width 1280 pitch 5120 (/4 1280) >[141799.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267a250] >[141799.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267a250] width 1280 pitch 5120 (/4 1280) >[141799.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x149f1a0] >[141799.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x149f1a0] width 1280 pitch 5120 (/4 1280) >[141799.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2c10] >[141799.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2c10] width 1280 pitch 5120 (/4 1280) >[141799.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3090140] >[141799.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3090140] width 1280 pitch 5120 (/4 1280) >[141799.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f42890] >[141799.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f42890] width 1280 pitch 5120 (/4 1280) >[141799.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c9380] >[141800.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c9380] width 1280 pitch 5120 (/4 1280) >[141810.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ffe30] >[141810.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ffe30] width 1280 pitch 5120 (/4 1280) >[141810.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c7e70] >[141810.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c7e70] width 1280 pitch 5120 (/4 1280) >[141810.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b4060] >[141810.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b4060] width 1280 pitch 5120 (/4 1280) >[141810.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f2b00] >[141810.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f2b00] width 1280 pitch 5120 (/4 1280) >[141811.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b4060] >[141811.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b4060] width 1280 pitch 5120 (/4 1280) >[141811.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c98b0] >[141811.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c98b0] width 1280 pitch 5120 (/4 1280) >[141811.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a25f0] >[141811.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a25f0] width 1280 pitch 5120 (/4 1280) >[141811.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c98b0] >[141811.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c98b0] width 1280 pitch 5120 (/4 1280) >[141825.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c0bd0] >[141825.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c0bd0] width 1280 pitch 5120 (/4 1280) >[141825.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1600] >[141825.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1600] width 1280 pitch 5120 (/4 1280) >[141845.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c98b0] >[141845.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c98b0] width 1280 pitch 5120 (/4 1280) >[141859.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289d9a0] >[141859.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289d9a0] width 1280 pitch 5120 (/4 1280) >[141872.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c1120] >[141872.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c1120] width 1280 pitch 5120 (/4 1280) >[141872.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2578540] >[141872.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2578540] width 1280 pitch 5120 (/4 1280) >[141884.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3c80] >[141884.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3c80] width 1280 pitch 5120 (/4 1280) >[141888.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a25f0] >[141888.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a25f0] width 1280 pitch 5120 (/4 1280) >[141889.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3c80] >[141889.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3c80] width 1280 pitch 5120 (/4 1280) >[141889.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a3e250] >[141889.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a3e250] width 1280 pitch 5120 (/4 1280) >[141889.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3c80] >[141889.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3c80] width 1280 pitch 5120 (/4 1280) >[141889.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674ee0] >[141889.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674ee0] width 1280 pitch 5120 (/4 1280) >[141889.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febb80] >[141889.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febb80] width 1280 pitch 5120 (/4 1280) >[141889.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c8520] >[141889.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c8520] width 1280 pitch 5120 (/4 1280) >[141889.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e90] >[141889.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e90] width 1280 pitch 5120 (/4 1280) >[141891.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e950] >[141891.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e950] width 1280 pitch 5120 (/4 1280) >[141891.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e110] >[141891.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e110] width 1280 pitch 5120 (/4 1280) >[141895.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eb690] >[141895.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eb690] width 1280 pitch 5120 (/4 1280) >[141905.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3c80] >[141905.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3c80] width 1280 pitch 5120 (/4 1280) >[141905.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ddba0] >[141905.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ddba0] width 1280 pitch 5120 (/4 1280) >[141905.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cf0f0] >[141905.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cf0f0] width 1280 pitch 5120 (/4 1280) >[141905.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141905.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141906.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141906.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141906.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e660] >[141906.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e660] width 1280 pitch 5120 (/4 1280) >[141906.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecff0] >[141906.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecff0] width 1280 pitch 5120 (/4 1280) >[141906.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141906.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141906.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2f30] >[141906.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2f30] width 1280 pitch 5120 (/4 1280) >[141907.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2f30] >[141907.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2f30] width 1280 pitch 5120 (/4 1280) >[141907.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e30] >[141907.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e30] width 1280 pitch 5120 (/4 1280) >[141907.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141907.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141909.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fea500] >[141909.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fea500] width 1280 pitch 5120 (/4 1280) >[141909.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257dc30] >[141909.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257dc30] width 1280 pitch 5120 (/4 1280) >[141920.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693b40] >[141920.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693b40] width 1280 pitch 5120 (/4 1280) >[141926.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141926.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141926.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141926.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141926.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e30] >[141926.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e30] width 1280 pitch 5120 (/4 1280) >[141926.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fc110] >[141926.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fc110] width 1280 pitch 5120 (/4 1280) >[141927.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e30] >[141927.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e30] width 1280 pitch 5120 (/4 1280) >[141927.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141927.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141927.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c6730] >[141927.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c6730] width 1280 pitch 5120 (/4 1280) >[141927.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141927.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141928.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700680] >[141928.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700680] width 1280 pitch 5120 (/4 1280) >[141928.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700680] >[141928.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700680] width 1280 pitch 5120 (/4 1280) >[141928.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e30] >[141928.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e30] width 1280 pitch 5120 (/4 1280) >[141928.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141928.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141929.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141929.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141929.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141929.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141929.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141929.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141929.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141929.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141944.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141944.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141944.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141944.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141944.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141944.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141944.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141944.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141944.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e660] >[141944.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e660] width 1280 pitch 5120 (/4 1280) >[141944.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141944.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141944.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266f490] >[141944.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266f490] width 1280 pitch 5120 (/4 1280) >[141944.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d04d0] >[141944.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d04d0] width 1280 pitch 5120 (/4 1280) >[141945.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d04d0] >[141945.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d04d0] width 1280 pitch 5120 (/4 1280) >[141945.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141945.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141945.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141945.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141945.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141945.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141946.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141946.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141947.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141947.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141947.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141947.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141947.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141947.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141948.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141948.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141948.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fad20] >[141949.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fad20] width 1280 pitch 5120 (/4 1280) >[141949.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141949.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141950.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141950.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141950.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eac60] >[141950.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eac60] width 1280 pitch 5120 (/4 1280) >[141950.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693cf0] >[141950.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693cf0] width 1280 pitch 5120 (/4 1280) >[141951.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1965ef0] >[141951.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1965ef0] width 1280 pitch 5120 (/4 1280) >[141952.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19630c0] >[141952.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19630c0] width 1280 pitch 5120 (/4 1280) >[141952.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c67b0] >[141952.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c67b0] width 1280 pitch 5120 (/4 1280) >[141952.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19630c0] >[141952.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19630c0] width 1280 pitch 5120 (/4 1280) >[141952.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19630c0] >[141952.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19630c0] width 1280 pitch 5120 (/4 1280) >[141952.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c67b0] >[141952.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c67b0] width 1280 pitch 5120 (/4 1280) >[141952.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288acc0] >[141952.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288acc0] width 1280 pitch 5120 (/4 1280) >[141952.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ca4a0] >[141952.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ca4a0] width 1280 pitch 5120 (/4 1280) >[141953.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141953.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141953.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141953.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141953.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[141953.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[141953.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[141953.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[141953.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[141953.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[141953.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4850] >[141953.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4850] width 1280 pitch 5120 (/4 1280) >[141953.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[141953.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[141953.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141953.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141953.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089850] >[141953.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089850] width 1280 pitch 5120 (/4 1280) >[141953.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c0f0] >[141953.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c0f0] width 1280 pitch 5120 (/4 1280) >[141953.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141953.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141953.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141953.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141953.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141953.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141953.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141953.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141953.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141954.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141954.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141954.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141954.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141954.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141954.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141954.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141954.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141954.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[141969.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[141969.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[141969.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[141969.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[141985.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[141985.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[141985.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281da70] >[141985.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281da70] width 1280 pitch 5120 (/4 1280) >[142000.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[142000.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[142000.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142000.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142000.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c0f0] >[142000.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c0f0] width 1280 pitch 5120 (/4 1280) >[142000.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c0f0] >[142000.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c0f0] width 1280 pitch 5120 (/4 1280) >[142001.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142001.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142001.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142001.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142001.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288adb0] >[142001.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288adb0] width 1280 pitch 5120 (/4 1280) >[142001.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142001.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142002.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[142002.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[142002.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288adb0] >[142002.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288adb0] width 1280 pitch 5120 (/4 1280) >[142002.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283c0f0] >[142002.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283c0f0] width 1280 pitch 5120 (/4 1280) >[142002.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27af690] >[142002.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27af690] width 1280 pitch 5120 (/4 1280) >[142044.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f12c0] >[142044.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f12c0] width 1280 pitch 5120 (/4 1280) >[142044.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142044.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142045.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f12c0] >[142045.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f12c0] width 1280 pitch 5120 (/4 1280) >[142045.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f12c0] >[142046.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f12c0] width 1280 pitch 5120 (/4 1280) >[142046.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae03c0] >[142046.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae03c0] width 1280 pitch 5120 (/4 1280) >[142046.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2666930] >[142046.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2666930] width 1280 pitch 5120 (/4 1280) >[142049.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2666930] >[142049.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2666930] width 1280 pitch 5120 (/4 1280) >[142050.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f12c0] >[142050.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f12c0] width 1280 pitch 5120 (/4 1280) >[142050.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142050.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142050.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[142050.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[142051.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142051.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142052.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142052.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142052.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142052.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142052.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142052.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142052.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142052.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142052.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142052.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142052.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142052.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142053.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142053.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142053.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1960930] >[142053.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1960930] width 1280 pitch 5120 (/4 1280) >[142053.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142053.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142054.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289b950] >[142054.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289b950] width 1280 pitch 5120 (/4 1280) >[142058.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279cc90] >[142058.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279cc90] width 1280 pitch 5120 (/4 1280) >[142058.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90a00] >[142058.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90a00] width 1280 pitch 5120 (/4 1280) >[142058.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7140] >[142058.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7140] width 1280 pitch 5120 (/4 1280) >[142058.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cb550] >[142059.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cb550] width 1280 pitch 5120 (/4 1280) >[142059.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142059.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142059.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f85060] >[142059.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f85060] width 1280 pitch 5120 (/4 1280) >[142059.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cb550] >[142059.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cb550] width 1280 pitch 5120 (/4 1280) >[142059.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cb4c0] >[142059.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cb4c0] width 1280 pitch 5120 (/4 1280) >[142060.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142060.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142060.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142060.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142060.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142060.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142060.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142060.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142060.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142060.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142061.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142061.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142076.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142076.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142076.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142076.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142076.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320af80] >[142076.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320af80] width 1280 pitch 5120 (/4 1280) >[142076.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c6a90] >[142076.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c6a90] width 1280 pitch 5120 (/4 1280) >[142077.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142077.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142077.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142077.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142077.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19614a0] >[142077.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19614a0] width 1280 pitch 5120 (/4 1280) >[142077.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ace20] >[142077.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ace20] width 1280 pitch 5120 (/4 1280) >[142078.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e070] >[142078.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e070] width 1280 pitch 5120 (/4 1280) >[142078.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ace20] >[142078.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ace20] width 1280 pitch 5120 (/4 1280) >[142078.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1961930] >[142078.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1961930] width 1280 pitch 5120 (/4 1280) >[142078.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289cc10] >[142078.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289cc10] width 1280 pitch 5120 (/4 1280) >[142080.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142080.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142089.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142089.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142089.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142089.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2789c90] >[142090.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2789c90] width 1280 pitch 5120 (/4 1280) >[142090.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142090.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142090.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142090.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142090.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825600] >[142090.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825600] width 1280 pitch 5120 (/4 1280) >[142090.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142090.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142091.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142091.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142091.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142091.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142091.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7150] >[142091.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7150] width 1280 pitch 5120 (/4 1280) >[142091.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142092.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142092.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142092.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142092.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142092.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142104.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142104.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142105.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142105.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142105.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2789bb0] >[142105.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2789bb0] width 1280 pitch 5120 (/4 1280) >[142105.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142105.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142107.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278df10] >[142107.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278df10] width 1280 pitch 5120 (/4 1280) >[142124.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281bf60] >[142124.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281bf60] width 1280 pitch 5120 (/4 1280) >[142124.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f94a0] >[142124.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f94a0] width 1280 pitch 5120 (/4 1280) >[142124.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f94a0] >[142124.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f94a0] width 1280 pitch 5120 (/4 1280) >[142124.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142124.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142124.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142124.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142124.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142124.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793270] >[142124.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793270] width 1280 pitch 5120 (/4 1280) >[142124.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142124.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142125.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142125.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142125.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142125.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142125.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142125.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142125.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142125.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142125.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142125.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142125.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142125.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142125.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142125.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142125.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142125.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142125.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142125.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142145.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142145.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142145.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142145.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142145.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e7b0] >[142145.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e7b0] width 1280 pitch 5120 (/4 1280) >[142146.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142146.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142146.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e040] >[142146.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e040] width 1280 pitch 5120 (/4 1280) >[142146.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2666930] >[142146.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2666930] width 1280 pitch 5120 (/4 1280) >[142146.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142146.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142146.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142146.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142152.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7150] >[142152.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7150] width 1280 pitch 5120 (/4 1280) >[142152.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142152.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142152.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825710] >[142152.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825710] width 1280 pitch 5120 (/4 1280) >[142152.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142152.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142155.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d08f0] >[142155.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d08f0] width 1280 pitch 5120 (/4 1280) >[142160.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783b70] >[142160.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783b70] width 1280 pitch 5120 (/4 1280) >[142162.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142162.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142162.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142162.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142162.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142163.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d10d0] >[142163.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d10d0] width 1280 pitch 5120 (/4 1280) >[142163.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142163.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142163.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142163.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142163.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142163.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142163.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142163.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142163.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142163.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142163.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142163.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142163.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142163.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142163.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142163.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142163.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b037a0] >[142163.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b037a0] width 1280 pitch 5120 (/4 1280) >[142174.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142174.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142174.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142174.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142174.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1466f20] >[142175.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1466f20] width 1280 pitch 5120 (/4 1280) >[142175.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f82e90] >[142175.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f82e90] width 1280 pitch 5120 (/4 1280) >[142175.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x117b320] >[142175.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x117b320] width 1280 pitch 5120 (/4 1280) >[142175.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83e10] >[142176.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83e10] width 1280 pitch 5120 (/4 1280) >[142176.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142176.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142176.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83e10] >[142176.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83e10] width 1280 pitch 5120 (/4 1280) >[142177.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142177.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142177.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142177.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142177.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cbf10] >[142177.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cbf10] width 1280 pitch 5120 (/4 1280) >[142177.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb3e0] >[142177.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb3e0] width 1280 pitch 5120 (/4 1280) >[142178.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cbf10] >[142178.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cbf10] width 1280 pitch 5120 (/4 1280) >[142178.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10faf30] >[142178.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10faf30] width 1280 pitch 5120 (/4 1280) >[142178.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10faf30] >[142178.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10faf30] width 1280 pitch 5120 (/4 1280) >[142178.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142178.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142192.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19608f0] >[142192.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19608f0] width 1280 pitch 5120 (/4 1280) >[142192.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2fc0] >[142192.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2fc0] width 1280 pitch 5120 (/4 1280) >[142192.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142192.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142192.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1960870] >[142192.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1960870] width 1280 pitch 5120 (/4 1280) >[142192.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825510] >[142192.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825510] width 1280 pitch 5120 (/4 1280) >[142192.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142192.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142192.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669040] >[142192.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669040] width 1280 pitch 5120 (/4 1280) >[142192.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142192.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142202.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2584170] >[142202.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2584170] width 1280 pitch 5120 (/4 1280) >[142202.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2949960] >[142202.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2949960] width 1280 pitch 5120 (/4 1280) >[142216.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff23a0] >[142216.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff23a0] width 1280 pitch 5120 (/4 1280) >[142216.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142216.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142216.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3175cc0] >[142216.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3175cc0] width 1280 pitch 5120 (/4 1280) >[142216.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783cb0] >[142216.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783cb0] width 1280 pitch 5120 (/4 1280) >[142217.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246a0] >[142217.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246a0] width 1280 pitch 5120 (/4 1280) >[142217.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff23a0] >[142217.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff23a0] width 1280 pitch 5120 (/4 1280) >[142217.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2583c70] >[142217.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2583c70] width 1280 pitch 5120 (/4 1280) >[142217.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff23a0] >[142217.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff23a0] width 1280 pitch 5120 (/4 1280) >[142221.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246a0] >[142221.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246a0] width 1280 pitch 5120 (/4 1280) >[142221.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fbce0] >[142221.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fbce0] width 1280 pitch 5120 (/4 1280) >[142222.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2583c70] >[142222.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2583c70] width 1280 pitch 5120 (/4 1280) >[142222.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142222.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142222.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246a0] >[142222.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246a0] width 1280 pitch 5120 (/4 1280) >[142222.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f400] >[142222.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f400] width 1280 pitch 5120 (/4 1280) >[142222.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c9b90] >[142222.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c9b90] width 1280 pitch 5120 (/4 1280) >[142227.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c9b90] >[142227.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c9b90] width 1280 pitch 5120 (/4 1280) >[142227.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142227.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142227.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142227.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142227.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142227.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142228.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142228.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142228.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142228.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142228.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142228.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142228.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142228.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142228.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142228.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142259.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142259.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142259.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142259.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142259.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142259.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142259.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d10d0] >[142259.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d10d0] width 1280 pitch 5120 (/4 1280) >[142260.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142260.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142260.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142260.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142260.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142260.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142260.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142260.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142260.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d10d0] >[142260.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d10d0] width 1280 pitch 5120 (/4 1280) >[142260.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142260.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142260.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142261.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142261.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142261.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142261.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142261.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142263.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fd8e0] >[142263.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fd8e0] width 1280 pitch 5120 (/4 1280) >[142263.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fd8e0] >[142263.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fd8e0] width 1280 pitch 5120 (/4 1280) >[142274.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195fe70] >[142274.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195fe70] width 1280 pitch 5120 (/4 1280) >[142274.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fd8e0] >[142274.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fd8e0] width 1280 pitch 5120 (/4 1280) >[142274.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142274.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142274.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fd8e0] >[142274.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fd8e0] width 1280 pitch 5120 (/4 1280) >[142274.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142274.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142280.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142280.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142280.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294c770] >[142280.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294c770] width 1280 pitch 5120 (/4 1280) >[142280.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb8b0] >[142280.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb8b0] width 1280 pitch 5120 (/4 1280) >[142280.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142280.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142281.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[142281.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[142281.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142281.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142281.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142281.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142281.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142281.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142283.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c78d0] >[142283.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c78d0] width 1280 pitch 5120 (/4 1280) >[142293.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90a00] >[142293.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90a00] width 1280 pitch 5120 (/4 1280) >[142293.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142293.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142293.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142293.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142293.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142293.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[142293.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[142293.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819e90] >[142293.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819e90] width 1280 pitch 5120 (/4 1280) >[142295.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819d90] >[142295.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819d90] width 1280 pitch 5120 (/4 1280) >[142295.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d2530] >[142295.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d2530] width 1280 pitch 5120 (/4 1280) >[142295.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d7f0] >[142295.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d7f0] width 1280 pitch 5120 (/4 1280) >[142295.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d24d0] >[142295.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d24d0] width 1280 pitch 5120 (/4 1280) >[142295.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142295.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142295.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142295.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142295.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142295.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142295.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142295.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142295.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142295.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142295.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28256b0] >[142295.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28256b0] width 1280 pitch 5120 (/4 1280) >[142295.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142295.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142295.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142295.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142295.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142295.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142295.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142295.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142295.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142295.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142295.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[142295.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[142295.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142295.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142296.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90a00] >[142296.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90a00] width 1280 pitch 5120 (/4 1280) >[142296.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9db00] >[142296.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9db00] width 1280 pitch 5120 (/4 1280) >[142296.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9db00] >[142296.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9db00] width 1280 pitch 5120 (/4 1280) >[142296.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142296.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142296.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294c840] >[142296.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294c840] width 1280 pitch 5120 (/4 1280) >[142296.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266dd80] >[142296.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266dd80] width 1280 pitch 5120 (/4 1280) >[142296.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19624b0] >[142296.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19624b0] width 1280 pitch 5120 (/4 1280) >[142297.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266dd80] >[142297.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266dd80] width 1280 pitch 5120 (/4 1280) >[142300.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27e97c0] >[142300.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27e97c0] width 1280 pitch 5120 (/4 1280) >[142300.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142301.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142301.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce4600] >[142301.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce4600] width 1280 pitch 5120 (/4 1280) >[142301.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142301.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142301.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[142301.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[142301.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9db00] >[142301.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9db00] width 1280 pitch 5120 (/4 1280) >[142301.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142302.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142302.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27c9590] >[142302.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27c9590] width 1280 pitch 5120 (/4 1280) >[142302.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f220] >[142302.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f220] width 1280 pitch 5120 (/4 1280) >[142303.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257c710] >[142303.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257c710] width 1280 pitch 5120 (/4 1280) >[142305.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b74e0] >[142305.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b74e0] width 1280 pitch 5120 (/4 1280) >[142305.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142305.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142305.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff0b80] >[142305.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff0b80] width 1280 pitch 5120 (/4 1280) >[142305.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff0b80] >[142305.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff0b80] width 1280 pitch 5120 (/4 1280) >[142305.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cadf0] >[142305.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cadf0] width 1280 pitch 5120 (/4 1280) >[142306.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff0b80] >[142306.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff0b80] width 1280 pitch 5120 (/4 1280) >[142306.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142306.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142306.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ddb60] >[142306.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ddb60] width 1280 pitch 5120 (/4 1280) >[142325.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142325.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142325.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ddb60] >[142325.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ddb60] width 1280 pitch 5120 (/4 1280) >[142325.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142325.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142325.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28431e0] >[142325.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28431e0] width 1280 pitch 5120 (/4 1280) >[142345.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f82d10] >[142345.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f82d10] width 1280 pitch 5120 (/4 1280) >[142345.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff0b80] >[142345.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff0b80] width 1280 pitch 5120 (/4 1280) >[142345.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6e90] >[142345.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6e90] width 1280 pitch 5120 (/4 1280) >[142345.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff0b80] >[142345.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff0b80] width 1280 pitch 5120 (/4 1280) >[142345.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f82d10] >[142345.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f82d10] width 1280 pitch 5120 (/4 1280) >[142346.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f82d10] >[142346.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f82d10] width 1280 pitch 5120 (/4 1280) >[142346.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af7510] >[142346.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af7510] width 1280 pitch 5120 (/4 1280) >[142346.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142346.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142350.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142350.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142350.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142350.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142350.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cb4c0] >[142350.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cb4c0] width 1280 pitch 5120 (/4 1280) >[142350.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2843640] >[142350.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2843640] width 1280 pitch 5120 (/4 1280) >[142350.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cb4c0] >[142350.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cb4c0] width 1280 pitch 5120 (/4 1280) >[142350.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2843640] >[142350.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2843640] width 1280 pitch 5120 (/4 1280) >[142350.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f12c0] >[142350.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f12c0] width 1280 pitch 5120 (/4 1280) >[142350.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2843640] >[142350.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2843640] width 1280 pitch 5120 (/4 1280) >[142385.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142385.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142386.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ddb60] >[142386.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ddb60] width 1280 pitch 5120 (/4 1280) >[142386.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142386.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142386.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142386.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142386.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25610e0] >[142386.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25610e0] width 1280 pitch 5120 (/4 1280) >[142387.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b250] >[142387.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b250] width 1280 pitch 5120 (/4 1280) >[142406.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142406.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142406.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142406.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142406.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142407.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142407.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142407.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142433.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b1f0] >[142433.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b1f0] width 1280 pitch 5120 (/4 1280) >[142435.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x299a860] >[142435.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x299a860] width 1280 pitch 5120 (/4 1280) >[142435.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27ea1f0] >[142436.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27ea1f0] width 1280 pitch 5120 (/4 1280) >[142436.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c1f40] >[142436.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c1f40] width 1280 pitch 5120 (/4 1280) >[142436.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283e040] >[142436.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283e040] width 1280 pitch 5120 (/4 1280) >[142437.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb3e0] >[142437.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb3e0] width 1280 pitch 5120 (/4 1280) >[142437.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84e30] >[142437.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84e30] width 1280 pitch 5120 (/4 1280) >[142437.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[142437.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[142437.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84e30] >[142437.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84e30] width 1280 pitch 5120 (/4 1280) >[142502.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[142502.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[142502.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c9bf0] >[142502.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c9bf0] width 1280 pitch 5120 (/4 1280) >[142502.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142502.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142502.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142502.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142503.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142503.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142503.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142503.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142503.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d9a0] >[142503.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d9a0] width 1280 pitch 5120 (/4 1280) >[142503.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142503.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142504.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266f8b0] >[142504.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266f8b0] width 1280 pitch 5120 (/4 1280) >[142504.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294c0d0] >[142504.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294c0d0] width 1280 pitch 5120 (/4 1280) >[142516.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142516.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142516.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19686f0] >[142516.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19686f0] width 1280 pitch 5120 (/4 1280) >[142516.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb3d0] >[142516.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb3d0] width 1280 pitch 5120 (/4 1280) >[142516.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266f8b0] >[142516.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266f8b0] width 1280 pitch 5120 (/4 1280) >[142516.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1968920] >[142516.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1968920] width 1280 pitch 5120 (/4 1280) >[142517.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d370] >[142517.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d370] width 1280 pitch 5120 (/4 1280) >[142517.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1170] >[142517.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1170] width 1280 pitch 5120 (/4 1280) >[142517.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a1d370] >[142517.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a1d370] width 1280 pitch 5120 (/4 1280) >[142526.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[142526.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[142526.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[142526.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[142526.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142526.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142526.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142526.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142526.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142526.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142526.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x299a860] >[142526.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x299a860] width 1280 pitch 5120 (/4 1280) >[142526.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142526.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142526.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1968630] >[142526.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1968630] width 1280 pitch 5120 (/4 1280) >[142529.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2898300] >[142529.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2898300] width 1280 pitch 5120 (/4 1280) >[142529.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[142529.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[142529.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142529.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142529.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142529.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142529.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586480] >[142529.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586480] width 1280 pitch 5120 (/4 1280) >[142529.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[142529.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[142529.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142530.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142530.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142530.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142538.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af75b0] >[142538.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af75b0] width 1280 pitch 5120 (/4 1280) >[142538.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[142538.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[142538.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ff130] >[142538.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ff130] width 1280 pitch 5120 (/4 1280) >[142538.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ff130] >[142538.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ff130] width 1280 pitch 5120 (/4 1280) >[142539.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1968630] >[142539.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1968630] width 1280 pitch 5120 (/4 1280) >[142539.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ff130] >[142539.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ff130] width 1280 pitch 5120 (/4 1280) >[142539.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5c60] >[142539.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5c60] width 1280 pitch 5120 (/4 1280) >[142539.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[142539.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[142540.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142540.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142540.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142540.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142540.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5c60] >[142540.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5c60] width 1280 pitch 5120 (/4 1280) >[142540.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142540.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142546.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142546.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142546.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142546.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142546.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444b80] >[142546.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444b80] width 1280 pitch 5120 (/4 1280) >[142546.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19602c0] >[142546.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19602c0] width 1280 pitch 5120 (/4 1280) >[142546.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257ce70] >[142546.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257ce70] width 1280 pitch 5120 (/4 1280) >[142546.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142546.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142546.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142546.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142547.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142547.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142547.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142547.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142547.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa6f20] >[142547.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa6f20] width 1280 pitch 5120 (/4 1280) >[142547.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af75b0] >[142547.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af75b0] width 1280 pitch 5120 (/4 1280) >[142547.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f110] >[142547.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f110] width 1280 pitch 5120 (/4 1280) >[142547.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d7ee0] >[142547.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d7ee0] width 1280 pitch 5120 (/4 1280) >[142548.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142548.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142548.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142548.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142548.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f110] >[142548.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f110] width 1280 pitch 5120 (/4 1280) >[142556.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142556.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142556.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84a00] >[142556.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84a00] width 1280 pitch 5120 (/4 1280) >[142556.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279a7c0] >[142556.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279a7c0] width 1280 pitch 5120 (/4 1280) >[142556.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142556.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142556.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x205f110] >[142556.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x205f110] width 1280 pitch 5120 (/4 1280) >[142556.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142556.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142556.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c380] >[142556.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c380] width 1280 pitch 5120 (/4 1280) >[142556.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142556.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142606.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b3b40] >[142606.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b3b40] width 1280 pitch 5120 (/4 1280) >[142606.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28bfdd0] >[142606.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28bfdd0] width 1280 pitch 5120 (/4 1280) >[142606.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ac9500] >[142606.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ac9500] width 1280 pitch 5120 (/4 1280) >[142606.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142606.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142607.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142607.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142607.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142608.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142608.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142608.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142608.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142608.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142608.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142608.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142608.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838d70] >[142608.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838d70] width 1280 pitch 5120 (/4 1280) >[142608.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d10d0] >[142608.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d10d0] width 1280 pitch 5120 (/4 1280) >[142608.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30893f0] >[142608.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30893f0] width 1280 pitch 5120 (/4 1280) >[142608.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142608.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142608.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142608.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142608.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142608.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142608.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142608.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142608.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142608.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142608.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279c320] >[142608.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279c320] width 1280 pitch 5120 (/4 1280) >[142608.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[142608.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[142608.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142608.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142608.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142608.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142608.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142608.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142608.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a6210] >[142609.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a6210] width 1280 pitch 5120 (/4 1280) >[142609.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[142609.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[142613.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fb460] >[142613.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fb460] width 1280 pitch 5120 (/4 1280) >[142614.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142614.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142614.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142614.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142614.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142614.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142614.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142614.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142614.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142614.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142614.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142614.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142614.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142614.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142615.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142615.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142615.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142615.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142615.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142615.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142615.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142615.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142615.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142615.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142615.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142615.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142615.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142615.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142616.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142616.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142616.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142616.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142616.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142616.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x277ff30] >[142616.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x277ff30] width 1280 pitch 5120 (/4 1280) >[142616.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142616.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142616.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142616.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142616.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142616.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142616.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142616.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142616.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142616.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142616.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142616.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142616.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142616.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142618.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142618.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142618.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142618.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142618.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142618.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142618.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142618.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142618.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142618.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142619.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142619.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142619.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142619.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142620.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142620.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142620.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142620.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142620.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142620.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142620.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142620.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142620.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142620.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142620.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2783d10] >[142620.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2783d10] width 1280 pitch 5120 (/4 1280) >[142620.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142620.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142620.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aca410] >[142620.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aca410] width 1280 pitch 5120 (/4 1280) >[142620.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142620.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142620.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aca410] >[142620.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aca410] width 1280 pitch 5120 (/4 1280) >[142774.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799770] >[142774.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799770] width 1280 pitch 5120 (/4 1280) >[142774.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x193c9d0] >[142774.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x193c9d0] width 1280 pitch 5120 (/4 1280) >[142774.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x193c9d0] >[142774.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x193c9d0] width 1280 pitch 5120 (/4 1280) >[142774.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f880] >[142774.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f880] width 1280 pitch 5120 (/4 1280) >[142774.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266f850] >[142774.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266f850] width 1280 pitch 5120 (/4 1280) >[142774.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142774.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142774.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142774.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142774.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142774.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142774.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feccf0] >[142774.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feccf0] width 1280 pitch 5120 (/4 1280) >[142774.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2799770] >[142774.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2799770] width 1280 pitch 5120 (/4 1280) >[142775.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x193c9d0] >[142775.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x193c9d0] width 1280 pitch 5120 (/4 1280) >[142775.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f880] >[142775.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f880] width 1280 pitch 5120 (/4 1280) >[142775.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266f850] >[142775.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266f850] width 1280 pitch 5120 (/4 1280) >[142775.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142775.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142775.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ed40] >[142775.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ed40] width 1280 pitch 5120 (/4 1280) >[142775.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f880] >[142775.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f880] width 1280 pitch 5120 (/4 1280) >[142847.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142847.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142847.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28cba10] >[142847.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28cba10] width 1280 pitch 5120 (/4 1280) >[142882.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x279b360] >[142882.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x279b360] width 1280 pitch 5120 (/4 1280) >[142882.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c9d160] >[142882.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c9d160] width 1280 pitch 5120 (/4 1280) >[142963.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c3990] >[142963.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c3990] width 1280 pitch 5120 (/4 1280) >[142993.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[142993.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[142993.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecf60] >[142993.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecf60] width 1280 pitch 5120 (/4 1280) >[143017.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5fa0] >[143017.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5fa0] width 1280 pitch 5120 (/4 1280) >[143017.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x208cb50] >[143017.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x208cb50] width 1280 pitch 5120 (/4 1280) >[143021.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[143021.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[143022.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[143022.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[143022.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143022.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143022.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9db00] >[143022.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9db00] width 1280 pitch 5120 (/4 1280) >[143022.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226f00] >[143022.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226f00] width 1280 pitch 5120 (/4 1280) >[143023.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[143023.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[143024.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[143024.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[143024.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c3600] >[143024.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c3600] width 1280 pitch 5120 (/4 1280) >[143024.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[143024.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[143024.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c3600] >[143024.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c3600] width 1280 pitch 5120 (/4 1280) >[143025.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[143025.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[143026.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143026.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143026.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c3600] >[143026.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c3600] width 1280 pitch 5120 (/4 1280) >[143026.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32195e0] >[143026.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32195e0] width 1280 pitch 5120 (/4 1280) >[143026.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27299f0] >[143026.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27299f0] width 1280 pitch 5120 (/4 1280) >[143027.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143027.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143034.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143034.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143034.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143034.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143034.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143034.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143034.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143034.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143034.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143034.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143034.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[143034.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[143035.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0a6b0] >[143035.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0a6b0] width 1280 pitch 5120 (/4 1280) >[143035.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143035.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143035.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143035.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143036.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143036.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143036.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143036.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143036.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143036.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143036.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143036.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143036.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143036.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143036.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143036.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143036.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143037.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143037.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143037.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143037.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143037.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143037.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143037.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143037.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143037.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143037.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143037.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143038.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143038.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143038.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143038.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143038.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143038.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143038.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143038.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581680] >[143038.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581680] width 1280 pitch 5120 (/4 1280) >[143038.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ad580] >[143038.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ad580] width 1280 pitch 5120 (/4 1280) >[143038.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ab2f0] >[143038.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ab2f0] width 1280 pitch 5120 (/4 1280) >[143038.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[143038.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[143038.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[143038.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[143038.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[143038.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[143038.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1e90] >[143038.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1e90] width 1280 pitch 5120 (/4 1280) >[143038.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[143038.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[143038.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ad580] >[143038.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ad580] width 1280 pitch 5120 (/4 1280) >[143038.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ab2f0] >[143038.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ab2f0] width 1280 pitch 5120 (/4 1280) >[143038.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e9e80] >[143038.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e9e80] width 1280 pitch 5120 (/4 1280) >[143038.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffb00] >[143038.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffb00] width 1280 pitch 5120 (/4 1280) >[143648.000] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[143648.000] (II) RADEON(0): Printing DDC gathered Modelines: >[143648.000] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[143737.929] (II) RADEON(0): RADEONSaveScreen(2) >[143737.933] (II) RADEON(0): RADEONSaveScreen(0) >[144543.400] (II) RADEON(0): RADEONSaveScreen(1) >[144548.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144548.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144549.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144549.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144549.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144549.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144550.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257c8e0] >[144550.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257c8e0] width 1280 pitch 5120 (/4 1280) >[144550.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144550.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144550.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144550.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144550.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144550.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144550.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144550.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144550.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144550.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144550.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144550.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144550.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144550.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144550.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144550.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144551.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144551.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144551.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838930] >[144551.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838930] width 1280 pitch 5120 (/4 1280) >[144551.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838930] >[144551.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838930] width 1280 pitch 5120 (/4 1280) >[144551.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144551.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144551.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838930] >[144551.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838930] width 1280 pitch 5120 (/4 1280) >[144551.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144551.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144553.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144553.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144553.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144553.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144553.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144555.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbf50] >[144555.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbf50] width 1280 pitch 5120 (/4 1280) >[144555.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144555.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144555.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144555.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144555.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbf50] >[144555.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbf50] width 1280 pitch 5120 (/4 1280) >[144555.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144555.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144555.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144555.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144555.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f400] >[144555.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f400] width 1280 pitch 5120 (/4 1280) >[144555.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144555.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144555.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144555.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144555.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144555.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144555.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144555.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144555.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cbf50] >[144555.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cbf50] width 1280 pitch 5120 (/4 1280) >[144555.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144555.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144555.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c1c0] >[144555.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c1c0] width 1280 pitch 5120 (/4 1280) >[144555.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f400] >[144555.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f400] width 1280 pitch 5120 (/4 1280) >[144555.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x288fc60] >[144555.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x288fc60] width 1280 pitch 5120 (/4 1280) >[144555.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144555.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5690] >[144555.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5690] width 1280 pitch 5120 (/4 1280) >[144555.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2838930] >[144555.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2838930] width 1280 pitch 5120 (/4 1280) >[144555.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257c8e0] >[144555.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257c8e0] width 1280 pitch 5120 (/4 1280) >[144555.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f400] >[144555.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f400] width 1280 pitch 5120 (/4 1280) >[144555.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144555.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144559.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270bae0] >[144559.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270bae0] width 1280 pitch 5120 (/4 1280) >[144559.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2780da0] >[144559.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2780da0] width 1280 pitch 5120 (/4 1280) >[144559.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200b50] >[144559.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200b50] width 1280 pitch 5120 (/4 1280) >[144559.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257c8e0] >[144559.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257c8e0] width 1280 pitch 5120 (/4 1280) >[144559.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8f8d0] >[144559.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8f8d0] width 1280 pitch 5120 (/4 1280) >[144559.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586960] >[144559.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586960] width 1280 pitch 5120 (/4 1280) >[144559.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2717650] >[144559.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2717650] width 1280 pitch 5120 (/4 1280) >[144559.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7900] >[144559.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7900] width 1280 pitch 5120 (/4 1280) >[144559.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fc7a0] >[144559.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fc7a0] width 1280 pitch 5120 (/4 1280) >[144559.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27648f0] >[144559.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27648f0] width 1280 pitch 5120 (/4 1280) >[144559.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7900] >[144559.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7900] width 1280 pitch 5120 (/4 1280) >[144559.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27648f0] >[144559.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27648f0] width 1280 pitch 5120 (/4 1280) >[144559.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276c740] >[144559.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276c740] width 1280 pitch 5120 (/4 1280) >[144559.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7900] >[144559.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7900] width 1280 pitch 5120 (/4 1280) >[144560.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2717650] >[144560.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2717650] width 1280 pitch 5120 (/4 1280) >[144560.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586960] >[144560.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586960] width 1280 pitch 5120 (/4 1280) >[144560.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x243f0b0] >[144560.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x243f0b0] width 1280 pitch 5120 (/4 1280) >[144560.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20396c0] >[144560.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20396c0] width 1280 pitch 5120 (/4 1280) >[144560.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586960] >[144560.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586960] width 1280 pitch 5120 (/4 1280) >[144560.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276c740] >[144560.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276c740] width 1280 pitch 5120 (/4 1280) >[144560.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f91230] >[144560.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f91230] width 1280 pitch 5120 (/4 1280) >[144560.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x243f0b0] >[144560.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x243f0b0] width 1280 pitch 5120 (/4 1280) >[144560.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f91230] >[144560.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f91230] width 1280 pitch 5120 (/4 1280) >[144560.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x243f0b0] >[144560.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x243f0b0] width 1280 pitch 5120 (/4 1280) >[144560.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f91230] >[144560.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f91230] width 1280 pitch 5120 (/4 1280) >[144560.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276c740] >[144560.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276c740] width 1280 pitch 5120 (/4 1280) >[144560.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2717650] >[144560.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2717650] width 1280 pitch 5120 (/4 1280) >[144561.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ba00] >[144561.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ba00] width 1280 pitch 5120 (/4 1280) >[144561.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e81d0] >[144561.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e81d0] width 1280 pitch 5120 (/4 1280) >[144561.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f790] >[144561.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f790] width 1280 pitch 5120 (/4 1280) >[144562.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ccd0] >[144562.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ccd0] width 1280 pitch 5120 (/4 1280) >[144562.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3cd30] >[144562.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3cd30] width 1280 pitch 5120 (/4 1280) >[144562.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ccd0] >[144562.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ccd0] width 1280 pitch 5120 (/4 1280) >[144562.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3cd30] >[144562.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3cd30] width 1280 pitch 5120 (/4 1280) >[144562.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ccd0] >[144562.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ccd0] width 1280 pitch 5120 (/4 1280) >[144562.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3cd30] >[144562.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3cd30] width 1280 pitch 5120 (/4 1280) >[144562.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3ccd0] >[144562.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3ccd0] width 1280 pitch 5120 (/4 1280) >[144562.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3cd30] >[144562.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3cd30] width 1280 pitch 5120 (/4 1280) >[144562.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f790] >[144562.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f790] width 1280 pitch 5120 (/4 1280) >[144562.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c28d70] >[144562.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c28d70] width 1280 pitch 5120 (/4 1280) >[144562.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffe4a0] >[144562.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffe4a0] width 1280 pitch 5120 (/4 1280) >[144562.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f790] >[144562.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f790] width 1280 pitch 5120 (/4 1280) >[144562.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2661f40] >[144562.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2661f40] width 1280 pitch 5120 (/4 1280) >[144562.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144562.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144562.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31e81d0] >[144562.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31e81d0] width 1280 pitch 5120 (/4 1280) >[144568.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fce50] >[144568.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fce50] width 1280 pitch 5120 (/4 1280) >[144681.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2744f90] >[144681.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2744f90] width 1280 pitch 5120 (/4 1280) >[144687.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2744f90] >[144687.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2744f90] width 1280 pitch 5120 (/4 1280) >[144688.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0f9e0] >[144688.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0f9e0] width 1280 pitch 5120 (/4 1280) >[144691.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719b30] >[144691.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719b30] width 1280 pitch 5120 (/4 1280) >[144696.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b4620] >[144696.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b4620] width 1280 pitch 5120 (/4 1280) >[144696.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b4620] >[144696.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b4620] width 1280 pitch 5120 (/4 1280) >[144737.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726a10] >[144737.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726a10] width 1280 pitch 5120 (/4 1280) >[144737.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028620] >[144737.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028620] width 1280 pitch 5120 (/4 1280) >[144737.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726a10] >[144737.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726a10] width 1280 pitch 5120 (/4 1280) >[144737.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154190] >[144737.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154190] width 1280 pitch 5120 (/4 1280) >[144738.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154190] >[144738.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154190] width 1280 pitch 5120 (/4 1280) >[144738.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x194d480] >[144738.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x194d480] width 1280 pitch 5120 (/4 1280) >[144738.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b97020] >[144738.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b97020] width 1280 pitch 5120 (/4 1280) >[144738.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f11f0] >[144738.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f11f0] width 1280 pitch 5120 (/4 1280) >[144743.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b3ae0] >[144743.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b3ae0] width 1280 pitch 5120 (/4 1280) >[144743.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089230] >[144743.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089230] width 1280 pitch 5120 (/4 1280) >[144743.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b3ae0] >[144743.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b3ae0] width 1280 pitch 5120 (/4 1280) >[144743.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726a10] >[144743.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726a10] width 1280 pitch 5120 (/4 1280) >[144744.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2024310] >[144744.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2024310] width 1280 pitch 5120 (/4 1280) >[144744.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24421d0] >[144744.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24421d0] width 1280 pitch 5120 (/4 1280) >[144744.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028620] >[144744.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028620] width 1280 pitch 5120 (/4 1280) >[144744.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24421d0] >[144744.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24421d0] width 1280 pitch 5120 (/4 1280) >[144744.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2726a10] >[144744.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2726a10] width 1280 pitch 5120 (/4 1280) >[144745.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb270] >[144745.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb270] width 1280 pitch 5120 (/4 1280) >[145367.424] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[145367.424] (II) RADEON(0): Printing DDC gathered Modelines: >[145367.424] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[145457.892] (II) RADEON(0): RADEONSaveScreen(2) >[145457.892] (II) RADEON(0): RADEONSaveScreen(0) >[145633.125] (II) RADEON(0): RADEONSaveScreen(1) >[145639.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145639.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145653.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145653.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145653.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145653.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145653.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145653.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145653.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145653.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145653.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145653.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145653.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145653.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145653.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145653.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145654.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145654.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145654.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145654.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145654.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145654.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145654.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145654.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145654.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145654.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145654.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145654.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145654.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145654.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145654.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145654.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4d1a0] >[145654.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4d1a0] width 1280 pitch 5120 (/4 1280) >[145654.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa02f0] >[145654.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa02f0] width 1280 pitch 5120 (/4 1280) >[145801.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2994b00] >[145801.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2994b00] width 1280 pitch 5120 (/4 1280) >[145801.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fff20] >[145801.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fff20] width 1280 pitch 5120 (/4 1280) >[145928.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824870] >[145928.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824870] width 1280 pitch 5120 (/4 1280) >[145982.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2582220] >[145982.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2582220] width 1280 pitch 5120 (/4 1280) >[145982.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x148e1a0] >[145982.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x148e1a0] width 1280 pitch 5120 (/4 1280) >[146158.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2798a60] >[146158.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2798a60] width 1280 pitch 5120 (/4 1280) >[146158.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2798a60] >[146158.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2798a60] width 1280 pitch 5120 (/4 1280) >[146222.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146222.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146222.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146222.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146222.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146223.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146223.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146223.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146223.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146224.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146224.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146224.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e56d50] >[146224.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e56d50] width 1280 pitch 5120 (/4 1280) >[146225.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146225.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146225.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294ae20] >[146225.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294ae20] width 1280 pitch 5120 (/4 1280) >[146225.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2023190] >[146225.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2023190] width 1280 pitch 5120 (/4 1280) >[146225.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c72f0] >[146225.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c72f0] width 1280 pitch 5120 (/4 1280) >[146225.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294adb0] >[146225.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294adb0] width 1280 pitch 5120 (/4 1280) >[146225.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a650] >[146225.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a650] width 1280 pitch 5120 (/4 1280) >[146225.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294ae20] >[146225.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294ae20] width 1280 pitch 5120 (/4 1280) >[146225.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258dd50] >[146225.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258dd50] width 1280 pitch 5120 (/4 1280) >[146225.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294ae20] >[146225.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294ae20] width 1280 pitch 5120 (/4 1280) >[146225.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2023190] >[146225.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2023190] width 1280 pitch 5120 (/4 1280) >[146225.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cba30] >[146225.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cba30] width 1280 pitch 5120 (/4 1280) >[146232.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258dd30] >[146232.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258dd30] width 1280 pitch 5120 (/4 1280) >[146232.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271e3d0] >[146232.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271e3d0] width 1280 pitch 5120 (/4 1280) >[146242.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2575ed0] >[146242.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2575ed0] width 1280 pitch 5120 (/4 1280) >[146242.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2841ed0] >[146242.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2841ed0] width 1280 pitch 5120 (/4 1280) >[146243.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2576740] >[146243.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2576740] width 1280 pitch 5120 (/4 1280) >[146243.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2841ed0] >[146243.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2841ed0] width 1280 pitch 5120 (/4 1280) >[146243.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2576740] >[146243.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2576740] width 1280 pitch 5120 (/4 1280) >[146243.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2841ed0] >[146243.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2841ed0] width 1280 pitch 5120 (/4 1280) >[146243.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2576740] >[146243.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2576740] width 1280 pitch 5120 (/4 1280) >[146243.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2841ed0] >[146243.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2841ed0] width 1280 pitch 5120 (/4 1280) >[146243.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2576740] >[146243.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2576740] width 1280 pitch 5120 (/4 1280) >[146243.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2841ed0] >[146243.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2841ed0] width 1280 pitch 5120 (/4 1280) >[146243.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2576740] >[146243.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2576740] width 1280 pitch 5120 (/4 1280) >[146250.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1f0] >[146250.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1f0] width 1280 pitch 5120 (/4 1280) >[146250.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25781d0] >[146250.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25781d0] width 1280 pitch 5120 (/4 1280) >[146250.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d835c0] >[146250.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d835c0] width 1280 pitch 5120 (/4 1280) >[146250.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1f0] >[146250.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1f0] width 1280 pitch 5120 (/4 1280) >[146250.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d835c0] >[146250.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d835c0] width 1280 pitch 5120 (/4 1280) >[146250.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1f0] >[146250.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1f0] width 1280 pitch 5120 (/4 1280) >[146250.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d835c0] >[146250.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d835c0] width 1280 pitch 5120 (/4 1280) >[146250.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1f0] >[146250.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1f0] width 1280 pitch 5120 (/4 1280) >[146250.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d835c0] >[146250.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d835c0] width 1280 pitch 5120 (/4 1280) >[146251.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27809d0] >[146251.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27809d0] width 1280 pitch 5120 (/4 1280) >[146252.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb490] >[146252.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb490] width 1280 pitch 5120 (/4 1280) >[146255.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281fe60] >[146255.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281fe60] width 1280 pitch 5120 (/4 1280) >[146255.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281fe60] >[146255.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281fe60] width 1280 pitch 5120 (/4 1280) >[146256.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb590] >[146256.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb590] width 1280 pitch 5120 (/4 1280) >[146256.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb6f0] >[146256.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb6f0] width 1280 pitch 5120 (/4 1280) >[146256.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb590] >[146256.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb590] width 1280 pitch 5120 (/4 1280) >[146256.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb6f0] >[146256.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb6f0] width 1280 pitch 5120 (/4 1280) >[146256.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb590] >[146256.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb590] width 1280 pitch 5120 (/4 1280) >[146256.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1c0] >[146256.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1c0] width 1280 pitch 5120 (/4 1280) >[146256.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278cf70] >[146256.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278cf70] width 1280 pitch 5120 (/4 1280) >[146256.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb6f0] >[146256.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb6f0] width 1280 pitch 5120 (/4 1280) >[146256.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1c0] >[146256.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1c0] width 1280 pitch 5120 (/4 1280) >[146256.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281fe60] >[146256.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281fe60] width 1280 pitch 5120 (/4 1280) >[146256.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146256.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146257.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278b660] >[146257.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278b660] width 1280 pitch 5120 (/4 1280) >[146257.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cb6f0] >[146257.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cb6f0] width 1280 pitch 5120 (/4 1280) >[146257.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146257.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146257.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278b660] >[146257.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278b660] width 1280 pitch 5120 (/4 1280) >[146257.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146257.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146257.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278b660] >[146257.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278b660] width 1280 pitch 5120 (/4 1280) >[146257.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146257.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146257.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146257.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146257.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278b660] >[146257.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278b660] width 1280 pitch 5120 (/4 1280) >[146257.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146257.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146257.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967710] >[146258.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967710] width 1280 pitch 5120 (/4 1280) >[146258.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146258.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146258.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146258.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146258.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146258.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146258.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146258.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146258.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146258.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146259.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146259.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146262.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146262.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146262.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146262.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146263.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146263.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146263.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146263.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146263.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146263.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146263.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146263.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146263.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146263.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146263.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146263.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146263.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146263.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146263.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146263.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146263.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146263.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146264.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146264.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146264.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146264.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146264.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146264.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146264.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146264.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146264.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146264.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146264.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146264.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146264.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146264.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146264.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1af6af0] >[146264.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1af6af0] width 1280 pitch 5120 (/4 1280) >[146264.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2787580] >[146264.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2787580] width 1280 pitch 5120 (/4 1280) >[146266.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19678b0] >[146266.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19678b0] width 1280 pitch 5120 (/4 1280) >[146266.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2560f10] >[146266.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2560f10] width 1280 pitch 5120 (/4 1280) >[146269.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cacb0] >[146269.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cacb0] width 1280 pitch 5120 (/4 1280) >[146269.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146269.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146269.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967970] >[146269.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967970] width 1280 pitch 5120 (/4 1280) >[146269.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cacb0] >[146269.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cacb0] width 1280 pitch 5120 (/4 1280) >[146269.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967970] >[146269.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967970] width 1280 pitch 5120 (/4 1280) >[146269.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cacb0] >[146269.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cacb0] width 1280 pitch 5120 (/4 1280) >[146269.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146269.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146269.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967070] >[146269.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967070] width 1280 pitch 5120 (/4 1280) >[146269.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cacb0] >[146269.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cacb0] width 1280 pitch 5120 (/4 1280) >[146269.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146269.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146271.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146271.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146271.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cacb0] >[146271.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cacb0] width 1280 pitch 5120 (/4 1280) >[146271.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2560410] >[146271.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2560410] width 1280 pitch 5120 (/4 1280) >[146271.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146271.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146271.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967970] >[146271.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967970] width 1280 pitch 5120 (/4 1280) >[146271.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2560410] >[146271.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2560410] width 1280 pitch 5120 (/4 1280) >[146271.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2908fa0] >[146271.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2908fa0] width 1280 pitch 5120 (/4 1280) >[146271.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146271.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146271.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2560410] >[146271.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2560410] width 1280 pitch 5120 (/4 1280) >[146271.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26689b0] >[146271.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26689b0] width 1280 pitch 5120 (/4 1280) >[146277.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d1c0] >[146277.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d1c0] width 1280 pitch 5120 (/4 1280) >[146277.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1967840] >[146277.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1967840] width 1280 pitch 5120 (/4 1280) >[146468.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816dc0] >[146468.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816dc0] width 1280 pitch 5120 (/4 1280) >[146468.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816dc0] >[146468.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816dc0] width 1280 pitch 5120 (/4 1280) >[146568.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294abe0] >[146568.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294abe0] width 1280 pitch 5120 (/4 1280) >[146568.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d1290] >[146568.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d1290] width 1280 pitch 5120 (/4 1280) >[146612.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2814e30] >[146612.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2814e30] width 1280 pitch 5120 (/4 1280) >[146612.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28150b0] >[146612.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28150b0] width 1280 pitch 5120 (/4 1280) >[146642.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29454f0] >[146642.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29454f0] width 1280 pitch 5120 (/4 1280) >[146643.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272c110] >[146643.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272c110] width 1280 pitch 5120 (/4 1280) >[146688.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29459c0] >[146688.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29459c0] width 1280 pitch 5120 (/4 1280) >[146688.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2944530] >[146688.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2944530] width 1280 pitch 5120 (/4 1280) >[146757.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29483e0] >[146757.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29483e0] width 1280 pitch 5120 (/4 1280) >[147126.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810af0] >[147126.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810af0] width 1280 pitch 5120 (/4 1280) >[147126.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29403a0] >[147126.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29403a0] width 1280 pitch 5120 (/4 1280) >[147299.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028540] >[147299.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028540] width 1280 pitch 5120 (/4 1280) >[147299.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x295a310] >[147299.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x295a310] width 1280 pitch 5120 (/4 1280) >[147560.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ac7380] >[147560.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ac7380] width 1280 pitch 5120 (/4 1280) >[147560.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ac7380] >[147560.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ac7380] width 1280 pitch 5120 (/4 1280) >[147961.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b38c0] >[147961.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b38c0] width 1280 pitch 5120 (/4 1280) >[147961.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29688d0] >[147961.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29688d0] width 1280 pitch 5120 (/4 1280) >[148278.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ac47b0] >[148278.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ac47b0] width 1280 pitch 5120 (/4 1280) >[148278.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1449120] >[148278.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1449120] width 1280 pitch 5120 (/4 1280) >[150063.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2876cd0] >[150063.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2876cd0] width 1280 pitch 5120 (/4 1280) >[150063.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28fac40] >[150063.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28fac40] width 1280 pitch 5120 (/4 1280) >[150065.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27dfff0] >[150065.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27dfff0] width 1280 pitch 5120 (/4 1280) >[150065.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2876380] >[150065.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2876380] width 1280 pitch 5120 (/4 1280) >[150080.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297ecc0] >[150081.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297ecc0] width 1280 pitch 5120 (/4 1280) >[150081.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2876cd0] >[150081.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2876cd0] width 1280 pitch 5120 (/4 1280) >[150082.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297ecc0] >[150082.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297ecc0] width 1280 pitch 5120 (/4 1280) >[150083.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b2d70] >[150083.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b2d70] width 1280 pitch 5120 (/4 1280) >[150127.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ac1340] >[150127.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ac1340] width 1280 pitch 5120 (/4 1280) >[150127.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2973ed0] >[150127.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2973ed0] width 1280 pitch 5120 (/4 1280) >[150327.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2979e00] >[150327.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2979e00] width 1280 pitch 5120 (/4 1280) >[150328.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2979f30] >[150328.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2979f30] width 1280 pitch 5120 (/4 1280) >[150513.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150513.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150513.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150513.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977330] >[150513.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977330] width 1280 pitch 5120 (/4 1280) >[150514.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d5e10] >[150514.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d5e10] width 1280 pitch 5120 (/4 1280) >[150514.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297f030] >[150514.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297f030] width 1280 pitch 5120 (/4 1280) >[150514.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d7f20] >[150514.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d7f20] width 1280 pitch 5120 (/4 1280) >[150514.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x296df50] >[150514.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x296df50] width 1280 pitch 5120 (/4 1280) >[150514.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2979eb0] >[150514.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2979eb0] width 1280 pitch 5120 (/4 1280) >[150514.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2973d30] >[150514.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2973d30] width 1280 pitch 5120 (/4 1280) >[150514.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2973d30] >[150514.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2973d30] width 1280 pitch 5120 (/4 1280) >[150514.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150514.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150514.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150514.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150514.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150514.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150514.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150514.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150514.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1341200] >[150514.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1341200] width 1280 pitch 5120 (/4 1280) >[150514.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d81e0] >[150514.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d81e0] width 1280 pitch 5120 (/4 1280) >[150514.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d5e10] >[150514.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d5e10] width 1280 pitch 5120 (/4 1280) >[150514.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d5e10] >[150514.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d5e10] width 1280 pitch 5120 (/4 1280) >[151356.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e2b10] >[151356.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e2b10] width 1280 pitch 5120 (/4 1280) >[151356.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e2b10] >[151356.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e2b10] width 1280 pitch 5120 (/4 1280) >[151403.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab4800] >[151403.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab4800] width 1280 pitch 5120 (/4 1280) >[151403.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951f60] >[151403.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951f60] width 1280 pitch 5120 (/4 1280) >[151978.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28d3950] >[151978.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28d3950] width 1280 pitch 5120 (/4 1280) >[151978.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab6090] >[151978.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab6090] width 1280 pitch 5120 (/4 1280) >[152261.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab7600] >[152261.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab7600] width 1280 pitch 5120 (/4 1280) >[152261.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab7600] >[152261.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab7600] width 1280 pitch 5120 (/4 1280) >[152466.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x143fc80] >[152466.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x143fc80] width 1280 pitch 5120 (/4 1280) >[152466.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2870500] >[152466.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2870500] width 1280 pitch 5120 (/4 1280) >[152467.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ea8c0] >[152467.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ea8c0] width 1280 pitch 5120 (/4 1280) >[152468.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x143fc80] >[152468.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x143fc80] width 1280 pitch 5120 (/4 1280) >[152469.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab7600] >[152469.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab7600] width 1280 pitch 5120 (/4 1280) >[152469.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x143fc80] >[152469.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x143fc80] width 1280 pitch 5120 (/4 1280) >[152469.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab7600] >[152469.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab7600] width 1280 pitch 5120 (/4 1280) >[152469.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ea8c0] >[152469.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ea8c0] width 1280 pitch 5120 (/4 1280) >[152469.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2870500] >[152469.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2870500] width 1280 pitch 5120 (/4 1280) >[152469.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e51c0] >[152469.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e51c0] width 1280 pitch 5120 (/4 1280) >[152469.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x143fc80] >[152469.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x143fc80] width 1280 pitch 5120 (/4 1280) >[152469.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e51c0] >[152469.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e51c0] width 1280 pitch 5120 (/4 1280) >[152469.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab55d0] >[152469.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab55d0] width 1280 pitch 5120 (/4 1280) >[152469.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ea8c0] >[152469.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ea8c0] width 1280 pitch 5120 (/4 1280) >[152469.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2870500] >[152469.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2870500] width 1280 pitch 5120 (/4 1280) >[152469.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ea8c0] >[152469.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ea8c0] width 1280 pitch 5120 (/4 1280) >[152469.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e51c0] >[152469.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e51c0] width 1280 pitch 5120 (/4 1280) >[152469.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x143fc80] >[152469.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x143fc80] width 1280 pitch 5120 (/4 1280) >[152470.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e51c0] >[152470.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e51c0] width 1280 pitch 5120 (/4 1280) >[152470.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab55d0] >[152470.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab55d0] width 1280 pitch 5120 (/4 1280) >[152470.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e51c0] >[152470.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e51c0] width 1280 pitch 5120 (/4 1280) >[152512.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab4210] >[152512.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab4210] width 1280 pitch 5120 (/4 1280) >[152512.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2709890] >[152512.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2709890] width 1280 pitch 5120 (/4 1280) >[153209.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2782040] >[153209.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2782040] width 1280 pitch 5120 (/4 1280) >[153209.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278e430] >[153209.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278e430] width 1280 pitch 5120 (/4 1280) >[153229.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2734930] >[153229.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2734930] width 1280 pitch 5120 (/4 1280) >[153229.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2734930] >[153229.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2734930] width 1280 pitch 5120 (/4 1280) >[153233.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a048e0] >[153233.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a048e0] width 1280 pitch 5120 (/4 1280) >[153233.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x296a4a0] >[153233.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x296a4a0] width 1280 pitch 5120 (/4 1280) >[153436.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d671b0] >[153436.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d671b0] width 1280 pitch 5120 (/4 1280) >[153436.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2886350] >[153436.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2886350] width 1280 pitch 5120 (/4 1280) >[153527.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab6a90] >[153527.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab6a90] width 1280 pitch 5120 (/4 1280) >[153528.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d65b20] >[153528.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d65b20] width 1280 pitch 5120 (/4 1280) >[153528.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28863f0] >[153528.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28863f0] width 1280 pitch 5120 (/4 1280) >[153529.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272e1f0] >[153529.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272e1f0] width 1280 pitch 5120 (/4 1280) >[153697.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153697.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153698.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153698.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153698.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153698.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153701.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153701.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153701.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153701.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153701.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153701.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153701.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153701.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153701.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28889b0] >[153701.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28889b0] width 1280 pitch 5120 (/4 1280) >[153701.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de350] >[153701.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de350] width 1280 pitch 5120 (/4 1280) >[153701.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28de400] >[153701.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28de400] width 1280 pitch 5120 (/4 1280) >[153701.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153701.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2739df0] >[153701.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2739df0] width 1280 pitch 5120 (/4 1280) >[153701.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d270] >[153701.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d270] width 1280 pitch 5120 (/4 1280) >[153809.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270afb0] >[153809.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270afb0] width 1280 pitch 5120 (/4 1280) >[153809.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a05940] >[153809.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a05940] width 1280 pitch 5120 (/4 1280) >[153835.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28867a0] >[153835.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28867a0] width 1280 pitch 5120 (/4 1280) >[153886.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b930] >[153886.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b930] width 1280 pitch 5120 (/4 1280) >[153886.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b930] >[153886.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b930] width 1280 pitch 5120 (/4 1280) >[153913.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d6a0] >[153913.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d6a0] width 1280 pitch 5120 (/4 1280) >[153913.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270fde0] >[153913.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270fde0] width 1280 pitch 5120 (/4 1280) >[153922.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2720ef0] >[153922.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2720ef0] width 1280 pitch 5120 (/4 1280) >[153922.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28717c0] >[153922.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28717c0] width 1280 pitch 5120 (/4 1280) >[153947.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153947.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153964.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd450] >[153964.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd450] width 1280 pitch 5120 (/4 1280) >[153964.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153964.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153964.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153964.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153965.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153965.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153965.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153965.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153965.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153965.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153965.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153965.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153965.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153965.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153965.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153965.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153965.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153965.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153965.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153965.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153965.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153966.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153967.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153967.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153967.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153967.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153969.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153969.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153969.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153969.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153969.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153969.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153970.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153970.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153970.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914f90] >[153970.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914f90] width 1280 pitch 5120 (/4 1280) >[153970.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153970.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153970.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2578270] >[153970.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2578270] width 1280 pitch 5120 (/4 1280) >[153970.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153970.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153970.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2578270] >[153970.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2578270] width 1280 pitch 5120 (/4 1280) >[153970.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7f0] >[153970.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7f0] width 1280 pitch 5120 (/4 1280) >[153970.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2578270] >[153970.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2578270] width 1280 pitch 5120 (/4 1280) >[154002.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25868f0] >[154002.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25868f0] width 1280 pitch 5120 (/4 1280) >[154272.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25868f0] >[154272.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25868f0] width 1280 pitch 5120 (/4 1280) >[154272.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2977720] >[154272.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2977720] width 1280 pitch 5120 (/4 1280) >[154272.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2871990] >[154272.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2871990] width 1280 pitch 5120 (/4 1280) >[154272.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x299c480] >[154272.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x299c480] width 1280 pitch 5120 (/4 1280) >[154273.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2911b70] >[154274.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2911b70] width 1280 pitch 5120 (/4 1280) >[154274.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed9a0] >[154274.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed9a0] width 1280 pitch 5120 (/4 1280) >[154274.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fed9a0] >[154274.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fed9a0] width 1280 pitch 5120 (/4 1280) >[154274.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2911b70] >[154274.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2911b70] width 1280 pitch 5120 (/4 1280) >[154275.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[154275.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[154275.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2911b70] >[154275.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2911b70] width 1280 pitch 5120 (/4 1280) >[154275.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[154275.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[154275.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2911b70] >[154275.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2911b70] width 1280 pitch 5120 (/4 1280) >[154275.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2721640] >[154275.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2721640] width 1280 pitch 5120 (/4 1280) >[154276.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5b70] >[154276.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5b70] width 1280 pitch 5120 (/4 1280) >[154276.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[154276.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[154276.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2911b70] >[154276.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2911b70] width 1280 pitch 5120 (/4 1280) >[154276.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[154276.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[154276.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5b70] >[154276.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5b70] width 1280 pitch 5120 (/4 1280) >[154276.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2797ea0] >[154276.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2797ea0] width 1280 pitch 5120 (/4 1280) >[154505.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271bdd0] >[154505.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271bdd0] width 1280 pitch 5120 (/4 1280) >[154505.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271c170] >[154505.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271c170] width 1280 pitch 5120 (/4 1280) >[154505.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272ea70] >[154505.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272ea70] width 1280 pitch 5120 (/4 1280) >[154505.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25857c0] >[154505.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25857c0] width 1280 pitch 5120 (/4 1280) >[154508.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272ea70] >[154508.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272ea70] width 1280 pitch 5120 (/4 1280) >[154508.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ab25b0] >[154508.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ab25b0] width 1280 pitch 5120 (/4 1280) >[154528.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2715df0] >[154528.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2715df0] width 1280 pitch 5120 (/4 1280) >[154528.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x272d520] >[154528.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x272d520] width 1280 pitch 5120 (/4 1280) >[154752.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a1fe0] >[154752.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a1fe0] width 1280 pitch 5120 (/4 1280) >[154752.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2572910] >[154752.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2572910] width 1280 pitch 5120 (/4 1280) >[154766.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f8c80] >[154766.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f8c80] width 1280 pitch 5120 (/4 1280) >[154766.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f8780] >[154766.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f8780] width 1280 pitch 5120 (/4 1280) >[154793.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28066d0] >[154793.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28066d0] width 1280 pitch 5120 (/4 1280) >[154795.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28066d0] >[154795.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28066d0] width 1280 pitch 5120 (/4 1280) >[154981.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3084ca0] >[154981.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3084ca0] width 1280 pitch 5120 (/4 1280) >[154981.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3084ca0] >[154981.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3084ca0] width 1280 pitch 5120 (/4 1280) >[155085.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fff8c0] >[155085.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fff8c0] width 1280 pitch 5120 (/4 1280) >[155085.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28db280] >[155085.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28db280] width 1280 pitch 5120 (/4 1280) >[155085.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086080] >[155085.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086080] width 1280 pitch 5120 (/4 1280) >[155085.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086080] >[155085.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086080] width 1280 pitch 5120 (/4 1280) >[155085.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086080] >[155085.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086080] width 1280 pitch 5120 (/4 1280) >[155085.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086080] >[155085.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086080] width 1280 pitch 5120 (/4 1280) >[155085.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fff8c0] >[155085.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fff8c0] width 1280 pitch 5120 (/4 1280) >[155085.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155085.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155085.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155085.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155085.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155086.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155086.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155086.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155086.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155086.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155086.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155086.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155086.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155086.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155086.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155086.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155086.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f08a0] >[155086.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f08a0] width 1280 pitch 5120 (/4 1280) >[155086.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f0cf0] >[155086.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f0cf0] width 1280 pitch 5120 (/4 1280) >[155086.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fff8c0] >[155086.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fff8c0] width 1280 pitch 5120 (/4 1280) >[155086.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3083c40] >[155086.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3083c40] width 1280 pitch 5120 (/4 1280) >[155086.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086080] >[155086.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086080] width 1280 pitch 5120 (/4 1280) >[155131.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3000960] >[155131.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3000960] width 1280 pitch 5120 (/4 1280) >[155137.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x256df60] >[155137.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x256df60] width 1280 pitch 5120 (/4 1280) >[155145.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2912020] >[155145.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2912020] width 1280 pitch 5120 (/4 1280) >[155145.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2912020] >[155145.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2912020] width 1280 pitch 5120 (/4 1280) >[155157.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x256ee70] >[155157.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x256ee70] width 1280 pitch 5120 (/4 1280) >[155157.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2916800] >[155157.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2916800] width 1280 pitch 5120 (/4 1280) >[155425.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2888680] >[155425.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2888680] width 1280 pitch 5120 (/4 1280) >[155425.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2888680] >[155425.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2888680] width 1280 pitch 5120 (/4 1280) >[156538.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2895080] >[156538.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2895080] width 1280 pitch 5120 (/4 1280) >[156538.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b4a80] >[156538.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b4a80] width 1280 pitch 5120 (/4 1280) >[156570.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294e0f0] >[156570.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294e0f0] width 1280 pitch 5120 (/4 1280) >[156570.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1343210] >[156570.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1343210] width 1280 pitch 5120 (/4 1280) >[157005.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29cb1e0] >[157005.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29cb1e0] width 1280 pitch 5120 (/4 1280) >[157502.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a06fc0] >[157502.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a06fc0] width 1280 pitch 5120 (/4 1280) >[157503.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d3f30] >[157503.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d3f30] width 1280 pitch 5120 (/4 1280) >[157571.124] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[157571.124] (II) RADEON(0): Printing DDC gathered Modelines: >[157571.124] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[158170.830] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[158170.830] (II) RADEON(0): Printing DDC gathered Modelines: >[158170.830] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[158260.927] (II) RADEON(0): RADEONSaveScreen(2) >[158260.932] (II) RADEON(0): RADEONSaveScreen(0) >[187335.005] (II) RADEON(0): RADEONSaveScreen(1) >[187347.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c9290] >[187347.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c9290] width 1280 pitch 5120 (/4 1280) >[187499.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40600] >[187499.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40600] width 1280 pitch 5120 (/4 1280) >[187507.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[187507.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[187507.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f19500] >[187507.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f19500] width 1280 pitch 5120 (/4 1280) >[187507.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351720] >[187507.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351720] width 1280 pitch 5120 (/4 1280) >[187507.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4c990] >[187507.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4c990] width 1280 pitch 5120 (/4 1280) >[187521.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aa0aa0] >[187521.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aa0aa0] width 1280 pitch 5120 (/4 1280) >[187523.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d4350] >[187523.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d4350] width 1280 pitch 5120 (/4 1280) >[187523.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11dad30] >[187523.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11dad30] width 1280 pitch 5120 (/4 1280) >[187524.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[187524.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[187524.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x15195b0] >[187524.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x15195b0] width 1280 pitch 5120 (/4 1280) >[187533.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecf0e0] >[187533.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecf0e0] width 1280 pitch 5120 (/4 1280) >[187534.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276f750] >[187534.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276f750] width 1280 pitch 5120 (/4 1280) >[187535.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43640] >[187535.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43640] width 1280 pitch 5120 (/4 1280) >[187535.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2754420] >[187535.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2754420] width 1280 pitch 5120 (/4 1280) >[187535.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d1d70] >[187535.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d1d70] width 1280 pitch 5120 (/4 1280) >[187543.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d2ed50] >[187543.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d2ed50] width 1280 pitch 5120 (/4 1280) >[187544.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db5c50] >[187544.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db5c50] width 1280 pitch 5120 (/4 1280) >[187544.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2419c90] >[187544.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2419c90] width 1280 pitch 5120 (/4 1280) >[187544.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[187544.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[187544.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276f750] >[187544.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276f750] width 1280 pitch 5120 (/4 1280) >[187555.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19a3400] >[187555.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19a3400] width 1280 pitch 5120 (/4 1280) >[187556.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11653c0] >[187557.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11653c0] width 1280 pitch 5120 (/4 1280) >[187557.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[187557.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[187557.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f71d0] >[187557.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f71d0] width 1280 pitch 5120 (/4 1280) >[187557.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134a9b0] >[187557.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134a9b0] width 1280 pitch 5120 (/4 1280) >[187563.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1425720] >[187563.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1425720] width 1280 pitch 5120 (/4 1280) >[187566.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c8250] >[187566.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c8250] width 1280 pitch 5120 (/4 1280) >[187566.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[187566.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[187566.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dba500] >[187566.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dba500] width 1280 pitch 5120 (/4 1280) >[187566.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27207e0] >[187566.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27207e0] width 1280 pitch 5120 (/4 1280) >[187573.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xffdc20] >[187573.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xffdc20] width 1280 pitch 5120 (/4 1280) >[187580.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147a100] >[187580.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147a100] width 1280 pitch 5120 (/4 1280) >[187582.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da29e0] >[187582.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da29e0] width 1280 pitch 5120 (/4 1280) >[187582.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x127f0a0] >[187582.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x127f0a0] width 1280 pitch 5120 (/4 1280) >[187582.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27afd10] >[187582.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27afd10] width 1280 pitch 5120 (/4 1280) >[187582.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xfec070] >[187582.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xfec070] width 1280 pitch 5120 (/4 1280) >[189281.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e96110] >[189281.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e96110] width 1280 pitch 5120 (/4 1280) >[189281.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14e0320] >[189281.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14e0320] width 1280 pitch 5120 (/4 1280) >[189281.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e96110] >[189281.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e96110] width 1280 pitch 5120 (/4 1280) >[189281.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a759a0] >[189281.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a759a0] width 1280 pitch 5120 (/4 1280) >[189281.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e96110] >[189281.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e96110] width 1280 pitch 5120 (/4 1280) >[189281.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[189281.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[189281.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e96110] >[189281.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e96110] width 1280 pitch 5120 (/4 1280) >[189281.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[189281.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[189281.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36290e0] >[189281.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36290e0] width 1280 pitch 5120 (/4 1280) >[189281.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6bde0] >[189281.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6bde0] width 1280 pitch 5120 (/4 1280) >[189281.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a3b30] >[189281.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a3b30] width 1280 pitch 5120 (/4 1280) >[189281.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a78f80] >[189281.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a78f80] width 1280 pitch 5120 (/4 1280) >[189281.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fba4e0] >[189281.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fba4e0] width 1280 pitch 5120 (/4 1280) >[189281.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2364e80] >[189281.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2364e80] width 1280 pitch 5120 (/4 1280) >[189282.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[189282.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[189282.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e250] >[189282.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e250] width 1280 pitch 5120 (/4 1280) >[189282.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e770] >[189282.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e770] width 1280 pitch 5120 (/4 1280) >[189282.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ba420] >[189282.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ba420] width 1280 pitch 5120 (/4 1280) >[189282.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40520] >[189282.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40520] width 1280 pitch 5120 (/4 1280) >[189282.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20517d0] >[189282.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20517d0] width 1280 pitch 5120 (/4 1280) >[189282.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40520] >[189282.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40520] width 1280 pitch 5120 (/4 1280) >[189282.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20517d0] >[189282.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20517d0] width 1280 pitch 5120 (/4 1280) >[189282.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40520] >[189282.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40520] width 1280 pitch 5120 (/4 1280) >[189282.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20517d0] >[189282.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20517d0] width 1280 pitch 5120 (/4 1280) >[189282.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40520] >[189282.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40520] width 1280 pitch 5120 (/4 1280) >[189282.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20517d0] >[189282.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20517d0] width 1280 pitch 5120 (/4 1280) >[189282.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40520] >[189282.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40520] width 1280 pitch 5120 (/4 1280) >[189477.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13aa5b0] >[189477.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13aa5b0] width 1280 pitch 5120 (/4 1280) >[189477.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c9290] >[189477.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c9290] width 1280 pitch 5120 (/4 1280) >[189597.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12fff40] >[189597.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12fff40] width 1280 pitch 5120 (/4 1280) >[189606.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e3c00] >[189606.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e3c00] width 1280 pitch 5120 (/4 1280) >[189627.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa0320] >[189627.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa0320] width 1280 pitch 5120 (/4 1280) >[189627.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1236fa0] >[189627.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1236fa0] width 1280 pitch 5120 (/4 1280) >[189633.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fc410] >[189633.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fc410] width 1280 pitch 5120 (/4 1280) >[189633.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fe210] >[189633.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fe210] width 1280 pitch 5120 (/4 1280) >[189681.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3100620] >[189681.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3100620] width 1280 pitch 5120 (/4 1280) >[189681.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d43310] >[189681.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d43310] width 1280 pitch 5120 (/4 1280) >[189696.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364d280] >[189696.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364d280] width 1280 pitch 5120 (/4 1280) >[189720.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d6d0] >[189720.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d6d0] width 1280 pitch 5120 (/4 1280) >[189727.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29a8160] >[189727.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29a8160] width 1280 pitch 5120 (/4 1280) >[189727.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9eac0] >[189727.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9eac0] width 1280 pitch 5120 (/4 1280) >[189727.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[189727.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[189728.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621f10] >[189728.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621f10] width 1280 pitch 5120 (/4 1280) >[189730.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697100] >[189730.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697100] width 1280 pitch 5120 (/4 1280) >[189730.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a75d60] >[189731.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a75d60] width 1280 pitch 5120 (/4 1280) >[189732.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36290e0] >[189732.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36290e0] width 1280 pitch 5120 (/4 1280) >[189732.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[189732.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[189771.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189771.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189771.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d6d0] >[189771.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d6d0] width 1280 pitch 5120 (/4 1280) >[189771.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189771.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189771.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d6d0] >[189771.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d6d0] width 1280 pitch 5120 (/4 1280) >[189771.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189771.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189771.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d6d0] >[189771.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d6d0] width 1280 pitch 5120 (/4 1280) >[189771.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189771.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189771.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d6d0] >[189771.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d6d0] width 1280 pitch 5120 (/4 1280) >[189771.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189771.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189771.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a75d60] >[189771.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a75d60] width 1280 pitch 5120 (/4 1280) >[189771.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189772.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189772.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a75d60] >[189772.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a75d60] width 1280 pitch 5120 (/4 1280) >[189772.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189772.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189772.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d8360] >[189772.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d8360] width 1280 pitch 5120 (/4 1280) >[189772.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eac8e0] >[189772.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eac8e0] width 1280 pitch 5120 (/4 1280) >[189772.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d8360] >[189772.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d8360] width 1280 pitch 5120 (/4 1280) >[190011.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190011.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190011.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190011.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190011.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190011.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190011.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190011.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190011.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190011.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190011.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190011.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190011.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190011.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190011.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190012.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190012.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190012.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190012.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190012.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190012.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190012.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190012.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190012.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190012.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190012.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190012.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[190012.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[190012.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190012.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190012.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190013.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190013.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190013.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190013.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190013.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190013.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190013.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190013.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190013.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190013.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190013.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190013.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190013.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190013.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190013.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190013.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8da10] >[190013.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8da10] width 1280 pitch 5120 (/4 1280) >[190013.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190013.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190013.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd8060] >[190013.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd8060] width 1280 pitch 5120 (/4 1280) >[190014.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663dc0] >[190014.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663dc0] width 1280 pitch 5120 (/4 1280) >[190014.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190014.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190014.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26834a0] >[190014.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26834a0] width 1280 pitch 5120 (/4 1280) >[190014.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b7e0] >[190014.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b7e0] width 1280 pitch 5120 (/4 1280) >[190014.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b780] >[190014.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b780] width 1280 pitch 5120 (/4 1280) >[190016.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89730] >[190016.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89730] width 1280 pitch 5120 (/4 1280) >[190016.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a88880] >[190016.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a88880] width 1280 pitch 5120 (/4 1280) >[190016.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683700] >[190017.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683700] width 1280 pitch 5120 (/4 1280) >[190017.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b5b0] >[190017.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b5b0] width 1280 pitch 5120 (/4 1280) >[190017.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649bc0] >[190017.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649bc0] width 1280 pitch 5120 (/4 1280) >[190017.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36532d0] >[190017.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36532d0] width 1280 pitch 5120 (/4 1280) >[190017.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190017.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36532d0] >[190017.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36532d0] width 1280 pitch 5120 (/4 1280) >[190017.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653160] >[190017.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653160] width 1280 pitch 5120 (/4 1280) >[190017.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89980] >[190017.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89980] width 1280 pitch 5120 (/4 1280) >[190091.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e780] >[190091.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e780] width 1280 pitch 5120 (/4 1280) >[190091.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31822c0] >[190091.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31822c0] width 1280 pitch 5120 (/4 1280) >[190192.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fc60] >[190192.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fc60] width 1280 pitch 5120 (/4 1280) >[190192.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a1c870] >[190192.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a1c870] width 1280 pitch 5120 (/4 1280) >[190303.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089ca0] >[190303.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089ca0] width 1280 pitch 5120 (/4 1280) >[190303.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febc50] >[190303.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febc50] width 1280 pitch 5120 (/4 1280) >[190385.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190385.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190385.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190385.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190385.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190385.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190385.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190385.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190385.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190385.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190385.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190385.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190385.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190385.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190385.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190385.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190385.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190385.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190385.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190385.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190385.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190385.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190385.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190385.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190385.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190385.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190386.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190386.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190390.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4630] >[190390.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4630] width 1280 pitch 5120 (/4 1280) >[190391.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190391.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190391.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190391.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190393.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190393.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190393.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190393.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190393.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190393.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190393.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190393.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190393.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190393.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190393.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190393.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190393.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190393.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190394.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190394.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220a30] >[190394.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220a30] width 1280 pitch 5120 (/4 1280) >[190394.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a817d0] >[190394.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a817d0] width 1280 pitch 5120 (/4 1280) >[190394.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190394.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190394.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a2cb0] >[190394.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a2cb0] width 1280 pitch 5120 (/4 1280) >[190394.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a817d0] >[190394.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a817d0] width 1280 pitch 5120 (/4 1280) >[190394.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febc50] >[190394.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febc50] width 1280 pitch 5120 (/4 1280) >[190394.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb4630] >[190394.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb4630] width 1280 pitch 5120 (/4 1280) >[190394.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f260] >[190394.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f260] width 1280 pitch 5120 (/4 1280) >[190394.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3089ca0] >[190394.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3089ca0] width 1280 pitch 5120 (/4 1280) >[190394.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190394.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190394.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a2cb0] >[190394.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a2cb0] width 1280 pitch 5120 (/4 1280) >[190394.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a817d0] >[190394.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a817d0] width 1280 pitch 5120 (/4 1280) >[190394.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f260] >[190394.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f260] width 1280 pitch 5120 (/4 1280) >[190394.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2693ce0] >[190394.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2693ce0] width 1280 pitch 5120 (/4 1280) >[190394.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190394.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190394.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29fcb40] >[190394.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29fcb40] width 1280 pitch 5120 (/4 1280) >[190394.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a2cb0] >[190394.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a2cb0] width 1280 pitch 5120 (/4 1280) >[190394.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d39c0] >[190394.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d39c0] width 1280 pitch 5120 (/4 1280) >[190394.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220a30] >[190394.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220a30] width 1280 pitch 5120 (/4 1280) >[190394.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f0d0] >[190394.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f0d0] width 1280 pitch 5120 (/4 1280) >[190394.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190394.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190394.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a2cb0] >[190394.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a2cb0] width 1280 pitch 5120 (/4 1280) >[190396.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9e540] >[190396.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9e540] width 1280 pitch 5120 (/4 1280) >[190396.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28a2cb0] >[190396.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28a2cb0] width 1280 pitch 5120 (/4 1280) >[190725.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a95d40] >[190725.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a95d40] width 1280 pitch 5120 (/4 1280) >[190725.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a955d0] >[190725.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a955d0] width 1280 pitch 5120 (/4 1280) >[190977.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a2ba10] >[190977.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a2ba10] width 1280 pitch 5120 (/4 1280) >[190977.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a2df90] >[190977.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a2df90] width 1280 pitch 5120 (/4 1280) >[191188.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a3c3f0] >[191188.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a3c3f0] width 1280 pitch 5120 (/4 1280) >[191188.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x289d650] >[191188.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x289d650] width 1280 pitch 5120 (/4 1280) >[191201.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9da10] >[191201.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9da10] width 1280 pitch 5120 (/4 1280) >[191201.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac150] >[191201.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac150] width 1280 pitch 5120 (/4 1280) >[191201.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9da10] >[191201.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9da10] width 1280 pitch 5120 (/4 1280) >[191204.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9da10] >[191204.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9da10] width 1280 pitch 5120 (/4 1280) >[191546.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3666d10] >[191546.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3666d10] width 1280 pitch 5120 (/4 1280) >[191546.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a12f0] >[191546.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a12f0] width 1280 pitch 5120 (/4 1280) >[191811.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2250] >[191811.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2250] width 1280 pitch 5120 (/4 1280) >[191811.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x121cfb0] >[191811.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x121cfb0] width 1280 pitch 5120 (/4 1280) >[191811.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64f0] >[191812.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64f0] width 1280 pitch 5120 (/4 1280) >[191812.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x121cfb0] >[191812.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x121cfb0] width 1280 pitch 5120 (/4 1280) >[191987.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a3d940] >[191987.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a3d940] width 1280 pitch 5120 (/4 1280) >[192135.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36be670] >[192135.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36be670] width 1280 pitch 5120 (/4 1280) >[192135.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d0ed0] >[192135.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d0ed0] width 1280 pitch 5120 (/4 1280) >[192305.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f3d10] >[192305.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f3d10] width 1280 pitch 5120 (/4 1280) >[192305.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f3d10] >[192305.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f3d10] width 1280 pitch 5120 (/4 1280) >[192305.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c2030] >[192305.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c2030] width 1280 pitch 5120 (/4 1280) >[192305.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0920] >[192305.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0920] width 1280 pitch 5120 (/4 1280) >[192312.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36efe20] >[192312.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36efe20] width 1280 pitch 5120 (/4 1280) >[192312.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb070] >[192312.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb070] width 1280 pitch 5120 (/4 1280) >[192787.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3737200] >[192787.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3737200] width 1280 pitch 5120 (/4 1280) >[192791.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37378c0] >[192791.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37378c0] width 1280 pitch 5120 (/4 1280) >[193082.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374b7c0] >[193082.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374b7c0] width 1280 pitch 5120 (/4 1280) >[193390.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758fc0] >[193390.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758fc0] width 1280 pitch 5120 (/4 1280) >[193517.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d040] >[193517.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d040] width 1280 pitch 5120 (/4 1280) >[193643.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366c4d0] >[193643.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366c4d0] width 1280 pitch 5120 (/4 1280) >[193643.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3762310] >[193643.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3762310] width 1280 pitch 5120 (/4 1280) >[193707.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787840] >[193707.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787840] width 1280 pitch 5120 (/4 1280) >[193708.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37518a0] >[193708.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37518a0] width 1280 pitch 5120 (/4 1280) >[193824.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193824.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193824.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193824.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193824.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120ef40] >[193824.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120ef40] width 1280 pitch 5120 (/4 1280) >[193824.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193824.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193824.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193824.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193824.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120ef40] >[193824.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120ef40] width 1280 pitch 5120 (/4 1280) >[193824.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193824.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193825.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193825.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120f6a0] >[193825.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120f6a0] width 1280 pitch 5120 (/4 1280) >[193825.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120c960] >[193825.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120c960] width 1280 pitch 5120 (/4 1280) >[193825.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193825.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193825.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193825.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193825.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193825.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193825.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193825.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193825.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193825.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193825.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193825.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193826.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193826.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193826.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210e30] >[193826.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210e30] width 1280 pitch 5120 (/4 1280) >[193826.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193826.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193826.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193826.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193826.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193826.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193826.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x120cd90] >[193826.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x120cd90] width 1280 pitch 5120 (/4 1280) >[193826.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193826.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193866.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211ff0] >[193866.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211ff0] width 1280 pitch 5120 (/4 1280) >[193866.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[193866.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[193871.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193871.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193871.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[193871.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[193872.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12126a0] >[193872.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12126a0] width 1280 pitch 5120 (/4 1280) >[193872.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[193872.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[193872.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211ff0] >[193872.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211ff0] width 1280 pitch 5120 (/4 1280) >[193872.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12126a0] >[193872.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12126a0] width 1280 pitch 5120 (/4 1280) >[193873.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212ff0] >[193873.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212ff0] width 1280 pitch 5120 (/4 1280) >[193873.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3762310] >[193873.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3762310] width 1280 pitch 5120 (/4 1280) >[193873.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[193873.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[193873.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[193873.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[193873.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3762310] >[193874.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3762310] width 1280 pitch 5120 (/4 1280) >[193874.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1211090] >[193874.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1211090] width 1280 pitch 5120 (/4 1280) >[193874.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[193874.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[193874.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[193874.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[194473.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[194473.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[194473.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[194473.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[194473.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[194473.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[194473.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[194473.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[194473.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[194473.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[194473.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[194473.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[194473.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a0b0] >[194473.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a0b0] width 1280 pitch 5120 (/4 1280) >[194473.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212200] >[194473.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212200] width 1280 pitch 5120 (/4 1280) >[194474.341] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[194474.341] (II) RADEON(0): Printing DDC gathered Modelines: >[194474.341] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[194563.926] (II) RADEON(0): RADEONSaveScreen(2) >[194563.930] (II) RADEON(0): RADEONSaveScreen(0) >[195840.645] (II) RADEON(0): RADEONSaveScreen(1) >[195847.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae4020] >[195847.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae4020] width 1280 pitch 5120 (/4 1280) >[195849.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa620] >[195849.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa620] width 1280 pitch 5120 (/4 1280) >[195849.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae4020] >[195849.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae4020] width 1280 pitch 5120 (/4 1280) >[195850.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffa620] >[195850.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffa620] width 1280 pitch 5120 (/4 1280) >[195850.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae4020] >[195850.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae4020] width 1280 pitch 5120 (/4 1280) >[195885.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1216990] >[195885.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1216990] width 1280 pitch 5120 (/4 1280) >[195885.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a107a0] >[195885.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a107a0] width 1280 pitch 5120 (/4 1280) >[196048.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a107a0] >[196048.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a107a0] width 1280 pitch 5120 (/4 1280) >[196048.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bef30] >[196048.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bef30] width 1280 pitch 5120 (/4 1280) >[196048.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a107a0] >[196048.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a107a0] width 1280 pitch 5120 (/4 1280) >[196048.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bef30] >[196048.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bef30] width 1280 pitch 5120 (/4 1280) >[196048.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a107a0] >[196048.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a107a0] width 1280 pitch 5120 (/4 1280) >[196048.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bef30] >[196048.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bef30] width 1280 pitch 5120 (/4 1280) >[196048.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a107a0] >[196048.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a107a0] width 1280 pitch 5120 (/4 1280) >[196048.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bef30] >[196048.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bef30] width 1280 pitch 5120 (/4 1280) >[196048.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a6e50] >[196048.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a6e50] width 1280 pitch 5120 (/4 1280) >[196048.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bef30] >[196049.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bef30] width 1280 pitch 5120 (/4 1280) >[196049.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[196049.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[196049.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[196049.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[196049.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[196049.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[196049.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[196049.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[196049.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2577ec0] >[196049.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2577ec0] width 1280 pitch 5120 (/4 1280) >[196049.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2577ec0] >[196049.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2577ec0] width 1280 pitch 5120 (/4 1280) >[196049.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29d42b0] >[196049.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29d42b0] width 1280 pitch 5120 (/4 1280) >[196049.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37819b0] >[196049.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37819b0] width 1280 pitch 5120 (/4 1280) >[196049.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37819b0] >[196049.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37819b0] width 1280 pitch 5120 (/4 1280) >[196049.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37819b0] >[196049.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37819b0] width 1280 pitch 5120 (/4 1280) >[196049.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2443810] >[196049.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2443810] width 1280 pitch 5120 (/4 1280) >[196049.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2443810] >[196049.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2443810] width 1280 pitch 5120 (/4 1280) >[196049.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2443810] >[196049.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2443810] width 1280 pitch 5120 (/4 1280) >[196049.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9420] >[196049.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9420] width 1280 pitch 5120 (/4 1280) >[196049.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2443810] >[196049.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2443810] width 1280 pitch 5120 (/4 1280) >[196105.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a3d80] >[196105.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a3d80] width 1280 pitch 5120 (/4 1280) >[196105.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b60] >[196105.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b60] width 1280 pitch 5120 (/4 1280) >[196373.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811510] >[196373.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811510] width 1280 pitch 5120 (/4 1280) >[196373.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361fe10] >[196373.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361fe10] width 1280 pitch 5120 (/4 1280) >[196405.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3807d90] >[196405.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3807d90] width 1280 pitch 5120 (/4 1280) >[196405.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3807950] >[196405.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3807950] width 1280 pitch 5120 (/4 1280) >[196405.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3807d90] >[196405.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3807d90] width 1280 pitch 5120 (/4 1280) >[196405.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3807950] >[196405.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3807950] width 1280 pitch 5120 (/4 1280) >[196474.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196474.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196475.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196475.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196475.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196475.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196475.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196475.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196475.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196475.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196475.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196475.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196475.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196475.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196475.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196475.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196475.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196475.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196475.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196475.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196476.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196476.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196476.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196476.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196476.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196476.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196476.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196476.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196476.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196476.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196476.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196476.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196476.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196476.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196476.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196476.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196476.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196476.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196477.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196477.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196477.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196477.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196478.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196478.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196478.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38199f0] >[196478.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38199f0] width 1280 pitch 5120 (/4 1280) >[196479.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196479.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196479.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196479.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196479.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196479.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196479.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196479.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196479.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819f50] >[196479.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819f50] width 1280 pitch 5120 (/4 1280) >[196479.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196479.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196482.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196482.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196495.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196495.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196495.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196495.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196499.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196499.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196499.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196499.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196499.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196499.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196499.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196499.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196499.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196499.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196499.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196499.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196499.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196499.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196499.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196499.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196499.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196499.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196499.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196499.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196499.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196499.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196499.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196499.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196499.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196499.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196499.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196499.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196499.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196499.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196499.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196499.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196499.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196499.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196500.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196500.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196500.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196500.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196500.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196500.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196500.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196500.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196500.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3855d40] >[196500.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3855d40] width 1280 pitch 5120 (/4 1280) >[196500.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffedc0] >[196500.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffedc0] width 1280 pitch 5120 (/4 1280) >[196500.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196500.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819830] >[196500.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819830] width 1280 pitch 5120 (/4 1280) >[196500.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819660] >[196500.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819660] width 1280 pitch 5120 (/4 1280) >[196600.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37c7720] >[196600.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37c7720] width 1280 pitch 5120 (/4 1280) >[196651.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3904440] >[196651.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3904440] width 1280 pitch 5120 (/4 1280) >[196651.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3904440] >[196651.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3904440] width 1280 pitch 5120 (/4 1280) >[196717.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f650] >[196717.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f650] width 1280 pitch 5120 (/4 1280) >[196717.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913d10] >[196717.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913d10] width 1280 pitch 5120 (/4 1280) >[196778.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[196778.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[196778.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[196778.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[196876.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[196876.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[196876.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21410] >[196876.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21410] width 1280 pitch 5120 (/4 1280) >[196938.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0a2d0] >[196938.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0a2d0] width 1280 pitch 5120 (/4 1280) >[196938.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[196938.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[197321.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197321.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197325.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197325.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197340.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197340.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197340.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197340.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197340.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197340.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197340.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197340.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197341.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39102a0] >[197341.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39102a0] width 1280 pitch 5120 (/4 1280) >[197341.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197341.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197341.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197341.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197341.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376ad90] >[197341.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376ad90] width 1280 pitch 5120 (/4 1280) >[197341.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197341.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197341.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197341.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197341.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0df50] >[197341.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0df50] width 1280 pitch 5120 (/4 1280) >[197341.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21410] >[197341.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21410] width 1280 pitch 5120 (/4 1280) >[197341.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197341.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197342.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197342.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197342.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21410] >[197342.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21410] width 1280 pitch 5120 (/4 1280) >[197342.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197342.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197342.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21410] >[197342.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21410] width 1280 pitch 5120 (/4 1280) >[197344.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197344.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197344.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197344.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197344.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197344.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197344.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197344.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197344.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197344.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197344.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197344.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197344.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197344.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197344.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197344.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197344.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197344.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197344.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197344.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197344.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197344.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197344.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0df50] >[197344.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0df50] width 1280 pitch 5120 (/4 1280) >[197344.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197344.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197344.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197344.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197344.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197344.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197344.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39102a0] >[197345.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39102a0] width 1280 pitch 5120 (/4 1280) >[197345.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197345.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197345.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197345.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197345.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197345.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0df50] >[197345.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0df50] width 1280 pitch 5120 (/4 1280) >[197345.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197345.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197346.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197346.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197346.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197346.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197346.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197346.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197346.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197346.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197346.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197346.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197346.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39102a0] >[197346.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39102a0] width 1280 pitch 5120 (/4 1280) >[197346.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197346.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197346.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39102a0] >[197346.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39102a0] width 1280 pitch 5120 (/4 1280) >[197430.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197430.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197430.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197430.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197430.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197430.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197430.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197430.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197431.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197431.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197431.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e99a0] >[197431.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e99a0] width 1280 pitch 5120 (/4 1280) >[197431.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39102a0] >[197431.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39102a0] width 1280 pitch 5120 (/4 1280) >[197431.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197431.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197432.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197432.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197432.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197432.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197433.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197433.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197433.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197433.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197433.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197433.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197433.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197433.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197433.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197433.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197433.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197433.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197433.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a02b80] >[197433.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a02b80] width 1280 pitch 5120 (/4 1280) >[197433.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a18d0] >[197433.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a18d0] width 1280 pitch 5120 (/4 1280) >[197434.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e18c0] >[197434.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e18c0] width 1280 pitch 5120 (/4 1280) >[197434.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197434.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197434.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21410] >[197434.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21410] width 1280 pitch 5120 (/4 1280) >[197435.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197435.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197435.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3909210] >[197435.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3909210] width 1280 pitch 5120 (/4 1280) >[197723.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197723.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197723.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197723.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197723.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197723.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197723.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197723.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197723.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197723.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197724.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197724.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197724.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197724.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197724.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197724.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197724.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197724.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197724.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197724.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197724.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197724.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197724.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197724.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197724.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197724.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197724.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197724.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197724.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197724.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197724.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197724.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197724.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197724.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197724.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197724.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197724.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197724.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197724.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197724.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197724.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197724.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197724.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197725.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197725.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197725.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197725.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197739.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197739.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197739.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197739.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197739.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197739.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197739.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197739.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197739.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197739.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197739.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197739.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197739.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197739.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197739.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197739.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197739.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197739.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197739.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197739.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197739.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197739.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197739.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197739.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197739.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197739.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197739.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197739.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197739.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197739.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197739.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197739.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197739.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197739.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197739.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197739.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197739.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197740.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197740.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197740.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197740.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197740.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197740.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197740.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197740.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197740.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197740.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197740.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197740.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197740.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fdcb0] >[197740.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fdcb0] width 1280 pitch 5120 (/4 1280) >[197740.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4390] >[197740.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4390] width 1280 pitch 5120 (/4 1280) >[197740.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3801810] >[197740.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3801810] width 1280 pitch 5120 (/4 1280) >[197740.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[197740.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[197740.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ad990] >[197740.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ad990] width 1280 pitch 5120 (/4 1280) >[197740.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ac0] >[197740.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ac0] width 1280 pitch 5120 (/4 1280) >[197740.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c35a0] >[197740.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c35a0] width 1280 pitch 5120 (/4 1280) >[197740.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[197740.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[197740.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285dcd0] >[197740.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285dcd0] width 1280 pitch 5120 (/4 1280) >[197740.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb9d0] >[197740.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb9d0] width 1280 pitch 5120 (/4 1280) >[197740.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d0d0] >[197740.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d0d0] width 1280 pitch 5120 (/4 1280) >[197866.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[197866.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198119.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198119.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198119.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198119.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[198120.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[198120.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198120.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198120.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198120.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198120.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198120.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198120.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198121.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198121.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198121.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7080] >[198121.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7080] width 1280 pitch 5120 (/4 1280) >[198121.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198121.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198121.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3911df0] >[198121.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3911df0] width 1280 pitch 5120 (/4 1280) >[198121.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2663dc0] >[198121.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2663dc0] width 1280 pitch 5120 (/4 1280) >[198121.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[198121.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[198121.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22f79a0] >[198121.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22f79a0] width 1280 pitch 5120 (/4 1280) >[198121.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22f79a0] >[198121.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22f79a0] width 1280 pitch 5120 (/4 1280) >[198121.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[198121.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[198121.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22f79a0] >[198121.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22f79a0] width 1280 pitch 5120 (/4 1280) >[198121.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d260] >[198121.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d260] width 1280 pitch 5120 (/4 1280) >[198121.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[198121.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[198122.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e10] >[198122.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e10] width 1280 pitch 5120 (/4 1280) >[198122.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28abb50] >[198122.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28abb50] width 1280 pitch 5120 (/4 1280) >[198122.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc030] >[198122.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc030] width 1280 pitch 5120 (/4 1280) >[198122.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5500] >[198122.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5500] width 1280 pitch 5120 (/4 1280) >[198122.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2757780] >[198122.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2757780] width 1280 pitch 5120 (/4 1280) >[198122.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198122.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198122.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664a50] >[198122.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664a50] width 1280 pitch 5120 (/4 1280) >[198122.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198122.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198122.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664a50] >[198122.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664a50] width 1280 pitch 5120 (/4 1280) >[198122.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a102d0] >[198122.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a102d0] width 1280 pitch 5120 (/4 1280) >[198122.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664a50] >[198122.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664a50] width 1280 pitch 5120 (/4 1280) >[198122.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198122.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198122.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664a50] >[198123.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664a50] width 1280 pitch 5120 (/4 1280) >[198123.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664a50] >[198123.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664a50] width 1280 pitch 5120 (/4 1280) >[198123.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198123.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26616c0] >[198123.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26616c0] width 1280 pitch 5120 (/4 1280) >[198123.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ecea0] >[198123.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ecea0] width 1280 pitch 5120 (/4 1280) >[198125.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d6bf0] >[198125.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d6bf0] width 1280 pitch 5120 (/4 1280) >[198125.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f46760] >[198125.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f46760] width 1280 pitch 5120 (/4 1280) >[198125.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d6bf0] >[198125.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d6bf0] width 1280 pitch 5120 (/4 1280) >[198125.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d1810] >[198125.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d1810] width 1280 pitch 5120 (/4 1280) >[198125.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f46760] >[198125.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f46760] width 1280 pitch 5120 (/4 1280) >[198125.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3646600] >[198125.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3646600] width 1280 pitch 5120 (/4 1280) >[198125.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e4c00] >[198125.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e4c00] width 1280 pitch 5120 (/4 1280) >[198125.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a6b0] >[198125.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a6b0] width 1280 pitch 5120 (/4 1280) >[198125.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e4c00] >[198125.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e4c00] width 1280 pitch 5120 (/4 1280) >[198125.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a6b0] >[198125.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a6b0] width 1280 pitch 5120 (/4 1280) >[198126.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e4c00] >[198126.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e4c00] width 1280 pitch 5120 (/4 1280) >[198127.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d6bf0] >[198127.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d6bf0] width 1280 pitch 5120 (/4 1280) >[198127.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d1810] >[198127.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d1810] width 1280 pitch 5120 (/4 1280) >[198127.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3646600] >[198127.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3646600] width 1280 pitch 5120 (/4 1280) >[198127.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc0e0] >[198127.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc0e0] width 1280 pitch 5120 (/4 1280) >[198127.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a6b0] >[198127.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a6b0] width 1280 pitch 5120 (/4 1280) >[198325.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f2670] >[198325.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f2670] width 1280 pitch 5120 (/4 1280) >[198325.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a221e0] >[198325.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a221e0] width 1280 pitch 5120 (/4 1280) >[198518.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a970] >[198518.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a970] width 1280 pitch 5120 (/4 1280) >[198518.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619ea0] >[198518.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619ea0] width 1280 pitch 5120 (/4 1280) >[198518.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a970] >[198518.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a970] width 1280 pitch 5120 (/4 1280) >[198518.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697ed0] >[198518.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697ed0] width 1280 pitch 5120 (/4 1280) >[198518.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697ed0] >[198518.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697ed0] width 1280 pitch 5120 (/4 1280) >[198518.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697ed0] >[198518.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697ed0] width 1280 pitch 5120 (/4 1280) >[198518.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697ed0] >[198518.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697ed0] width 1280 pitch 5120 (/4 1280) >[198518.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a970] >[198518.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a970] width 1280 pitch 5120 (/4 1280) >[198524.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697ed0] >[198524.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697ed0] width 1280 pitch 5120 (/4 1280) >[198524.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619ea0] >[198524.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619ea0] width 1280 pitch 5120 (/4 1280) >[198616.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a0030] >[198616.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a0030] width 1280 pitch 5120 (/4 1280) >[198616.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198616.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a0030] >[198616.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a0030] width 1280 pitch 5120 (/4 1280) >[198616.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198616.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a0030] >[198616.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a0030] width 1280 pitch 5120 (/4 1280) >[198616.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198616.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a0030] >[198616.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a0030] width 1280 pitch 5120 (/4 1280) >[198616.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198616.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a0030] >[198616.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a0030] width 1280 pitch 5120 (/4 1280) >[198616.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198616.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198616.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198616.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198616.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198616.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198616.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198617.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198617.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198617.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198617.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198618.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198618.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198618.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198618.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198618.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a02b0] >[198618.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a02b0] width 1280 pitch 5120 (/4 1280) >[198618.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198618.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198618.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198618.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198618.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198618.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198618.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198618.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198619.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198619.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198619.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2793580] >[198619.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2793580] width 1280 pitch 5120 (/4 1280) >[198619.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198619.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198619.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf3b0] >[198619.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf3b0] width 1280 pitch 5120 (/4 1280) >[198619.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198619.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198619.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf3b0] >[198619.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf3b0] width 1280 pitch 5120 (/4 1280) >[198619.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198619.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf3b0] >[198620.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf3b0] width 1280 pitch 5120 (/4 1280) >[198620.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf3b0] >[198620.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf3b0] width 1280 pitch 5120 (/4 1280) >[198620.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf3b0] >[198620.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf3b0] width 1280 pitch 5120 (/4 1280) >[198620.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198620.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271b830] >[198620.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271b830] width 1280 pitch 5120 (/4 1280) >[198620.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39eee20] >[198620.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39eee20] width 1280 pitch 5120 (/4 1280) >[198622.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267df80] >[198622.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267df80] width 1280 pitch 5120 (/4 1280) >[198622.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2765080] >[198622.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2765080] width 1280 pitch 5120 (/4 1280) >[198622.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d940] >[198622.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d940] width 1280 pitch 5120 (/4 1280) >[198623.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e64c0] >[198623.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e64c0] width 1280 pitch 5120 (/4 1280) >[198626.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2584860] >[198626.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2584860] width 1280 pitch 5120 (/4 1280) >[198778.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198778.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198778.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198778.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198778.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198780.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198780.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198780.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198780.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198781.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198781.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198781.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198781.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198781.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198781.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198781.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198781.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198781.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198781.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198781.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198781.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198781.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198781.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[198781.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[198781.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[198788.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[198788.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[199456.982] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[199456.982] (II) RADEON(0): Printing DDC gathered Modelines: >[199456.982] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[199546.906] (II) RADEON(0): RADEONSaveScreen(2) >[199546.906] (II) RADEON(0): RADEONSaveScreen(0) >[199950.089] (II) RADEON(0): RADEONSaveScreen(1) >[199967.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[199967.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[199967.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3868d50] >[199967.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3868d50] width 1280 pitch 5120 (/4 1280) >[199969.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751e30] >[199969.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751e30] width 1280 pitch 5120 (/4 1280) >[200009.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39de480] >[200009.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39de480] width 1280 pitch 5120 (/4 1280) >[200009.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x387da30] >[200009.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x387da30] width 1280 pitch 5120 (/4 1280) >[200010.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39de480] >[200010.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39de480] width 1280 pitch 5120 (/4 1280) >[200010.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x387da30] >[200010.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x387da30] width 1280 pitch 5120 (/4 1280) >[200121.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39e9f40] >[200121.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39e9f40] width 1280 pitch 5120 (/4 1280) >[200121.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[200121.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[200122.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[200122.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[200123.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39e9b70] >[200123.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39e9b70] width 1280 pitch 5120 (/4 1280) >[200126.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200127.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200127.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200127.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200127.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200127.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200127.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200127.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200127.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200127.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200127.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200127.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200127.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200127.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200127.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200127.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200138.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200138.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200138.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200138.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200138.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a41ea0] >[200138.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a41ea0] width 1280 pitch 5120 (/4 1280) >[200138.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200138.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200138.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1212e80] >[200138.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1212e80] width 1280 pitch 5120 (/4 1280) >[200138.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ad1450] >[200138.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ad1450] width 1280 pitch 5120 (/4 1280) >[200138.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23123d0] >[200139.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23123d0] width 1280 pitch 5120 (/4 1280) >[200139.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[200139.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[200139.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[200139.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[200303.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cce70] >[200303.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cce70] width 1280 pitch 5120 (/4 1280) >[200303.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38806e0] >[200303.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38806e0] width 1280 pitch 5120 (/4 1280) >[200529.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3847ec0] >[200529.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3847ec0] width 1280 pitch 5120 (/4 1280) >[200529.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x384f870] >[200529.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x384f870] width 1280 pitch 5120 (/4 1280) >[200548.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[200548.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[200549.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39e9b70] >[200549.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39e9b70] width 1280 pitch 5120 (/4 1280) >[200567.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x387da30] >[200567.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x387da30] width 1280 pitch 5120 (/4 1280) >[200787.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be690] >[200787.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be690] width 1280 pitch 5120 (/4 1280) >[200787.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c5a80] >[200787.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c5a80] width 1280 pitch 5120 (/4 1280) >[200850.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9250] >[200850.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9250] width 1280 pitch 5120 (/4 1280) >[200850.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697c40] >[200850.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697c40] width 1280 pitch 5120 (/4 1280) >[200850.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb8d0] >[200850.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb8d0] width 1280 pitch 5120 (/4 1280) >[200850.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c92b0] >[200850.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c92b0] width 1280 pitch 5120 (/4 1280) >[200850.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9250] >[200850.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9250] width 1280 pitch 5120 (/4 1280) >[200850.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9250] >[200850.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9250] width 1280 pitch 5120 (/4 1280) >[200850.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9250] >[200850.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9250] width 1280 pitch 5120 (/4 1280) >[200850.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200850.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200850.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c92b0] >[200850.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c92b0] width 1280 pitch 5120 (/4 1280) >[200850.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e6620] >[200850.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e6620] width 1280 pitch 5120 (/4 1280) >[200850.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200850.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200850.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200850.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200850.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200851.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200851.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200851.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200851.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200851.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200851.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200851.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200851.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200851.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200851.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200851.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200851.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200851.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200851.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200851.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200851.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f1050] >[200851.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f1050] width 1280 pitch 5120 (/4 1280) >[200851.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e1a10] >[200851.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e1a10] width 1280 pitch 5120 (/4 1280) >[200889.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38778a0] >[200889.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38778a0] width 1280 pitch 5120 (/4 1280) >[200890.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ec090] >[200890.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ec090] width 1280 pitch 5120 (/4 1280) >[200974.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x387bf10] >[200974.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x387bf10] width 1280 pitch 5120 (/4 1280) >[200974.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382abd0] >[200974.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382abd0] width 1280 pitch 5120 (/4 1280) >[201289.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201289.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201324.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664470] >[201324.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664470] width 1280 pitch 5120 (/4 1280) >[201324.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201324.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201324.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664470] >[201324.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664470] width 1280 pitch 5120 (/4 1280) >[201324.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201324.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201324.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664470] >[201324.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664470] width 1280 pitch 5120 (/4 1280) >[201324.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201324.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201324.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664470] >[201324.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664470] width 1280 pitch 5120 (/4 1280) >[201324.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201324.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201324.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ab700] >[201324.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ab700] width 1280 pitch 5120 (/4 1280) >[201324.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201324.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201324.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ab700] >[201324.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ab700] width 1280 pitch 5120 (/4 1280) >[201325.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201325.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201326.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201326.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201326.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ab700] >[201326.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ab700] width 1280 pitch 5120 (/4 1280) >[201326.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201326.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201326.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201326.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201326.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201326.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201326.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201326.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201326.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2664470] >[201326.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2664470] width 1280 pitch 5120 (/4 1280) >[201326.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201327.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201327.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201327.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201327.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201327.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201327.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201327.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201327.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0cd0] >[201327.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0cd0] width 1280 pitch 5120 (/4 1280) >[201327.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201327.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201327.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201327.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201331.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201331.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201331.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201331.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201332.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201332.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201349.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201349.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201362.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201362.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201362.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201362.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201363.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389fc80] >[201363.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389fc80] width 1280 pitch 5120 (/4 1280) >[201363.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fb60] >[201363.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fb60] width 1280 pitch 5120 (/4 1280) >[201365.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ab700] >[201365.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ab700] width 1280 pitch 5120 (/4 1280) >[201365.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201365.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201365.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383df60] >[201365.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383df60] width 1280 pitch 5120 (/4 1280) >[201365.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201365.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201365.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383df60] >[201365.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383df60] width 1280 pitch 5120 (/4 1280) >[201365.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386fdf0] >[201365.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386fdf0] width 1280 pitch 5120 (/4 1280) >[201365.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383df60] >[201365.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383df60] width 1280 pitch 5120 (/4 1280) >[201365.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201365.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201367.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383df60] >[201367.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383df60] width 1280 pitch 5120 (/4 1280) >[201367.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ab700] >[201367.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ab700] width 1280 pitch 5120 (/4 1280) >[201392.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389fc80] >[201392.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389fc80] width 1280 pitch 5120 (/4 1280) >[201392.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c80c0] >[201392.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c80c0] width 1280 pitch 5120 (/4 1280) >[201397.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c98d0] >[201397.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c98d0] width 1280 pitch 5120 (/4 1280) >[201397.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8930] >[201397.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8930] width 1280 pitch 5120 (/4 1280) >[201397.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201397.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201397.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389e1d0] >[201397.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389e1d0] width 1280 pitch 5120 (/4 1280) >[201397.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201397.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201397.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389e1d0] >[201397.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389e1d0] width 1280 pitch 5120 (/4 1280) >[201397.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201397.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201397.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389e1d0] >[201398.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389e1d0] width 1280 pitch 5120 (/4 1280) >[201398.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201398.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201398.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389e1d0] >[201398.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389e1d0] width 1280 pitch 5120 (/4 1280) >[201398.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201398.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201399.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201399.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201399.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201399.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201399.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201425.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201425.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201434.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267d680] >[201434.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267d680] width 1280 pitch 5120 (/4 1280) >[201434.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201434.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201434.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201434.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201434.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201434.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201434.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201434.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201434.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201434.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201434.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201434.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201434.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201434.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201434.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201434.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201434.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201435.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201435.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201435.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201435.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201435.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201435.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201435.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201435.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201435.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201435.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201435.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201435.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201436.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d83c0] >[201436.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d83c0] width 1280 pitch 5120 (/4 1280) >[201436.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2080] >[201436.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2080] width 1280 pitch 5120 (/4 1280) >[201452.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201452.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201452.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201452.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201452.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201452.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201452.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201452.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201453.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201453.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201453.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201453.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201453.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a19f0] >[201453.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a19f0] width 1280 pitch 5120 (/4 1280) >[201453.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201453.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201453.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201453.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201453.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361add0] >[201453.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361add0] width 1280 pitch 5120 (/4 1280) >[201453.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201453.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201453.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201453.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201453.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201453.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201453.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201453.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201453.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201453.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201453.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201453.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201453.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9aa0] >[201453.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9aa0] width 1280 pitch 5120 (/4 1280) >[201453.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c98d0] >[201453.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c98d0] width 1280 pitch 5120 (/4 1280) >[201453.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9aa0] >[201453.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9aa0] width 1280 pitch 5120 (/4 1280) >[201461.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a56a0] >[201461.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a56a0] width 1280 pitch 5120 (/4 1280) >[201461.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201461.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201461.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201461.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201461.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201462.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201462.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201462.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201462.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca4f0] >[201462.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca4f0] width 1280 pitch 5120 (/4 1280) >[201462.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201462.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201462.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a19f0] >[201462.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a19f0] width 1280 pitch 5120 (/4 1280) >[201462.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201462.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201463.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a19f0] >[201463.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a19f0] width 1280 pitch 5120 (/4 1280) >[201463.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a86a20] >[201463.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a86a20] width 1280 pitch 5120 (/4 1280) >[201463.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201463.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201463.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201463.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201463.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201463.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201463.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201463.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201463.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201463.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201463.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201463.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201463.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201463.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201463.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201463.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201463.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201463.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201463.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201463.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201463.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c98d0] >[201463.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c98d0] width 1280 pitch 5120 (/4 1280) >[201463.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201463.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201463.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361add0] >[201463.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361add0] width 1280 pitch 5120 (/4 1280) >[201463.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201463.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201463.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9aa0] >[201463.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9aa0] width 1280 pitch 5120 (/4 1280) >[201463.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201463.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201464.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c98d0] >[201464.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c98d0] width 1280 pitch 5120 (/4 1280) >[201464.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201464.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201464.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c98d0] >[201464.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c98d0] width 1280 pitch 5120 (/4 1280) >[201464.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201464.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201465.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9aa0] >[201465.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9aa0] width 1280 pitch 5120 (/4 1280) >[201465.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201465.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201465.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201465.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201465.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a56a0] >[201465.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a56a0] width 1280 pitch 5120 (/4 1280) >[201465.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201465.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201465.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a56a0] >[201465.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a56a0] width 1280 pitch 5120 (/4 1280) >[201465.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201465.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201465.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a56a0] >[201465.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a56a0] width 1280 pitch 5120 (/4 1280) >[201465.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201465.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201465.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201465.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201465.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201465.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201466.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201466.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201466.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201466.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201466.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb170] >[201466.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb170] width 1280 pitch 5120 (/4 1280) >[201466.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201466.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201466.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d7bf0] >[201466.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d7bf0] width 1280 pitch 5120 (/4 1280) >[201466.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201466.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201466.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201466.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201466.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1d40] >[201466.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1d40] width 1280 pitch 5120 (/4 1280) >[201466.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201466.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201466.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361add0] >[201466.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361add0] width 1280 pitch 5120 (/4 1280) >[201466.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ef00] >[201466.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ef00] width 1280 pitch 5120 (/4 1280) >[201466.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361add0] >[201466.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361add0] width 1280 pitch 5120 (/4 1280) >[201466.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ce0] >[201467.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ce0] width 1280 pitch 5120 (/4 1280) >[201527.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201527.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201527.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201527.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201527.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201527.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201527.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201527.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201527.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201527.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201527.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201527.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201527.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201527.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201527.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201527.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201527.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201527.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201528.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201528.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201528.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201528.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201528.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201528.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201528.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201528.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201528.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201528.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201528.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201528.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201528.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201528.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201528.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e47c0] >[201528.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e47c0] width 1280 pitch 5120 (/4 1280) >[201528.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ccef0] >[201528.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ccef0] width 1280 pitch 5120 (/4 1280) >[201588.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391da70] >[201588.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391da70] width 1280 pitch 5120 (/4 1280) >[201588.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b21d0] >[201588.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b21d0] width 1280 pitch 5120 (/4 1280) >[201611.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbbe0] >[201611.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbbe0] width 1280 pitch 5120 (/4 1280) >[201611.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbbe0] >[201611.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbbe0] width 1280 pitch 5120 (/4 1280) >[201869.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39776d0] >[201869.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39776d0] width 1280 pitch 5120 (/4 1280) >[201869.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3926930] >[201869.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3926930] width 1280 pitch 5120 (/4 1280) >[202086.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29412e0] >[202086.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29412e0] width 1280 pitch 5120 (/4 1280) >[202086.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39c6eb0] >[202086.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39c6eb0] width 1280 pitch 5120 (/4 1280) >[202146.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a41c0] >[202146.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a41c0] width 1280 pitch 5120 (/4 1280) >[202146.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39c98a0] >[202146.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39c98a0] width 1280 pitch 5120 (/4 1280) >[202187.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28649e0] >[202187.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28649e0] width 1280 pitch 5120 (/4 1280) >[202188.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28649e0] >[202188.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28649e0] width 1280 pitch 5120 (/4 1280) >[202190.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39987d0] >[202190.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39987d0] width 1280 pitch 5120 (/4 1280) >[202190.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39c82e0] >[202190.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39c82e0] width 1280 pitch 5120 (/4 1280) >[202216.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a6e0] >[202216.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a6e0] width 1280 pitch 5120 (/4 1280) >[202217.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a44690] >[202217.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a44690] width 1280 pitch 5120 (/4 1280) >[202217.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45420] >[202217.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45420] width 1280 pitch 5120 (/4 1280) >[202250.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391de60] >[202250.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391de60] width 1280 pitch 5120 (/4 1280) >[202250.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a4d20] >[202250.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a4d20] width 1280 pitch 5120 (/4 1280) >[202280.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39969c0] >[202280.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39969c0] width 1280 pitch 5120 (/4 1280) >[202280.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39969c0] >[202280.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39969c0] width 1280 pitch 5120 (/4 1280) >[202501.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39c2210] >[202501.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39c2210] width 1280 pitch 5120 (/4 1280) >[202501.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3990e90] >[202501.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3990e90] width 1280 pitch 5120 (/4 1280) >[202706.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3f780] >[202706.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3f780] width 1280 pitch 5120 (/4 1280) >[202706.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3923df0] >[202706.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3923df0] width 1280 pitch 5120 (/4 1280) >[202706.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5370] >[202706.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5370] width 1280 pitch 5120 (/4 1280) >[202706.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3923df0] >[202706.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3923df0] width 1280 pitch 5120 (/4 1280) >[202707.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8eef0] >[202708.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8eef0] width 1280 pitch 5120 (/4 1280) >[202708.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3923df0] >[202708.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3923df0] width 1280 pitch 5120 (/4 1280) >[202714.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a356c0] >[202714.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a356c0] width 1280 pitch 5120 (/4 1280) >[202714.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a356c0] >[202714.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a356c0] width 1280 pitch 5120 (/4 1280) >[202790.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45170] >[202790.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45170] width 1280 pitch 5120 (/4 1280) >[202790.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a356c0] >[202790.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a356c0] width 1280 pitch 5120 (/4 1280) >[203056.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203056.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203056.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203056.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203056.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203086.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a27e10] >[203086.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a27e10] width 1280 pitch 5120 (/4 1280) >[203086.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203086.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203086.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a7f30] >[203086.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a7f30] width 1280 pitch 5120 (/4 1280) >[203086.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a7f30] >[203086.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a7f30] width 1280 pitch 5120 (/4 1280) >[203086.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a7f30] >[203086.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a7f30] width 1280 pitch 5120 (/4 1280) >[203086.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828f70] >[203086.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828f70] width 1280 pitch 5120 (/4 1280) >[203086.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828f70] >[203086.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828f70] width 1280 pitch 5120 (/4 1280) >[203086.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828f70] >[203086.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828f70] width 1280 pitch 5120 (/4 1280) >[203086.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828f70] >[203086.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828f70] width 1280 pitch 5120 (/4 1280) >[203086.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203086.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203086.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3828ea0] >[203086.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3828ea0] width 1280 pitch 5120 (/4 1280) >[203086.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a27610] >[203086.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a27610] width 1280 pitch 5120 (/4 1280) >[203086.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a30830] >[203086.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a30830] width 1280 pitch 5120 (/4 1280) >[203086.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a27610] >[203086.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a27610] width 1280 pitch 5120 (/4 1280) >[203086.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a30830] >[203086.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a30830] width 1280 pitch 5120 (/4 1280) >[203086.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a27610] >[203086.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a27610] width 1280 pitch 5120 (/4 1280) >[203086.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203086.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203086.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a7f30] >[203086.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a7f30] width 1280 pitch 5120 (/4 1280) >[203086.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[203086.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[203086.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203086.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203086.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f720] >[203086.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f720] width 1280 pitch 5120 (/4 1280) >[203101.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a27e10] >[203101.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a27e10] width 1280 pitch 5120 (/4 1280) >[203102.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a54b0] >[203102.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a54b0] width 1280 pitch 5120 (/4 1280) >[203141.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38904b0] >[203141.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38904b0] width 1280 pitch 5120 (/4 1280) >[203141.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a010] >[203141.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a010] width 1280 pitch 5120 (/4 1280) >[203141.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388fb20] >[203141.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388fb20] width 1280 pitch 5120 (/4 1280) >[203141.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388fb20] >[203141.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388fb20] width 1280 pitch 5120 (/4 1280) >[203141.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388fa20] >[203142.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388fa20] width 1280 pitch 5120 (/4 1280) >[203142.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388fb90] >[203142.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388fb90] width 1280 pitch 5120 (/4 1280) >[203142.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38904b0] >[203142.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38904b0] width 1280 pitch 5120 (/4 1280) >[203142.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203142.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203142.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203142.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203142.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203142.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203142.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203142.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203142.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203142.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203142.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203142.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203142.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203143.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203143.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203143.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3860f40] >[203143.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3860f40] width 1280 pitch 5120 (/4 1280) >[203143.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203143.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203143.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9d40] >[203143.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9d40] width 1280 pitch 5120 (/4 1280) >[203143.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203143.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203143.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203143.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203143.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203143.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203143.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203143.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203143.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203143.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203143.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203143.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203143.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e10] >[203143.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e10] width 1280 pitch 5120 (/4 1280) >[203143.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e10] >[203144.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e10] width 1280 pitch 5120 (/4 1280) >[203144.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203144.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203144.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267e000] >[203144.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267e000] width 1280 pitch 5120 (/4 1280) >[203144.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a0ff70] >[203144.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a0ff70] width 1280 pitch 5120 (/4 1280) >[203144.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203144.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203144.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27eacf0] >[203144.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27eacf0] width 1280 pitch 5120 (/4 1280) >[203144.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203144.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203144.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3889720] >[203144.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3889720] width 1280 pitch 5120 (/4 1280) >[203144.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210900] >[203144.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210900] width 1280 pitch 5120 (/4 1280) >[203144.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267e000] >[203144.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267e000] width 1280 pitch 5120 (/4 1280) >[203144.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203144.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203144.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2757520] >[203144.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2757520] width 1280 pitch 5120 (/4 1280) >[203144.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e31f0] >[203144.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e31f0] width 1280 pitch 5120 (/4 1280) >[203144.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2757520] >[203144.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2757520] width 1280 pitch 5120 (/4 1280) >[203144.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[203145.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[203145.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203145.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203145.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[203145.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[203145.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203145.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203145.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[203145.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[203145.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203145.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203145.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[203145.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[203145.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203145.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203145.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f5400] >[203145.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f5400] width 1280 pitch 5120 (/4 1280) >[203145.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203145.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203145.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e10] >[203145.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e10] width 1280 pitch 5120 (/4 1280) >[203145.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7ee00] >[203145.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7ee00] width 1280 pitch 5120 (/4 1280) >[203157.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9360] >[203157.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9360] width 1280 pitch 5120 (/4 1280) >[203229.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28abc70] >[203229.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28abc70] width 1280 pitch 5120 (/4 1280) >[203229.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b160] >[203229.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b160] width 1280 pitch 5120 (/4 1280) >[203229.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203229.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203229.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203229.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203229.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[203229.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[203229.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203229.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203229.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef100] >[203229.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef100] width 1280 pitch 5120 (/4 1280) >[203229.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203229.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203229.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef100] >[203229.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef100] width 1280 pitch 5120 (/4 1280) >[203229.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203229.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203229.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef100] >[203229.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef100] width 1280 pitch 5120 (/4 1280) >[203229.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203229.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203229.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ef100] >[203230.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ef100] width 1280 pitch 5120 (/4 1280) >[203230.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388f9a0] >[203230.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388f9a0] width 1280 pitch 5120 (/4 1280) >[203230.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1a70] >[203230.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1a70] width 1280 pitch 5120 (/4 1280) >[203230.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d15b0] >[203230.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d15b0] width 1280 pitch 5120 (/4 1280) >[203230.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203230.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203230.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203230.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203230.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203230.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203230.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203230.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203230.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203231.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203231.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203231.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203231.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203231.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203231.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c4e0] >[203231.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c4e0] width 1280 pitch 5120 (/4 1280) >[203231.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38620f0] >[203231.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38620f0] width 1280 pitch 5120 (/4 1280) >[203231.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885130] >[203231.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885130] width 1280 pitch 5120 (/4 1280) >[203232.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a713a0] >[203232.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a713a0] width 1280 pitch 5120 (/4 1280) >[203233.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a89c70] >[203233.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a89c70] width 1280 pitch 5120 (/4 1280) >[203233.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210900] >[203233.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210900] width 1280 pitch 5120 (/4 1280) >[203838.014] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[203838.014] (II) RADEON(0): Printing DDC gathered Modelines: >[203838.014] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[203927.891] (II) RADEON(0): RADEONSaveScreen(2) >[203927.891] (II) RADEON(0): RADEONSaveScreen(0) >[204717.426] (II) RADEON(0): RADEONSaveScreen(1) >[204724.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389c1f0] >[204724.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389c1f0] width 1280 pitch 5120 (/4 1280) >[204729.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f8c00] >[204729.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f8c00] width 1280 pitch 5120 (/4 1280) >[204729.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[204729.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[204729.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674e10] >[204729.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674e10] width 1280 pitch 5120 (/4 1280) >[204729.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f1d00] >[204729.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f1d00] width 1280 pitch 5120 (/4 1280) >[204730.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1178380] >[204730.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1178380] width 1280 pitch 5120 (/4 1280) >[204731.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1210900] >[204731.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1210900] width 1280 pitch 5120 (/4 1280) >[204731.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a2590] >[204731.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a2590] width 1280 pitch 5120 (/4 1280) >[204731.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267db00] >[204731.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267db00] width 1280 pitch 5120 (/4 1280) >[204775.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ea90] >[204775.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ea90] width 1280 pitch 5120 (/4 1280) >[204833.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9bb0] >[204833.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9bb0] width 1280 pitch 5120 (/4 1280) >[204833.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39d37e0] >[204833.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39d37e0] width 1280 pitch 5120 (/4 1280) >[204982.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a669d0] >[204982.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a669d0] width 1280 pitch 5120 (/4 1280) >[204982.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a661f0] >[204982.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a661f0] width 1280 pitch 5120 (/4 1280) >[204993.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a747d0] >[204993.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a747d0] width 1280 pitch 5120 (/4 1280) >[204998.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38608c0] >[204998.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38608c0] width 1280 pitch 5120 (/4 1280) >[204998.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38608c0] >[204998.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38608c0] width 1280 pitch 5120 (/4 1280) >[205100.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f8c00] >[205100.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f8c00] width 1280 pitch 5120 (/4 1280) >[205101.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a503f0] >[205101.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a503f0] width 1280 pitch 5120 (/4 1280) >[205166.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a83d0] >[205166.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a83d0] width 1280 pitch 5120 (/4 1280) >[205166.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39c17d0] >[205166.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39c17d0] width 1280 pitch 5120 (/4 1280) >[205167.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a74690] >[205167.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a74690] width 1280 pitch 5120 (/4 1280) >[205209.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a74690] >[205209.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a74690] width 1280 pitch 5120 (/4 1280) >[205215.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a6a320] >[205215.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a6a320] width 1280 pitch 5120 (/4 1280) >[205363.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395a910] >[205363.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395a910] width 1280 pitch 5120 (/4 1280) >[205365.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a54a60] >[205365.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a54a60] width 1280 pitch 5120 (/4 1280) >[205437.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3961750] >[205437.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3961750] width 1280 pitch 5120 (/4 1280) >[205437.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a58780] >[205437.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a58780] width 1280 pitch 5120 (/4 1280) >[205438.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a587c0] >[205438.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a587c0] width 1280 pitch 5120 (/4 1280) >[205438.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39370c0] >[205438.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39370c0] width 1280 pitch 5120 (/4 1280) >[205918.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c430] >[205918.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c430] width 1280 pitch 5120 (/4 1280) >[205918.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d9ba0] >[205918.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d9ba0] width 1280 pitch 5120 (/4 1280) >[205924.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aca540] >[205924.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aca540] width 1280 pitch 5120 (/4 1280) >[205924.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac4ab0] >[205924.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac4ab0] width 1280 pitch 5120 (/4 1280) >[205953.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac97d0] >[205953.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac97d0] width 1280 pitch 5120 (/4 1280) >[205953.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad8690] >[205953.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad8690] width 1280 pitch 5120 (/4 1280) >[205959.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23d30] >[205959.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23d30] width 1280 pitch 5120 (/4 1280) >[205959.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1e6d0] >[205959.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1e6d0] width 1280 pitch 5120 (/4 1280) >[205970.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a66930] >[205970.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a66930] width 1280 pitch 5120 (/4 1280) >[205971.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1e070] >[205971.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1e070] width 1280 pitch 5120 (/4 1280) >[205971.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d390] >[205971.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d390] width 1280 pitch 5120 (/4 1280) >[205971.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a66930] >[205971.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a66930] width 1280 pitch 5120 (/4 1280) >[205971.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a66930] >[205971.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a66930] width 1280 pitch 5120 (/4 1280) >[205987.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[205987.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206000.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206000.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206000.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d390] >[206000.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d390] width 1280 pitch 5120 (/4 1280) >[206000.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206000.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206000.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206000.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206000.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206000.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206000.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206000.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206000.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d390] >[206000.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d390] width 1280 pitch 5120 (/4 1280) >[206000.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d390] >[206001.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d390] width 1280 pitch 5120 (/4 1280) >[206001.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206001.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206001.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206001.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206001.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a7d390] >[206001.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a7d390] width 1280 pitch 5120 (/4 1280) >[206001.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206001.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206001.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206001.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206001.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206001.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206005.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37ef0] >[206005.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37ef0] width 1280 pitch 5120 (/4 1280) >[206010.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39870] >[206010.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39870] width 1280 pitch 5120 (/4 1280) >[206010.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1364670] >[206010.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1364670] width 1280 pitch 5120 (/4 1280) >[206010.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206010.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206010.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a69460] >[206010.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a69460] width 1280 pitch 5120 (/4 1280) >[206010.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206010.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206010.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1364670] >[206010.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1364670] width 1280 pitch 5120 (/4 1280) >[206010.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206010.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206010.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a69460] >[206010.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a69460] width 1280 pitch 5120 (/4 1280) >[206010.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206010.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206010.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1364670] >[206010.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1364670] width 1280 pitch 5120 (/4 1280) >[206010.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39870] >[206010.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39870] width 1280 pitch 5120 (/4 1280) >[206010.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3930f00] >[206010.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3930f00] width 1280 pitch 5120 (/4 1280) >[206010.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206010.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206010.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39870] >[206010.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39870] width 1280 pitch 5120 (/4 1280) >[206010.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1364670] >[206010.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1364670] width 1280 pitch 5120 (/4 1280) >[206012.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206012.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206012.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38550] >[206012.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38550] width 1280 pitch 5120 (/4 1280) >[206012.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd2780] >[206012.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd2780] width 1280 pitch 5120 (/4 1280) >[206012.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd2780] >[206012.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd2780] width 1280 pitch 5120 (/4 1280) >[206012.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd2780] >[206012.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd2780] width 1280 pitch 5120 (/4 1280) >[206012.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd2780] >[206012.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd2780] width 1280 pitch 5120 (/4 1280) >[206012.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cb140] >[206012.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cb140] width 1280 pitch 5120 (/4 1280) >[206012.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd2780] >[206012.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd2780] width 1280 pitch 5120 (/4 1280) >[206017.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b217c0] >[206017.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b217c0] width 1280 pitch 5120 (/4 1280) >[206040.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd3640] >[206040.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd3640] width 1280 pitch 5120 (/4 1280) >[206045.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a63080] >[206045.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a63080] width 1280 pitch 5120 (/4 1280) >[206046.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15910] >[206046.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15910] width 1280 pitch 5120 (/4 1280) >[206046.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd1240] >[206046.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd1240] width 1280 pitch 5120 (/4 1280) >[206047.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a62550] >[206047.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a62550] width 1280 pitch 5120 (/4 1280) >[206047.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27fda30] >[206047.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27fda30] width 1280 pitch 5120 (/4 1280) >[206048.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd11a0] >[206048.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd11a0] width 1280 pitch 5120 (/4 1280) >[206048.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b84f60] >[206048.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b84f60] width 1280 pitch 5120 (/4 1280) >[206048.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd11a0] >[206048.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd11a0] width 1280 pitch 5120 (/4 1280) >[206048.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a62550] >[206048.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a62550] width 1280 pitch 5120 (/4 1280) >[206048.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd11a0] >[206048.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd11a0] width 1280 pitch 5120 (/4 1280) >[206048.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a62550] >[206048.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a62550] width 1280 pitch 5120 (/4 1280) >[206048.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd11a0] >[206048.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd11a0] width 1280 pitch 5120 (/4 1280) >[206049.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd0fc0] >[206049.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd0fc0] width 1280 pitch 5120 (/4 1280) >[206049.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d910] >[206049.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d910] width 1280 pitch 5120 (/4 1280) >[206049.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d910] >[206049.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d910] width 1280 pitch 5120 (/4 1280) >[206049.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd55c0] >[206049.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd55c0] width 1280 pitch 5120 (/4 1280) >[206049.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d910] >[206050.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d910] width 1280 pitch 5120 (/4 1280) >[206050.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f3baa0] >[206050.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f3baa0] width 1280 pitch 5120 (/4 1280) >[206050.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d910] >[206050.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d910] width 1280 pitch 5120 (/4 1280) >[206423.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15910] >[206423.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15910] width 1280 pitch 5120 (/4 1280) >[206427.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206427.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206427.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206427.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206427.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206427.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206427.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206427.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206429.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793060] >[206429.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793060] width 1280 pitch 5120 (/4 1280) >[206429.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793060] >[206429.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793060] width 1280 pitch 5120 (/4 1280) >[206429.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793060] >[206429.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793060] width 1280 pitch 5120 (/4 1280) >[206429.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206429.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206429.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206429.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206429.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793060] >[206429.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793060] width 1280 pitch 5120 (/4 1280) >[206429.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206429.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206429.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206429.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206429.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206429.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206430.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793060] >[206430.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793060] width 1280 pitch 5120 (/4 1280) >[206430.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206430.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206430.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206430.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206431.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206431.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206431.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b880] >[206431.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b880] width 1280 pitch 5120 (/4 1280) >[206431.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38da0] >[206431.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38da0] width 1280 pitch 5120 (/4 1280) >[206431.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206431.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206431.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b880] >[206431.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b880] width 1280 pitch 5120 (/4 1280) >[206431.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2730110] >[206431.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2730110] width 1280 pitch 5120 (/4 1280) >[206434.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206434.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206434.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206434.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206434.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b880] >[206434.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b880] width 1280 pitch 5120 (/4 1280) >[206434.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38da0] >[206434.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38da0] width 1280 pitch 5120 (/4 1280) >[206434.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad79a0] >[206434.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad79a0] width 1280 pitch 5120 (/4 1280) >[206434.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b880] >[206434.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b880] width 1280 pitch 5120 (/4 1280) >[206435.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206435.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206435.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbc60] >[206435.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbc60] width 1280 pitch 5120 (/4 1280) >[206435.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235b880] >[206435.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235b880] width 1280 pitch 5120 (/4 1280) >[206436.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206f6f0] >[206436.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206f6f0] width 1280 pitch 5120 (/4 1280) >[206436.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x206f6f0] >[206436.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x206f6f0] width 1280 pitch 5120 (/4 1280) >[206498.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x316af10] >[206498.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x316af10] width 1280 pitch 5120 (/4 1280) >[206943.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38da0] >[206943.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38da0] width 1280 pitch 5120 (/4 1280) >[206944.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b6f0] >[206944.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b6f0] width 1280 pitch 5120 (/4 1280) >[206944.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206944.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206944.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b6f0] >[206944.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b6f0] width 1280 pitch 5120 (/4 1280) >[206944.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206944.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206944.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b6f0] >[206944.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b6f0] width 1280 pitch 5120 (/4 1280) >[206944.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206944.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206944.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b6f0] >[206944.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b6f0] width 1280 pitch 5120 (/4 1280) >[206944.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206944.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206945.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b6f0] >[206945.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b6f0] width 1280 pitch 5120 (/4 1280) >[206946.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206946.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206946.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd3230] >[206946.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd3230] width 1280 pitch 5120 (/4 1280) >[206946.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dc90] >[206946.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dc90] width 1280 pitch 5120 (/4 1280) >[206946.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14b10] >[206946.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14b10] width 1280 pitch 5120 (/4 1280) >[206967.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22234e0] >[206967.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22234e0] width 1280 pitch 5120 (/4 1280) >[206967.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22234e0] >[206967.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22234e0] width 1280 pitch 5120 (/4 1280) >[206967.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22234e0] >[206967.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22234e0] width 1280 pitch 5120 (/4 1280) >[206967.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23c60] >[206967.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23c60] width 1280 pitch 5120 (/4 1280) >[206970.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b04430] >[206970.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b04430] width 1280 pitch 5120 (/4 1280) >[206973.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22234e0] >[206973.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22234e0] width 1280 pitch 5120 (/4 1280) >[206973.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d640] >[206973.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d640] width 1280 pitch 5120 (/4 1280) >[206974.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b314f0] >[206974.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b314f0] width 1280 pitch 5120 (/4 1280) >[206974.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b379a0] >[206974.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b379a0] width 1280 pitch 5120 (/4 1280) >[206974.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b04370] >[206974.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b04370] width 1280 pitch 5120 (/4 1280) >[206974.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b38da0] >[206974.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b38da0] width 1280 pitch 5120 (/4 1280) >[206978.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b126d0] >[206978.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b126d0] width 1280 pitch 5120 (/4 1280) >[206978.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b379a0] >[206978.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b379a0] width 1280 pitch 5120 (/4 1280) >[206979.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b042a0] >[206979.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b042a0] width 1280 pitch 5120 (/4 1280) >[206985.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22234e0] >[206985.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22234e0] width 1280 pitch 5120 (/4 1280) >[206985.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b126d0] >[206985.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b126d0] width 1280 pitch 5120 (/4 1280) >[206990.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23550] >[206990.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23550] width 1280 pitch 5120 (/4 1280) >[207005.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14ad0] >[207005.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14ad0] width 1280 pitch 5120 (/4 1280) >[207005.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b126d0] >[207005.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b126d0] width 1280 pitch 5120 (/4 1280) >[207031.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b43d90] >[207031.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b43d90] width 1280 pitch 5120 (/4 1280) >[207088.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207088.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207089.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b13d50] >[207089.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b13d50] width 1280 pitch 5120 (/4 1280) >[207094.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c990] >[207094.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c990] width 1280 pitch 5120 (/4 1280) >[207098.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b13140] >[207098.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b13140] width 1280 pitch 5120 (/4 1280) >[207099.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b16190] >[207099.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b16190] width 1280 pitch 5120 (/4 1280) >[207099.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0dd50] >[207099.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0dd50] width 1280 pitch 5120 (/4 1280) >[207099.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b13140] >[207099.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b13140] width 1280 pitch 5120 (/4 1280) >[207099.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39500a0] >[207099.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39500a0] width 1280 pitch 5120 (/4 1280) >[207099.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b13bd0] >[207099.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b13bd0] width 1280 pitch 5120 (/4 1280) >[207099.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39500a0] >[207099.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39500a0] width 1280 pitch 5120 (/4 1280) >[207099.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b13bd0] >[207099.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b13bd0] width 1280 pitch 5120 (/4 1280) >[207100.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b470] >[207100.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b470] width 1280 pitch 5120 (/4 1280) >[207100.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b09d80] >[207100.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b09d80] width 1280 pitch 5120 (/4 1280) >[207100.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b48d70] >[207100.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b48d70] width 1280 pitch 5120 (/4 1280) >[207100.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a6cea0] >[207100.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a6cea0] width 1280 pitch 5120 (/4 1280) >[207175.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad9360] >[207175.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad9360] width 1280 pitch 5120 (/4 1280) >[207175.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3965920] >[207175.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3965920] width 1280 pitch 5120 (/4 1280) >[207179.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad9360] >[207179.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad9360] width 1280 pitch 5120 (/4 1280) >[207180.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ad9360] >[207180.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ad9360] width 1280 pitch 5120 (/4 1280) >[207207.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207207.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207207.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207207.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207207.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207208.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207208.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207208.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b339e0] >[207208.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b339e0] width 1280 pitch 5120 (/4 1280) >[207215.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207215.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207215.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207215.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207215.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207215.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207215.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207215.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207215.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207215.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207215.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207215.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207215.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207215.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207215.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2686dd0] >[207215.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2686dd0] width 1280 pitch 5120 (/4 1280) >[207215.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207215.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207215.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207215.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207215.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207215.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207215.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39e0ad0] >[207215.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39e0ad0] width 1280 pitch 5120 (/4 1280) >[207216.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207216.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207216.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207216.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207216.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2d9f0] >[207216.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2d9f0] width 1280 pitch 5120 (/4 1280) >[207216.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207216.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207216.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac9330] >[207216.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac9330] width 1280 pitch 5120 (/4 1280) >[207216.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378e160] >[207216.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378e160] width 1280 pitch 5120 (/4 1280) >[207216.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac9330] >[207216.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac9330] width 1280 pitch 5120 (/4 1280) >[207216.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac9330] >[207216.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac9330] width 1280 pitch 5120 (/4 1280) >[207216.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207216.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207216.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378e160] >[207216.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378e160] width 1280 pitch 5120 (/4 1280) >[207217.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378e160] >[207217.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378e160] width 1280 pitch 5120 (/4 1280) >[207217.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378e160] >[207217.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378e160] width 1280 pitch 5120 (/4 1280) >[207217.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378e160] >[207217.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378e160] width 1280 pitch 5120 (/4 1280) >[207217.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a98d50] >[207217.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a98d50] width 1280 pitch 5120 (/4 1280) >[207217.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2679ab0] >[207217.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2679ab0] width 1280 pitch 5120 (/4 1280) >[207217.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207217.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207217.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207217.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207217.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207217.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207217.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207217.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207217.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207217.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207217.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207218.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7a770] >[207218.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7a770] width 1280 pitch 5120 (/4 1280) >[207218.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207218.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207219.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2218fa0] >[207219.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2218fa0] width 1280 pitch 5120 (/4 1280) >[207239.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36220] >[207239.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36220] width 1280 pitch 5120 (/4 1280) >[207239.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207239.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207239.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36220] >[207239.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36220] width 1280 pitch 5120 (/4 1280) >[207239.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207239.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207271.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383cad0] >[207271.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383cad0] width 1280 pitch 5120 (/4 1280) >[207271.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e110] >[207271.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e110] width 1280 pitch 5120 (/4 1280) >[207271.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24dbd30] >[207271.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24dbd30] width 1280 pitch 5120 (/4 1280) >[207271.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14550] >[207271.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14550] width 1280 pitch 5120 (/4 1280) >[207271.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a0190] >[207271.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a0190] width 1280 pitch 5120 (/4 1280) >[207272.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10fab50] >[207272.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10fab50] width 1280 pitch 5120 (/4 1280) >[207272.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383cad0] >[207272.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383cad0] width 1280 pitch 5120 (/4 1280) >[207272.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a84b0] >[207272.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a84b0] width 1280 pitch 5120 (/4 1280) >[207272.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2222e00] >[207272.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2222e00] width 1280 pitch 5120 (/4 1280) >[207272.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a84b0] >[207272.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a84b0] width 1280 pitch 5120 (/4 1280) >[207275.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2222e00] >[207275.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2222e00] width 1280 pitch 5120 (/4 1280) >[207459.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afb200] >[207459.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afb200] width 1280 pitch 5120 (/4 1280) >[207460.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a9e2b0] >[207460.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a9e2b0] width 1280 pitch 5120 (/4 1280) >[207460.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2218710] >[207460.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2218710] width 1280 pitch 5120 (/4 1280) >[207460.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcede0] >[207460.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcede0] width 1280 pitch 5120 (/4 1280) >[207460.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcede0] >[207460.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcede0] width 1280 pitch 5120 (/4 1280) >[207512.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d763c0] >[207512.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d763c0] width 1280 pitch 5120 (/4 1280) >[207512.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d763c0] >[207512.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d763c0] width 1280 pitch 5120 (/4 1280) >[207651.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3ac60] >[207651.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3ac60] width 1280 pitch 5120 (/4 1280) >[207651.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af66c0] >[207651.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af66c0] width 1280 pitch 5120 (/4 1280) >[207656.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914ec0] >[207656.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914ec0] width 1280 pitch 5120 (/4 1280) >[207656.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5bc90] >[207656.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5bc90] width 1280 pitch 5120 (/4 1280) >[207657.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5bc90] >[207657.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5bc90] width 1280 pitch 5120 (/4 1280) >[207657.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2914ec0] >[207657.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2914ec0] width 1280 pitch 5120 (/4 1280) >[207712.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1db10] >[207712.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1db10] width 1280 pitch 5120 (/4 1280) >[207715.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b77a10] >[207715.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b77a10] width 1280 pitch 5120 (/4 1280) >[207715.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3862960] >[207715.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3862960] width 1280 pitch 5120 (/4 1280) >[207715.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b1e0] >[207715.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b1e0] width 1280 pitch 5120 (/4 1280) >[207715.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b6c150] >[207715.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b6c150] width 1280 pitch 5120 (/4 1280) >[207715.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b6c150] >[207715.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b6c150] width 1280 pitch 5120 (/4 1280) >[207717.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b1e0] >[207717.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b1e0] width 1280 pitch 5120 (/4 1280) >[207718.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b1e0] >[207718.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b1e0] width 1280 pitch 5120 (/4 1280) >[207718.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b92b10] >[207718.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b92b10] width 1280 pitch 5120 (/4 1280) >[207718.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266b1e0] >[207718.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266b1e0] width 1280 pitch 5120 (/4 1280) >[207718.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b6c150] >[207718.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b6c150] width 1280 pitch 5120 (/4 1280) >[207718.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a6cda0] >[207718.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a6cda0] width 1280 pitch 5120 (/4 1280) >[207719.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2217e10] >[207719.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2217e10] width 1280 pitch 5120 (/4 1280) >[207737.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f190] >[207737.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f190] width 1280 pitch 5120 (/4 1280) >[207758.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ac70d0] >[207758.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ac70d0] width 1280 pitch 5120 (/4 1280) >[207758.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3d020] >[207758.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3d020] width 1280 pitch 5120 (/4 1280) >[207924.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2aa70] >[207924.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2aa70] width 1280 pitch 5120 (/4 1280) >[207924.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b29f40] >[207924.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b29f40] width 1280 pitch 5120 (/4 1280) >[208655.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa18b0] >[208655.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa18b0] width 1280 pitch 5120 (/4 1280) >[208673.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b6ce90] >[208673.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b6ce90] width 1280 pitch 5120 (/4 1280) >[208673.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa70b0] >[208673.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa70b0] width 1280 pitch 5120 (/4 1280) >[208682.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1105850] >[208682.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1105850] width 1280 pitch 5120 (/4 1280) >[208683.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa14b0] >[208683.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa14b0] width 1280 pitch 5120 (/4 1280) >[208685.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1ccc0] >[208685.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1ccc0] width 1280 pitch 5120 (/4 1280) >[208687.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39f60] >[208687.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39f60] width 1280 pitch 5120 (/4 1280) >[208687.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc2a0] >[208687.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc2a0] width 1280 pitch 5120 (/4 1280) >[208687.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39f60] >[208687.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39f60] width 1280 pitch 5120 (/4 1280) >[208687.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c880] >[208687.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c880] width 1280 pitch 5120 (/4 1280) >[208687.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a776e0] >[208687.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a776e0] width 1280 pitch 5120 (/4 1280) >[208687.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddc570] >[208687.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddc570] width 1280 pitch 5120 (/4 1280) >[208688.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a776e0] >[208688.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a776e0] width 1280 pitch 5120 (/4 1280) >[208688.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddc570] >[208688.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddc570] width 1280 pitch 5120 (/4 1280) >[208688.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a776e0] >[208688.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a776e0] width 1280 pitch 5120 (/4 1280) >[208688.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a97540] >[208688.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a97540] width 1280 pitch 5120 (/4 1280) >[208688.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a2b0] >[208688.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a2b0] width 1280 pitch 5120 (/4 1280) >[208688.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1c250] >[208688.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1c250] width 1280 pitch 5120 (/4 1280) >[208688.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b775d0] >[208688.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b775d0] width 1280 pitch 5120 (/4 1280) >[208688.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1c250] >[208688.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1c250] width 1280 pitch 5120 (/4 1280) >[208688.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aaa1d0] >[208688.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aaa1d0] width 1280 pitch 5120 (/4 1280) >[208688.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc2a0] >[208688.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc2a0] width 1280 pitch 5120 (/4 1280) >[208688.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1c250] >[208688.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1c250] width 1280 pitch 5120 (/4 1280) >[208688.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc2a0] >[208688.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc2a0] width 1280 pitch 5120 (/4 1280) >[208688.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa5a10] >[208688.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa5a10] width 1280 pitch 5120 (/4 1280) >[208688.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1c250] >[208688.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1c250] width 1280 pitch 5120 (/4 1280) >[208688.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa5a10] >[208688.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa5a10] width 1280 pitch 5120 (/4 1280) >[208688.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208688.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208688.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa5a10] >[208688.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa5a10] width 1280 pitch 5120 (/4 1280) >[208688.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208688.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208688.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8da0] >[208688.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8da0] width 1280 pitch 5120 (/4 1280) >[208688.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208688.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208688.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8d40] >[208688.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8d40] width 1280 pitch 5120 (/4 1280) >[208688.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208688.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208688.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8d40] >[208688.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8d40] width 1280 pitch 5120 (/4 1280) >[208688.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc2a0] >[208688.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc2a0] width 1280 pitch 5120 (/4 1280) >[208688.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8d40] >[208688.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8d40] width 1280 pitch 5120 (/4 1280) >[208688.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208688.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208688.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8d40] >[208688.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8d40] width 1280 pitch 5120 (/4 1280) >[208689.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208689.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208689.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a98690] >[208689.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a98690] width 1280 pitch 5120 (/4 1280) >[208689.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a985c0] >[208689.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a985c0] width 1280 pitch 5120 (/4 1280) >[208689.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a98690] >[208689.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a98690] width 1280 pitch 5120 (/4 1280) >[208689.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208689.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208689.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8d40] >[208689.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8d40] width 1280 pitch 5120 (/4 1280) >[208689.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa8da0] >[208689.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa8da0] width 1280 pitch 5120 (/4 1280) >[208689.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a270] >[208689.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a270] width 1280 pitch 5120 (/4 1280) >[208689.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a985c0] >[208689.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a985c0] width 1280 pitch 5120 (/4 1280) >[208689.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a985c0] >[208689.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a985c0] width 1280 pitch 5120 (/4 1280) >[208695.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afb110] >[208695.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afb110] width 1280 pitch 5120 (/4 1280) >[208924.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba70b0] >[208924.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba70b0] width 1280 pitch 5120 (/4 1280) >[208924.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9cf70] >[208924.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9cf70] width 1280 pitch 5120 (/4 1280) >[208956.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba0f50] >[208956.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba0f50] width 1280 pitch 5120 (/4 1280) >[208965.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b880b0] >[208965.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b880b0] width 1280 pitch 5120 (/4 1280) >[208965.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa51f0] >[208965.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa51f0] width 1280 pitch 5120 (/4 1280) >[209055.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b812e0] >[209055.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b812e0] width 1280 pitch 5120 (/4 1280) >[209055.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc07a0] >[209055.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc07a0] width 1280 pitch 5120 (/4 1280) >[209176.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdeac0] >[209176.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdeac0] width 1280 pitch 5120 (/4 1280) >[209176.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[209176.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[209418.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57050] >[209418.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57050] width 1280 pitch 5120 (/4 1280) >[209418.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c589f0] >[209418.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c589f0] width 1280 pitch 5120 (/4 1280) >[209501.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f030] >[209501.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f030] width 1280 pitch 5120 (/4 1280) >[209501.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60c70] >[209501.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60c70] width 1280 pitch 5120 (/4 1280) >[209591.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdeac0] >[209591.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdeac0] width 1280 pitch 5120 (/4 1280) >[209634.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31680] >[209634.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31680] width 1280 pitch 5120 (/4 1280) >[209634.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2fd90] >[209634.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2fd90] width 1280 pitch 5120 (/4 1280) >[209705.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20c70] >[209705.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20c70] width 1280 pitch 5120 (/4 1280) >[209705.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20c70] >[209705.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20c70] width 1280 pitch 5120 (/4 1280) >[210102.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3130070] >[210102.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3130070] width 1280 pitch 5120 (/4 1280) >[210104.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c39cf0] >[210104.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c39cf0] width 1280 pitch 5120 (/4 1280) >[210116.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210116.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210116.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bd00] >[210116.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bd00] width 1280 pitch 5120 (/4 1280) >[210116.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210116.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210116.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bd00] >[210116.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bd00] width 1280 pitch 5120 (/4 1280) >[210116.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210116.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210116.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bd00] >[210116.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bd00] width 1280 pitch 5120 (/4 1280) >[210116.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210116.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210116.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bd00] >[210116.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bd00] width 1280 pitch 5120 (/4 1280) >[210116.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210116.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210116.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210117.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210117.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210117.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210117.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d090] >[210117.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d090] width 1280 pitch 5120 (/4 1280) >[210117.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c671b0] >[210117.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c671b0] width 1280 pitch 5120 (/4 1280) >[210117.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c671b0] >[210117.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c671b0] width 1280 pitch 5120 (/4 1280) >[210117.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c671b0] >[210117.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c671b0] width 1280 pitch 5120 (/4 1280) >[210117.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c671b0] >[210117.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c671b0] width 1280 pitch 5120 (/4 1280) >[210117.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c671b0] >[210117.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c671b0] width 1280 pitch 5120 (/4 1280) >[210117.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210117.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210117.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210117.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210117.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d090] >[210117.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d090] width 1280 pitch 5120 (/4 1280) >[210117.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210117.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210117.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d090] >[210117.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d090] width 1280 pitch 5120 (/4 1280) >[210117.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210118.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210118.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d090] >[210118.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d090] width 1280 pitch 5120 (/4 1280) >[210118.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210118.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210118.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d090] >[210118.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d090] width 1280 pitch 5120 (/4 1280) >[210118.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40fc0] >[210118.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40fc0] width 1280 pitch 5120 (/4 1280) >[210118.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210118.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210118.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210118.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210118.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210118.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210118.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210118.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210118.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210118.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210118.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c757e0] >[210118.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c757e0] width 1280 pitch 5120 (/4 1280) >[210118.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfac0] >[210118.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfac0] width 1280 pitch 5120 (/4 1280) >[210337.726] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[210337.726] (II) RADEON(0): Printing DDC gathered Modelines: >[210337.726] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[211145.824] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[211145.824] (II) RADEON(0): Printing DDC gathered Modelines: >[211145.824] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[211235.890] (II) RADEON(0): RADEONSaveScreen(2) >[211235.890] (II) RADEON(0): RADEONSaveScreen(0) >[214114.165] (II) RADEON(0): RADEONSaveScreen(1) >[214119.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ae1f80] >[214119.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ae1f80] width 1280 pitch 5120 (/4 1280) >[214119.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb0f0] >[214119.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb0f0] width 1280 pitch 5120 (/4 1280) >[214119.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f650] >[214119.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f650] width 1280 pitch 5120 (/4 1280) >[214126.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb0f0] >[214126.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb0f0] width 1280 pitch 5120 (/4 1280) >[214126.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb0f0] >[214126.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb0f0] width 1280 pitch 5120 (/4 1280) >[214126.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214126.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214126.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214126.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214126.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214127.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38766b0] >[214127.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38766b0] width 1280 pitch 5120 (/4 1280) >[214127.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbb0f0] >[214127.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbb0f0] width 1280 pitch 5120 (/4 1280) >[214128.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d23230] >[214128.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d23230] width 1280 pitch 5120 (/4 1280) >[214128.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793270] >[214128.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793270] width 1280 pitch 5120 (/4 1280) >[214128.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3793270] >[214128.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3793270] width 1280 pitch 5120 (/4 1280) >[214128.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214128.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d23230] >[214128.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d23230] width 1280 pitch 5120 (/4 1280) >[214128.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d23230] >[214128.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d23230] width 1280 pitch 5120 (/4 1280) >[214128.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd6b0] >[214128.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd6b0] width 1280 pitch 5120 (/4 1280) >[214128.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b200] >[214128.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b200] width 1280 pitch 5120 (/4 1280) >[214207.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbb690] >[214207.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbb690] width 1280 pitch 5120 (/4 1280) >[214207.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be56f0] >[214207.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be56f0] width 1280 pitch 5120 (/4 1280) >[214746.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b7b720] >[214746.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b7b720] width 1280 pitch 5120 (/4 1280) >[214746.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79710] >[214746.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79710] width 1280 pitch 5120 (/4 1280) >[214746.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc4e0] >[214746.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc4e0] width 1280 pitch 5120 (/4 1280) >[214746.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc4e0] >[214746.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc4e0] width 1280 pitch 5120 (/4 1280) >[214901.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8a960] >[214901.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8a960] width 1280 pitch 5120 (/4 1280) >[214902.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccf4c0] >[214902.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccf4c0] width 1280 pitch 5120 (/4 1280) >[214903.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3199070] >[214903.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3199070] width 1280 pitch 5120 (/4 1280) >[214911.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79480] >[214911.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79480] width 1280 pitch 5120 (/4 1280) >[214911.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79480] >[214911.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79480] width 1280 pitch 5120 (/4 1280) >[214942.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb770] >[214942.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb770] width 1280 pitch 5120 (/4 1280) >[214944.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cce140] >[214944.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cce140] width 1280 pitch 5120 (/4 1280) >[214946.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3156730] >[214946.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3156730] width 1280 pitch 5120 (/4 1280) >[214946.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cce1c0] >[214946.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cce1c0] width 1280 pitch 5120 (/4 1280) >[214948.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d28f20] >[214948.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d28f20] width 1280 pitch 5120 (/4 1280) >[214949.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3156730] >[214949.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3156730] width 1280 pitch 5120 (/4 1280) >[214965.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1f530] >[214965.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1f530] width 1280 pitch 5120 (/4 1280) >[214968.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83e70] >[214968.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83e70] width 1280 pitch 5120 (/4 1280) >[215023.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d157c0] >[215023.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d157c0] width 1280 pitch 5120 (/4 1280) >[215023.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d157c0] >[215023.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d157c0] width 1280 pitch 5120 (/4 1280) >[215488.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c82a30] >[215488.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c82a30] width 1280 pitch 5120 (/4 1280) >[215489.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c82be0] >[215489.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c82be0] width 1280 pitch 5120 (/4 1280) >[215497.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c82a50] >[215497.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c82a50] width 1280 pitch 5120 (/4 1280) >[215497.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c82a50] >[215497.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c82a50] width 1280 pitch 5120 (/4 1280) >[215821.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03420] >[215821.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03420] width 1280 pitch 5120 (/4 1280) >[215821.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03420] >[215821.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03420] width 1280 pitch 5120 (/4 1280) >[215902.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[215902.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216382.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216382.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216382.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d28700] >[216382.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d28700] width 1280 pitch 5120 (/4 1280) >[216382.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216382.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216382.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c904b0] >[216382.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c904b0] width 1280 pitch 5120 (/4 1280) >[216382.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216382.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216382.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cee0] >[216382.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cee0] width 1280 pitch 5120 (/4 1280) >[216382.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d28700] >[216382.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d28700] width 1280 pitch 5120 (/4 1280) >[216382.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216382.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216382.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216382.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216382.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cee0] >[216382.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cee0] width 1280 pitch 5120 (/4 1280) >[216382.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216382.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216382.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216382.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216382.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216383.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216383.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d28700] >[216383.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d28700] width 1280 pitch 5120 (/4 1280) >[216383.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cee0] >[216383.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cee0] width 1280 pitch 5120 (/4 1280) >[216383.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216383.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216383.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216383.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216383.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216383.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216383.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216383.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216383.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216383.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216383.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216383.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216383.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216383.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216384.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216384.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216384.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216384.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216384.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe620] >[216384.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe620] width 1280 pitch 5120 (/4 1280) >[216384.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216384.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216385.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216385.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216385.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cee0] >[216385.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cee0] width 1280 pitch 5120 (/4 1280) >[216385.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216385.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216385.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cee0] >[216385.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cee0] width 1280 pitch 5120 (/4 1280) >[216385.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bbe0] >[216385.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bbe0] width 1280 pitch 5120 (/4 1280) >[216385.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9bfc0] >[216385.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9bfc0] width 1280 pitch 5120 (/4 1280) >[216572.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2e60] >[216572.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2e60] width 1280 pitch 5120 (/4 1280) >[216572.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2e60] >[216572.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2e60] width 1280 pitch 5120 (/4 1280) >[216573.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2e60] >[216573.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2e60] width 1280 pitch 5120 (/4 1280) >[216573.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2b50] >[216573.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2b50] width 1280 pitch 5120 (/4 1280) >[216588.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4290] >[216588.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4290] width 1280 pitch 5120 (/4 1280) >[216588.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216588.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216666.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216666.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216666.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216666.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216666.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216666.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216666.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216666.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216666.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216666.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216666.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216666.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216667.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216667.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216667.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216667.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216667.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216667.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216667.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216667.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216667.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216667.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216667.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbde30] >[216667.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbde30] width 1280 pitch 5120 (/4 1280) >[216667.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afe810] >[216667.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afe810] width 1280 pitch 5120 (/4 1280) >[216667.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf3b0] >[216667.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf3b0] width 1280 pitch 5120 (/4 1280) >[216667.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc7b0] >[216667.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc7b0] width 1280 pitch 5120 (/4 1280) >[216667.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc7b0] >[216667.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc7b0] width 1280 pitch 5120 (/4 1280) >[216667.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc7b0] >[216667.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc7b0] width 1280 pitch 5120 (/4 1280) >[216667.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc7b0] >[216667.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc7b0] width 1280 pitch 5120 (/4 1280) >[216667.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc950] >[216667.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc950] width 1280 pitch 5120 (/4 1280) >[216667.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf200] >[216667.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf200] width 1280 pitch 5120 (/4 1280) >[216667.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf1a0] >[216667.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf1a0] width 1280 pitch 5120 (/4 1280) >[216667.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdc870] >[216667.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdc870] width 1280 pitch 5120 (/4 1280) >[216667.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf210] >[216667.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf210] width 1280 pitch 5120 (/4 1280) >[216667.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf1a0] >[216667.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf1a0] width 1280 pitch 5120 (/4 1280) >[216667.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf1a0] >[216667.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf1a0] width 1280 pitch 5120 (/4 1280) >[216667.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216667.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216667.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf1a0] >[216667.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf1a0] width 1280 pitch 5120 (/4 1280) >[216682.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216682.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216682.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4710] >[216682.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4710] width 1280 pitch 5120 (/4 1280) >[216683.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00a90] >[216683.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00a90] width 1280 pitch 5120 (/4 1280) >[216683.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4710] >[216683.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4710] width 1280 pitch 5120 (/4 1280) >[216702.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4d80] >[216702.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4d80] width 1280 pitch 5120 (/4 1280) >[216702.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2100] >[216702.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2100] width 1280 pitch 5120 (/4 1280) >[216722.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4710] >[216722.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4710] width 1280 pitch 5120 (/4 1280) >[216722.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d10f10] >[216722.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d10f10] width 1280 pitch 5120 (/4 1280) >[216777.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4710] >[216777.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4710] width 1280 pitch 5120 (/4 1280) >[216777.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce2100] >[216777.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce2100] width 1280 pitch 5120 (/4 1280) >[216858.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64fb0] >[216858.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64fb0] width 1280 pitch 5120 (/4 1280) >[216858.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91500] >[216858.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91500] width 1280 pitch 5120 (/4 1280) >[216874.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[216874.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[216914.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cba5c0] >[216914.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cba5c0] width 1280 pitch 5120 (/4 1280) >[216914.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d35060] >[216914.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d35060] width 1280 pitch 5120 (/4 1280) >[217239.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4d80] >[217239.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4d80] width 1280 pitch 5120 (/4 1280) >[217245.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4d80] >[217245.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4d80] width 1280 pitch 5120 (/4 1280) >[217253.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217253.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217253.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d387c0] >[217253.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d387c0] width 1280 pitch 5120 (/4 1280) >[217254.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217254.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217254.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d387c0] >[217254.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d387c0] width 1280 pitch 5120 (/4 1280) >[217254.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217254.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217254.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d387c0] >[217254.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d387c0] width 1280 pitch 5120 (/4 1280) >[217254.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217254.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217254.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d387c0] >[217254.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d387c0] width 1280 pitch 5120 (/4 1280) >[217254.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217254.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217254.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d387c0] >[217254.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d387c0] width 1280 pitch 5120 (/4 1280) >[217254.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217254.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217255.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217255.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217255.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99160] >[217255.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99160] width 1280 pitch 5120 (/4 1280) >[217255.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217255.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217255.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99160] >[217255.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99160] width 1280 pitch 5120 (/4 1280) >[217255.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d015f0] >[217255.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d015f0] width 1280 pitch 5120 (/4 1280) >[217292.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a460] >[217292.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a460] width 1280 pitch 5120 (/4 1280) >[217292.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x267e120] >[217292.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x267e120] width 1280 pitch 5120 (/4 1280) >[217516.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d63d90] >[217516.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d63d90] width 1280 pitch 5120 (/4 1280) >[217517.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d2eb20] >[217517.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d2eb20] width 1280 pitch 5120 (/4 1280) >[217599.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d44b20] >[217599.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d44b20] width 1280 pitch 5120 (/4 1280) >[217599.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x387e200] >[217599.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x387e200] width 1280 pitch 5120 (/4 1280) >[217600.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49b30] >[217600.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49b30] width 1280 pitch 5120 (/4 1280) >[217643.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11490] >[217643.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11490] width 1280 pitch 5120 (/4 1280) >[217644.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baec80] >[217644.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baec80] width 1280 pitch 5120 (/4 1280) >[217644.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d36ec0] >[217645.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d36ec0] width 1280 pitch 5120 (/4 1280) >[217645.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd8ae0] >[217645.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd8ae0] width 1280 pitch 5120 (/4 1280) >[217859.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d553b0] >[217859.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d553b0] width 1280 pitch 5120 (/4 1280) >[217859.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b57720] >[217859.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b57720] width 1280 pitch 5120 (/4 1280) >[218189.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ec40] >[218189.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ec40] width 1280 pitch 5120 (/4 1280) >[218189.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b48390] >[218189.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b48390] width 1280 pitch 5120 (/4 1280) >[218488.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218488.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218488.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218488.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218488.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218488.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218488.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218488.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218488.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218489.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218489.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218489.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218489.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218489.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218489.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afaf30] >[218489.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afaf30] width 1280 pitch 5120 (/4 1280) >[218489.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218489.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218489.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218489.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218489.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218489.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218489.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218489.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218504.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218504.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218504.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218504.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218504.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218504.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218504.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218504.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218504.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218504.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218504.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218504.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218504.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218504.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218504.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218504.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218504.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218504.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218505.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218505.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218505.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218505.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218505.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218505.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218505.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d66c90] >[218505.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d66c90] width 1280 pitch 5120 (/4 1280) >[218505.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d66c90] >[218505.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d66c90] width 1280 pitch 5120 (/4 1280) >[218505.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218505.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218505.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d614e0] >[218505.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d614e0] width 1280 pitch 5120 (/4 1280) >[218505.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218505.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218524.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218524.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218524.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233fa50] >[218524.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233fa50] width 1280 pitch 5120 (/4 1280) >[218766.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7f460] >[218766.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7f460] width 1280 pitch 5120 (/4 1280) >[218766.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24af9e0] >[218766.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24af9e0] width 1280 pitch 5120 (/4 1280) >[219258.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6d5d0] >[219258.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6d5d0] width 1280 pitch 5120 (/4 1280) >[219258.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6e010] >[219258.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6e010] width 1280 pitch 5120 (/4 1280) >[219433.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0980] >[219433.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0980] width 1280 pitch 5120 (/4 1280) >[219433.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7160] >[219433.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7160] width 1280 pitch 5120 (/4 1280) >[219645.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db06d0] >[219645.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db06d0] width 1280 pitch 5120 (/4 1280) >[219647.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db06d0] >[219647.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db06d0] width 1280 pitch 5120 (/4 1280) >[219779.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1540] >[219779.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1540] width 1280 pitch 5120 (/4 1280) >[219779.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd2720] >[219779.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd2720] width 1280 pitch 5120 (/4 1280) >[219780.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced260] >[219780.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced260] width 1280 pitch 5120 (/4 1280) >[219780.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced260] >[219780.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced260] width 1280 pitch 5120 (/4 1280) >[220295.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdf60] >[220295.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdf60] width 1280 pitch 5120 (/4 1280) >[220296.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x150f600] >[220296.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x150f600] width 1280 pitch 5120 (/4 1280) >[220372.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1210] >[220372.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1210] width 1280 pitch 5120 (/4 1280) >[220386.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db35f0] >[220386.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db35f0] width 1280 pitch 5120 (/4 1280) >[220386.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db35f0] >[220386.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db35f0] width 1280 pitch 5120 (/4 1280) >[220386.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1210] >[220386.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1210] width 1280 pitch 5120 (/4 1280) >[220386.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db35f0] >[220386.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db35f0] width 1280 pitch 5120 (/4 1280) >[220397.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd9c00] >[220397.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd9c00] width 1280 pitch 5120 (/4 1280) >[220397.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd9c00] >[220397.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd9c00] width 1280 pitch 5120 (/4 1280) >[220486.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220486.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50] >[220486.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1280 pitch 5120 (/4 1280) >[220486.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220486.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50] >[220486.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1280 pitch 5120 (/4 1280) >[220486.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220486.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50] >[220486.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1280 pitch 5120 (/4 1280) >[220486.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220486.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50] >[220486.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1280 pitch 5120 (/4 1280) >[220486.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220486.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50] >[220486.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1280 pitch 5120 (/4 1280) >[220486.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6510] >[220486.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6510] width 1280 pitch 5120 (/4 1280) >[220788.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dce7d0] >[220788.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dce7d0] width 1280 pitch 5120 (/4 1280) >[220788.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd5530] >[220788.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd5530] width 1280 pitch 5120 (/4 1280) >[220788.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d32f70] >[220788.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d32f70] width 1280 pitch 5120 (/4 1280) >[220793.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dddde0] >[220793.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dddde0] width 1280 pitch 5120 (/4 1280) >[221086.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d32f70] >[221086.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d32f70] width 1280 pitch 5120 (/4 1280) >[221086.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dddde0] >[221086.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dddde0] width 1280 pitch 5120 (/4 1280) >[221086.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d32f70] >[221086.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d32f70] width 1280 pitch 5120 (/4 1280) >[221086.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dddde0] >[221086.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dddde0] width 1280 pitch 5120 (/4 1280) >[221086.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d32f70] >[221086.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d32f70] width 1280 pitch 5120 (/4 1280) >[221086.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dddde0] >[221086.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dddde0] width 1280 pitch 5120 (/4 1280) >[221086.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d32f70] >[221086.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d32f70] width 1280 pitch 5120 (/4 1280) >[221086.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dddde0] >[221086.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dddde0] width 1280 pitch 5120 (/4 1280) >[221087.309] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[221087.309] (II) RADEON(0): Printing DDC gathered Modelines: >[221087.309] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[221176.899] (II) RADEON(0): RADEONSaveScreen(2) >[221176.899] (II) RADEON(0): RADEONSaveScreen(0) >[223959.527] (II) RADEON(0): RADEONSaveScreen(1) >[223963.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c0c0] >[223963.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c0c0] width 1280 pitch 5120 (/4 1280) >[223964.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df80c0] >[223964.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df80c0] width 1280 pitch 5120 (/4 1280) >[223964.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c0c0] >[223964.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c0c0] width 1280 pitch 5120 (/4 1280) >[223964.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df80c0] >[223964.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df80c0] width 1280 pitch 5120 (/4 1280) >[223964.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c0c0] >[223964.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c0c0] width 1280 pitch 5120 (/4 1280) >[224598.930] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[224598.930] (II) RADEON(0): Printing DDC gathered Modelines: >[224598.930] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[224688.887] (II) RADEON(0): RADEONSaveScreen(2) >[224688.887] (II) RADEON(0): RADEONSaveScreen(0) >[225843.622] (II) RADEON(0): RADEONSaveScreen(1) >[225848.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da4f80] >[225848.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da4f80] width 1280 pitch 5120 (/4 1280) >[225848.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54fe0] >[225848.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54fe0] width 1280 pitch 5120 (/4 1280) >[225848.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51640] >[225848.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51640] width 1280 pitch 5120 (/4 1280) >[225918.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d553b0] >[225919.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d553b0] width 1280 pitch 5120 (/4 1280) >[225919.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9e0b0] >[225919.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9e0b0] width 1280 pitch 5120 (/4 1280) >[225919.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd06f0] >[225919.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd06f0] width 1280 pitch 5120 (/4 1280) >[225919.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd06f0] >[225919.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd06f0] width 1280 pitch 5120 (/4 1280) >[225927.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b071b0] >[225927.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b071b0] width 1280 pitch 5120 (/4 1280) >[225927.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b071b0] >[225927.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b071b0] width 1280 pitch 5120 (/4 1280) >[225927.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9e0b0] >[225927.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9e0b0] width 1280 pitch 5120 (/4 1280) >[225928.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b071b0] >[225928.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b071b0] width 1280 pitch 5120 (/4 1280) >[226016.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226016.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226016.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226016.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226016.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226016.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226016.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226016.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226016.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226016.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226016.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226016.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226016.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226016.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226016.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9da10] >[226016.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9da10] width 1280 pitch 5120 (/4 1280) >[226016.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e04f50] >[226016.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e04f50] width 1280 pitch 5120 (/4 1280) >[226016.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13410] >[226016.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13410] width 1280 pitch 5120 (/4 1280) >[226016.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e04f50] >[226016.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e04f50] width 1280 pitch 5120 (/4 1280) >[226016.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13410] >[226016.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13410] width 1280 pitch 5120 (/4 1280) >[226017.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226017.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226017.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226017.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226017.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226017.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226017.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226017.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226017.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226017.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226017.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226017.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226017.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226017.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226017.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96f70] >[226017.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96f70] width 1280 pitch 5120 (/4 1280) >[226018.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d815d0] >[226018.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d815d0] width 1280 pitch 5120 (/4 1280) >[226018.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226018.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226018.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd5940] >[226018.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd5940] width 1280 pitch 5120 (/4 1280) >[226018.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d978d0] >[226018.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d978d0] width 1280 pitch 5120 (/4 1280) >[226018.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226018.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226018.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d978d0] >[226018.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d978d0] width 1280 pitch 5120 (/4 1280) >[226018.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226018.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226018.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9da10] >[226018.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9da10] width 1280 pitch 5120 (/4 1280) >[226018.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226018.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226018.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9da10] >[226018.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9da10] width 1280 pitch 5120 (/4 1280) >[226018.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd6570] >[226019.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd6570] width 1280 pitch 5120 (/4 1280) >[226019.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226019.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226019.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226019.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226019.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51e50] >[226019.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51e50] width 1280 pitch 5120 (/4 1280) >[226019.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226019.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226022.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x10f6a10] >[226022.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x10f6a10] width 1280 pitch 5120 (/4 1280) >[226025.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d18300] >[226025.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d18300] width 1280 pitch 5120 (/4 1280) >[226025.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d18300] >[226025.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d18300] width 1280 pitch 5120 (/4 1280) >[226126.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226126.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226127.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45e30] >[226127.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45e30] width 1280 pitch 5120 (/4 1280) >[226127.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45e30] >[226127.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45e30] width 1280 pitch 5120 (/4 1280) >[226127.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[226127.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[226127.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45e30] >[226127.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45e30] width 1280 pitch 5120 (/4 1280) >[226128.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45e30] >[226128.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45e30] width 1280 pitch 5120 (/4 1280) >[226128.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226128.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de56a0] >[226149.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de56a0] width 1280 pitch 5120 (/4 1280) >[226149.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de56a0] >[226149.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de56a0] width 1280 pitch 5120 (/4 1280) >[226149.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de56a0] >[226149.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de56a0] width 1280 pitch 5120 (/4 1280) >[226149.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de56a0] >[226149.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de56a0] width 1280 pitch 5120 (/4 1280) >[226149.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de56a0] >[226149.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de56a0] width 1280 pitch 5120 (/4 1280) >[226149.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df68a0] >[226149.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df68a0] width 1280 pitch 5120 (/4 1280) >[226149.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45e30] >[226149.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45e30] width 1280 pitch 5120 (/4 1280) >[226149.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226149.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71a60] >[226149.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71a60] width 1280 pitch 5120 (/4 1280) >[226149.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226149.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226153.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e413a0] >[226153.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e413a0] width 1280 pitch 5120 (/4 1280) >[226272.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226272.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226272.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e41160] >[226272.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e41160] width 1280 pitch 5120 (/4 1280) >[226272.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9da10] >[226272.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9da10] width 1280 pitch 5120 (/4 1280) >[226272.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13410] >[226272.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13410] width 1280 pitch 5120 (/4 1280) >[226272.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e41160] >[226272.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e41160] width 1280 pitch 5120 (/4 1280) >[226274.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e43640] >[226274.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e43640] width 1280 pitch 5120 (/4 1280) >[226274.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3881a50] >[226274.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3881a50] width 1280 pitch 5120 (/4 1280) >[226274.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e13290] >[226274.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e13290] width 1280 pitch 5120 (/4 1280) >[226411.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423fdd0] >[226411.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423fdd0] width 1280 pitch 5120 (/4 1280) >[226411.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423fdd0] >[226411.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423fdd0] width 1280 pitch 5120 (/4 1280) >[226411.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423fdd0] >[226411.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423fdd0] width 1280 pitch 5120 (/4 1280) >[226411.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423fdd0] >[226411.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423fdd0] width 1280 pitch 5120 (/4 1280) >[226418.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dee3f0] >[226418.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dee3f0] width 1280 pitch 5120 (/4 1280) >[226418.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dee3f0] >[226418.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dee3f0] width 1280 pitch 5120 (/4 1280) >[226700.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f234c0] >[226700.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f234c0] width 1280 pitch 5120 (/4 1280) >[226700.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dee820] >[226700.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dee820] width 1280 pitch 5120 (/4 1280) >[226702.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dee820] >[226702.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dee820] width 1280 pitch 5120 (/4 1280) >[226702.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5540] >[226702.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5540] width 1280 pitch 5120 (/4 1280) >[226816.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e20430] >[226816.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e20430] width 1280 pitch 5120 (/4 1280) >[226816.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e20430] >[226816.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e20430] width 1280 pitch 5120 (/4 1280) >[226856.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e52bc0] >[226856.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e52bc0] width 1280 pitch 5120 (/4 1280) >[226856.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226856.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226856.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e52bc0] >[226856.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e52bc0] width 1280 pitch 5120 (/4 1280) >[226856.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226856.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226856.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e52bc0] >[226856.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e52bc0] width 1280 pitch 5120 (/4 1280) >[226856.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226856.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226856.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e52bc0] >[226856.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e52bc0] width 1280 pitch 5120 (/4 1280) >[226856.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226856.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226856.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226856.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226856.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226856.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226856.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226856.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226856.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226856.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226856.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226856.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226856.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226856.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226856.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226856.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226856.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226856.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226856.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226856.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226856.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226856.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226857.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226857.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226857.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226857.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226857.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226857.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226857.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226857.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226857.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226857.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226857.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226857.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226857.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226857.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226857.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226857.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226859.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226859.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226859.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226859.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226859.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226859.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226859.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226859.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226859.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226860.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226860.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5c100] >[226860.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5c100] width 1280 pitch 5120 (/4 1280) >[226860.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226860.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226860.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226860.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226860.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64b40] >[226860.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64b40] width 1280 pitch 5120 (/4 1280) >[226860.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[226860.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[226904.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea46a0] >[226904.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea46a0] width 1280 pitch 5120 (/4 1280) >[226910.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de5020] >[226910.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de5020] width 1280 pitch 5120 (/4 1280) >[226983.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e62f40] >[226983.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e62f40] width 1280 pitch 5120 (/4 1280) >[227060.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7a10] >[227060.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7a10] width 1280 pitch 5120 (/4 1280) >[227060.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7a10] >[227060.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7a10] width 1280 pitch 5120 (/4 1280) >[227060.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd640] >[227060.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd640] width 1280 pitch 5120 (/4 1280) >[227060.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd640] >[227060.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd640] width 1280 pitch 5120 (/4 1280) >[227060.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edffd0] >[227060.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edffd0] width 1280 pitch 5120 (/4 1280) >[227060.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee05b0] >[227060.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee05b0] width 1280 pitch 5120 (/4 1280) >[227060.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee05b0] >[227060.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee05b0] width 1280 pitch 5120 (/4 1280) >[227060.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee05b0] >[227060.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee05b0] width 1280 pitch 5120 (/4 1280) >[227060.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227060.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227060.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227060.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd640] >[227060.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd640] width 1280 pitch 5120 (/4 1280) >[227060.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd640] >[227060.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd640] width 1280 pitch 5120 (/4 1280) >[227060.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7410] >[227060.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7410] width 1280 pitch 5120 (/4 1280) >[227061.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edff30] >[227061.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edff30] width 1280 pitch 5120 (/4 1280) >[227265.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227265.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227265.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227265.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227265.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227265.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227265.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227265.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227265.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227265.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227265.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227265.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227265.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227265.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227265.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227265.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227265.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227265.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227265.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227266.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227266.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227266.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227266.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227266.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227266.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227266.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227266.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227266.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227266.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227266.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227266.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227267.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227267.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227267.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7b90] >[227267.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7b90] width 1280 pitch 5120 (/4 1280) >[227267.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227267.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227268.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed59c0] >[227268.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed59c0] width 1280 pitch 5120 (/4 1280) >[227268.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227268.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227273.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227273.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227275.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb87a0] >[227275.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb87a0] width 1280 pitch 5120 (/4 1280) >[227275.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb87a0] >[227275.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb87a0] width 1280 pitch 5120 (/4 1280) >[227275.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227275.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227275.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e10c50] >[227275.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e10c50] width 1280 pitch 5120 (/4 1280) >[227284.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227284.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227284.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d42c10] >[227284.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d42c10] width 1280 pitch 5120 (/4 1280) >[227284.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227284.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227284.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227284.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227285.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227285.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227285.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4fd0] >[227285.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4fd0] width 1280 pitch 5120 (/4 1280) >[227285.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227285.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227285.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39dead0] >[227285.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39dead0] width 1280 pitch 5120 (/4 1280) >[227286.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4fd0] >[227286.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4fd0] width 1280 pitch 5120 (/4 1280) >[227286.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4fd0] >[227286.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4fd0] width 1280 pitch 5120 (/4 1280) >[227286.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227286.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227286.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92f60] >[227286.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92f60] width 1280 pitch 5120 (/4 1280) >[227295.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227295.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227295.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227295.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227295.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227295.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227295.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227295.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227295.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[227295.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[227296.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee3320] >[227296.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee3320] width 1280 pitch 5120 (/4 1280) >[227300.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee3320] >[227300.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee3320] width 1280 pitch 5120 (/4 1280) >[227300.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227300.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227300.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[227300.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[227300.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227300.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227333.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227333.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227333.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227333.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227333.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227333.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227333.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[227333.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[227333.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227333.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227333.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[227333.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[227333.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227333.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227333.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[227333.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[227398.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[227398.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[227398.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227398.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227401.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[227401.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[227402.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[227402.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[227402.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227402.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[227402.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e40eb0] >[227402.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e40eb0] width 1280 pitch 5120 (/4 1280) >[227402.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[227402.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[227403.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[227403.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[227403.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[227403.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[227403.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[227403.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[228004.568] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[228004.568] (II) RADEON(0): Printing DDC gathered Modelines: >[228004.568] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[228094.887] (II) RADEON(0): RADEONSaveScreen(2) >[228094.887] (II) RADEON(0): RADEONSaveScreen(0) >[228359.580] (II) RADEON(0): RADEONSaveScreen(1) >[228363.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228363.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228363.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7a20] >[228363.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7a20] width 1280 pitch 5120 (/4 1280) >[228363.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228363.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228365.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228365.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228365.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[228365.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[228365.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228365.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228365.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[228365.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[228365.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228365.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228365.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[228365.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[228365.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228365.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228365.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb85e0] >[228365.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb85e0] width 1280 pitch 5120 (/4 1280) >[228366.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[228366.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[228366.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd350] >[228366.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd350] width 1280 pitch 5120 (/4 1280) >[228366.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228366.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228366.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd350] >[228366.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd350] width 1280 pitch 5120 (/4 1280) >[228366.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228366.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228366.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd350] >[228366.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd350] width 1280 pitch 5120 (/4 1280) >[228366.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfa2b0] >[228366.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfa2b0] width 1280 pitch 5120 (/4 1280) >[228367.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228367.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228367.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228367.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228367.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228367.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228367.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228367.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228367.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228367.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228367.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228367.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228367.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228367.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228367.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228367.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228368.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd350] >[228368.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd350] width 1280 pitch 5120 (/4 1280) >[228368.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228368.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228368.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa96b0] >[228368.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa96b0] width 1280 pitch 5120 (/4 1280) >[228368.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228368.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228368.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa96b0] >[228368.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa96b0] width 1280 pitch 5120 (/4 1280) >[228368.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3defdc0] >[228368.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3defdc0] width 1280 pitch 5120 (/4 1280) >[228368.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd350] >[228368.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd350] width 1280 pitch 5120 (/4 1280) >[228370.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[228370.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[228619.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228619.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228619.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20525d0] >[228620.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20525d0] width 1280 pitch 5120 (/4 1280) >[228620.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228620.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228620.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20525d0] >[228620.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20525d0] width 1280 pitch 5120 (/4 1280) >[228620.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228620.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228620.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20525d0] >[228620.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20525d0] width 1280 pitch 5120 (/4 1280) >[228620.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[228620.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[228620.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20525d0] >[228620.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20525d0] width 1280 pitch 5120 (/4 1280) >[228920.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e26930] >[228920.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e26930] width 1280 pitch 5120 (/4 1280) >[228920.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[228920.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[228920.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24040] >[228920.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24040] width 1280 pitch 5120 (/4 1280) >[228925.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[228925.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229219.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[229219.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229219.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[229219.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[229219.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[229219.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229219.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[229220.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[229220.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[229220.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229220.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[229220.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[229220.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[229220.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229220.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3ca40] >[229220.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3ca40] width 1280 pitch 5120 (/4 1280) >[229220.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e42590] >[229220.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e42590] width 1280 pitch 5120 (/4 1280) >[229220.858] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[229220.858] (II) RADEON(0): Printing DDC gathered Modelines: >[229220.858] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[229309.887] (II) RADEON(0): RADEONSaveScreen(2) >[229309.887] (II) RADEON(0): RADEONSaveScreen(0) >[229437.730] (II) RADEON(0): RADEONSaveScreen(1) >[229511.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e26930] >[229511.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e26930] width 1280 pitch 5120 (/4 1280) >[229740.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e24190] >[229740.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e24190] width 1280 pitch 5120 (/4 1280) >[229740.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[229740.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230155.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e83cc0] >[230155.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e83cc0] width 1280 pitch 5120 (/4 1280) >[230163.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36060] >[230163.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36060] width 1280 pitch 5120 (/4 1280) >[230163.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e24810] >[230163.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e24810] width 1280 pitch 5120 (/4 1280) >[230163.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc6fd0] >[230163.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc6fd0] width 1280 pitch 5120 (/4 1280) >[230163.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32720] >[230163.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32720] width 1280 pitch 5120 (/4 1280) >[230166.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0] >[230166.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1280 pitch 5120 (/4 1280) >[230172.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e00d70] >[230172.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e00d70] width 1280 pitch 5120 (/4 1280) >[230186.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243a0] >[230186.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243a0] width 1280 pitch 5120 (/4 1280) >[230217.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e326c0] >[230217.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e326c0] width 1280 pitch 5120 (/4 1280) >[230222.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7b4f0] >[230222.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7b4f0] width 1280 pitch 5120 (/4 1280) >[230222.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db86f0] >[230222.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db86f0] width 1280 pitch 5120 (/4 1280) >[230222.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd39d0] >[230222.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd39d0] width 1280 pitch 5120 (/4 1280) >[230222.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230222.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230233.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ee00] >[230233.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ee00] width 1280 pitch 5120 (/4 1280) >[230233.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ee00] >[230233.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ee00] width 1280 pitch 5120 (/4 1280) >[230233.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ee00] >[230233.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ee00] width 1280 pitch 5120 (/4 1280) >[230233.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230233.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230233.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfd560] >[230233.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfd560] width 1280 pitch 5120 (/4 1280) >[230233.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230233.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230233.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfd560] >[230233.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfd560] width 1280 pitch 5120 (/4 1280) >[230233.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230233.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230233.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230233.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230233.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230233.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230233.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230234.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230234.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230234.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230234.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230234.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230234.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230234.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230234.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230234.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e307d0] >[230234.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e307d0] width 1280 pitch 5120 (/4 1280) >[230244.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230244.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230244.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f265f0] >[230244.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f265f0] width 1280 pitch 5120 (/4 1280) >[230245.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230245.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230245.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230245.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230245.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230245.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230245.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230245.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230245.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d6390] >[230245.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d6390] width 1280 pitch 5120 (/4 1280) >[230245.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4040] >[230245.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4040] width 1280 pitch 5120 (/4 1280) >[230245.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230245.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230245.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230245.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230245.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230245.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230245.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230245.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230245.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230245.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230245.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230245.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230245.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230245.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230245.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230245.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230245.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230245.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230245.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3f70] >[230245.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3f70] width 1280 pitch 5120 (/4 1280) >[230245.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230245.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230254.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27510] >[230254.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27510] width 1280 pitch 5120 (/4 1280) >[230256.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec2410] >[230256.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec2410] width 1280 pitch 5120 (/4 1280) >[230264.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc07e0] >[230264.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc07e0] width 1280 pitch 5120 (/4 1280) >[230404.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19230] >[230404.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19230] width 1280 pitch 5120 (/4 1280) >[230404.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee95f0] >[230404.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee95f0] width 1280 pitch 5120 (/4 1280) >[230404.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e819a0] >[230404.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e819a0] width 1280 pitch 5120 (/4 1280) >[230404.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db51f0] >[230404.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db51f0] width 1280 pitch 5120 (/4 1280) >[230404.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ee60] >[230404.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ee60] width 1280 pitch 5120 (/4 1280) >[230404.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e819a0] >[230404.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e819a0] width 1280 pitch 5120 (/4 1280) >[230404.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db51f0] >[230404.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db51f0] width 1280 pitch 5120 (/4 1280) >[230404.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ee60] >[230404.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ee60] width 1280 pitch 5120 (/4 1280) >[230404.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece310] >[230404.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece310] width 1280 pitch 5120 (/4 1280) >[230404.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230404.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230404.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece310] >[230404.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece310] width 1280 pitch 5120 (/4 1280) >[230404.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230404.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230404.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece310] >[230404.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece310] width 1280 pitch 5120 (/4 1280) >[230404.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230404.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230404.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece310] >[230404.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece310] width 1280 pitch 5120 (/4 1280) >[230404.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230404.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e819a0] >[230405.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e819a0] width 1280 pitch 5120 (/4 1280) >[230405.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ee60] >[230405.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ee60] width 1280 pitch 5120 (/4 1280) >[230405.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194f0] >[230405.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194f0] width 1280 pitch 5120 (/4 1280) >[230405.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194f0] >[230405.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194f0] width 1280 pitch 5120 (/4 1280) >[230405.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194f0] >[230405.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194f0] width 1280 pitch 5120 (/4 1280) >[230405.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194f0] >[230405.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194f0] width 1280 pitch 5120 (/4 1280) >[230405.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194f0] >[230405.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194f0] width 1280 pitch 5120 (/4 1280) >[230405.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230405.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230405.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230405.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230405.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230405.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230405.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230405.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230405.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ee60] >[230406.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ee60] width 1280 pitch 5120 (/4 1280) >[230406.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db51f0] >[230406.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db51f0] width 1280 pitch 5120 (/4 1280) >[230406.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ee60] >[230406.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ee60] width 1280 pitch 5120 (/4 1280) >[230406.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece150] >[230406.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece150] width 1280 pitch 5120 (/4 1280) >[230406.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230406.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230406.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230406.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230406.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230416.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230416.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230416.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230416.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230416.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230416.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230416.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230416.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230416.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230416.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230416.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230416.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230416.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230416.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230416.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230416.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230416.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230416.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230417.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230417.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230417.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230417.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230418.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230418.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230418.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230418.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230418.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230418.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230418.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230418.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230428.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230428.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230428.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230428.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230428.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230428.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230428.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27250] >[230428.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27250] width 1280 pitch 5120 (/4 1280) >[230428.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230428.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230428.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230428.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230428.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230428.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230428.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230428.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230429.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230429.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ece550] >[230429.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ece550] width 1280 pitch 5120 (/4 1280) >[230429.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32850] >[230429.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32850] width 1280 pitch 5120 (/4 1280) >[230429.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230429.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230429.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230429.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230429.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecee70] >[230429.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecee70] width 1280 pitch 5120 (/4 1280) >[230436.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230436.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230496.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230496.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230496.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230496.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230496.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230496.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230496.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230496.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230496.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230496.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230496.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230496.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230496.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230496.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230496.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230497.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77520] >[230497.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77520] width 1280 pitch 5120 (/4 1280) >[230497.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee97f0] >[230497.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee97f0] width 1280 pitch 5120 (/4 1280) >[230497.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230497.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230497.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee97f0] >[230497.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee97f0] width 1280 pitch 5120 (/4 1280) >[230497.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230497.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230497.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee97f0] >[230497.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee97f0] width 1280 pitch 5120 (/4 1280) >[230497.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84ed0] >[230497.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84ed0] width 1280 pitch 5120 (/4 1280) >[230497.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee97f0] >[230497.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee97f0] width 1280 pitch 5120 (/4 1280) >[230509.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230509.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230509.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19100] >[230509.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19100] width 1280 pitch 5120 (/4 1280) >[230511.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4b7a0] >[230511.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4b7a0] width 1280 pitch 5120 (/4 1280) >[230511.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19100] >[230511.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19100] width 1280 pitch 5120 (/4 1280) >[230511.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4b7a0] >[230511.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4b7a0] width 1280 pitch 5120 (/4 1280) >[230511.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19100] >[230511.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19100] width 1280 pitch 5120 (/4 1280) >[230511.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4b7a0] >[230511.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4b7a0] width 1280 pitch 5120 (/4 1280) >[230511.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230512.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230512.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230512.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230512.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230512.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230512.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230512.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230512.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230512.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230512.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230512.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230512.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230512.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230512.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230512.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230512.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230512.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230513.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e243e0] >[230513.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e243e0] width 1280 pitch 5120 (/4 1280) >[230513.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230513.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230513.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b060c0] >[230513.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b060c0] width 1280 pitch 5120 (/4 1280) >[230514.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1d100] >[230514.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1d100] width 1280 pitch 5120 (/4 1280) >[230514.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1155040] >[230514.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1155040] width 1280 pitch 5120 (/4 1280) >[230514.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea2be0] >[230514.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea2be0] width 1280 pitch 5120 (/4 1280) >[230514.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1155040] >[230514.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1155040] width 1280 pitch 5120 (/4 1280) >[230514.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[230514.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[230514.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5dc00] >[230514.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5dc00] width 1280 pitch 5120 (/4 1280) >[230524.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[230524.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[230527.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6f8f0] >[230527.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6f8f0] width 1280 pitch 5120 (/4 1280) >[230527.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[230527.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[230527.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2593900] >[230527.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2593900] width 1280 pitch 5120 (/4 1280) >[230544.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d44590] >[230544.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d44590] width 1280 pitch 5120 (/4 1280) >[230563.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[230563.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[230563.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea2be0] >[230563.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea2be0] width 1280 pitch 5120 (/4 1280) >[230576.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230576.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230576.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230577.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230577.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230577.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230577.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230577.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230577.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230577.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230577.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230577.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230577.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230577.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230577.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230577.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230578.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230578.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230578.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d966e0] >[230578.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d966e0] width 1280 pitch 5120 (/4 1280) >[230578.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230578.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230579.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d966e0] >[230579.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d966e0] width 1280 pitch 5120 (/4 1280) >[230579.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230579.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230579.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d966e0] >[230579.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d966e0] width 1280 pitch 5120 (/4 1280) >[230579.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230579.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230579.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03570] >[230579.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03570] width 1280 pitch 5120 (/4 1280) >[230579.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[230579.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[230579.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3830] >[230579.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3830] width 1280 pitch 5120 (/4 1280) >[230579.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87e40] >[230579.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87e40] width 1280 pitch 5120 (/4 1280) >[230579.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3830] >[230579.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3830] width 1280 pitch 5120 (/4 1280) >[230579.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87e40] >[230580.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87e40] width 1280 pitch 5120 (/4 1280) >[230580.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3830] >[230580.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3830] width 1280 pitch 5120 (/4 1280) >[230580.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87e40] >[230580.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87e40] width 1280 pitch 5120 (/4 1280) >[230580.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3830] >[230580.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3830] width 1280 pitch 5120 (/4 1280) >[230580.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87e40] >[230580.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87e40] width 1280 pitch 5120 (/4 1280) >[230580.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b160] >[230580.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b160] width 1280 pitch 5120 (/4 1280) >[230662.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a8610] >[230662.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a8610] width 1280 pitch 5120 (/4 1280) >[230662.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[230662.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[230683.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230683.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230684.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230684.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230684.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230684.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230684.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230684.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230684.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230684.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230684.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230684.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230684.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230684.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230684.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230684.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230684.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230684.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230684.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230684.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230684.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230684.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230685.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d9f040] >[230685.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d9f040] width 1280 pitch 5120 (/4 1280) >[230685.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x129be80] >[230685.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x129be80] width 1280 pitch 5120 (/4 1280) >[230685.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12bf650] >[230685.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12bf650] width 1280 pitch 5120 (/4 1280) >[230685.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13677f0] >[230685.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13677f0] width 1280 pitch 5120 (/4 1280) >[230685.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[230685.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[230685.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13677f0] >[230685.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13677f0] width 1280 pitch 5120 (/4 1280) >[230685.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[230685.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[230685.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13677f0] >[230685.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13677f0] width 1280 pitch 5120 (/4 1280) >[230688.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4a710] >[230688.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4a710] width 1280 pitch 5120 (/4 1280) >[230688.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230688.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230688.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4a710] >[230688.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4a710] width 1280 pitch 5120 (/4 1280) >[230688.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230688.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230688.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4a710] >[230689.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4a710] width 1280 pitch 5120 (/4 1280) >[230689.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230689.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230689.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4a710] >[230689.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4a710] width 1280 pitch 5120 (/4 1280) >[230689.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230689.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230689.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4a710] >[230689.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4a710] width 1280 pitch 5120 (/4 1280) >[230689.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[230689.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[230689.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19100] >[230690.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19100] width 1280 pitch 5120 (/4 1280) >[230690.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230690.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230690.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[230690.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[230690.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230690.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230690.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b2b3e0] >[230690.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b2b3e0] width 1280 pitch 5120 (/4 1280) >[230690.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e827c0] >[230690.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e827c0] width 1280 pitch 5120 (/4 1280) >[230690.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12c5200] >[230690.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12c5200] width 1280 pitch 5120 (/4 1280) >[230753.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[230753.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[230753.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[230753.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[230754.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230754.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230754.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230754.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[230754.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[230755.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d1020] >[230755.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d1020] width 1280 pitch 5120 (/4 1280) >[230755.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230755.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3873b80] >[230755.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3873b80] width 1280 pitch 5120 (/4 1280) >[230755.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb3e0] >[230755.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb3e0] width 1280 pitch 5120 (/4 1280) >[230979.887] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[230979.887] (II) RADEON(0): Printing DDC gathered Modelines: >[230979.887] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[231579.862] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[231579.862] (II) RADEON(0): Printing DDC gathered Modelines: >[231579.862] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[231669.892] (II) RADEON(0): RADEONSaveScreen(2) >[231669.892] (II) RADEON(0): RADEONSaveScreen(0) >[267911.616] (II) RADEON(0): RADEONSaveScreen(1) >[267919.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f2c450] >[267919.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f2c450] width 1280 pitch 5120 (/4 1280) >[267992.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3822b60] >[267992.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3822b60] width 1280 pitch 5120 (/4 1280) >[267992.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8160] >[267992.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8160] width 1280 pitch 5120 (/4 1280) >[267993.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d396d0] >[267993.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d396d0] width 1280 pitch 5120 (/4 1280) >[267993.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8160] >[267993.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8160] width 1280 pitch 5120 (/4 1280) >[267993.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d396d0] >[267993.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d396d0] width 1280 pitch 5120 (/4 1280) >[267993.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8160] >[267993.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8160] width 1280 pitch 5120 (/4 1280) >[267993.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d396d0] >[267993.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d396d0] width 1280 pitch 5120 (/4 1280) >[267993.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8160] >[267993.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8160] width 1280 pitch 5120 (/4 1280) >[267994.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d396d0] >[267994.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d396d0] width 1280 pitch 5120 (/4 1280) >[267994.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb8160] >[267994.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb8160] width 1280 pitch 5120 (/4 1280) >[267994.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[267994.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[267994.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138cd20] >[267994.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138cd20] width 1280 pitch 5120 (/4 1280) >[267994.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[267994.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[267994.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x138cd20] >[267994.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x138cd20] width 1280 pitch 5120 (/4 1280) >[267994.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3876150] >[267994.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3876150] width 1280 pitch 5120 (/4 1280) >[267994.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96a30] >[267994.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96a30] width 1280 pitch 5120 (/4 1280) >[267996.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a8610] >[267996.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a8610] width 1280 pitch 5120 (/4 1280) >[267996.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[267996.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[268048.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1500] >[268048.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1500] width 1280 pitch 5120 (/4 1280) >[268048.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f7a90] >[268048.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f7a90] width 1280 pitch 5120 (/4 1280) >[268050.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19df8b0] >[268050.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19df8b0] width 1280 pitch 5120 (/4 1280) >[268052.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6f8f0] >[268052.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6f8f0] width 1280 pitch 5120 (/4 1280) >[268125.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31370e0] >[268125.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31370e0] width 1280 pitch 5120 (/4 1280) >[268242.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233f830] >[268242.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233f830] width 1280 pitch 5120 (/4 1280) >[268386.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11e6a40] >[268386.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11e6a40] width 1280 pitch 5120 (/4 1280) >[268386.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13a2d20] >[268387.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13a2d20] width 1280 pitch 5120 (/4 1280) >[268387.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8870] >[268387.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8870] width 1280 pitch 5120 (/4 1280) >[268451.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268451.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268451.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[268451.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[268451.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268451.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268451.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[268451.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[268451.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268451.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268451.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[268452.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[268452.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268452.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268452.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[268452.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[268452.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268452.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268452.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[268452.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[268452.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[268452.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[268452.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[268452.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[268452.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da7370] >[268452.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da7370] width 1280 pitch 5120 (/4 1280) >[268452.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[268452.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[268452.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[268452.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[268453.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[268453.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[268453.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19bdd90] >[268453.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19bdd90] width 1280 pitch 5120 (/4 1280) >[268561.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[268561.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[268561.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d16c10] >[268561.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d16c10] width 1280 pitch 5120 (/4 1280) >[268562.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1228560] >[268562.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1228560] width 1280 pitch 5120 (/4 1280) >[268562.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df17e0] >[268562.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df17e0] width 1280 pitch 5120 (/4 1280) >[268709.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268709.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b2510] >[268709.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b2510] width 1280 pitch 5120 (/4 1280) >[268709.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268709.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b2510] >[268709.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b2510] width 1280 pitch 5120 (/4 1280) >[268709.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268709.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b2510] >[268709.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b2510] width 1280 pitch 5120 (/4 1280) >[268709.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268709.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b2510] >[268709.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b2510] width 1280 pitch 5120 (/4 1280) >[268709.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268709.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee89a0] >[268709.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee89a0] width 1280 pitch 5120 (/4 1280) >[268709.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268709.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268889.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b2510] >[268889.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b2510] width 1280 pitch 5120 (/4 1280) >[268889.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[268889.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[268889.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12f01c0] >[268889.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12f01c0] width 1280 pitch 5120 (/4 1280) >[268889.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[268889.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[268889.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c93b0] >[268889.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c93b0] width 1280 pitch 5120 (/4 1280) >[268889.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b56b80] >[268890.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b56b80] width 1280 pitch 5120 (/4 1280) >[268890.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4540] >[268890.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4540] width 1280 pitch 5120 (/4 1280) >[268890.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2462a60] >[268890.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2462a60] width 1280 pitch 5120 (/4 1280) >[268890.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x317cd10] >[268890.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x317cd10] width 1280 pitch 5120 (/4 1280) >[268890.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c93b0] >[268890.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c93b0] width 1280 pitch 5120 (/4 1280) >[268890.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[268890.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[268890.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c93b0] >[268890.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c93b0] width 1280 pitch 5120 (/4 1280) >[268890.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[268890.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[268904.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee89a0] >[268904.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee89a0] width 1280 pitch 5120 (/4 1280) >[268937.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13cefe0] >[268937.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13cefe0] width 1280 pitch 5120 (/4 1280) >[268937.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d7450] >[268937.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d7450] width 1280 pitch 5120 (/4 1280) >[269092.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fc860] >[269092.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fc860] width 1280 pitch 5120 (/4 1280) >[269092.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30313d0] >[269092.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30313d0] width 1280 pitch 5120 (/4 1280) >[269321.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269321.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2458970] >[269321.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2458970] width 1280 pitch 5120 (/4 1280) >[269321.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea1b0] >[269321.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea1b0] width 1280 pitch 5120 (/4 1280) >[269321.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248c550] >[269321.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248c550] width 1280 pitch 5120 (/4 1280) >[269321.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cbe0] >[269321.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cbe0] width 1280 pitch 5120 (/4 1280) >[269321.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269321.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cb80] >[269322.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cb80] width 1280 pitch 5120 (/4 1280) >[269322.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269322.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269322.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269322.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269322.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269322.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269322.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269322.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269322.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269323.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ddb0] >[269323.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ddb0] width 1280 pitch 5120 (/4 1280) >[269323.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24585d0] >[269323.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24585d0] width 1280 pitch 5120 (/4 1280) >[269323.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ddb0] >[269323.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ddb0] width 1280 pitch 5120 (/4 1280) >[269323.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269323.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269323.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ddb0] >[269323.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ddb0] width 1280 pitch 5120 (/4 1280) >[269323.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea650] >[269323.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea650] width 1280 pitch 5120 (/4 1280) >[269323.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea6b0] >[269323.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea6b0] width 1280 pitch 5120 (/4 1280) >[269323.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193900] >[269323.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193900] width 1280 pitch 5120 (/4 1280) >[269323.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ddb0] >[269323.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ddb0] width 1280 pitch 5120 (/4 1280) >[269323.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ddb0] >[269323.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ddb0] width 1280 pitch 5120 (/4 1280) >[269323.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b50] >[269323.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b50] width 1280 pitch 5120 (/4 1280) >[269323.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b50] >[269323.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b50] width 1280 pitch 5120 (/4 1280) >[269323.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269323.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269323.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269323.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193b10] >[269323.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193b10] width 1280 pitch 5120 (/4 1280) >[269324.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269324.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269324.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269324.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269324.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269325.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269325.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269325.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269325.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269326.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269326.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269326.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269326.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269327.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269327.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269327.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269327.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269327.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269327.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269327.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[269327.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[269327.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269327.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269329.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269329.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269329.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269329.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269329.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269329.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269329.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269329.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269329.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269329.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269329.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269329.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269329.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269329.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269329.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269329.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269329.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269329.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269330.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269330.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269330.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269330.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269358.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8c240] >[269358.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8c240] width 1280 pitch 5120 (/4 1280) >[269358.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[269358.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[269358.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a02f20] >[269358.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a02f20] width 1280 pitch 5120 (/4 1280) >[269358.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb5fa0] >[269358.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb5fa0] width 1280 pitch 5120 (/4 1280) >[269358.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb5fa0] >[269358.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb5fa0] width 1280 pitch 5120 (/4 1280) >[269358.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269358.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269358.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129250] >[269358.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129250] width 1280 pitch 5120 (/4 1280) >[269359.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8c240] >[269359.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8c240] width 1280 pitch 5120 (/4 1280) >[269359.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[269359.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[269359.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14879a0] >[269359.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14879a0] width 1280 pitch 5120 (/4 1280) >[269359.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14879a0] >[269359.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14879a0] width 1280 pitch 5120 (/4 1280) >[269359.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8c240] >[269359.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8c240] width 1280 pitch 5120 (/4 1280) >[269359.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8bb20] >[269359.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8bb20] width 1280 pitch 5120 (/4 1280) >[269359.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[269359.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[269359.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129250] >[269359.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129250] width 1280 pitch 5120 (/4 1280) >[269359.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1118a10] >[269359.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1118a10] width 1280 pitch 5120 (/4 1280) >[269359.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269359.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269359.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269359.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269359.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269359.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269359.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269359.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269359.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269359.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269359.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269359.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269360.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269360.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269360.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269360.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269360.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269360.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269360.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269360.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269360.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269360.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269360.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269360.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269361.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269361.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269361.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x274dbe0] >[269361.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x274dbe0] width 1280 pitch 5120 (/4 1280) >[269361.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269361.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269362.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269362.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269363.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269363.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269363.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269363.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269363.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea6c0] >[269363.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea6c0] width 1280 pitch 5120 (/4 1280) >[269363.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269363.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269363.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269363.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269363.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[269363.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[269363.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea6c0] >[269363.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea6c0] width 1280 pitch 5120 (/4 1280) >[269377.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269377.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269379.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269379.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269379.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269379.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269380.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269380.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[269380.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[269380.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[269380.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[269381.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9d50] >[269381.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9d50] width 1280 pitch 5120 (/4 1280) >[269382.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f14e00] >[269382.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f14e00] width 1280 pitch 5120 (/4 1280) >[269382.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56d50] >[269382.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56d50] width 1280 pitch 5120 (/4 1280) >[269382.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a35f0] >[269382.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a35f0] width 1280 pitch 5120 (/4 1280) >[269382.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f54040] >[269382.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f54040] width 1280 pitch 5120 (/4 1280) >[269382.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281cb70] >[269382.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281cb70] width 1280 pitch 5120 (/4 1280) >[269382.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f14f80] >[269382.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f14f80] width 1280 pitch 5120 (/4 1280) >[269393.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8c240] >[269393.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8c240] width 1280 pitch 5120 (/4 1280) >[269396.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11817d0] >[269396.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11817d0] width 1280 pitch 5120 (/4 1280) >[269399.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bffe0] >[269399.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bffe0] width 1280 pitch 5120 (/4 1280) >[269399.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269399.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269399.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bffe0] >[269399.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bffe0] width 1280 pitch 5120 (/4 1280) >[269400.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269400.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269400.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bffe0] >[269400.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bffe0] width 1280 pitch 5120 (/4 1280) >[269400.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269400.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269400.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bffe0] >[269400.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bffe0] width 1280 pitch 5120 (/4 1280) >[269400.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269400.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269401.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11bffe0] >[269401.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11bffe0] width 1280 pitch 5120 (/4 1280) >[269401.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11817d0] >[269401.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11817d0] width 1280 pitch 5120 (/4 1280) >[269401.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f4780] >[269401.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f4780] width 1280 pitch 5120 (/4 1280) >[269401.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269401.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269401.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f4780] >[269401.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f4780] width 1280 pitch 5120 (/4 1280) >[269401.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[269401.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[269401.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de7c40] >[269401.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de7c40] width 1280 pitch 5120 (/4 1280) >[269619.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f32250] >[269619.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f32250] width 1280 pitch 5120 (/4 1280) >[269959.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269959.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269959.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269959.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269959.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269959.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269959.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269959.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269959.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269959.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269959.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269959.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269959.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269959.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269959.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269960.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269960.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269960.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269960.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269960.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269960.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269960.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269960.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269960.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269960.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269960.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269960.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269961.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269961.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[269961.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[269961.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[269961.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[269961.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[269961.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[269961.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269961.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269961.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269961.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269961.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269962.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269962.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269962.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269962.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269962.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269962.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269962.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269962.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269962.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269962.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269962.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269962.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269962.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80060] >[269962.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80060] width 1280 pitch 5120 (/4 1280) >[269962.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269962.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269962.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87e60] >[269962.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87e60] width 1280 pitch 5120 (/4 1280) >[269963.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7580] >[269963.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7580] width 1280 pitch 5120 (/4 1280) >[269963.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269963.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269963.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269963.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269963.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269963.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269963.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269963.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269963.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269963.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269963.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269963.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269964.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[269964.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[269964.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eebb20] >[269964.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eebb20] width 1280 pitch 5120 (/4 1280) >[269968.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7600] >[269968.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7600] width 1280 pitch 5120 (/4 1280) >[270095.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270095.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270096.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[270096.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[270143.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270143.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270143.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270143.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270143.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270143.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270143.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270143.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270143.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270143.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270143.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270143.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270143.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270143.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270143.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270143.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270143.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270143.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270143.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270143.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270143.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270143.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270143.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270143.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270143.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270143.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270143.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270143.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270143.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270143.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270143.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270143.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270143.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270143.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270143.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270143.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270143.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270143.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270143.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270143.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270144.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270144.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270144.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270144.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270144.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270144.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270144.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270144.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270144.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270144.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270144.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270144.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270144.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270144.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270144.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270144.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270144.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270144.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270144.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270144.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270144.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270144.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270144.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270144.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270145.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270145.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270145.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270145.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270145.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270145.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270145.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270145.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270145.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270145.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270145.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270145.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270145.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270145.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270145.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9be10] >[270145.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9be10] width 1280 pitch 5120 (/4 1280) >[270145.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270145.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270145.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270145.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270145.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25f00] >[270145.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25f00] width 1280 pitch 5120 (/4 1280) >[270146.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270146.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270146.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270146.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270146.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270146.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270146.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270146.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270146.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270147.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270147.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270147.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270147.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270147.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5aa60] >[270147.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5aa60] width 1280 pitch 5120 (/4 1280) >[270150.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270150.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270162.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270162.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270162.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270162.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270162.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270162.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270162.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x146a3a0] >[270162.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x146a3a0] width 1280 pitch 5120 (/4 1280) >[270162.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270162.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270162.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270162.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270162.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270162.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270162.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270162.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270162.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1dc30] >[270162.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1dc30] width 1280 pitch 5120 (/4 1280) >[270162.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270162.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270162.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270162.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270162.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270162.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270162.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270162.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270162.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270162.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270162.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270162.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270162.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270162.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270162.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270162.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270162.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270163.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270163.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270163.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270163.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270163.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270163.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270163.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270163.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270163.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270163.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270163.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270163.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270163.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270163.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9600] >[270163.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9600] width 1280 pitch 5120 (/4 1280) >[270163.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23766c0] >[270163.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23766c0] width 1280 pitch 5120 (/4 1280) >[270163.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24475e0] >[270163.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24475e0] width 1280 pitch 5120 (/4 1280) >[270163.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0bc10] >[270163.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0bc10] width 1280 pitch 5120 (/4 1280) >[270163.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11586f0] >[270163.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11586f0] width 1280 pitch 5120 (/4 1280) >[270164.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbe1f0] >[270164.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbe1f0] width 1280 pitch 5120 (/4 1280) >[270164.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270164.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270164.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270164.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270164.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee69e0] >[270164.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee69e0] width 1280 pitch 5120 (/4 1280) >[270164.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270164.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270164.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee69e0] >[270164.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee69e0] width 1280 pitch 5120 (/4 1280) >[270164.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270164.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270164.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270164.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270164.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1158620] >[270164.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1158620] width 1280 pitch 5120 (/4 1280) >[270164.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1158620] >[270164.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1158620] width 1280 pitch 5120 (/4 1280) >[270164.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270164.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80fa0] >[270164.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80fa0] width 1280 pitch 5120 (/4 1280) >[270164.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270164.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270164.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b40] >[270164.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b40] width 1280 pitch 5120 (/4 1280) >[270165.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[270165.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[270165.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270165.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270165.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0ba30] >[270165.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0ba30] width 1280 pitch 5120 (/4 1280) >[270165.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270165.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270165.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87840] >[270165.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87840] width 1280 pitch 5120 (/4 1280) >[270165.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270165.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270165.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87840] >[270165.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87840] width 1280 pitch 5120 (/4 1280) >[270165.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a08a0] >[270165.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a08a0] width 1280 pitch 5120 (/4 1280) >[270165.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87840] >[270165.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87840] width 1280 pitch 5120 (/4 1280) >[270165.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a160] >[270165.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a160] width 1280 pitch 5120 (/4 1280) >[270165.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87840] >[270165.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87840] width 1280 pitch 5120 (/4 1280) >[270165.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1158890] >[270165.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1158890] width 1280 pitch 5120 (/4 1280) >[270165.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80fa0] >[270165.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80fa0] width 1280 pitch 5120 (/4 1280) >[270165.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[270165.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[270165.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270165.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270166.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270166.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270166.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fb010] >[270166.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fb010] width 1280 pitch 5120 (/4 1280) >[270166.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270166.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270166.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fb010] >[270166.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fb010] width 1280 pitch 5120 (/4 1280) >[270166.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[270166.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[270166.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fb010] >[270166.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fb010] width 1280 pitch 5120 (/4 1280) >[270166.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[270166.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[270166.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fb010] >[270166.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fb010] width 1280 pitch 5120 (/4 1280) >[270166.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[270166.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[270166.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270166.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270166.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[270166.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[270166.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270166.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270166.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[270166.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[270166.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270166.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270166.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[270166.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[270166.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270166.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270166.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[270166.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[270166.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270166.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270241.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270241.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270241.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270241.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270241.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270241.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270241.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270241.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270241.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270241.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270241.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[270241.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[270242.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[270242.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[270242.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[270242.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[270242.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[270242.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[270242.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[270242.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[270242.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270242.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270242.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270242.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270262.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270262.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270262.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270262.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270262.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270262.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270262.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270262.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270262.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270262.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270262.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270262.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270262.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270262.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270262.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270262.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270262.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270262.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270262.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270262.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270263.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270263.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270263.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270263.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270263.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270263.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270263.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270263.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270263.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270263.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270263.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270263.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270263.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270263.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270263.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270263.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270263.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270263.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270263.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270263.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270263.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270263.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270263.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270263.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270263.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270263.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x294bdb0] >[270263.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x294bdb0] width 1280 pitch 5120 (/4 1280) >[270264.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270264.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270264.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[270264.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[270264.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270264.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270264.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[270264.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[270264.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270264.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270264.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[270264.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[270264.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270264.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270264.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[270264.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[270264.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270264.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270264.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ff0] >[270264.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ff0] width 1280 pitch 5120 (/4 1280) >[270266.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270266.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270266.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114f9d0] >[270266.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114f9d0] width 1280 pitch 5120 (/4 1280) >[270266.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[270266.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[270266.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114f9d0] >[270266.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114f9d0] width 1280 pitch 5120 (/4 1280) >[270266.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270266.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270266.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114f9d0] >[270266.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114f9d0] width 1280 pitch 5120 (/4 1280) >[270266.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270266.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270266.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114f9d0] >[270266.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114f9d0] width 1280 pitch 5120 (/4 1280) >[270267.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270267.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270267.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270267.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270267.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29bab30] >[270267.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29bab30] width 1280 pitch 5120 (/4 1280) >[270267.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270267.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270267.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b05d10] >[270267.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b05d10] width 1280 pitch 5120 (/4 1280) >[270267.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[270267.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[270267.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eec6a0] >[270267.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eec6a0] width 1280 pitch 5120 (/4 1280) >[270267.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2467370] >[270267.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2467370] width 1280 pitch 5120 (/4 1280) >[270267.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eec6a0] >[270267.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eec6a0] width 1280 pitch 5120 (/4 1280) >[270270.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270270.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270271.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270271.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270271.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270271.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270271.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270271.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270271.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270271.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270271.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270271.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270271.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270271.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270272.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270272.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270272.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[270272.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[270272.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a230] >[270272.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a230] width 1280 pitch 5120 (/4 1280) >[270273.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d50] >[270273.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d50] width 1280 pitch 5120 (/4 1280) >[270273.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[270273.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[270273.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b540] >[270273.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b540] width 1280 pitch 5120 (/4 1280) >[270273.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a8e2f0] >[270273.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a8e2f0] width 1280 pitch 5120 (/4 1280) >[270273.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270273.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270273.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[270273.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[270273.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270273.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270273.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270273.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270274.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270274.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270274.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270274.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270274.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270274.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270274.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270274.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270274.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270274.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270274.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270274.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270274.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270274.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270274.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270274.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270275.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[270275.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[270275.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95800] >[270275.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95800] width 1280 pitch 5120 (/4 1280) >[270275.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202bde0] >[270275.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202bde0] width 1280 pitch 5120 (/4 1280) >[270275.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d50] >[270275.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d50] width 1280 pitch 5120 (/4 1280) >[270275.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270275.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270275.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d50] >[270275.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d50] width 1280 pitch 5120 (/4 1280) >[270275.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81970] >[270275.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81970] width 1280 pitch 5120 (/4 1280) >[270276.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5a00] >[270276.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5a00] width 1280 pitch 5120 (/4 1280) >[270276.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d50] >[270276.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d50] width 1280 pitch 5120 (/4 1280) >[270318.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8660] >[270318.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8660] width 1280 pitch 5120 (/4 1280) >[270326.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b8210] >[270326.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b8210] width 1280 pitch 5120 (/4 1280) >[270326.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7490] >[270326.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7490] width 1280 pitch 5120 (/4 1280) >[270326.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9a3c0] >[270326.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9a3c0] width 1280 pitch 5120 (/4 1280) >[270326.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1179c90] >[270326.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1179c90] width 1280 pitch 5120 (/4 1280) >[270326.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f1f60] >[270326.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f1f60] width 1280 pitch 5120 (/4 1280) >[270326.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8660] >[270326.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8660] width 1280 pitch 5120 (/4 1280) >[270326.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270326.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270326.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270326.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270326.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270326.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270326.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270326.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270327.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270327.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270327.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270327.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270327.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270327.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270328.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270328.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270328.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1360] >[270328.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1360] width 1280 pitch 5120 (/4 1280) >[270328.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270328.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270328.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1360] >[270328.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1360] width 1280 pitch 5120 (/4 1280) >[270328.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270328.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270328.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1360] >[270328.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1360] width 1280 pitch 5120 (/4 1280) >[270385.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270385.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270385.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270385.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270385.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270385.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270385.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270385.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270385.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270385.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270385.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[270385.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[270386.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270386.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270386.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270386.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270386.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19e70] >[270386.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19e70] width 1280 pitch 5120 (/4 1280) >[270386.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d9150] >[270386.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d9150] width 1280 pitch 5120 (/4 1280) >[270386.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784030] >[270386.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784030] width 1280 pitch 5120 (/4 1280) >[270386.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1450] >[270386.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1450] width 1280 pitch 5120 (/4 1280) >[270386.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784030] >[270386.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784030] width 1280 pitch 5120 (/4 1280) >[270386.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1450] >[270386.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1450] width 1280 pitch 5120 (/4 1280) >[270386.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784030] >[270386.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784030] width 1280 pitch 5120 (/4 1280) >[270408.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[270408.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[270408.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f54f10] >[270408.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f54f10] width 1280 pitch 5120 (/4 1280) >[270448.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[270448.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[270572.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f460] >[270572.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f460] width 1280 pitch 5120 (/4 1280) >[270582.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3022920] >[270582.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3022920] width 1280 pitch 5120 (/4 1280) >[271183.786] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[271183.786] (II) RADEON(0): Printing DDC gathered Modelines: >[271183.786] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[271273.894] (II) RADEON(0): RADEONSaveScreen(2) >[271273.894] (II) RADEON(0): RADEONSaveScreen(0) >[298978.187] (II) RADEON(0): RADEONSaveScreen(1) >[298985.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298985.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298985.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298985.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298985.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[298985.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[298985.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[298985.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[298985.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[298985.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[298985.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[298985.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[298985.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298985.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298985.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[298985.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[298985.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[298985.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[298985.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298985.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298985.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298985.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298985.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298986.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[298986.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[298986.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[298986.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[298986.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40265e0] >[298986.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40265e0] width 1280 pitch 5120 (/4 1280) >[298986.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f3620] >[298986.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f3620] width 1280 pitch 5120 (/4 1280) >[298986.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026820] >[298986.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026820] width 1280 pitch 5120 (/4 1280) >[298986.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[298986.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[298987.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298987.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298987.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298987.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298987.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298987.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298987.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298987.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298987.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298987.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298987.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298987.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298987.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298987.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298987.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298987.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298987.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298988.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[298988.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[298988.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025860] >[298988.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025860] width 1280 pitch 5120 (/4 1280) >[298989.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40248a0] >[298989.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40248a0] width 1280 pitch 5120 (/4 1280) >[298989.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025f20] >[298989.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025f20] width 1280 pitch 5120 (/4 1280) >[299031.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299031.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299031.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299031.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299031.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299031.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299031.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299031.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299031.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299031.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299032.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299032.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299032.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299032.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299033.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299033.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299033.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299033.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299033.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299033.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299033.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299033.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299033.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299033.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299033.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299033.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299033.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299033.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025aa0] >[299033.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025aa0] width 1280 pitch 5120 (/4 1280) >[299035.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024f60] >[299035.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024f60] width 1280 pitch 5120 (/4 1280) >[299035.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299035.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299035.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299035.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299035.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299035.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299035.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299035.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299035.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299035.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299035.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299035.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299035.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299035.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299035.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299036.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299036.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024660] >[299036.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024660] width 1280 pitch 5120 (/4 1280) >[299036.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299036.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299036.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024660] >[299036.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024660] width 1280 pitch 5120 (/4 1280) >[299036.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299036.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299036.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299036.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299036.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c470] >[299036.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c470] width 1280 pitch 5120 (/4 1280) >[299036.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c470] >[299036.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c470] width 1280 pitch 5120 (/4 1280) >[299036.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[299036.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[299037.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299037.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299037.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299037.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299037.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299037.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299038.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299038.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299038.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299038.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299038.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299038.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299038.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299038.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299038.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299038.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299038.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299038.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299038.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299038.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299038.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299038.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299039.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f3c0] >[299039.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f3c0] width 1280 pitch 5120 (/4 1280) >[299039.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299039.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299039.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299039.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299039.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299039.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299039.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299039.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299039.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299039.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299039.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299039.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299039.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299039.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299039.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299039.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299039.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299039.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299040.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299040.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299040.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[299040.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[299040.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024ae0] >[299040.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024ae0] width 1280 pitch 5120 (/4 1280) >[299040.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299041.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299041.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024ae0] >[299041.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024ae0] width 1280 pitch 5120 (/4 1280) >[299041.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299041.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299041.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024ae0] >[299041.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024ae0] width 1280 pitch 5120 (/4 1280) >[299041.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e2850] >[299041.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e2850] width 1280 pitch 5120 (/4 1280) >[299041.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f3c0] >[299041.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f3c0] width 1280 pitch 5120 (/4 1280) >[299041.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299041.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299041.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f3c0] >[299041.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f3c0] width 1280 pitch 5120 (/4 1280) >[299041.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299041.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299046.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299046.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299046.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23705a0] >[299046.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23705a0] width 1280 pitch 5120 (/4 1280) >[299046.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024420] >[299046.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024420] width 1280 pitch 5120 (/4 1280) >[299047.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024660] >[299047.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024660] width 1280 pitch 5120 (/4 1280) >[299047.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299047.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299047.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a120] >[299047.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a120] width 1280 pitch 5120 (/4 1280) >[299047.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025620] >[299047.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025620] width 1280 pitch 5120 (/4 1280) >[299048.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299048.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299048.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299048.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299048.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb3c0] >[299048.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb3c0] width 1280 pitch 5120 (/4 1280) >[299059.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb3c0] >[299059.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb3c0] width 1280 pitch 5120 (/4 1280) >[299059.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024420] >[299059.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024420] width 1280 pitch 5120 (/4 1280) >[299059.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024420] >[299059.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024420] width 1280 pitch 5120 (/4 1280) >[299059.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd0ea0] >[299059.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd0ea0] width 1280 pitch 5120 (/4 1280) >[299060.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024420] >[299060.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024420] width 1280 pitch 5120 (/4 1280) >[299060.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fce9d0] >[299060.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fce9d0] width 1280 pitch 5120 (/4 1280) >[299060.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4024420] >[299060.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4024420] width 1280 pitch 5120 (/4 1280) >[299060.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033510] >[299060.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033510] width 1280 pitch 5120 (/4 1280) >[299081.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[299081.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[299081.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299081.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299081.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[299081.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[299081.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[299081.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[299247.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0bbf0] >[299247.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0bbf0] width 1280 pitch 5120 (/4 1280) >[299248.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac230] >[299248.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac230] width 1280 pitch 5120 (/4 1280) >[299248.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9c0] >[299248.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9c0] width 1280 pitch 5120 (/4 1280) >[299248.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac230] >[299248.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac230] width 1280 pitch 5120 (/4 1280) >[299248.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9c0] >[299248.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9c0] width 1280 pitch 5120 (/4 1280) >[299248.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fabfa0] >[299248.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fabfa0] width 1280 pitch 5120 (/4 1280) >[299248.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fadc50] >[299249.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fadc50] width 1280 pitch 5120 (/4 1280) >[299249.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40744c0] >[299249.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40744c0] width 1280 pitch 5120 (/4 1280) >[299249.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4070340] >[299249.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4070340] width 1280 pitch 5120 (/4 1280) >[299249.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4070340] >[299249.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4070340] width 1280 pitch 5120 (/4 1280) >[299249.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4070340] >[299249.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4070340] width 1280 pitch 5120 (/4 1280) >[299250.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299250.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299250.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299250.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299250.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299250.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299250.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299250.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299250.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299253.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299253.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299254.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299254.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299254.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299254.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299254.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaeb0] >[299254.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaeb0] width 1280 pitch 5120 (/4 1280) >[299254.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299254.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299254.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074d10] >[299254.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074d10] width 1280 pitch 5120 (/4 1280) >[299254.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299254.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299254.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074d10] >[299254.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074d10] width 1280 pitch 5120 (/4 1280) >[299254.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299254.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299254.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074d10] >[299254.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074d10] width 1280 pitch 5120 (/4 1280) >[299254.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299254.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299254.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299254.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299255.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299255.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299255.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299255.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299255.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf10] >[299255.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf10] width 1280 pitch 5120 (/4 1280) >[299255.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299255.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299255.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f8c0] >[299255.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f8c0] width 1280 pitch 5120 (/4 1280) >[299255.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299255.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299255.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f8c0] >[299255.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f8c0] width 1280 pitch 5120 (/4 1280) >[299255.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f9e0] >[299255.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f9e0] width 1280 pitch 5120 (/4 1280) >[299255.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f8c0] >[299255.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f8c0] width 1280 pitch 5120 (/4 1280) >[299255.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f9e0] >[299255.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f9e0] width 1280 pitch 5120 (/4 1280) >[299255.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f8c0] >[299255.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f8c0] width 1280 pitch 5120 (/4 1280) >[299260.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8930] >[299260.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8930] width 1280 pitch 5120 (/4 1280) >[299260.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414f300] >[299260.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414f300] width 1280 pitch 5120 (/4 1280) >[299260.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b8d0] >[299260.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b8d0] width 1280 pitch 5120 (/4 1280) >[299261.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149a40] >[299261.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149a40] width 1280 pitch 5120 (/4 1280) >[299262.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078be0] >[299262.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078be0] width 1280 pitch 5120 (/4 1280) >[299262.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8930] >[299262.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8930] width 1280 pitch 5120 (/4 1280) >[299262.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf90] >[299262.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf90] width 1280 pitch 5120 (/4 1280) >[299262.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8930] >[299262.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8930] width 1280 pitch 5120 (/4 1280) >[299262.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf90] >[299262.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf90] width 1280 pitch 5120 (/4 1280) >[299262.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8930] >[299262.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8930] width 1280 pitch 5120 (/4 1280) >[299262.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf90] >[299262.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf90] width 1280 pitch 5120 (/4 1280) >[299262.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8930] >[299262.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8930] width 1280 pitch 5120 (/4 1280) >[299268.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf90] >[299268.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf90] width 1280 pitch 5120 (/4 1280) >[299277.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faada0] >[299277.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faada0] width 1280 pitch 5120 (/4 1280) >[299277.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faada0] >[299277.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faada0] width 1280 pitch 5120 (/4 1280) >[299277.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faada0] >[299277.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faada0] width 1280 pitch 5120 (/4 1280) >[299277.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faada0] >[299277.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faada0] width 1280 pitch 5120 (/4 1280) >[299277.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faada0] >[299277.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faada0] width 1280 pitch 5120 (/4 1280) >[299277.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4074c70] >[299277.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4074c70] width 1280 pitch 5120 (/4 1280) >[299277.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414ecd0] >[299277.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414ecd0] width 1280 pitch 5120 (/4 1280) >[299282.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab0d0] >[299282.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab0d0] width 1280 pitch 5120 (/4 1280) >[299282.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299282.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299283.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab0d0] >[299283.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab0d0] width 1280 pitch 5120 (/4 1280) >[299283.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299283.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299283.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab0d0] >[299283.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab0d0] width 1280 pitch 5120 (/4 1280) >[299283.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299283.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299283.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab0d0] >[299283.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab0d0] width 1280 pitch 5120 (/4 1280) >[299283.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299283.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299284.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab0d0] >[299284.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab0d0] width 1280 pitch 5120 (/4 1280) >[299284.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299284.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299285.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049970] >[299285.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049970] width 1280 pitch 5120 (/4 1280) >[299285.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e2850] >[299285.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e2850] width 1280 pitch 5120 (/4 1280) >[299285.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299285.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299285.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e2850] >[299285.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e2850] width 1280 pitch 5120 (/4 1280) >[299285.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299286.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299286.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e2850] >[299286.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e2850] width 1280 pitch 5120 (/4 1280) >[299289.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42319b0] >[299289.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42319b0] width 1280 pitch 5120 (/4 1280) >[299289.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40265e0] >[299289.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40265e0] width 1280 pitch 5120 (/4 1280) >[299291.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299291.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299291.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299291.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299291.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299292.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299292.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299292.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299292.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299293.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a640] >[299293.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a640] width 1280 pitch 5120 (/4 1280) >[299293.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299293.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299293.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049970] >[299293.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049970] width 1280 pitch 5120 (/4 1280) >[299293.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299293.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299293.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[299293.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[299293.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299293.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299293.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[299293.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[299293.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299293.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299293.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[299294.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[299294.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299294.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299294.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[299294.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[299294.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b4b0] >[299294.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b4b0] width 1280 pitch 5120 (/4 1280) >[299294.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b4b0] >[299294.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b4b0] width 1280 pitch 5120 (/4 1280) >[299299.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4235c90] >[299300.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4235c90] width 1280 pitch 5120 (/4 1280) >[299300.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299300.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299300.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299300.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299300.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299300.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299300.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299300.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299300.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299300.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299300.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299300.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299300.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299300.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299301.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299301.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299301.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b90] >[299301.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b90] width 1280 pitch 5120 (/4 1280) >[299302.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299302.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299302.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299302.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299302.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c370] >[299302.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c370] width 1280 pitch 5120 (/4 1280) >[299302.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299302.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299302.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299302.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299305.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299305.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299305.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299305.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299305.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299305.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299305.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299305.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299305.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299305.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299305.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299305.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299306.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299306.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299306.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299306.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299307.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299307.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299307.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299307.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299307.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d5290] >[299307.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d5290] width 1280 pitch 5120 (/4 1280) >[299307.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299307.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299307.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef5e30] >[299307.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef5e30] width 1280 pitch 5120 (/4 1280) >[299307.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c7a00] >[299307.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c7a00] width 1280 pitch 5120 (/4 1280) >[299307.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299307.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299307.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c7a00] >[299307.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c7a00] width 1280 pitch 5120 (/4 1280) >[299307.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299307.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299307.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c7a00] >[299307.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c7a00] width 1280 pitch 5120 (/4 1280) >[299307.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299307.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299307.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c7a00] >[299308.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c7a00] width 1280 pitch 5120 (/4 1280) >[299308.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299308.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299308.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299308.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299308.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299308.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299308.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299308.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299308.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299308.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299308.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299308.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299308.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299308.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299308.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4235b90] >[299308.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4235b90] width 1280 pitch 5120 (/4 1280) >[299309.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299309.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299309.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299309.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299309.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299309.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299309.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299309.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299309.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299309.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299309.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299309.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299309.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299309.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299309.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299309.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299310.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299310.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299310.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0] >[299310.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1280 pitch 5120 (/4 1280) >[299310.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40968f0] >[299310.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40968f0] width 1280 pitch 5120 (/4 1280) >[299310.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a278b0] >[299310.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a278b0] width 1280 pitch 5120 (/4 1280) >[299310.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4096940] >[299311.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4096940] width 1280 pitch 5120 (/4 1280) >[299311.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0] >[299311.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1280 pitch 5120 (/4 1280) >[299311.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4096850] >[299311.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4096850] width 1280 pitch 5120 (/4 1280) >[299311.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0] >[299311.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1280 pitch 5120 (/4 1280) >[299311.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4096850] >[299311.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4096850] width 1280 pitch 5120 (/4 1280) >[299311.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0] >[299311.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1280 pitch 5120 (/4 1280) >[299311.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4096850] >[299311.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4096850] width 1280 pitch 5120 (/4 1280) >[299311.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0] >[299311.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1280 pitch 5120 (/4 1280) >[299311.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4096850] >[299311.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4096850] width 1280 pitch 5120 (/4 1280) >[299317.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299317.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299319.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[299319.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[299319.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299319.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299319.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6960] >[299319.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6960] width 1280 pitch 5120 (/4 1280) >[299320.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[299320.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[299320.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[299320.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[299320.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299320.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299320.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[299320.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[299320.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40754d0] >[299320.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40754d0] width 1280 pitch 5120 (/4 1280) >[299320.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c2560] >[299320.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c2560] width 1280 pitch 5120 (/4 1280) >[299321.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faaf30] >[299321.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faaf30] width 1280 pitch 5120 (/4 1280) >[299321.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cf4c0] >[299321.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cf4c0] width 1280 pitch 5120 (/4 1280) >[299321.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d56f0] >[299321.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d56f0] width 1280 pitch 5120 (/4 1280) >[299321.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d56f0] >[299321.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d56f0] width 1280 pitch 5120 (/4 1280) >[299321.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cf350] >[299321.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cf350] width 1280 pitch 5120 (/4 1280) >[299325.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299325.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299326.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299326.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299326.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299326.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299326.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299327.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299327.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299327.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299327.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299327.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299327.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299327.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299327.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299327.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299327.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299327.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299327.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299327.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299327.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299327.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299327.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299327.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[299327.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[299327.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299327.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299327.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[299327.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[299327.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299327.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299327.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[299327.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[299327.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299327.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299327.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[299327.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[299328.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299328.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299328.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401b860] >[299328.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401b860] width 1280 pitch 5120 (/4 1280) >[299329.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401b860] >[299329.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401b860] width 1280 pitch 5120 (/4 1280) >[299329.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299329.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299329.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1110] >[299329.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1110] width 1280 pitch 5120 (/4 1280) >[299329.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1110] >[299329.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1110] width 1280 pitch 5120 (/4 1280) >[299329.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1110] >[299329.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1110] width 1280 pitch 5120 (/4 1280) >[299329.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1110] >[299329.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1110] width 1280 pitch 5120 (/4 1280) >[299329.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1110] >[299329.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1110] width 1280 pitch 5120 (/4 1280) >[299329.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299329.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299329.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401b860] >[299329.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401b860] width 1280 pitch 5120 (/4 1280) >[299329.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299330.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299330.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401b860] >[299330.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401b860] width 1280 pitch 5120 (/4 1280) >[299330.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[299330.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[299333.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299333.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299333.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299333.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299335.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299335.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299335.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299335.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299335.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299335.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299335.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299335.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299335.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299335.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299335.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299335.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299336.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[299336.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[299336.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406cbd0] >[299336.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406cbd0] width 1280 pitch 5120 (/4 1280) >[299336.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299336.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299336.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406cbd0] >[299336.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406cbd0] width 1280 pitch 5120 (/4 1280) >[299336.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299336.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299336.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406cbd0] >[299336.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406cbd0] width 1280 pitch 5120 (/4 1280) >[299336.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299336.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299336.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406cbd0] >[299336.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406cbd0] width 1280 pitch 5120 (/4 1280) >[299336.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299336.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299336.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406cbd0] >[299336.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406cbd0] width 1280 pitch 5120 (/4 1280) >[299336.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[299336.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[299337.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082a20] >[299337.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082a20] width 1280 pitch 5120 (/4 1280) >[299337.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0f80] >[299337.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0f80] width 1280 pitch 5120 (/4 1280) >[299343.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299343.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299345.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299345.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299350.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401bee0] >[299350.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401bee0] width 1280 pitch 5120 (/4 1280) >[299350.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299350.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299351.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086180] >[299351.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086180] width 1280 pitch 5120 (/4 1280) >[299352.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401bee0] >[299352.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401bee0] width 1280 pitch 5120 (/4 1280) >[299352.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086180] >[299352.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086180] width 1280 pitch 5120 (/4 1280) >[299352.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401bee0] >[299352.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401bee0] width 1280 pitch 5120 (/4 1280) >[299352.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086180] >[299352.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086180] width 1280 pitch 5120 (/4 1280) >[299352.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401bee0] >[299352.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401bee0] width 1280 pitch 5120 (/4 1280) >[299352.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086180] >[299352.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086180] width 1280 pitch 5120 (/4 1280) >[299353.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086180] >[299353.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086180] width 1280 pitch 5120 (/4 1280) >[299353.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408d7f0] >[299353.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408d7f0] width 1280 pitch 5120 (/4 1280) >[299353.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048e60] >[299353.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048e60] width 1280 pitch 5120 (/4 1280) >[299353.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408d0e0] >[299353.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408d0e0] width 1280 pitch 5120 (/4 1280) >[299353.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408d7f0] >[299353.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408d7f0] width 1280 pitch 5120 (/4 1280) >[299353.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13c1430] >[299353.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13c1430] width 1280 pitch 5120 (/4 1280) >[299475.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ced50] >[299475.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ced50] width 1280 pitch 5120 (/4 1280) >[299475.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ced50] >[299475.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ced50] width 1280 pitch 5120 (/4 1280) >[299534.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ccd90] >[299534.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ccd90] width 1280 pitch 5120 (/4 1280) >[299534.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ccd90] >[299534.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ccd90] width 1280 pitch 5120 (/4 1280) >[299576.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ffec40] >[299576.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ffec40] width 1280 pitch 5120 (/4 1280) >[299576.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412c200] >[299576.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412c200] width 1280 pitch 5120 (/4 1280) >[299590.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41cdab0] >[299590.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41cdab0] width 1280 pitch 5120 (/4 1280) >[299613.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299613.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299613.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e9600] >[299613.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e9600] width 1280 pitch 5120 (/4 1280) >[299631.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299631.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299631.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299631.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299670.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299670.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299685.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299685.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299685.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299685.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299685.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299685.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299685.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299685.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299685.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299685.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299685.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299685.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299685.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299685.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299685.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299685.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299685.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299685.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299685.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299685.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299685.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299685.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299685.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299685.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299685.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299685.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299685.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299685.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299685.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299686.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299686.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299686.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299686.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299686.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299686.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299686.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299686.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299686.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299686.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299686.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299686.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299686.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299686.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299686.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299686.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299686.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299686.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299686.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299686.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299686.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299686.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299686.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299686.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299686.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299686.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299686.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299686.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299687.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402adb0] >[299687.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402adb0] width 1280 pitch 5120 (/4 1280) >[299687.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e21a0] >[299687.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e21a0] width 1280 pitch 5120 (/4 1280) >[299687.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299687.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299687.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e21a0] >[299687.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e21a0] width 1280 pitch 5120 (/4 1280) >[299687.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[299687.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[299687.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e21a0] >[299687.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e21a0] width 1280 pitch 5120 (/4 1280) >[299687.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299687.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299687.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299687.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299687.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299687.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299687.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299687.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299687.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2bb0] >[299687.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2bb0] width 1280 pitch 5120 (/4 1280) >[299687.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4237ef0] >[299687.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4237ef0] width 1280 pitch 5120 (/4 1280) >[299687.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2bb0] >[299687.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2bb0] width 1280 pitch 5120 (/4 1280) >[299687.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fadd90] >[299687.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fadd90] width 1280 pitch 5120 (/4 1280) >[299688.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023900] >[299688.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023900] width 1280 pitch 5120 (/4 1280) >[299688.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023960] >[299688.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023960] width 1280 pitch 5120 (/4 1280) >[299688.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059630] >[299688.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059630] width 1280 pitch 5120 (/4 1280) >[299688.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059400] >[299688.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059400] width 1280 pitch 5120 (/4 1280) >[299688.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059460] >[299688.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059460] width 1280 pitch 5120 (/4 1280) >[299688.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053330] >[299688.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053330] width 1280 pitch 5120 (/4 1280) >[299688.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4068e50] >[299688.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4068e50] width 1280 pitch 5120 (/4 1280) >[299688.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405b7c0] >[299688.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405b7c0] width 1280 pitch 5120 (/4 1280) >[299688.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41cfa90] >[299688.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41cfa90] width 1280 pitch 5120 (/4 1280) >[299688.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4068e10] >[299688.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4068e10] width 1280 pitch 5120 (/4 1280) >[299688.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4068e10] >[299688.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4068e10] width 1280 pitch 5120 (/4 1280) >[299688.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c380] >[299688.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c380] width 1280 pitch 5120 (/4 1280) >[299688.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062e80] >[299688.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062e80] width 1280 pitch 5120 (/4 1280) >[299688.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059c20] >[299688.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059c20] width 1280 pitch 5120 (/4 1280) >[299688.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062e80] >[299688.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062e80] width 1280 pitch 5120 (/4 1280) >[299688.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c4f0] >[299688.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c4f0] width 1280 pitch 5120 (/4 1280) >[299688.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c4f0] >[299688.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c4f0] width 1280 pitch 5120 (/4 1280) >[299688.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c4f0] >[299688.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c4f0] width 1280 pitch 5120 (/4 1280) >[299688.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c4f0] >[299688.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c4f0] width 1280 pitch 5120 (/4 1280) >[299688.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c4f0] >[299688.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c4f0] width 1280 pitch 5120 (/4 1280) >[299688.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062eb0] >[299688.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062eb0] width 1280 pitch 5120 (/4 1280) >[299688.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062eb0] >[299688.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062eb0] width 1280 pitch 5120 (/4 1280) >[299688.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299688.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062eb0] >[299688.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062eb0] width 1280 pitch 5120 (/4 1280) >[299688.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e1f50] >[299688.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e1f50] width 1280 pitch 5120 (/4 1280) >[299689.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067c80] >[299689.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067c80] width 1280 pitch 5120 (/4 1280) >[299690.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299690.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299690.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299690.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299690.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402adb0] >[299690.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402adb0] width 1280 pitch 5120 (/4 1280) >[299690.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299690.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299690.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299690.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299690.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299690.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299690.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299690.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299690.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299690.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299690.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299690.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299690.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299690.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299691.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2bb0] >[299691.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2bb0] width 1280 pitch 5120 (/4 1280) >[299691.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fadd90] >[299691.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fadd90] width 1280 pitch 5120 (/4 1280) >[299691.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2bb0] >[299691.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2bb0] width 1280 pitch 5120 (/4 1280) >[299695.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299695.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299695.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4131b90] >[299695.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4131b90] width 1280 pitch 5120 (/4 1280) >[299695.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[299695.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[299695.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[299695.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[299695.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d804a0] >[299695.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d804a0] width 1280 pitch 5120 (/4 1280) >[299695.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[299695.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[299695.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423e250] >[299695.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423e250] width 1280 pitch 5120 (/4 1280) >[299695.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[299695.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[299696.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fadd90] >[299696.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fadd90] width 1280 pitch 5120 (/4 1280) >[299696.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299696.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299696.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402adb0] >[299696.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402adb0] width 1280 pitch 5120 (/4 1280) >[299696.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299696.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299696.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9acb0] >[299696.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9acb0] width 1280 pitch 5120 (/4 1280) >[299696.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd940] >[299696.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd940] width 1280 pitch 5120 (/4 1280) >[299705.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299705.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299705.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299705.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299705.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299705.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299705.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299705.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299705.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[299705.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[299705.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299705.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299705.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[299705.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[299705.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299705.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299705.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb28d0] >[299705.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb28d0] width 1280 pitch 5120 (/4 1280) >[299705.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[299705.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[299706.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299706.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299706.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[299706.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[299706.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c100] >[299706.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c100] width 1280 pitch 5120 (/4 1280) >[299706.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0bbf0] >[299706.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0bbf0] width 1280 pitch 5120 (/4 1280) >[299706.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299706.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299706.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0bbf0] >[299706.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0bbf0] width 1280 pitch 5120 (/4 1280) >[299706.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299706.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299706.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299706.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299706.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299706.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299706.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299706.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299706.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb28d0] >[299706.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb28d0] width 1280 pitch 5120 (/4 1280) >[299707.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402adb0] >[299707.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402adb0] width 1280 pitch 5120 (/4 1280) >[299707.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9acb0] >[299707.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9acb0] width 1280 pitch 5120 (/4 1280) >[299707.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299707.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299707.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2bb0] >[299707.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2bb0] width 1280 pitch 5120 (/4 1280) >[299707.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299707.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299707.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299707.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299707.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299707.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299707.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299707.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299707.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[299707.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[299707.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[299707.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[299707.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299707.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299707.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baaa0] >[299707.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baaa0] width 1280 pitch 5120 (/4 1280) >[299707.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0bbf0] >[299707.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0bbf0] width 1280 pitch 5120 (/4 1280) >[299707.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baaa0] >[299707.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baaa0] width 1280 pitch 5120 (/4 1280) >[299707.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299707.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299707.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baaa0] >[299707.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baaa0] width 1280 pitch 5120 (/4 1280) >[299707.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299707.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299707.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c100] >[299707.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c100] width 1280 pitch 5120 (/4 1280) >[299707.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[299707.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[299708.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299708.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299709.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299709.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299709.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[299709.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[299709.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299709.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299710.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[299710.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[299710.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6800] >[299710.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6800] width 1280 pitch 5120 (/4 1280) >[299710.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd650] >[299710.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd650] width 1280 pitch 5120 (/4 1280) >[299710.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9acb0] >[299710.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9acb0] width 1280 pitch 5120 (/4 1280) >[299710.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd650] >[299710.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd650] width 1280 pitch 5120 (/4 1280) >[299710.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9acb0] >[299710.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9acb0] width 1280 pitch 5120 (/4 1280) >[299710.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd650] >[299710.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd650] width 1280 pitch 5120 (/4 1280) >[299710.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299710.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299711.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c100] >[299711.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c100] width 1280 pitch 5120 (/4 1280) >[299711.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e990a0] >[299711.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e990a0] width 1280 pitch 5120 (/4 1280) >[299711.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6f30] >[299711.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6f30] width 1280 pitch 5120 (/4 1280) >[299711.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299711.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299711.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[299711.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[299711.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[299711.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[299711.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[299711.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[299712.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[299712.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[299712.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[299712.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[299712.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299712.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299712.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baaa0] >[299712.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baaa0] width 1280 pitch 5120 (/4 1280) >[299712.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401c710] >[299712.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401c710] width 1280 pitch 5120 (/4 1280) >[299712.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0bbf0] >[299712.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0bbf0] width 1280 pitch 5120 (/4 1280) >[299712.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1159950] >[299712.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1159950] width 1280 pitch 5120 (/4 1280) >[299713.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299713.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299713.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[299713.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[299714.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299714.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299714.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[299714.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[299714.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[299714.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[299714.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c3b0] >[299714.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c3b0] width 1280 pitch 5120 (/4 1280) >[299714.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299714.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299714.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299714.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299714.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299714.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299714.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[299714.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[299714.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299714.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299714.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4231930] >[299714.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4231930] width 1280 pitch 5120 (/4 1280) >[299714.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299714.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299714.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4231930] >[299714.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4231930] width 1280 pitch 5120 (/4 1280) >[299714.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[299714.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[299714.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[299714.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[299714.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[299714.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[299714.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[299714.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[299714.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299714.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299714.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[299714.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[299714.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299714.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299714.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[299714.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[299714.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[299714.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[299714.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[299714.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[299714.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[299714.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[299714.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[299714.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[299714.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[299714.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[299714.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[299714.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[299714.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[299714.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[299714.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[299714.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[299714.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299714.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299714.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[299714.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[299714.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[299714.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[299716.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[299716.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[299716.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40265e0] >[299716.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40265e0] width 1280 pitch 5120 (/4 1280) >[299716.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299716.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299716.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[299716.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[299716.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e2850] >[299716.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e2850] width 1280 pitch 5120 (/4 1280) >[299716.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[299717.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[299717.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[299717.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[299717.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025aa0] >[299717.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025aa0] width 1280 pitch 5120 (/4 1280) >[299718.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4231930] >[299718.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4231930] width 1280 pitch 5120 (/4 1280) >[299718.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4231930] >[299718.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4231930] width 1280 pitch 5120 (/4 1280) >[299718.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9acb0] >[299718.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9acb0] width 1280 pitch 5120 (/4 1280) >[299718.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c6e0] >[299718.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c6e0] width 1280 pitch 5120 (/4 1280) >[299718.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4231930] >[299718.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4231930] width 1280 pitch 5120 (/4 1280) >[299718.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c6e0] >[299718.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c6e0] width 1280 pitch 5120 (/4 1280) >[300016.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40253e0] >[300016.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40253e0] width 1280 pitch 5120 (/4 1280) >[300016.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ec290] >[300016.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ec290] width 1280 pitch 5120 (/4 1280) >[300016.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300016.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300016.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300016.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300016.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300016.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300016.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300016.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300016.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300016.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300016.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300016.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300016.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300017.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300017.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300017.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300017.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300017.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300017.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4019fd0] >[300017.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4019fd0] width 1280 pitch 5120 (/4 1280) >[300017.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c6e0] >[300017.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c6e0] width 1280 pitch 5120 (/4 1280) >[300017.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300017.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406c6e0] >[300017.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406c6e0] width 1280 pitch 5120 (/4 1280) >[300017.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[300017.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[300661.941] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[300661.941] (II) RADEON(0): Printing DDC gathered Modelines: >[300661.941] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[300751.886] (II) RADEON(0): RADEONSaveScreen(2) >[300751.886] (II) RADEON(0): RADEONSaveScreen(0) >[302169.063] (II) RADEON(0): RADEONSaveScreen(1) >[302179.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302179.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302185.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e4260] >[302185.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e4260] width 1280 pitch 5120 (/4 1280) >[302185.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406e030] >[302185.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406e030] width 1280 pitch 5120 (/4 1280) >[302337.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302337.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302337.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302337.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302337.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302337.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302337.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302337.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302337.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302337.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302337.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302337.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302337.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302338.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302338.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302338.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302338.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302338.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302338.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302338.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302338.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302338.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302338.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302338.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302338.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302338.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302338.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302338.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302338.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302338.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302338.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302338.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302339.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302339.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302339.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302339.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302339.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302339.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302340.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302340.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302340.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302340.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302340.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302340.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302340.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302340.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e43a0] >[302341.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e43a0] width 1280 pitch 5120 (/4 1280) >[302341.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302341.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302341.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302341.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302341.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302342.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302342.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d47e70] >[302342.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d47e70] width 1280 pitch 5120 (/4 1280) >[302342.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc97b0] >[302342.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc97b0] width 1280 pitch 5120 (/4 1280) >[302348.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb3a0] >[302348.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb3a0] width 1280 pitch 5120 (/4 1280) >[302350.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302350.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302352.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302352.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302353.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeec20] >[302353.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeec20] width 1280 pitch 5120 (/4 1280) >[302363.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc6520] >[302363.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc6520] width 1280 pitch 5120 (/4 1280) >[302492.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e48c0] >[302492.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e48c0] width 1280 pitch 5120 (/4 1280) >[302495.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5490] >[302495.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5490] width 1280 pitch 5120 (/4 1280) >[302497.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400c6d0] >[302497.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400c6d0] width 1280 pitch 5120 (/4 1280) >[302528.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4016490] >[302528.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4016490] width 1280 pitch 5120 (/4 1280) >[302538.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302538.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302538.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302538.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302538.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302538.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302538.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302538.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302538.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302538.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302538.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302538.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302538.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302538.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302538.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302538.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302538.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302538.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302538.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302538.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302538.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302538.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302538.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302538.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302538.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302538.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302538.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302539.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302539.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302539.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302539.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302539.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302539.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302539.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302539.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302539.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302539.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302539.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302539.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302539.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302539.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302539.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302539.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302539.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302539.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302539.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302539.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302539.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302539.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302539.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302539.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4017540] >[302539.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4017540] width 1280 pitch 5120 (/4 1280) >[302539.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302540.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302540.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302540.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302540.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302540.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302540.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2741710] >[302540.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2741710] width 1280 pitch 5120 (/4 1280) >[302540.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302540.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302540.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302540.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302540.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa8850] >[302540.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa8850] width 1280 pitch 5120 (/4 1280) >[302541.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302541.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa8850] >[302541.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa8850] width 1280 pitch 5120 (/4 1280) >[302541.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f3c30] >[302541.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f3c30] width 1280 pitch 5120 (/4 1280) >[302541.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302541.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302541.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302541.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302541.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302541.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302541.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa8850] >[302541.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa8850] width 1280 pitch 5120 (/4 1280) >[302541.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f3c30] >[302541.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f3c30] width 1280 pitch 5120 (/4 1280) >[302541.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302541.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302541.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa8850] >[302541.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa8850] width 1280 pitch 5120 (/4 1280) >[302541.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302541.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302541.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302541.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f3c30] >[302541.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f3c30] width 1280 pitch 5120 (/4 1280) >[302541.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd8d0] >[302541.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd8d0] width 1280 pitch 5120 (/4 1280) >[302541.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302541.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa8850] >[302541.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa8850] width 1280 pitch 5120 (/4 1280) >[302541.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f3c30] >[302541.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f3c30] width 1280 pitch 5120 (/4 1280) >[302541.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f29090] >[302541.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f29090] width 1280 pitch 5120 (/4 1280) >[302541.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f3c30] >[302541.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f3c30] width 1280 pitch 5120 (/4 1280) >[302541.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a390] >[302541.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a390] width 1280 pitch 5120 (/4 1280) >[302545.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4194f90] >[302545.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4194f90] width 1280 pitch 5120 (/4 1280) >[302552.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e4800] >[302552.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e4800] width 1280 pitch 5120 (/4 1280) >[302552.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e4800] >[302552.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e4800] width 1280 pitch 5120 (/4 1280) >[302559.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eceb70] >[302559.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eceb70] width 1280 pitch 5120 (/4 1280) >[302560.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5380] >[302560.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5380] width 1280 pitch 5120 (/4 1280) >[302585.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5530] >[302585.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5530] width 1280 pitch 5120 (/4 1280) >[302585.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039840] >[302585.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039840] width 1280 pitch 5120 (/4 1280) >[302633.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302633.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302633.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302633.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302633.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302633.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302633.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302633.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302633.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302633.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302633.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302634.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e5000] >[302634.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e5000] width 1280 pitch 5120 (/4 1280) >[302634.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff4730] >[302634.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff4730] width 1280 pitch 5120 (/4 1280) >[302634.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e5000] >[302634.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e5000] width 1280 pitch 5120 (/4 1280) >[302634.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff4730] >[302634.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff4730] width 1280 pitch 5120 (/4 1280) >[302634.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302634.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302634.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff4730] >[302634.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff4730] width 1280 pitch 5120 (/4 1280) >[302634.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302634.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302634.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff4730] >[302634.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff4730] width 1280 pitch 5120 (/4 1280) >[302635.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302635.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302635.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5530] >[302635.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5530] width 1280 pitch 5120 (/4 1280) >[302636.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5530] >[302636.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5530] width 1280 pitch 5120 (/4 1280) >[302636.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee870] >[302636.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee870] width 1280 pitch 5120 (/4 1280) >[302636.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302636.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302637.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae6b0] >[302637.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae6b0] width 1280 pitch 5120 (/4 1280) >[302637.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302637.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302680.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4136ac0] >[302680.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4136ac0] width 1280 pitch 5120 (/4 1280) >[302706.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa12a0] >[302706.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa12a0] width 1280 pitch 5120 (/4 1280) >[302706.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa2230] >[302706.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa2230] width 1280 pitch 5120 (/4 1280) >[302747.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5530] >[302747.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5530] width 1280 pitch 5120 (/4 1280) >[302747.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407d580] >[302747.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407d580] width 1280 pitch 5120 (/4 1280) >[302875.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa13e0] >[302875.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa13e0] width 1280 pitch 5120 (/4 1280) >[302876.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067550] >[302876.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067550] width 1280 pitch 5120 (/4 1280) >[303330.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff1850] >[303330.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff1850] width 1280 pitch 5120 (/4 1280) >[303330.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40662a0] >[303330.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40662a0] width 1280 pitch 5120 (/4 1280) >[303334.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41dc740] >[303334.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41dc740] width 1280 pitch 5120 (/4 1280) >[303335.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40662a0] >[303335.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40662a0] width 1280 pitch 5120 (/4 1280) >[303467.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fef9f0] >[303467.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fef9f0] width 1280 pitch 5120 (/4 1280) >[303589.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303589.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303589.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303589.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303589.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303589.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303589.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303589.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40203d0] >[303589.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40203d0] width 1280 pitch 5120 (/4 1280) >[303600.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff0a40] >[303600.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff0a40] width 1280 pitch 5120 (/4 1280) >[303600.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303600.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303600.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303600.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9b30] >[303600.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9b30] width 1280 pitch 5120 (/4 1280) >[303637.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4219a20] >[303637.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4219a20] width 1280 pitch 5120 (/4 1280) >[303969.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303969.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303969.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303969.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303969.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303969.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303970.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303970.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c8af0] >[303994.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c8af0] width 1280 pitch 5120 (/4 1280) >[303994.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303994.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303994.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303994.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303994.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303994.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303994.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303995.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303995.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303995.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303995.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303995.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303995.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303995.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303995.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303995.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303995.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303995.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303995.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303995.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303995.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303995.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303995.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303995.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303995.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303995.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303995.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303995.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303995.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303995.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303995.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303996.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303996.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303996.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303996.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303996.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303996.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303996.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303996.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303996.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303996.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303996.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303996.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303996.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303996.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303996.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4064e90] >[303996.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4064e90] width 1280 pitch 5120 (/4 1280) >[303996.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303996.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[303997.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303997.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303997.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303997.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303997.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303997.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303997.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303997.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303997.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[303997.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[303998.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303998.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303998.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303998.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303998.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303998.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303998.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303998.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303998.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[303998.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[303998.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c90c0] >[303998.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c90c0] width 1280 pitch 5120 (/4 1280) >[303998.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa71c0] >[303998.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa71c0] width 1280 pitch 5120 (/4 1280) >[304003.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304003.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304003.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304003.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304003.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304003.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304003.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304003.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304003.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304003.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304003.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304003.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304003.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304003.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304004.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304004.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304004.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304004.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304004.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304004.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304004.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304004.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304004.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304004.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304004.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304005.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304005.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304005.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304005.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304005.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304005.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304005.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304005.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304005.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304005.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304005.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304005.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304005.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304005.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304005.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304005.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304005.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304005.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f050] >[304006.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f050] width 1280 pitch 5120 (/4 1280) >[304006.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304006.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304006.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304006.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304006.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304006.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304006.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304006.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304006.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41504c0] >[304006.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41504c0] width 1280 pitch 5120 (/4 1280) >[304006.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304006.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304006.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304006.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304006.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b0f0] >[304006.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b0f0] width 1280 pitch 5120 (/4 1280) >[304006.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[304006.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[304006.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[304006.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[304006.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[304006.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[304006.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[304006.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[304006.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[304006.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[304007.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[304007.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[304007.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304007.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304007.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304007.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304007.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304063.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304063.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304063.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[304063.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[304063.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304063.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304063.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304064.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304064.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[304064.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[304064.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304064.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304064.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fdbf0] >[304064.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fdbf0] width 1280 pitch 5120 (/4 1280) >[304064.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304064.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304064.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42319b0] >[304064.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42319b0] width 1280 pitch 5120 (/4 1280) >[304064.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f130] >[304064.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f130] width 1280 pitch 5120 (/4 1280) >[304065.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42319b0] >[304065.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42319b0] width 1280 pitch 5120 (/4 1280) >[304065.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304065.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304066.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304066.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304066.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42317e0] >[304066.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42317e0] width 1280 pitch 5120 (/4 1280) >[304066.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304066.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304066.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42317e0] >[304066.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42317e0] width 1280 pitch 5120 (/4 1280) >[304066.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304066.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304066.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42317e0] >[304066.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42317e0] width 1280 pitch 5120 (/4 1280) >[304067.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304067.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304067.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304067.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304067.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304067.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304067.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304067.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304068.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304068.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304068.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304068.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304068.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304068.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304068.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304068.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304068.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0ea0] >[304068.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0ea0] width 1280 pitch 5120 (/4 1280) >[304068.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304069.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304069.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0ea0] >[304069.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0ea0] width 1280 pitch 5120 (/4 1280) >[304069.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304069.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304069.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0ea0] >[304069.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0ea0] width 1280 pitch 5120 (/4 1280) >[304069.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304069.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304069.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f263c0] >[304069.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f263c0] width 1280 pitch 5120 (/4 1280) >[304069.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304069.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304069.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304069.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304070.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304070.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304070.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e670] >[304070.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e670] width 1280 pitch 5120 (/4 1280) >[304070.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304070.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304070.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304070.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304070.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304070.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304070.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c2f0] >[304070.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c2f0] width 1280 pitch 5120 (/4 1280) >[304071.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304071.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304071.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304071.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304071.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304071.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304071.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304071.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304071.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304071.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304071.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f133c0] >[304071.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f133c0] width 1280 pitch 5120 (/4 1280) >[304071.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4380] >[304071.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4380] width 1280 pitch 5120 (/4 1280) >[304072.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5f90] >[304072.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5f90] width 1280 pitch 5120 (/4 1280) >[304074.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0ea0] >[304074.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0ea0] width 1280 pitch 5120 (/4 1280) >[304074.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304074.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304074.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0ea0] >[304074.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0ea0] width 1280 pitch 5120 (/4 1280) >[304074.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40954e0] >[304074.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40954e0] width 1280 pitch 5120 (/4 1280) >[304075.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40263a0] >[304075.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40263a0] width 1280 pitch 5120 (/4 1280) >[304075.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40954e0] >[304075.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40954e0] width 1280 pitch 5120 (/4 1280) >[304075.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304075.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304075.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304075.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304075.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304075.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304075.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304075.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304075.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304075.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304083.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304083.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304083.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304083.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304120.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40954e0] >[304120.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40954e0] width 1280 pitch 5120 (/4 1280) >[304120.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[304120.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[304512.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304512.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304512.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304512.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304512.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304512.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304512.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304512.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304512.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304512.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304512.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304512.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304512.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304512.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304512.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304512.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304512.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304512.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304512.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304512.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304512.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304512.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304512.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304512.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304512.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304512.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304513.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304513.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304513.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304513.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304513.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304513.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304513.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304513.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304513.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304513.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304513.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304513.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304513.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304513.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304513.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304513.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304514.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304514.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304514.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304514.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304514.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304514.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304514.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304514.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304514.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304514.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304514.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304514.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304514.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[304514.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[304514.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304514.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304514.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[304514.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[304514.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40554c0] >[304514.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40554c0] width 1280 pitch 5120 (/4 1280) >[304514.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304514.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304514.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304514.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304514.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304514.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304515.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304515.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304515.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304515.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304515.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304515.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304515.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304515.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304515.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304515.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304515.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304515.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304515.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304515.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304515.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feb970] >[304515.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feb970] width 1280 pitch 5120 (/4 1280) >[304515.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[304515.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[304515.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304515.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304516.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304516.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304517.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304517.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304517.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487850] >[304517.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487850] width 1280 pitch 5120 (/4 1280) >[304517.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304517.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304517.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[304517.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[304517.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3feac30] >[304517.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3feac30] width 1280 pitch 5120 (/4 1280) >[304517.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[304517.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[304517.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304517.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304517.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7870] >[304517.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7870] width 1280 pitch 5120 (/4 1280) >[304517.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40241e0] >[304517.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40241e0] width 1280 pitch 5120 (/4 1280) >[304517.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304517.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304517.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304517.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304517.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebd6b0] >[304517.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebd6b0] width 1280 pitch 5120 (/4 1280) >[304517.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa1e60] >[304517.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa1e60] width 1280 pitch 5120 (/4 1280) >[304517.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f3d0] >[304517.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f3d0] width 1280 pitch 5120 (/4 1280) >[304517.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa1e60] >[304517.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa1e60] width 1280 pitch 5120 (/4 1280) >[304517.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41524e0] >[304517.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41524e0] width 1280 pitch 5120 (/4 1280) >[304517.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa1e60] >[304517.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa1e60] width 1280 pitch 5120 (/4 1280) >[304517.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa35f0] >[304517.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa35f0] width 1280 pitch 5120 (/4 1280) >[304517.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa35f0] >[304517.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa35f0] width 1280 pitch 5120 (/4 1280) >[304517.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304517.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304517.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa35f0] >[304517.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa35f0] width 1280 pitch 5120 (/4 1280) >[304518.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304518.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304518.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa35f0] >[304518.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa35f0] width 1280 pitch 5120 (/4 1280) >[304518.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304518.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304518.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa35f0] >[304518.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa35f0] width 1280 pitch 5120 (/4 1280) >[304518.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4078ba0] >[304518.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4078ba0] width 1280 pitch 5120 (/4 1280) >[304534.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c170] >[304534.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c170] width 1280 pitch 5120 (/4 1280) >[304535.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[304535.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[304535.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41524e0] >[304535.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41524e0] width 1280 pitch 5120 (/4 1280) >[304696.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41524e0] >[304696.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41524e0] width 1280 pitch 5120 (/4 1280) >[304696.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[304696.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[304764.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421ee50] >[304764.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421ee50] width 1280 pitch 5120 (/4 1280) >[304764.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413be70] >[304764.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413be70] width 1280 pitch 5120 (/4 1280) >[304901.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4140ce0] >[304901.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4140ce0] width 1280 pitch 5120 (/4 1280) >[304901.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[304901.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[304913.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421e890] >[304913.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421e890] width 1280 pitch 5120 (/4 1280) >[304914.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[304914.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[304914.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[304914.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[304914.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[304914.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[304914.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[304914.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[304914.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[304914.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[304914.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[304914.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[304914.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[304914.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[304914.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[304914.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[304914.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[304914.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[304914.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[304914.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[304914.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[304914.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[304914.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[304914.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[304914.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[304914.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[305514.421] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[305514.421] (II) RADEON(0): Printing DDC gathered Modelines: >[305514.421] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[305604.886] (II) RADEON(0): RADEONSaveScreen(2) >[305604.886] (II) RADEON(0): RADEONSaveScreen(0) >[315262.311] (II) RADEON(0): RADEONSaveScreen(1) >[315266.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[315266.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[315267.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315267.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315267.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315267.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315270.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315270.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315270.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[315270.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[315270.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315270.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315270.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[315270.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[315270.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315270.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315270.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[315270.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[315270.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315270.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315271.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315271.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315271.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315271.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315271.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413be70] >[315271.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413be70] width 1280 pitch 5120 (/4 1280) >[315271.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315271.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315271.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4232c70] >[315271.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4232c70] width 1280 pitch 5120 (/4 1280) >[315285.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315285.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315285.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315285.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315286.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315286.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315286.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315286.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315286.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315286.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315286.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315286.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315286.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315286.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315286.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315286.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315286.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315286.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315286.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408c590] >[315286.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408c590] width 1280 pitch 5120 (/4 1280) >[315286.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315286.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315286.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408c590] >[315286.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408c590] width 1280 pitch 5120 (/4 1280) >[315286.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315286.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315286.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315286.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315286.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[315286.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[315286.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315286.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315286.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315286.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315286.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315286.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315286.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315286.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315286.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315286.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315286.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315286.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315286.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408c590] >[315286.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408c590] width 1280 pitch 5120 (/4 1280) >[315286.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408c590] >[315286.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408c590] width 1280 pitch 5120 (/4 1280) >[315286.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408c590] >[315286.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408c590] width 1280 pitch 5120 (/4 1280) >[315286.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12d0ce0] >[315286.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12d0ce0] width 1280 pitch 5120 (/4 1280) >[315286.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315286.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315286.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315286.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315286.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315286.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315286.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[315286.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[315304.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315304.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315304.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315304.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315304.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315304.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315304.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315304.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315304.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315304.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315304.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315304.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315304.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315304.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315304.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315304.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315304.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315304.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315305.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315305.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315305.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315305.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315305.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315305.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315305.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315305.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315305.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315305.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315305.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315305.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315305.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315305.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315305.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315305.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315305.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315305.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315305.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315306.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315306.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315306.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315306.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315306.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315306.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315306.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315306.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315306.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315306.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315306.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315306.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315306.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315323.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4540] >[315323.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4540] width 1280 pitch 5120 (/4 1280) >[315323.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315323.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315323.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25970] >[315323.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25970] width 1280 pitch 5120 (/4 1280) >[315323.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315323.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315323.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315324.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315324.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315324.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315324.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315324.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315324.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315324.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315324.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315324.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315324.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315324.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315324.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315324.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315327.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315327.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315327.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315327.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315327.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315327.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315327.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315327.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315327.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315327.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315327.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315327.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315347.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315347.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315347.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315347.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315348.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315348.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315348.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315348.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315348.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315348.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315348.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315348.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315348.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315348.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315348.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315348.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315348.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee89a0] >[315348.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee89a0] width 1280 pitch 5120 (/4 1280) >[315348.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315348.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315352.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315352.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315352.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315352.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315352.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315352.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315352.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315352.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315352.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315353.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315353.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315353.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315357.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315357.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315357.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315357.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315357.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315357.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315357.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315357.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315357.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315357.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315357.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315357.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315358.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9f00] >[315358.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9f00] width 1280 pitch 5120 (/4 1280) >[315358.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315358.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315358.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315358.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315358.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315358.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315358.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315358.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315358.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315358.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315358.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315358.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315358.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315358.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315358.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315358.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315358.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[315359.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[315359.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315359.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315359.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[315359.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[315359.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007010] >[315359.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007010] width 1280 pitch 5120 (/4 1280) >[315359.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315359.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315359.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007010] >[315359.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007010] width 1280 pitch 5120 (/4 1280) >[315359.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315359.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315359.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007010] >[315359.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007010] width 1280 pitch 5120 (/4 1280) >[315359.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315359.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315359.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007010] >[315359.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007010] width 1280 pitch 5120 (/4 1280) >[315359.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315359.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315359.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007010] >[315359.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007010] width 1280 pitch 5120 (/4 1280) >[315359.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315359.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315361.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315361.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315361.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315361.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315362.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[315362.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[315362.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[315362.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[315362.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[315362.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[315362.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fca0f0] >[315362.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fca0f0] width 1280 pitch 5120 (/4 1280) >[315362.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11836a0] >[315362.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11836a0] width 1280 pitch 5120 (/4 1280) >[315362.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11836a0] >[315362.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11836a0] width 1280 pitch 5120 (/4 1280) >[315362.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315362.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315362.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9f00] >[315362.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9f00] width 1280 pitch 5120 (/4 1280) >[315362.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315362.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315362.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9f00] >[315362.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9f00] width 1280 pitch 5120 (/4 1280) >[315362.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315362.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315362.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421e2f0] >[315362.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421e2f0] width 1280 pitch 5120 (/4 1280) >[315362.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315362.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315362.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421e2f0] >[315362.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421e2f0] width 1280 pitch 5120 (/4 1280) >[315362.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315362.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315362.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315362.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315362.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315362.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315362.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315362.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315362.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b116c0] >[315362.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b116c0] width 1280 pitch 5120 (/4 1280) >[315365.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315365.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315367.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315367.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315367.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b60] >[315367.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b60] width 1280 pitch 5120 (/4 1280) >[315367.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315367.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315373.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4540] >[315373.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4540] width 1280 pitch 5120 (/4 1280) >[315373.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[315373.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[315373.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4540] >[315373.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4540] width 1280 pitch 5120 (/4 1280) >[315373.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315373.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315373.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315373.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315373.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315373.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315373.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315373.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315373.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315373.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315373.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315373.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315373.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315373.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315373.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315373.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315374.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315374.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315374.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315374.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315374.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41404d0] >[315374.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41404d0] width 1280 pitch 5120 (/4 1280) >[315374.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315374.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315374.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2362400] >[315374.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2362400] width 1280 pitch 5120 (/4 1280) >[315374.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315374.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315374.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9f00] >[315374.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9f00] width 1280 pitch 5120 (/4 1280) >[315374.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315374.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315374.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315374.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315374.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315374.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc1620] >[315374.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc1620] width 1280 pitch 5120 (/4 1280) >[315374.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315374.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315375.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4145bb0] >[315375.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4145bb0] width 1280 pitch 5120 (/4 1280) >[315375.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315375.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315375.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f450] >[315375.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f450] width 1280 pitch 5120 (/4 1280) >[315375.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x145b420] >[315375.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x145b420] width 1280 pitch 5120 (/4 1280) >[315375.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b60] >[315375.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b60] width 1280 pitch 5120 (/4 1280) >[315375.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[315375.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[315375.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b60] >[315375.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b60] width 1280 pitch 5120 (/4 1280) >[315377.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b4540] >[315377.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b4540] width 1280 pitch 5120 (/4 1280) >[315378.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315378.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315378.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11836a0] >[315378.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11836a0] width 1280 pitch 5120 (/4 1280) >[315378.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb120] >[315378.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb120] width 1280 pitch 5120 (/4 1280) >[315378.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1966c50] >[315378.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1966c50] width 1280 pitch 5120 (/4 1280) >[315407.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebc9e0] >[315407.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebc9e0] width 1280 pitch 5120 (/4 1280) >[315407.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[315407.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[315412.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315412.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315412.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2794ba0] >[315413.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2794ba0] width 1280 pitch 5120 (/4 1280) >[315413.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315413.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315413.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315413.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315413.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315413.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315413.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315413.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315413.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315413.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315413.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315413.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315413.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315413.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315414.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315414.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315414.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[315414.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[315414.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315414.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315415.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[315415.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[315415.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315415.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315415.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c5fa0] >[315415.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c5fa0] width 1280 pitch 5120 (/4 1280) >[315415.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315415.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315415.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[315415.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[315415.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315415.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315423.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315423.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315423.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445e30] >[315423.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445e30] width 1280 pitch 5120 (/4 1280) >[315435.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315435.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315438.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbaf40] >[315438.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbaf40] width 1280 pitch 5120 (/4 1280) >[315438.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315438.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315438.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27d1000] >[315438.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27d1000] width 1280 pitch 5120 (/4 1280) >[315438.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[315438.895] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[315438.895] (II) RADEON(0): Printing DDC gathered Modelines: >[315438.895] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[315438.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[315439.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315439.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315441.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[315441.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[315441.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2794ba0] >[315441.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2794ba0] width 1280 pitch 5120 (/4 1280) >[315441.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202da20] >[315441.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202da20] width 1280 pitch 5120 (/4 1280) >[315441.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315441.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315441.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x195e0b0] >[315441.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x195e0b0] width 1280 pitch 5120 (/4 1280) >[315441.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315441.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315441.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315441.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315442.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315442.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315455.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315455.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315474.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315474.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315474.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315474.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315474.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315474.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315474.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315474.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315475.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315475.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315475.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315475.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315480.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315480.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315484.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2794ba0] >[315484.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2794ba0] width 1280 pitch 5120 (/4 1280) >[315484.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315484.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315484.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202da20] >[315484.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202da20] width 1280 pitch 5120 (/4 1280) >[315484.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315484.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315485.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413de20] >[315485.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413de20] width 1280 pitch 5120 (/4 1280) >[315485.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce3540] >[315485.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce3540] width 1280 pitch 5120 (/4 1280) >[315485.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[315485.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[315485.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315485.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315485.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315485.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315541.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315541.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315541.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315541.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315542.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312910] >[315542.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312910] width 1280 pitch 5120 (/4 1280) >[315542.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315542.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315542.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315542.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315542.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0b760] >[315542.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0b760] width 1280 pitch 5120 (/4 1280) >[315619.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[315619.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[315620.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315620.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315621.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315621.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315621.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315621.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315621.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315621.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315621.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315621.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315630.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315630.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315630.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315630.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315630.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306c60] >[315630.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306c60] width 1280 pitch 5120 (/4 1280) >[315630.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[315630.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[315631.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[315631.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[315631.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315631.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315631.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315631.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315631.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315631.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315632.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315632.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315633.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315633.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315633.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315633.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315633.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[315633.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[315633.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315633.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315634.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315634.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315634.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[315634.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[315634.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315634.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315634.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[315634.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[315658.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315658.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315659.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315659.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315659.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315659.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315659.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[315659.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[315660.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[315660.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[315660.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[315660.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[315660.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[315660.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[315660.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[315660.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[315661.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315661.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315661.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[315661.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[315661.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315661.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315661.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315661.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315662.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[315662.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[315662.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315662.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315662.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315662.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315662.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315662.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315662.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[315662.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[315662.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315662.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315662.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[315662.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[315663.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315663.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315663.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315663.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315663.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315663.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315663.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315663.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315663.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315663.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315667.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315667.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315667.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315667.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315669.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315669.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315682.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315682.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315682.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315682.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315682.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315682.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315682.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315683.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315683.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315683.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315683.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315683.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315685.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315685.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315695.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315695.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315696.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315696.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315696.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315696.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315696.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315696.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315697.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315697.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315715.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315715.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315716.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315716.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315716.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315716.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315716.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315716.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315717.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4294330] >[315717.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4294330] width 1280 pitch 5120 (/4 1280) >[315720.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315720.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315720.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315720.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315720.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315720.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315720.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315720.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315730.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315730.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315730.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315730.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315730.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315730.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315730.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315730.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315731.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315731.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315731.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315731.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315732.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315732.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315732.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c4a90] >[315732.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c4a90] width 1280 pitch 5120 (/4 1280) >[315744.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315744.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315744.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315744.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315757.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4271a80] >[315757.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4271a80] width 1280 pitch 5120 (/4 1280) >[315758.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315758.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315760.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315760.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315760.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302870] >[315760.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302870] width 1280 pitch 5120 (/4 1280) >[315760.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315760.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315781.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[315781.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[315781.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315781.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315784.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4294330] >[315784.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4294330] width 1280 pitch 5120 (/4 1280) >[315784.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c4a90] >[315784.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c4a90] width 1280 pitch 5120 (/4 1280) >[315784.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315784.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315784.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315784.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315787.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315787.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315787.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315787.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315787.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315787.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315801.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315801.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315801.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[315801.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[315801.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315801.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315801.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[315801.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[315812.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[315812.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[315812.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315812.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315812.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315812.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315812.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315812.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315813.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315813.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315813.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fea230] >[315813.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fea230] width 1280 pitch 5120 (/4 1280) >[315813.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315813.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315813.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[315813.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[315813.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4290da0] >[315813.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4290da0] width 1280 pitch 5120 (/4 1280) >[315814.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315814.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315814.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315814.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315814.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284120] >[315814.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284120] width 1280 pitch 5120 (/4 1280) >[315866.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315866.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315867.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315867.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315867.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[315867.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[315867.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315867.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315871.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315871.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315872.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315872.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315872.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[315872.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[315872.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315872.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315878.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315878.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315878.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[315878.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[315878.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315878.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315878.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315878.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315890.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[315890.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[315894.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[315894.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[315896.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315896.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315896.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315896.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[315896.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[315896.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315896.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[315896.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[315896.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315896.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[315896.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[315896.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[315896.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[315896.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[315896.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[315896.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315896.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[315896.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[315896.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315896.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[315896.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[315896.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315896.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315897.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315897.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315898.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[315898.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[315898.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[315898.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[315898.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[315898.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[315902.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[315902.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[315902.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[315902.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[315902.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315902.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315902.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315902.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315902.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315902.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315903.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315903.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315903.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[315903.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[315903.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[315903.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[315903.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315903.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315903.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315903.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315903.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[315903.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[315903.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315903.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315904.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315904.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315905.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302870] >[315905.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302870] width 1280 pitch 5120 (/4 1280) >[315905.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[315905.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[315905.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[315905.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[315906.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42949f0] >[315906.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42949f0] width 1280 pitch 5120 (/4 1280) >[315932.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[315932.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[315944.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315944.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315944.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[315944.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[315944.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[315944.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[315944.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315944.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[315945.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[315945.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[315945.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[315945.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[315945.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[315945.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[315945.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[315945.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[315946.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[315946.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[315946.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315946.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315946.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[315946.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[315946.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fc590] >[315946.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fc590] width 1280 pitch 5120 (/4 1280) >[315959.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[315959.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[315959.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302870] >[315959.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302870] width 1280 pitch 5120 (/4 1280) >[315959.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[315959.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[315959.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[315959.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[315959.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[315959.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[315969.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[315969.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[315993.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[315993.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316000.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302870] >[316000.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302870] width 1280 pitch 5120 (/4 1280) >[316000.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[316000.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[316000.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316000.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316001.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316002.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316002.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316002.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316002.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316002.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316002.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[316002.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[316004.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316004.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316004.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316004.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316004.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316004.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316010.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316010.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316011.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316011.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316011.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316011.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316011.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c390] >[316011.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c390] width 1280 pitch 5120 (/4 1280) >[316011.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[316011.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[316011.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316011.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316015.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316015.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316016.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316016.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316016.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c390] >[316016.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c390] width 1280 pitch 5120 (/4 1280) >[316016.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316016.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316016.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316016.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316016.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316016.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316020.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[316020.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[316021.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316021.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316021.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316021.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316021.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316021.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316022.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316022.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316022.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41bca40] >[316022.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41bca40] width 1280 pitch 5120 (/4 1280) >[316022.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316022.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316022.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[316022.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[316023.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316023.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316023.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316023.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316041.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316041.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316043.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316043.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316043.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316043.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316043.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316043.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316045.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316045.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316046.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42747e0] >[316046.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42747e0] width 1280 pitch 5120 (/4 1280) >[316046.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316046.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316046.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42747e0] >[316046.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42747e0] width 1280 pitch 5120 (/4 1280) >[316060.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316060.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316062.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316062.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316083.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316083.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316083.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316083.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316083.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42747e0] >[316083.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42747e0] width 1280 pitch 5120 (/4 1280) >[316083.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316083.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316084.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316084.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316084.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316084.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316084.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316084.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316085.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[316085.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[316085.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14a6db0] >[316085.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14a6db0] width 1280 pitch 5120 (/4 1280) >[316086.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316086.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316086.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316086.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316086.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316086.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316086.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279570] >[316086.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279570] width 1280 pitch 5120 (/4 1280) >[316086.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316086.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316087.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316087.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316087.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316087.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316094.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316094.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316094.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316094.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316095.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316095.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316095.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316095.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316100.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316100.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316100.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316100.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316100.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316100.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316100.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316100.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316137.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316137.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316137.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316137.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316137.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316137.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316137.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316137.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316138.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[316138.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[316138.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316138.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316138.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316138.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316139.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316139.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316139.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316139.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316140.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316140.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316140.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316140.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316140.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[316140.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[316140.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316140.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316140.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316140.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316140.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316140.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316140.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316140.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316140.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316140.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316140.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316140.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316140.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316140.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316140.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316140.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316140.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316141.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316141.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316141.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316141.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316141.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316141.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316141.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316141.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42747e0] >[316141.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42747e0] width 1280 pitch 5120 (/4 1280) >[316141.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316141.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316141.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316141.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316141.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316141.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316141.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316141.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316141.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316141.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316141.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316141.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316141.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316141.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316141.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316141.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316141.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316141.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316141.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316141.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316141.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316141.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316142.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316142.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316142.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316142.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316142.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316142.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316147.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316147.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316147.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316147.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316148.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316148.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316148.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202c160] >[316148.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202c160] width 1280 pitch 5120 (/4 1280) >[316148.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316148.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316149.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316149.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316149.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316149.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316149.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316149.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316149.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316149.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316149.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316149.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316150.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316150.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316150.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316150.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316150.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316150.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316150.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316150.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316150.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316150.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316153.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316153.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316153.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316153.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316154.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316154.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316155.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316155.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316155.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316155.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316155.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316156.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316156.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316156.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316156.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316156.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316156.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316156.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316157.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316157.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316157.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316157.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316157.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316158.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316158.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316158.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316158.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316158.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316158.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316158.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316158.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316159.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40df690] >[316159.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40df690] width 1280 pitch 5120 (/4 1280) >[316160.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[316160.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[316160.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412f860] >[316160.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412f860] width 1280 pitch 5120 (/4 1280) >[316160.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bdd0] >[316160.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bdd0] width 1280 pitch 5120 (/4 1280) >[316160.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316160.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316160.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316160.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4439dc0] >[316163.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4439dc0] width 1280 pitch 5120 (/4 1280) >[316163.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4439dc0] >[316163.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4439dc0] width 1280 pitch 5120 (/4 1280) >[316163.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4439dc0] >[316163.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4439dc0] width 1280 pitch 5120 (/4 1280) >[316163.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4431ef0] >[316163.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4431ef0] width 1280 pitch 5120 (/4 1280) >[316163.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316163.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4431ef0] >[316163.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4431ef0] width 1280 pitch 5120 (/4 1280) >[316163.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4431ef0] >[316163.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4431ef0] width 1280 pitch 5120 (/4 1280) >[316163.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316163.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316164.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316164.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316164.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316164.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316165.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316165.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316165.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316165.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316165.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316165.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316166.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316166.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316166.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316166.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316167.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316167.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316167.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316167.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39bf0b0] >[316167.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39bf0b0] width 1280 pitch 5120 (/4 1280) >[316171.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f8d90] >[316171.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f8d90] width 1280 pitch 5120 (/4 1280) >[316171.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d330] >[316171.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d330] width 1280 pitch 5120 (/4 1280) >[316172.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2d0] >[316172.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2d0] width 1280 pitch 5120 (/4 1280) >[316172.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d330] >[316172.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d330] width 1280 pitch 5120 (/4 1280) >[316172.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2d0] >[316172.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2d0] width 1280 pitch 5120 (/4 1280) >[316172.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d190] >[316172.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d190] width 1280 pitch 5120 (/4 1280) >[316172.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d560] >[316172.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d560] width 1280 pitch 5120 (/4 1280) >[316172.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d190] >[316172.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d190] width 1280 pitch 5120 (/4 1280) >[316172.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d560] >[316173.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d560] width 1280 pitch 5120 (/4 1280) >[316173.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d190] >[316173.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d190] width 1280 pitch 5120 (/4 1280) >[316173.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d1f0] >[316173.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d1f0] width 1280 pitch 5120 (/4 1280) >[316183.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316183.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316183.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414160] >[316183.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414160] width 1280 pitch 5120 (/4 1280) >[316183.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316184.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316184.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414160] >[316184.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414160] width 1280 pitch 5120 (/4 1280) >[316184.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316184.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316184.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414160] >[316184.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414160] width 1280 pitch 5120 (/4 1280) >[316185.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316185.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316185.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414160] >[316185.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414160] width 1280 pitch 5120 (/4 1280) >[316185.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316185.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316185.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316185.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316185.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401d4a0] >[316185.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401d4a0] width 1280 pitch 5120 (/4 1280) >[316185.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316185.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316186.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316186.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316186.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414df0] >[316186.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414df0] width 1280 pitch 5120 (/4 1280) >[316186.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316186.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316186.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414df0] >[316186.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414df0] width 1280 pitch 5120 (/4 1280) >[316186.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316186.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316186.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414df0] >[316186.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414df0] width 1280 pitch 5120 (/4 1280) >[316186.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316187.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316187.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414df0] >[316187.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414df0] width 1280 pitch 5120 (/4 1280) >[316187.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d2b0] >[316187.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d2b0] width 1280 pitch 5120 (/4 1280) >[316187.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316187.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316187.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316187.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316187.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316187.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316187.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316187.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316188.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316188.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316189.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316189.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316189.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316189.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316189.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316189.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316189.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316189.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316189.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316189.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316190.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316190.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316192.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316192.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316192.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316192.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316192.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316192.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316192.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316192.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316192.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ff30] >[316192.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ff30] width 1280 pitch 5120 (/4 1280) >[316193.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316193.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316194.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316194.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316194.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316194.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316194.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316194.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316194.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414470] >[316194.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414470] width 1280 pitch 5120 (/4 1280) >[316195.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443af10] >[316195.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443af10] width 1280 pitch 5120 (/4 1280) >[316195.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d62200] >[316195.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d62200] width 1280 pitch 5120 (/4 1280) >[316195.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414df0] >[316195.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414df0] width 1280 pitch 5120 (/4 1280) >[316195.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443b240] >[316195.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443b240] width 1280 pitch 5120 (/4 1280) >[316195.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c28d00] >[316195.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c28d00] width 1280 pitch 5120 (/4 1280) >[316195.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443b240] >[316195.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443b240] width 1280 pitch 5120 (/4 1280) >[316205.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4410600] >[316205.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4410600] width 1280 pitch 5120 (/4 1280) >[316206.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316206.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316206.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4410600] >[316206.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4410600] width 1280 pitch 5120 (/4 1280) >[316206.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443af10] >[316206.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443af10] width 1280 pitch 5120 (/4 1280) >[316206.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ee5c0] >[316206.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ee5c0] width 1280 pitch 5120 (/4 1280) >[316206.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[316206.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[316207.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316207.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316208.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316208.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316209.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ee5c0] >[316209.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ee5c0] width 1280 pitch 5120 (/4 1280) >[316209.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316209.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316209.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ee5c0] >[316209.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ee5c0] width 1280 pitch 5120 (/4 1280) >[316214.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4410600] >[316214.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4410600] width 1280 pitch 5120 (/4 1280) >[316215.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316215.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316215.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316215.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316215.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d1d0] >[316215.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d1d0] width 1280 pitch 5120 (/4 1280) >[316215.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316215.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316216.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316216.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316216.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d1d0] >[316216.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d1d0] width 1280 pitch 5120 (/4 1280) >[316216.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316216.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316216.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d1d0] >[316216.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d1d0] width 1280 pitch 5120 (/4 1280) >[316216.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4410600] >[316216.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4410600] width 1280 pitch 5120 (/4 1280) >[316216.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4421500] >[316216.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4421500] width 1280 pitch 5120 (/4 1280) >[316216.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ee5c0] >[316216.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ee5c0] width 1280 pitch 5120 (/4 1280) >[316217.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446e5f0] >[316217.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446e5f0] width 1280 pitch 5120 (/4 1280) >[316225.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443b310] >[316225.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443b310] width 1280 pitch 5120 (/4 1280) >[316225.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316225.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316225.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443b310] >[316225.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443b310] width 1280 pitch 5120 (/4 1280) >[316225.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4474370] >[316226.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4474370] width 1280 pitch 5120 (/4 1280) >[316226.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443b310] >[316226.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443b310] width 1280 pitch 5120 (/4 1280) >[316228.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316228.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316228.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292900] >[316228.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292900] width 1280 pitch 5120 (/4 1280) >[316230.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316230.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316230.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316230.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316230.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412f860] >[316230.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412f860] width 1280 pitch 5120 (/4 1280) >[316230.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316230.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316230.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316230.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316230.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316230.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316230.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316230.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316230.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a5a0] >[316231.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a5a0] width 1280 pitch 5120 (/4 1280) >[316231.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316231.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316231.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316231.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316231.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316231.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316232.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316232.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316232.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316232.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316234.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316234.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316234.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316234.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316234.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316234.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316235.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4284dc0] >[316235.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4284dc0] width 1280 pitch 5120 (/4 1280) >[316235.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316235.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316235.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412f860] >[316236.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412f860] width 1280 pitch 5120 (/4 1280) >[316236.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316236.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316236.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f1e10] >[316236.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f1e10] width 1280 pitch 5120 (/4 1280) >[316236.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e42b0] >[316236.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e42b0] width 1280 pitch 5120 (/4 1280) >[316236.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316236.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316236.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316236.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316236.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316236.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316236.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316236.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316236.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316236.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316236.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316236.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316237.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316237.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316237.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412f860] >[316237.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412f860] width 1280 pitch 5120 (/4 1280) >[316237.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316237.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316237.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316237.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316237.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316237.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316237.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316237.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316237.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316237.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316237.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316237.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316237.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316237.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316237.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316237.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316237.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316237.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316237.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316237.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316237.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316237.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316237.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316237.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316237.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316237.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316237.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316237.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316237.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316237.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316237.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316237.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316238.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316238.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316238.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316238.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316238.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316238.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316238.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316238.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316238.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316239.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316239.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316239.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316239.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316239.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316239.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316239.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[316239.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[316239.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40df690] >[316239.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40df690] width 1280 pitch 5120 (/4 1280) >[316239.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316239.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316256.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4199a60] >[316256.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4199a60] width 1280 pitch 5120 (/4 1280) >[316372.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316372.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316372.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316372.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316372.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316372.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316372.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4471db0] >[316372.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4471db0] width 1280 pitch 5120 (/4 1280) >[316373.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316373.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316373.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316373.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316373.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44720b0] >[316373.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44720b0] width 1280 pitch 5120 (/4 1280) >[316373.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316373.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316376.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402890] >[316376.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402890] width 1280 pitch 5120 (/4 1280) >[316376.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316376.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316377.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402890] >[316377.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402890] width 1280 pitch 5120 (/4 1280) >[316377.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316377.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316378.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316378.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316378.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40788a0] >[316378.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40788a0] width 1280 pitch 5120 (/4 1280) >[316378.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316378.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279630] >[316378.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279630] width 1280 pitch 5120 (/4 1280) >[316378.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316378.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316381.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316381.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316382.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446bfe0] >[316382.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446bfe0] width 1280 pitch 5120 (/4 1280) >[316382.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4193d60] >[316382.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4193d60] width 1280 pitch 5120 (/4 1280) >[316382.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316382.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316382.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446bfe0] >[316382.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446bfe0] width 1280 pitch 5120 (/4 1280) >[316383.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316383.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316383.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430f1f0] >[316383.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430f1f0] width 1280 pitch 5120 (/4 1280) >[316383.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316383.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316386.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316386.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316387.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316387.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316387.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316387.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316387.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316387.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316394.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316394.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316395.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316395.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316395.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316395.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316395.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316395.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316396.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40df690] >[316396.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40df690] width 1280 pitch 5120 (/4 1280) >[316396.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316396.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316396.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[316396.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[316396.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316396.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316397.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316397.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316398.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316398.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316398.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316398.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316398.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446bfe0] >[316398.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446bfe0] width 1280 pitch 5120 (/4 1280) >[316398.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[316398.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[316400.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316400.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316400.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316400.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316400.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[316400.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[316414.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316414.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316416.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[316416.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[316417.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316417.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316417.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316417.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316417.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316417.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316418.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[316418.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[316419.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316419.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316419.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316419.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316419.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316419.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316419.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316419.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316420.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316420.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316420.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[316420.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[316420.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316420.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316422.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[316422.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[316429.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316429.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316433.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316433.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316433.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[316433.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[316433.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316433.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316433.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316433.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316434.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446bfe0] >[316434.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446bfe0] width 1280 pitch 5120 (/4 1280) >[316434.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44068e0] >[316434.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44068e0] width 1280 pitch 5120 (/4 1280) >[316434.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd3e00] >[316434.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd3e00] width 1280 pitch 5120 (/4 1280) >[316434.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44068e0] >[316434.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44068e0] width 1280 pitch 5120 (/4 1280) >[316434.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316434.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316435.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44068e0] >[316435.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44068e0] width 1280 pitch 5120 (/4 1280) >[316435.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e58e0] >[316435.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e58e0] width 1280 pitch 5120 (/4 1280) >[316435.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44068e0] >[316435.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44068e0] width 1280 pitch 5120 (/4 1280) >[316436.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316436.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316437.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316437.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316437.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316437.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316437.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316437.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316437.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43105a0] >[316437.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43105a0] width 1280 pitch 5120 (/4 1280) >[316440.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[316440.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[316440.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf360] >[316440.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf360] width 1280 pitch 5120 (/4 1280) >[316440.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316440.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316446.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[316446.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[316446.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[316446.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[316446.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[316446.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[316446.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[316446.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[316446.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446d8b0] >[316446.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446d8b0] width 1280 pitch 5120 (/4 1280) >[316446.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[316447.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[316447.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240] >[316447.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1280 pitch 5120 (/4 1280) >[316447.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240] >[316447.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1280 pitch 5120 (/4 1280) >[316447.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316447.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316448.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[316448.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[316448.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[316448.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[316448.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[316448.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[316454.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316454.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316454.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316454.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316456.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316456.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316456.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316456.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316456.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316456.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316465.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316465.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316466.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316466.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316467.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316467.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316467.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316467.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316467.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316467.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316468.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316468.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316468.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316468.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316469.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316469.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316469.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316469.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316487.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316487.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316487.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316487.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316538.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200e70] >[316538.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200e70] width 1280 pitch 5120 (/4 1280) >[316538.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42855c0] >[316538.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42855c0] width 1280 pitch 5120 (/4 1280) >[316585.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428dc20] >[316585.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428dc20] width 1280 pitch 5120 (/4 1280) >[316585.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316585.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316585.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292630] >[316585.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292630] width 1280 pitch 5120 (/4 1280) >[316586.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316586.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316617.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316617.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316617.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316617.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316617.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316617.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316617.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316617.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316618.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316618.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316618.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316618.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316619.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316619.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316619.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316619.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316619.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316619.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316619.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316619.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316653.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316653.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316653.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d665e0] >[316653.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d665e0] width 1280 pitch 5120 (/4 1280) >[316653.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316653.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316653.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316653.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316660.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316660.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316660.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42950b0] >[316660.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42950b0] width 1280 pitch 5120 (/4 1280) >[316660.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2e40] >[316661.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2e40] width 1280 pitch 5120 (/4 1280) >[316672.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42950b0] >[316672.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42950b0] width 1280 pitch 5120 (/4 1280) >[316672.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2e40] >[316672.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2e40] width 1280 pitch 5120 (/4 1280) >[316672.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316672.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316672.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316672.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316674.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316674.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316674.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1200900] >[316674.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1200900] width 1280 pitch 5120 (/4 1280) >[316710.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316710.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316710.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316710.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316710.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316710.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316710.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2e40] >[316710.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2e40] width 1280 pitch 5120 (/4 1280) >[316710.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316710.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316710.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316710.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316710.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316710.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316710.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316711.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316712.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316712.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316712.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292630] >[316712.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292630] width 1280 pitch 5120 (/4 1280) >[316713.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316713.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316715.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[316715.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[316715.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4208190] >[316715.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4208190] width 1280 pitch 5120 (/4 1280) >[316715.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4285180] >[316715.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4285180] width 1280 pitch 5120 (/4 1280) >[316716.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4285180] >[316716.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4285180] width 1280 pitch 5120 (/4 1280) >[316717.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479bd30] >[316717.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479bd30] width 1280 pitch 5120 (/4 1280) >[316717.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316717.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316717.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2e40] >[316717.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2e40] width 1280 pitch 5120 (/4 1280) >[316719.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316719.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316720.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316720.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316720.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[316720.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[316720.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292630] >[316720.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292630] width 1280 pitch 5120 (/4 1280) >[316720.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316720.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316720.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292630] >[316720.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292630] width 1280 pitch 5120 (/4 1280) >[316754.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[316754.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[316755.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316755.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316755.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316755.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316755.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316755.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316755.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316755.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316756.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316756.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316756.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316756.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316756.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302fb0] >[316756.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302fb0] width 1280 pitch 5120 (/4 1280) >[316756.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302fb0] >[316756.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302fb0] width 1280 pitch 5120 (/4 1280) >[316759.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316759.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316760.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316760.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316760.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[316760.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[316760.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[316760.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[316764.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[316764.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[316764.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316764.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316764.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316764.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316764.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316765.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316765.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316765.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316766.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316766.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316766.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479ce70] >[316766.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479ce70] width 1280 pitch 5120 (/4 1280) >[316766.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42841c0] >[316766.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42841c0] width 1280 pitch 5120 (/4 1280) >[316776.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479ce70] >[316776.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479ce70] width 1280 pitch 5120 (/4 1280) >[316776.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316776.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316776.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1890] >[316776.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1890] width 1280 pitch 5120 (/4 1280) >[316776.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316776.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316776.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[316776.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[316777.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[316777.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[316777.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240] >[316777.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1280 pitch 5120 (/4 1280) >[316777.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[316777.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[316788.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316788.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316788.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316788.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316788.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316788.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316788.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479ce70] >[316788.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479ce70] width 1280 pitch 5120 (/4 1280) >[316791.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44079d0] >[316791.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44079d0] width 1280 pitch 5120 (/4 1280) >[316794.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bae20] >[316794.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bae20] width 1280 pitch 5120 (/4 1280) >[316814.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316814.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316814.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[316814.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[316817.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[316817.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[316817.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[316817.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[316817.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ba1c0] >[316817.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ba1c0] width 1280 pitch 5120 (/4 1280) >[316817.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479ce70] >[316817.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479ce70] width 1280 pitch 5120 (/4 1280) >[316844.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316844.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316845.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[316845.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[316849.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316849.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316849.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316849.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316849.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[316849.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[316849.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[316849.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[316878.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316878.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316878.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[316878.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[316878.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[316878.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[316878.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[316878.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[316883.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9870] >[316883.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9870] width 1280 pitch 5120 (/4 1280) >[316883.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[316884.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[316905.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316905.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316905.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[316905.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[316960.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279980] >[316960.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279980] width 1280 pitch 5120 (/4 1280) >[316960.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279980] >[316960.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279980] width 1280 pitch 5120 (/4 1280) >[316968.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279d10] >[316968.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279d10] width 1280 pitch 5120 (/4 1280) >[316968.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42feca0] >[316968.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42feca0] width 1280 pitch 5120 (/4 1280) >[316973.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316973.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316973.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316973.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316973.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c2280] >[316973.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c2280] width 1280 pitch 5120 (/4 1280) >[316973.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316973.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316979.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42feca0] >[316979.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42feca0] width 1280 pitch 5120 (/4 1280) >[316979.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279d10] >[316979.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279d10] width 1280 pitch 5120 (/4 1280) >[316980.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316980.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316980.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316980.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316980.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fdad0] >[316980.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fdad0] width 1280 pitch 5120 (/4 1280) >[316980.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4199b60] >[316980.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4199b60] width 1280 pitch 5120 (/4 1280) >[316980.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4199b60] >[316980.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4199b60] width 1280 pitch 5120 (/4 1280) >[316980.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316980.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[316980.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[316980.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[316980.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[316980.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317014.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42924a0] >[317014.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42924a0] width 1280 pitch 5120 (/4 1280) >[317014.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42924a0] >[317014.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42924a0] width 1280 pitch 5120 (/4 1280) >[317026.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317026.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317026.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317026.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317028.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317028.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317028.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317028.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317028.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[317028.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[317029.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317029.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317029.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[317029.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[317029.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317029.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317029.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317029.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317029.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317029.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317034.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[317035.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[317035.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[317035.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[317035.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317035.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317035.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[317035.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[317035.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[317035.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[317035.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317035.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317036.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317036.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317036.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317036.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317036.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317036.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317036.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317036.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317059.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317059.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317059.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317059.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317059.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317059.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317059.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317059.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317059.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317059.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317061.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317061.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317061.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446aee0] >[317061.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446aee0] width 1280 pitch 5120 (/4 1280) >[317061.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317061.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317095.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446aee0] >[317095.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446aee0] width 1280 pitch 5120 (/4 1280) >[317096.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279d10] >[317096.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279d10] width 1280 pitch 5120 (/4 1280) >[317096.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317096.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317096.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317096.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317096.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dfdd0] >[317096.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dfdd0] width 1280 pitch 5120 (/4 1280) >[317096.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446aee0] >[317096.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446aee0] width 1280 pitch 5120 (/4 1280) >[317096.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446aee0] >[317096.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446aee0] width 1280 pitch 5120 (/4 1280) >[317096.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dfdd0] >[317096.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dfdd0] width 1280 pitch 5120 (/4 1280) >[317097.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317097.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317097.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dfdd0] >[317097.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dfdd0] width 1280 pitch 5120 (/4 1280) >[317104.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[317104.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[317104.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[317104.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[317105.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317105.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317105.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[317105.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[317109.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317109.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317109.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317109.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317109.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317109.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317109.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317109.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317109.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317109.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317109.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317109.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317109.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317109.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317109.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317109.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317109.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317109.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317109.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317109.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317110.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317110.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317110.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317110.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317110.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4292cd0] >[317110.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4292cd0] width 1280 pitch 5120 (/4 1280) >[317110.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[317110.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[317110.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c41f0] >[317110.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c41f0] width 1280 pitch 5120 (/4 1280) >[317110.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317110.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317111.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[317111.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[317111.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[317111.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[317111.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[317111.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[317111.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[317111.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[317111.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317111.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317111.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317111.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317111.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446d8b0] >[317111.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446d8b0] width 1280 pitch 5120 (/4 1280) >[317111.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317111.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317111.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446d8b0] >[317111.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446d8b0] width 1280 pitch 5120 (/4 1280) >[317111.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317111.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317111.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446d8b0] >[317111.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446d8b0] width 1280 pitch 5120 (/4 1280) >[317111.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317111.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317111.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446d8b0] >[317111.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446d8b0] width 1280 pitch 5120 (/4 1280) >[317111.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317111.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317111.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317111.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317111.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317111.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317111.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317111.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317111.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[317111.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[317111.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317111.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317111.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[317111.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[317152.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[317152.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[317152.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[317152.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[317156.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c73b0] >[317156.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c73b0] width 1280 pitch 5120 (/4 1280) >[317156.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c73b0] >[317156.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c73b0] width 1280 pitch 5120 (/4 1280) >[317160.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[317160.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[317160.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317160.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317164.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[317164.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[317164.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42795d0] >[317164.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42795d0] width 1280 pitch 5120 (/4 1280) >[317165.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317165.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317165.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c73b0] >[317165.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c73b0] width 1280 pitch 5120 (/4 1280) >[317167.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[317167.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[317167.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317167.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317168.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317168.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317168.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317168.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317176.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317176.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317176.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[317176.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[317176.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[317176.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[317176.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a69f50] >[317176.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a69f50] width 1280 pitch 5120 (/4 1280) >[317178.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317178.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317178.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317178.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317178.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[317178.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[317183.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317183.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317183.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317183.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317191.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406dc0] >[317191.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406dc0] width 1280 pitch 5120 (/4 1280) >[317200.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429b3d0] >[317200.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429b3d0] width 1280 pitch 5120 (/4 1280) >[317202.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f880] >[317202.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f880] width 1280 pitch 5120 (/4 1280) >[317202.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429b220] >[317202.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429b220] width 1280 pitch 5120 (/4 1280) >[317203.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317203.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317203.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317203.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317203.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440faf0] >[317203.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440faf0] width 1280 pitch 5120 (/4 1280) >[317203.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317203.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317204.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440faf0] >[317204.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440faf0] width 1280 pitch 5120 (/4 1280) >[317204.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317204.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317204.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb50] >[317204.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb50] width 1280 pitch 5120 (/4 1280) >[317204.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317204.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317205.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429b400] >[317205.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429b400] width 1280 pitch 5120 (/4 1280) >[317205.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ef90] >[317205.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ef90] width 1280 pitch 5120 (/4 1280) >[317205.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440e660] >[317205.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440e660] width 1280 pitch 5120 (/4 1280) >[317205.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407f40] >[317206.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407f40] width 1280 pitch 5120 (/4 1280) >[317207.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c2f40] >[317207.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c2f40] width 1280 pitch 5120 (/4 1280) >[317208.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fc00] >[317208.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fc00] width 1280 pitch 5120 (/4 1280) >[317208.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5220] >[317208.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5220] width 1280 pitch 5120 (/4 1280) >[317208.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5220] >[317208.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5220] width 1280 pitch 5120 (/4 1280) >[317209.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fbc0] >[317209.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fbc0] width 1280 pitch 5120 (/4 1280) >[317211.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36060] >[317211.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36060] width 1280 pitch 5120 (/4 1280) >[317211.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fcde0] >[317211.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fcde0] width 1280 pitch 5120 (/4 1280) >[317211.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd5a60] >[317211.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd5a60] width 1280 pitch 5120 (/4 1280) >[317211.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd5a60] >[317211.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd5a60] width 1280 pitch 5120 (/4 1280) >[317212.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407cc0] >[317212.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407cc0] width 1280 pitch 5120 (/4 1280) >[317212.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407d50] >[317212.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407d50] width 1280 pitch 5120 (/4 1280) >[317212.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317212.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317226.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a0cb0] >[317226.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a0cb0] width 1280 pitch 5120 (/4 1280) >[317226.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c620] >[317226.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c620] width 1280 pitch 5120 (/4 1280) >[317227.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[317227.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[317227.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317227.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317227.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317227.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317227.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dfd90] >[317227.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dfd90] width 1280 pitch 5120 (/4 1280) >[317232.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317232.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317232.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317232.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317232.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317232.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317232.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317232.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317232.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317232.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317232.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317232.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317232.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f730] >[317232.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f730] width 1280 pitch 5120 (/4 1280) >[317232.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317232.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317234.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317234.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317234.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317234.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317234.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317239.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317239.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317239.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317239.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317239.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c30650] >[317240.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c30650] width 1280 pitch 5120 (/4 1280) >[317240.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317240.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317240.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4207560] >[317240.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4207560] width 1280 pitch 5120 (/4 1280) >[317240.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317240.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317240.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[317240.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[317240.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317240.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317242.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eaba20] >[317242.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eaba20] width 1280 pitch 5120 (/4 1280) >[317242.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400340] >[317242.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400340] width 1280 pitch 5120 (/4 1280) >[317242.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b0cc00] >[317242.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b0cc00] width 1280 pitch 5120 (/4 1280) >[317243.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400340] >[317243.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400340] width 1280 pitch 5120 (/4 1280) >[317243.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317243.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317243.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317243.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317244.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317244.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317244.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317244.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317245.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[317245.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[317246.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[317246.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[317246.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317246.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317246.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317246.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317255.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[317255.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[317255.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317255.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317255.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317255.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317255.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317255.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317256.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317256.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317256.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317256.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317256.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[317256.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[317256.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317256.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317278.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317278.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317278.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317278.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317278.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317278.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317278.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317278.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317278.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317278.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317279.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317279.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317279.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317279.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317279.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317279.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317287.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43095d0] >[317287.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43095d0] width 1280 pitch 5120 (/4 1280) >[317287.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317287.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317287.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317287.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317288.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317288.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317288.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fb240] >[317288.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fb240] width 1280 pitch 5120 (/4 1280) >[317288.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fcde0] >[317288.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fcde0] width 1280 pitch 5120 (/4 1280) >[317291.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317291.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317291.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317291.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317291.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317291.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317291.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317291.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317292.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317292.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317292.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317292.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317292.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317292.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317292.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[317292.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[317303.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317303.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317303.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317303.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317304.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317304.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317304.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[317304.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[317304.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c73b0] >[317304.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c73b0] width 1280 pitch 5120 (/4 1280) >[317304.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317304.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317316.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[317316.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[317317.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e40] >[317317.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e40] width 1280 pitch 5120 (/4 1280) >[317318.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[317318.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[317319.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c73b0] >[317319.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c73b0] width 1280 pitch 5120 (/4 1280) >[317338.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317338.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317338.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42008e0] >[317338.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42008e0] width 1280 pitch 5120 (/4 1280) >[317338.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317338.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317346.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[317346.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[317346.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[317346.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[317346.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[317346.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[317346.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317346.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317346.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317346.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317346.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317346.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317347.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317347.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317347.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317347.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317347.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317347.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317347.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317347.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317347.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317347.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317348.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317348.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317348.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317348.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317348.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317348.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317348.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317348.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317349.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317349.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317349.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317349.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317349.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317349.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317350.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313e140] >[317350.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313e140] width 1280 pitch 5120 (/4 1280) >[317351.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317351.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317351.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317351.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317353.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317353.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317353.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d5c0] >[317353.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d5c0] width 1280 pitch 5120 (/4 1280) >[317353.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x442eef0] >[317353.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x442eef0] width 1280 pitch 5120 (/4 1280) >[317354.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d5c0] >[317354.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d5c0] width 1280 pitch 5120 (/4 1280) >[317355.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317355.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317355.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313e140] >[317355.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313e140] width 1280 pitch 5120 (/4 1280) >[317355.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317355.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317382.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313e140] >[317382.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313e140] width 1280 pitch 5120 (/4 1280) >[317382.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317382.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317383.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279090] >[317383.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279090] width 1280 pitch 5120 (/4 1280) >[317383.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317383.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317383.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317383.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317383.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[317383.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[317384.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317384.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317385.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317385.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317385.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317385.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317385.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317385.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317385.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317385.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317385.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317385.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317386.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313e140] >[317386.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313e140] width 1280 pitch 5120 (/4 1280) >[317386.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317386.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317386.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317386.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317386.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403b310] >[317386.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403b310] width 1280 pitch 5120 (/4 1280) >[317391.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317391.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317391.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408b250] >[317391.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408b250] width 1280 pitch 5120 (/4 1280) >[317391.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e3e30] >[317391.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e3e30] width 1280 pitch 5120 (/4 1280) >[317391.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408b250] >[317391.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408b250] width 1280 pitch 5120 (/4 1280) >[317392.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1710] >[317392.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1710] width 1280 pitch 5120 (/4 1280) >[317392.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317392.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317392.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317392.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317393.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317393.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317397.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317397.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317401.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27aba40] >[317401.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27aba40] width 1280 pitch 5120 (/4 1280) >[317401.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a6c030] >[317401.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a6c030] width 1280 pitch 5120 (/4 1280) >[317401.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c2ea0] >[317401.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c2ea0] width 1280 pitch 5120 (/4 1280) >[317402.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42954b0] >[317402.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42954b0] width 1280 pitch 5120 (/4 1280) >[317402.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403b310] >[317402.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403b310] width 1280 pitch 5120 (/4 1280) >[317402.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42954b0] >[317402.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42954b0] width 1280 pitch 5120 (/4 1280) >[317407.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317407.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317407.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317407.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317407.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d090] >[317407.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d090] width 1280 pitch 5120 (/4 1280) >[317407.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317407.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317407.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206e20] >[317407.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206e20] width 1280 pitch 5120 (/4 1280) >[317408.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400340] >[317408.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400340] width 1280 pitch 5120 (/4 1280) >[317408.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317408.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317408.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317408.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317410.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317410.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317410.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446c6a0] >[317410.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446c6a0] width 1280 pitch 5120 (/4 1280) >[317410.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41998b0] >[317410.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41998b0] width 1280 pitch 5120 (/4 1280) >[317410.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317410.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317410.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317410.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317411.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317411.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317411.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4472380] >[317411.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4472380] width 1280 pitch 5120 (/4 1280) >[317411.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe9ab0] >[317411.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe9ab0] width 1280 pitch 5120 (/4 1280) >[317411.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317411.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317411.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408b250] >[317411.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408b250] width 1280 pitch 5120 (/4 1280) >[317411.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408b250] >[317411.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408b250] width 1280 pitch 5120 (/4 1280) >[317412.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317412.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317412.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317412.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317412.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317412.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317412.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2441cd0] >[317412.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2441cd0] width 1280 pitch 5120 (/4 1280) >[317412.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317412.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317413.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317413.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317413.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317413.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317413.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317413.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317413.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317413.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317419.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317419.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317419.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317419.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317419.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317419.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317419.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317419.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317420.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317420.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317420.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317420.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317420.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4310690] >[317420.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4310690] width 1280 pitch 5120 (/4 1280) >[317420.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42074f0] >[317420.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42074f0] width 1280 pitch 5120 (/4 1280) >[317421.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fb200] >[317421.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fb200] width 1280 pitch 5120 (/4 1280) >[317421.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317421.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317422.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317422.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317423.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317423.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317423.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317423.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317423.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317423.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317423.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317423.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317424.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317424.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317425.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317425.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317425.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317425.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317425.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317425.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317425.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317425.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317438.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fade10] >[317438.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fade10] width 1280 pitch 5120 (/4 1280) >[317438.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317438.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317438.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317438.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317438.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a26eb0] >[317438.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a26eb0] width 1280 pitch 5120 (/4 1280) >[317438.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317438.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317438.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317438.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317438.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d390] >[317438.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d390] width 1280 pitch 5120 (/4 1280) >[317439.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317439.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317439.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317439.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317439.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317439.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317439.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401da30] >[317440.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401da30] width 1280 pitch 5120 (/4 1280) >[317440.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317440.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317442.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42adf80] >[317442.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42adf80] width 1280 pitch 5120 (/4 1280) >[317442.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317442.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317442.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317442.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317442.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d390] >[317442.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d390] width 1280 pitch 5120 (/4 1280) >[317443.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42adf80] >[317443.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42adf80] width 1280 pitch 5120 (/4 1280) >[317443.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317443.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317443.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317443.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317443.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317443.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317444.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317444.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317444.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277f90] >[317444.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277f90] width 1280 pitch 5120 (/4 1280) >[317444.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317444.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317444.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[317444.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[317460.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317460.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317460.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446aa80] >[317460.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446aa80] width 1280 pitch 5120 (/4 1280) >[317460.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42074f0] >[317460.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42074f0] width 1280 pitch 5120 (/4 1280) >[317460.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405db00] >[317460.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405db00] width 1280 pitch 5120 (/4 1280) >[317460.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317460.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317460.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317460.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317460.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317460.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317461.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d390] >[317461.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d390] width 1280 pitch 5120 (/4 1280) >[317462.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317462.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317462.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44180a0] >[317462.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44180a0] width 1280 pitch 5120 (/4 1280) >[317462.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317462.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317463.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f1f20] >[317463.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f1f20] width 1280 pitch 5120 (/4 1280) >[317463.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f1f20] >[317463.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f1f20] width 1280 pitch 5120 (/4 1280) >[317463.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4201150] >[317463.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4201150] width 1280 pitch 5120 (/4 1280) >[317463.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42027b0] >[317463.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42027b0] width 1280 pitch 5120 (/4 1280) >[317464.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac5f0] >[317464.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac5f0] width 1280 pitch 5120 (/4 1280) >[317465.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd0630] >[317465.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd0630] width 1280 pitch 5120 (/4 1280) >[317465.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440d390] >[317465.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440d390] width 1280 pitch 5120 (/4 1280) >[317465.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317465.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317465.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317465.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317466.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2ba0] >[317466.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2ba0] width 1280 pitch 5120 (/4 1280) >[317466.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317466.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317466.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f2ba0] >[317466.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f2ba0] width 1280 pitch 5120 (/4 1280) >[317475.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317475.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317476.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317476.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317476.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bbff0] >[317476.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bbff0] width 1280 pitch 5120 (/4 1280) >[317476.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317476.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317477.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317477.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317477.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317477.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317477.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317477.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317477.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053720] >[317477.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053720] width 1280 pitch 5120 (/4 1280) >[317481.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317481.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317482.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317482.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317482.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1af0] >[317482.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1af0] width 1280 pitch 5120 (/4 1280) >[317482.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fade10] >[317482.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fade10] width 1280 pitch 5120 (/4 1280) >[317498.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[317498.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[317498.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fade10] >[317498.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fade10] width 1280 pitch 5120 (/4 1280) >[317498.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bbff0] >[317498.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bbff0] width 1280 pitch 5120 (/4 1280) >[317498.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28c7650] >[317498.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28c7650] width 1280 pitch 5120 (/4 1280) >[317543.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317543.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317543.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bbff0] >[317543.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bbff0] width 1280 pitch 5120 (/4 1280) >[317547.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bbff0] >[317547.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bbff0] width 1280 pitch 5120 (/4 1280) >[317547.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317547.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317547.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317547.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317547.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317547.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317547.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317547.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317547.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317547.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317548.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317548.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317548.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317548.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317548.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317548.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317548.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317548.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317548.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317548.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317548.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317548.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317548.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317548.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317548.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bbff0] >[317548.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bbff0] width 1280 pitch 5120 (/4 1280) >[317550.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317550.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317550.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317550.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317550.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317551.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317551.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317551.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317551.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317551.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317551.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317551.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317552.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317552.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317552.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317552.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317552.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317552.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317552.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4091e00] >[317552.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4091e00] width 1280 pitch 5120 (/4 1280) >[317552.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317552.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317552.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fb200] >[317552.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fb200] width 1280 pitch 5120 (/4 1280) >[317564.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317564.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317564.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317565.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317565.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317565.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317566.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40867b0] >[317566.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40867b0] width 1280 pitch 5120 (/4 1280) >[317566.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82770] >[317566.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82770] width 1280 pitch 5120 (/4 1280) >[317566.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317566.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317568.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317568.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317569.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317569.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317569.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317569.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317569.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[317569.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[317582.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317582.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317582.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317582.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317582.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317582.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317582.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317582.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317582.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4271090] >[317582.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4271090] width 1280 pitch 5120 (/4 1280) >[317584.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317584.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317585.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317585.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317585.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bc5a0] >[317585.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bc5a0] width 1280 pitch 5120 (/4 1280) >[317585.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317585.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317585.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317585.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317586.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[317586.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[317586.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40867b0] >[317586.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40867b0] width 1280 pitch 5120 (/4 1280) >[317586.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317586.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317607.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bc5a0] >[317607.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bc5a0] width 1280 pitch 5120 (/4 1280) >[317607.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317607.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317607.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317608.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317608.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d7a0] >[317608.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d7a0] width 1280 pitch 5120 (/4 1280) >[317610.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317610.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317610.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317610.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317610.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317610.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317610.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317610.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317611.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317612.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317612.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82770] >[317612.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82770] width 1280 pitch 5120 (/4 1280) >[317612.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317612.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317612.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82770] >[317612.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82770] width 1280 pitch 5120 (/4 1280) >[317612.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317613.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317613.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317613.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317613.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317613.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317613.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317613.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317614.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317614.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317614.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317614.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317615.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317615.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317615.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317615.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317618.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317618.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317618.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317618.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317618.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317618.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317618.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317618.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317618.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317618.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317618.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317618.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317619.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317619.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317619.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317619.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317619.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317619.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317619.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317619.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317620.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317620.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317620.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317620.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317620.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317620.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317620.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bc5a0] >[317620.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bc5a0] width 1280 pitch 5120 (/4 1280) >[317620.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4217920] >[317620.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4217920] width 1280 pitch 5120 (/4 1280) >[317620.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317620.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317621.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317621.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317621.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317621.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317621.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317621.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317621.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317621.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317621.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317621.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317622.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317622.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317622.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317622.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317622.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317622.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317622.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317622.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317622.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317622.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317623.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317623.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317623.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317623.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317623.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317623.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317625.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317625.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317628.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317628.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317629.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317629.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317629.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317629.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317629.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317629.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317629.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317629.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317629.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317629.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317629.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674cd0] >[317629.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674cd0] width 1280 pitch 5120 (/4 1280) >[317629.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317629.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317630.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317630.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317630.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317630.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317630.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317630.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317631.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317631.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317631.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317631.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317631.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b6e80] >[317631.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b6e80] width 1280 pitch 5120 (/4 1280) >[317631.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317631.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317631.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317631.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317631.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317631.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317631.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317631.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317631.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317632.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317632.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317632.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317634.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317634.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317635.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317635.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317636.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317636.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317636.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440f560] >[317636.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440f560] width 1280 pitch 5120 (/4 1280) >[317636.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317636.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317666.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317666.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317667.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317667.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317667.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317667.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317667.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317667.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317667.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40867b0] >[317667.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40867b0] width 1280 pitch 5120 (/4 1280) >[317668.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317668.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317668.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317668.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317668.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317668.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317676.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317676.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317676.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317676.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317676.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317676.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317676.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317676.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317677.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317677.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317677.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317677.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317677.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317677.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317677.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40867b0] >[317677.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40867b0] width 1280 pitch 5120 (/4 1280) >[317683.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317683.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317683.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317684.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317684.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317684.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317684.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317684.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317684.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317684.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317684.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317684.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317684.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317684.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317684.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317684.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317691.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317691.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317691.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317691.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317691.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317691.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317692.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317692.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317692.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317692.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317692.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317692.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317692.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317692.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317692.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317692.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317692.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317692.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317693.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317693.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317693.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317693.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317693.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40867b0] >[317693.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40867b0] width 1280 pitch 5120 (/4 1280) >[317698.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bc5a0] >[317698.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bc5a0] width 1280 pitch 5120 (/4 1280) >[317698.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317698.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317698.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317698.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317698.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317698.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317761.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317761.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317761.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317761.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317762.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317762.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317762.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317762.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317762.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317762.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317762.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317762.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317762.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317762.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317763.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317763.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317763.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317763.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317763.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317763.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317763.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317763.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317763.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317763.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317763.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317763.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317764.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317764.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317764.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317764.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317764.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317764.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317764.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317764.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317764.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317764.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317764.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317764.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317764.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317764.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317764.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317764.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317764.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317764.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317764.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317764.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317764.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317764.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317764.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317764.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317764.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317764.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317764.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317764.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317765.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317765.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317765.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317765.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317765.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317765.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317765.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317766.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317766.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317766.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317766.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317766.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317766.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317766.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317766.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317766.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317766.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317766.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317766.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317766.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317768.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317768.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317768.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317768.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317768.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317768.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317769.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317769.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317769.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317769.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317769.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317770.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317770.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317770.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317770.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317770.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317770.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317770.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317770.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317770.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317770.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317770.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317770.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317770.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317770.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317770.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317784.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317784.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317785.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317785.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317785.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317785.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317785.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[317785.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[317787.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317787.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317788.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401a930] >[317788.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401a930] width 1280 pitch 5120 (/4 1280) >[317788.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317788.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317788.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317788.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317788.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317788.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317790.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317790.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317791.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317791.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317792.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317792.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317793.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317793.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317793.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317793.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317793.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317793.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317796.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317796.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317796.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317796.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317796.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317796.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317806.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317806.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317807.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317807.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317807.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317807.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317807.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317807.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317807.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317807.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317807.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x430af00] >[317807.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x430af00] width 1280 pitch 5120 (/4 1280) >[317808.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317808.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317808.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317808.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317809.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317809.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317809.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[317809.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[317814.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317814.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317814.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317814.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317814.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317814.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317815.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317815.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317816.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317816.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317816.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317816.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317816.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206dc0] >[317816.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206dc0] width 1280 pitch 5120 (/4 1280) >[317816.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317816.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317831.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317831.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317831.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317831.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317831.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317831.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317831.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317831.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317847.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206dc0] >[317847.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206dc0] width 1280 pitch 5120 (/4 1280) >[317847.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317847.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317847.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317847.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317847.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317847.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317858.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd8f0] >[317858.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd8f0] width 1280 pitch 5120 (/4 1280) >[317858.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317858.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317858.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317858.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317858.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317858.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317862.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[317862.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[317862.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317862.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317864.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317864.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317864.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317864.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317870.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317870.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317870.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3520] >[317870.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3520] width 1280 pitch 5120 (/4 1280) >[317870.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317870.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317873.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317873.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317873.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206dc0] >[317873.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206dc0] width 1280 pitch 5120 (/4 1280) >[317873.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d1d10] >[317873.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d1d10] width 1280 pitch 5120 (/4 1280) >[317873.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317873.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317898.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317898.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317898.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317898.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317898.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317898.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317898.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317898.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317915.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[317915.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[317915.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c3360] >[317915.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c3360] width 1280 pitch 5120 (/4 1280) >[317915.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11f5670] >[317915.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11f5670] width 1280 pitch 5120 (/4 1280) >[317915.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[317915.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[317936.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317936.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317937.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[317937.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[317937.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3520] >[317937.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3520] width 1280 pitch 5120 (/4 1280) >[317937.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317937.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317937.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3520] >[317937.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3520] width 1280 pitch 5120 (/4 1280) >[317937.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317937.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317937.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3520] >[317937.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3520] width 1280 pitch 5120 (/4 1280) >[317937.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317937.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317938.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3520] >[317938.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3520] width 1280 pitch 5120 (/4 1280) >[317938.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317938.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317938.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9f50] >[317938.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9f50] width 1280 pitch 5120 (/4 1280) >[317938.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[317938.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[317938.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317938.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317946.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[317946.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[317946.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[317946.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[317946.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317946.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317946.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317946.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317946.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317946.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317946.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317946.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317946.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317946.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317947.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317947.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317947.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317947.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317948.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317948.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317948.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317948.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317948.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317948.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317948.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317948.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317948.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317948.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317949.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317949.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317949.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317949.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317950.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[317950.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[317950.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[317950.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[317950.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[317950.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[317950.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[317951.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[317951.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[317951.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[317951.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317951.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317951.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317951.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317951.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317951.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317951.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317951.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317951.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317951.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317951.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317951.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317952.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317952.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317952.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317952.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317952.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317952.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317952.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317952.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317952.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317952.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317952.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317952.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[317952.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[317952.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[317953.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[317953.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[318011.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414b570] >[318011.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414b570] width 1280 pitch 5120 (/4 1280) >[318012.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[318012.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[318012.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa43a0] >[318012.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa43a0] width 1280 pitch 5120 (/4 1280) >[318012.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302130] >[318012.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302130] width 1280 pitch 5120 (/4 1280) >[318112.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43fee70] >[318112.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43fee70] width 1280 pitch 5120 (/4 1280) >[318112.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4311e10] >[318113.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4311e10] width 1280 pitch 5120 (/4 1280) >[318114.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4311e10] >[318114.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4311e10] width 1280 pitch 5120 (/4 1280) >[318114.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4308ea0] >[318114.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4308ea0] width 1280 pitch 5120 (/4 1280) >[318114.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43fee70] >[318114.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43fee70] width 1280 pitch 5120 (/4 1280) >[318136.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4088a30] >[318136.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4088a30] width 1280 pitch 5120 (/4 1280) >[318137.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c050] >[318137.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c050] width 1280 pitch 5120 (/4 1280) >[318137.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4088a30] >[318137.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4088a30] width 1280 pitch 5120 (/4 1280) >[318137.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c050] >[318137.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c050] width 1280 pitch 5120 (/4 1280) >[318137.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4088a30] >[318137.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4088a30] width 1280 pitch 5120 (/4 1280) >[318138.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[318138.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[318138.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318138.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318138.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318138.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318138.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318138.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318138.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318138.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318138.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318138.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318182.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[318182.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[318182.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4081d30] >[318182.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4081d30] width 1280 pitch 5120 (/4 1280) >[318182.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318182.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318182.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318182.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318183.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[318183.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[318184.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4081d30] >[318184.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4081d30] width 1280 pitch 5120 (/4 1280) >[318184.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[318184.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[318184.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43fee70] >[318184.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43fee70] width 1280 pitch 5120 (/4 1280) >[318184.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318184.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318184.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43fee70] >[318184.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43fee70] width 1280 pitch 5120 (/4 1280) >[318232.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318232.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318233.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318233.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318233.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318233.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318233.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318233.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318234.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318234.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318234.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318234.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318234.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318234.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318234.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42718e0] >[318234.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42718e0] width 1280 pitch 5120 (/4 1280) >[318237.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318237.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318237.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318237.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318237.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318237.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318237.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318237.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318237.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318237.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318238.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318238.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318238.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318238.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318239.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318239.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318239.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318239.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318239.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318239.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318239.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318239.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318239.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318239.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318239.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318239.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318239.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487350] >[318239.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487350] width 1280 pitch 5120 (/4 1280) >[318240.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318240.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318240.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318240.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318240.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318240.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318240.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318240.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318240.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318240.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318240.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318240.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318240.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318240.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318241.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318241.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318242.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318242.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318243.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318243.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318243.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318243.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318243.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318243.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318243.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318243.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318243.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318243.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318243.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318243.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318249.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487350] >[318249.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487350] width 1280 pitch 5120 (/4 1280) >[318249.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318249.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318249.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487350] >[318249.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487350] width 1280 pitch 5120 (/4 1280) >[318249.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318249.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318284.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403b2b0] >[318284.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403b2b0] width 1280 pitch 5120 (/4 1280) >[318284.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487350] >[318284.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487350] width 1280 pitch 5120 (/4 1280) >[318284.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318284.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318284.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[318284.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[318285.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318285.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318286.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318286.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318286.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d260] >[318286.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d260] width 1280 pitch 5120 (/4 1280) >[318286.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318286.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318290.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318290.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318291.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318291.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318291.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318291.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318291.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318291.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318470.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318470.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318470.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318470.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318470.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318470.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318470.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318470.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318470.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318470.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318470.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318470.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318471.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318471.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318471.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318471.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318471.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318471.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318471.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318471.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318471.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318471.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318471.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318471.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318471.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318471.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318486.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318486.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318487.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318487.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318487.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[318487.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[318487.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1487350] >[318487.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1487350] width 1280 pitch 5120 (/4 1280) >[318488.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[318488.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[318488.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318488.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318488.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318488.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318488.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318488.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318489.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318489.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318489.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318489.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318489.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318490.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318490.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318490.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318490.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318490.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318490.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318490.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318490.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318490.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318490.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318490.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318490.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318490.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318490.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318490.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318490.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318490.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318490.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318490.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318490.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318490.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318490.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[318490.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[318490.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318490.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318490.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318490.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318490.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318490.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318490.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318490.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318490.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318490.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318490.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318491.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318491.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318491.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318491.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318491.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318491.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318491.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318491.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318491.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318497.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x442b5b0] >[318497.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x442b5b0] width 1280 pitch 5120 (/4 1280) >[318498.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318498.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318520.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318520.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318521.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318521.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318521.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318521.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318521.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318521.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318522.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318522.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318522.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42718e0] >[318522.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42718e0] width 1280 pitch 5120 (/4 1280) >[318522.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318522.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318522.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318522.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318569.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f6ea0] >[318569.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f6ea0] width 1280 pitch 5120 (/4 1280) >[318577.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318577.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318578.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318578.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318578.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318578.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318578.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318578.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318595.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318595.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318595.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318595.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318603.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318603.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318603.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318603.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318603.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318603.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318603.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318603.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318603.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318603.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318603.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318603.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318603.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318603.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318604.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318604.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318604.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318604.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318604.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318604.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318604.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318604.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318604.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318604.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318604.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318604.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318604.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318604.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318604.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318605.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318605.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318606.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318606.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318606.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318606.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318606.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318606.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318610.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318610.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318611.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318611.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318611.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318611.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318611.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318612.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318612.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[318612.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[318614.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318614.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318617.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318617.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318617.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[318617.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[318617.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318617.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318637.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318637.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318637.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318637.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318637.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318637.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318637.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318637.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318656.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318656.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318657.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318657.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318658.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318658.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318659.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318659.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318659.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1297640] >[318659.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1297640] width 1280 pitch 5120 (/4 1280) >[318660.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a5f10] >[318660.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a5f10] width 1280 pitch 5120 (/4 1280) >[318672.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318672.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318681.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ab40] >[318681.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ab40] width 1280 pitch 5120 (/4 1280) >[318682.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a37f0] >[318682.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a37f0] width 1280 pitch 5120 (/4 1280) >[318683.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42aa450] >[318683.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42aa450] width 1280 pitch 5120 (/4 1280) >[318684.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318684.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318684.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318684.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318684.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318684.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318684.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318684.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318684.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318684.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318684.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318684.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318684.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318684.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318684.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318684.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318684.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318684.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318684.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318684.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318684.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318684.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318684.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318684.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318684.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318684.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318684.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318684.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318684.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318684.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318684.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318684.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318685.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318685.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318685.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318685.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318685.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318752.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318752.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318753.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318753.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318753.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318753.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318753.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318753.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318753.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318753.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318753.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318753.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318754.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318754.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318754.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318754.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318754.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[318754.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[318754.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318754.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318754.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318754.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318755.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318755.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318755.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318755.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318755.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318755.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318757.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318757.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318757.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318757.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318757.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318757.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318757.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[318757.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[318758.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318758.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318758.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318758.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318758.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318758.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318758.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318758.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318758.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318758.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318758.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318758.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318759.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318759.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318759.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318759.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318759.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318759.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318760.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318760.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318760.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318760.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318760.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318760.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318804.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318804.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318804.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318804.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318804.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318804.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318804.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318804.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318806.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318806.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318806.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318806.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318806.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318806.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318825.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318825.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318825.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318825.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318825.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318825.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318825.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318825.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318828.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318828.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318828.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318828.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318828.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[318828.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[318828.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[318828.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[318851.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318851.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318851.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318851.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318851.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318851.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318851.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318851.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318851.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[318851.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[318852.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318852.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318852.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318852.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318853.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318853.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318853.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318853.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318853.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318853.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318854.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44e3a30] >[318854.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44e3a30] width 1280 pitch 5120 (/4 1280) >[318854.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318854.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318854.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318855.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318855.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318855.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318855.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318855.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318856.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318856.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318856.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318856.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318896.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318896.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318896.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318896.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318897.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3f40] >[318897.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3f40] width 1280 pitch 5120 (/4 1280) >[318897.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[318897.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[318897.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[318897.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[318898.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[318898.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[318898.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318898.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318898.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318898.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318898.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318898.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318898.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318898.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318898.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318898.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318899.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318899.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318899.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318899.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318899.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318899.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318899.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[318899.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[318901.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318901.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318901.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318901.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318901.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318901.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318901.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318901.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318901.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fdc70] >[318901.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fdc70] width 1280 pitch 5120 (/4 1280) >[318901.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[318901.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[318901.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318901.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318901.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318901.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318901.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318901.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318901.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318901.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318901.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318901.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318901.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318901.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318901.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318902.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[318902.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[318902.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318902.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318902.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318902.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318902.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318902.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318902.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318902.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318902.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318902.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[318902.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[318902.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318902.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318903.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[318903.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[318903.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[318903.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[318903.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318903.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318903.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318903.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318903.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318903.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318903.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318903.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318903.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318903.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318903.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318903.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318903.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318903.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318903.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[318903.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[318905.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318905.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318906.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318906.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318907.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[318907.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[318907.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[318907.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[318922.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[318922.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[318922.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318922.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318933.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318933.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318935.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fbd30] >[318935.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fbd30] width 1280 pitch 5120 (/4 1280) >[318935.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[318935.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[318935.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318935.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318935.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[318935.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[318935.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318935.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318938.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318938.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318939.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fbd30] >[318939.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fbd30] width 1280 pitch 5120 (/4 1280) >[318939.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[318939.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[318939.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[318940.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[318940.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[318940.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[318942.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[318942.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[318942.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[318942.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[318942.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318942.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[318942.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[318942.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[318943.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[318943.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[318943.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[318943.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[318943.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[318943.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[318989.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[318989.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[318989.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[318989.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[318989.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[318989.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[318989.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440c000] >[318989.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440c000] width 1280 pitch 5120 (/4 1280) >[318990.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[318990.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[318990.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[318990.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[318991.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[318991.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[318991.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[318991.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319069.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[319069.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[319071.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319071.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319071.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319071.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319071.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319071.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319073.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319073.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319074.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319074.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319074.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319074.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319074.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319074.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319076.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319076.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319077.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319077.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319078.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319078.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319078.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319078.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319078.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319078.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319078.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319078.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319153.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[319153.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[319155.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[319155.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[319156.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319156.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319156.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319156.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319156.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319156.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319166.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319166.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319166.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[319166.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[319166.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319166.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319166.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319166.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319203.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319203.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319204.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[319204.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[319205.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319205.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319205.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319205.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319205.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[319205.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[319205.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319205.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319225.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319225.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319226.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319226.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319226.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319226.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319226.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319226.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319231.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319231.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319232.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319232.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319232.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319232.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319232.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319232.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319232.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319232.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319247.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319247.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319247.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319247.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319293.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319293.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319293.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319293.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319293.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[319293.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[319293.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319294.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319294.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407710] >[319294.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407710] width 1280 pitch 5120 (/4 1280) >[319307.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[319307.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[319308.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319308.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319308.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319308.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319308.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319308.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319309.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319309.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319309.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[319309.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[319310.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319310.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319310.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c7bd0] >[319310.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c7bd0] width 1280 pitch 5120 (/4 1280) >[319358.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097440] >[319358.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097440] width 1280 pitch 5120 (/4 1280) >[319360.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319360.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319360.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319360.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319360.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319360.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319360.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319360.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319360.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319360.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319360.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319360.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319360.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319360.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319360.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319360.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319360.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319360.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319360.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319360.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319360.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319360.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319360.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319360.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319360.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319360.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319360.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319360.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319360.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319360.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319361.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319361.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac800] >[319361.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac800] width 1280 pitch 5120 (/4 1280) >[319361.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319361.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319370.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319370.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319371.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319371.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319371.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319371.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319371.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319371.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319372.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[319372.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[319372.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319373.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319373.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319373.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319373.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319373.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319373.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319373.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319374.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319374.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319376.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319376.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319376.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319376.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319376.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[319376.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[319437.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319437.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319437.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319438.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319438.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[319438.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[319438.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[319438.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[319477.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319477.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319477.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319477.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319478.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319478.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319478.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319478.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319478.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319478.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319479.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319479.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319485.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319485.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319485.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319485.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319485.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319485.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319485.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319485.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319486.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319486.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319486.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319486.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319486.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[319486.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[319486.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319486.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319487.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319487.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319488.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319488.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319488.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319488.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319488.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319488.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319541.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319541.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319541.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42357b0] >[319541.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42357b0] width 1280 pitch 5120 (/4 1280) >[319542.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[319542.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[319542.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319542.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319544.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319544.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319544.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42357b0] >[319544.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42357b0] width 1280 pitch 5120 (/4 1280) >[319544.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319544.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319544.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42357b0] >[319544.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42357b0] width 1280 pitch 5120 (/4 1280) >[319544.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[319544.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[319550.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319550.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319550.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319550.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319550.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319551.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319551.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[319551.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[319568.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319568.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319569.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[319569.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[319569.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319569.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319569.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42357b0] >[319569.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42357b0] width 1280 pitch 5120 (/4 1280) >[319569.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42357b0] >[319569.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42357b0] width 1280 pitch 5120 (/4 1280) >[319569.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[319569.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[319570.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319570.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319571.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319571.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319571.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319571.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319571.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319571.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319600.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319600.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319600.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[319600.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[319601.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319601.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319601.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319601.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319601.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319601.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319601.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319601.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319602.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319602.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319603.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319603.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319603.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[319603.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[319603.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319603.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319609.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319609.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319609.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319609.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319610.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319610.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319610.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319610.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319610.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319610.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319610.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319610.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319611.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[319611.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[319612.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319612.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319612.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319612.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319612.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319612.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319621.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319621.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319622.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319622.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319622.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319622.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319622.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319622.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319622.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319622.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319622.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319622.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319623.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319623.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319624.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319624.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319624.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319624.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319624.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319624.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319624.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319624.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319662.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319662.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319662.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319662.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319662.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[319662.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[319662.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319662.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319662.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319662.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319662.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319662.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319662.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[319662.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[319662.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319662.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319671.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319671.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319671.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319671.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319672.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319672.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319672.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[319672.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[319707.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319707.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319707.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319707.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319707.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319707.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319707.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319707.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319707.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319707.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319707.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319707.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319707.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319707.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319707.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319707.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319707.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319715.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319715.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319715.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319715.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319715.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319715.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319715.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319730.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319730.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319730.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319730.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319730.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[319730.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[319730.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319731.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319750.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319750.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319751.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319751.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319751.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319751.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319751.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319751.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319752.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319752.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319756.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319756.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319756.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319756.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319756.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319756.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319759.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[319759.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[319759.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319759.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319759.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319759.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319759.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319759.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319760.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319760.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319760.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319760.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319760.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319760.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319760.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319760.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319761.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319761.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319761.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319761.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319761.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319761.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319761.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319761.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319770.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319770.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319770.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319770.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319770.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[319770.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[319770.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319770.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319770.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[319770.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[319770.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319770.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319770.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[319770.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[319770.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319770.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319771.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[319771.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[319777.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[319777.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[319777.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[319777.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[319777.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[319777.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[319777.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319777.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319787.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319787.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319787.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319787.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319787.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[319787.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[319787.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319787.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319803.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319803.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319803.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319803.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319803.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[319803.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[319803.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[319803.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[319807.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[319807.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[319807.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319807.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319809.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319809.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319809.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319809.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319812.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319812.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319812.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319812.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319812.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[319812.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[319812.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[319812.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[319820.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319820.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319820.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319820.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319820.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[319820.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[319820.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319820.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319822.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319822.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319822.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319822.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319822.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[319822.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[319822.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[319822.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[319858.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319858.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319859.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319859.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319859.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319859.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319859.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319859.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319874.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319874.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319874.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319874.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319890.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[319890.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[319890.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319890.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319890.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[319890.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[319891.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319891.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319891.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[319891.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[319891.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[319891.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[319906.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[319906.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[319906.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f3a40] >[319906.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f3a40] width 1280 pitch 5120 (/4 1280) >[319906.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[319906.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[319906.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f3a40] >[319906.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f3a40] width 1280 pitch 5120 (/4 1280) >[319907.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319907.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319907.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[319907.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[319907.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319907.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319907.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[319907.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[319907.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319907.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319907.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319907.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319907.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[319907.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[319907.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319907.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319934.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319934.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319934.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[319934.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[319946.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319946.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319946.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319946.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319954.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319954.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319954.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319954.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319954.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319954.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319954.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319954.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319955.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[319955.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[319956.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319956.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319956.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[319956.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[319956.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[319956.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[319956.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319956.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319957.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060bc0] >[319957.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060bc0] width 1280 pitch 5120 (/4 1280) >[319957.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319957.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319957.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319957.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319975.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319975.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319975.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[319975.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[319975.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[319975.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[319975.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319975.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319975.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319975.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319975.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319975.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319975.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319975.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319975.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319975.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319975.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319975.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319975.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319975.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319975.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319975.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319975.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319976.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319976.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319976.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319976.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319976.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319976.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319976.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319976.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319976.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319976.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319976.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319976.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319976.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319976.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319976.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319976.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319976.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319976.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319977.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319977.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319977.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[319977.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[319977.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319977.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319979.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319979.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319979.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319979.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319979.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319979.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[319979.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[319979.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[319979.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[319981.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[319981.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[319981.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319981.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319981.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319981.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319981.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319982.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319982.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319982.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319982.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319982.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[319982.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[319982.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[319982.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[319982.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319982.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319982.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319982.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319982.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319983.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319983.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319983.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319983.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319983.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc7690] >[319983.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc7690] width 1280 pitch 5120 (/4 1280) >[319983.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[319983.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[319983.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[319983.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[319983.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319983.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319983.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[319983.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[319983.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319983.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319983.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[319983.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[319983.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[319983.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[319983.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319983.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319983.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319983.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319983.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319984.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319984.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319984.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319984.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319984.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319984.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319985.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[319985.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[319985.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[319985.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[319985.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319985.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319985.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319985.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[319985.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[319985.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[319985.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[319985.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320018.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320018.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320019.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320019.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320019.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[320019.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[320020.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320020.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320055.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320055.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320055.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320055.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320060.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[320060.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[320060.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097090] >[320060.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097090] width 1280 pitch 5120 (/4 1280) >[320065.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320065.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320066.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320066.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320066.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320066.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320066.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[320066.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[320070.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320070.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320070.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320070.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320070.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320070.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320070.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320070.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320070.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320070.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320070.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320070.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320070.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320070.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320070.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320070.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320070.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320070.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320070.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320070.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320071.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320071.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320071.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320071.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320071.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320071.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320071.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320071.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320071.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320071.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320071.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320071.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320071.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4b3f0] >[320071.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4b3f0] width 1280 pitch 5120 (/4 1280) >[320071.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320071.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320071.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320071.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320071.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320072.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320072.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320072.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320072.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320072.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320072.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320154.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4b3f0] >[320154.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4b3f0] width 1280 pitch 5120 (/4 1280) >[320155.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320155.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320155.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320155.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320155.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320155.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320159.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320159.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320160.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320160.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320160.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320160.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320160.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320160.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320160.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320160.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320161.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320162.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320162.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320162.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320162.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320162.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320162.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320162.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320162.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320162.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320162.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320162.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320165.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320165.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320165.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320165.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320165.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320165.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320165.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320165.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320165.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320165.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320166.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320166.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320167.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320167.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320167.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320167.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320167.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[320167.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[320167.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320167.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320167.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[320167.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[320167.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320167.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320169.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320169.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320169.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320169.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320169.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320169.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320170.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320170.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320170.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320170.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320170.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320170.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320170.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320170.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320170.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320170.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320171.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320171.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320171.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320171.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320171.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320171.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320172.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320172.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320172.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320173.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320173.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320173.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320173.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320173.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320173.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407ead0] >[320173.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407ead0] width 1280 pitch 5120 (/4 1280) >[320173.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320173.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320173.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407ead0] >[320173.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407ead0] width 1280 pitch 5120 (/4 1280) >[320173.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320173.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320253.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320253.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320254.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320254.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320254.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320254.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320254.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[320254.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[320254.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320254.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320254.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320254.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320254.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320254.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320254.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320254.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320256.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320256.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320257.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320257.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320257.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[320257.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[320257.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320257.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320257.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320257.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320258.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320258.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320258.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320258.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320258.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320258.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320259.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320259.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320259.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320259.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320259.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320259.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320260.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320260.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320260.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320260.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320260.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320260.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320260.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320260.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320260.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320260.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320296.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320296.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320296.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320296.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320296.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320296.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320296.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320296.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320297.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320297.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320297.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320297.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320297.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320297.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320297.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320297.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320307.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320307.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320307.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320307.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320307.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320307.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320307.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320307.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320307.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[320307.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[320307.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc130] >[320307.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc130] width 1280 pitch 5120 (/4 1280) >[320363.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320363.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320363.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320363.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320363.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320363.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320364.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320364.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320364.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320364.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320364.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320364.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320372.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320372.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320372.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320372.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320372.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320372.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320372.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320372.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320372.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320372.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320373.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320373.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320373.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[320373.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[320373.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320373.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320383.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320383.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320388.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320388.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320392.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320392.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320392.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320392.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320392.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320392.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320392.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320392.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320392.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320392.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320393.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[320393.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[320393.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320393.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320393.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[320393.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[320402.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320402.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320402.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320402.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320402.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320402.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320403.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320403.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320403.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320403.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320403.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320403.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320405.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320405.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320405.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320405.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320405.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320405.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320405.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320405.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320405.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[320405.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[320405.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320405.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320413.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320413.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320413.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320413.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320413.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320413.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320413.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320413.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320414.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320414.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320414.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320414.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320414.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320414.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320414.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320414.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320418.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[320418.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[320418.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320418.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320418.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320418.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320418.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320418.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320418.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320418.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320418.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320418.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320423.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320423.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320423.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[320423.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[320423.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320423.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320423.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[320423.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[320424.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320424.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320424.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320424.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320424.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320424.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320424.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320424.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320425.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320425.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320425.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320425.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320425.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[320425.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[320425.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320425.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320428.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320428.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320428.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320428.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320428.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320428.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320428.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320428.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320428.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440ae80] >[320428.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440ae80] width 1280 pitch 5120 (/4 1280) >[320428.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320428.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320428.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320428.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320429.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[320429.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[320439.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[320439.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[320439.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320439.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320439.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320439.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320440.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320440.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320440.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320440.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320440.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320440.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320440.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320440.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320440.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320440.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320450.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320450.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320450.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320450.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320450.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320450.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320450.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[320450.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[320450.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320450.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320450.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320450.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320450.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320450.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320450.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320450.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320460.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320460.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320460.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320460.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320460.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320460.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320460.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320460.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320461.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320461.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320461.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[320461.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[320461.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320461.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320461.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320461.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320469.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320469.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320469.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320469.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320470.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320470.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320470.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[320470.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[320470.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320470.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320470.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320470.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320494.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320494.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320494.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320494.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320494.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320494.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320494.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320494.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320494.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320494.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320494.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320494.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320494.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320494.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320494.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320494.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320501.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320501.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320501.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320501.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320501.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320501.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320501.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320501.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320501.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320501.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320501.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc130] >[320501.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc130] width 1280 pitch 5120 (/4 1280) >[320501.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320501.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320501.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc130] >[320502.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc130] width 1280 pitch 5120 (/4 1280) >[320517.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320517.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320517.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320518.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320518.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320518.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320518.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320518.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320518.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320518.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320518.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320518.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320518.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320518.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320518.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320518.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320523.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[320523.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[320523.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320523.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320523.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320523.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320523.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320523.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320524.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320524.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320524.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320524.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320524.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320524.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320524.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[320524.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[320529.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320529.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320530.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320530.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320530.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320530.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320530.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[320530.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[320530.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320530.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320533.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[320533.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[320533.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320533.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320533.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320533.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320534.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320534.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320535.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320535.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320535.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320535.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320535.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[320535.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[320546.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42355d0] >[320546.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42355d0] width 1280 pitch 5120 (/4 1280) >[320547.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320547.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320547.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320547.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320547.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320547.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320547.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320547.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320547.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[320547.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[320550.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320550.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320550.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320550.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320550.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320550.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320557.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320557.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320557.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320557.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320557.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320557.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320557.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[320557.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[320558.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320558.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320558.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[320558.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[320558.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320558.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320558.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320558.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320564.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320564.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320581.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[320581.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[320581.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[320581.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[320581.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320581.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320582.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320582.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320582.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320582.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320582.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320582.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320582.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320582.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320582.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320582.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320599.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320599.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320600.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320600.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320600.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320600.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320600.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320600.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320600.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[320601.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[320601.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320601.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320601.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[320601.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[320602.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320602.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320602.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320602.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320603.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320603.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320603.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320603.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320603.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320603.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320635.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ae0b0] >[320635.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ae0b0] width 1280 pitch 5120 (/4 1280) >[320635.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[320635.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[320635.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320635.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320635.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[320635.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[320635.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320635.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320636.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320636.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320636.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320636.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320636.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320636.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320638.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320638.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320639.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[320639.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[320639.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[320639.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[320639.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320639.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320660.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320660.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320660.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[320660.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[320677.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320677.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320677.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[320677.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[320682.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[320682.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[320682.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320682.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320683.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[320683.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[320691.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320691.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320691.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320691.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320691.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320691.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320691.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ae0b0] >[320691.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ae0b0] width 1280 pitch 5120 (/4 1280) >[320692.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320692.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320692.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cbad0] >[320692.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cbad0] width 1280 pitch 5120 (/4 1280) >[320724.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[320724.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[320724.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320724.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320724.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4df0] >[320724.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4df0] width 1280 pitch 5120 (/4 1280) >[320724.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320724.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320729.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[320729.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[320729.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[320729.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[320729.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320729.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320729.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320729.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320731.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320731.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320731.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320731.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[320731.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320731.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320731.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320731.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320733.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320733.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320733.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320733.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320785.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[320785.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[320785.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320785.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320785.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db950] >[320785.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db950] width 1280 pitch 5120 (/4 1280) >[320785.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cbad0] >[320785.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cbad0] width 1280 pitch 5120 (/4 1280) >[320785.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320785.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320785.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[320785.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[320785.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320786.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320786.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320786.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320786.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320786.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320786.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[320786.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[320786.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[320786.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[320786.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[320786.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[320786.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4df0] >[320786.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4df0] width 1280 pitch 5120 (/4 1280) >[320787.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320787.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320787.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[320787.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[320787.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320787.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320787.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320787.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320788.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bddbe0] >[320788.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bddbe0] width 1280 pitch 5120 (/4 1280) >[320788.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320788.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320788.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[320788.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[320801.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320801.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320802.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320802.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320802.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[320802.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[320802.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320802.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320803.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[320803.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[320803.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320803.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320803.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[320803.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[320814.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320814.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320814.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320814.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320814.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[320814.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[320814.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320814.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320814.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[320814.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[320815.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320815.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320815.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c31b0] >[320815.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c31b0] width 1280 pitch 5120 (/4 1280) >[320815.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320815.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320922.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320922.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320922.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320922.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320922.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320922.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320922.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320922.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320922.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320922.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320922.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320922.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320922.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320922.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320923.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320923.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320923.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320923.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320923.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320924.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320924.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320924.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320924.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320924.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320924.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320924.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320924.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320924.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320924.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c1e80] >[320924.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c1e80] width 1280 pitch 5120 (/4 1280) >[320924.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[320924.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[320937.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320937.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320937.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320937.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320941.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320941.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320941.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320941.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320941.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320941.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320941.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320941.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320941.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320941.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320941.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320941.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320941.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320941.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320942.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320942.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320943.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320943.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320944.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320944.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320944.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320944.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320944.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320944.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320944.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320944.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320944.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320944.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320944.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320944.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320956.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320956.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320957.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320957.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320957.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320957.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320957.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320957.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320971.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320971.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320971.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320971.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320971.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fee130] >[320971.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fee130] width 1280 pitch 5120 (/4 1280) >[320971.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320971.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320975.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[320975.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[320975.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419a130] >[320975.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419a130] width 1280 pitch 5120 (/4 1280) >[320976.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320976.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320976.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4319240] >[320976.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4319240] width 1280 pitch 5120 (/4 1280) >[320976.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[320976.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[320977.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[320977.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[320977.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320977.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320977.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320977.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320981.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320981.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320981.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[320981.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[320981.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ae0b0] >[320981.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ae0b0] width 1280 pitch 5120 (/4 1280) >[320981.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac4e0] >[320981.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac4e0] width 1280 pitch 5120 (/4 1280) >[320982.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[320982.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[320982.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320982.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320982.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406260] >[320982.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406260] width 1280 pitch 5120 (/4 1280) >[320982.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4df0] >[320982.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4df0] width 1280 pitch 5120 (/4 1280) >[320983.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320983.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320984.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[320984.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[320984.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[320984.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[320984.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[320984.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[320984.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[320984.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[320985.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[320985.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[320985.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4df0] >[320985.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4df0] width 1280 pitch 5120 (/4 1280) >[320985.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320985.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320993.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[320993.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[320993.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320993.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320993.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[320993.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[320993.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[320993.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[320994.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[320994.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[320994.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320994.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320994.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320994.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320994.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320994.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320995.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x441b7e0] >[320995.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x441b7e0] width 1280 pitch 5120 (/4 1280) >[320995.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[320995.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[320995.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320995.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320995.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320995.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320996.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320996.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320996.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320996.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320996.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4312000] >[320997.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4312000] width 1280 pitch 5120 (/4 1280) >[320997.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[320997.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[320997.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4df0] >[320997.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4df0] width 1280 pitch 5120 (/4 1280) >[320998.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[320998.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[320998.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[320998.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[320998.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[320998.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[320998.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[320998.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[320999.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[320999.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[320999.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[320999.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[320999.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[320999.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[320999.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[320999.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[321001.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[321001.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[321001.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[321001.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[321001.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431ba90] >[321001.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431ba90] width 1280 pitch 5120 (/4 1280) >[321032.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321032.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321032.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[321032.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[321032.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321032.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321032.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[321032.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[321032.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321032.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321032.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[321032.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[321032.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321032.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321032.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[321032.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[321032.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321032.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321032.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9d720] >[321033.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9d720] width 1280 pitch 5120 (/4 1280) >[321033.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[321033.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[321033.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321033.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321033.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321033.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321033.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321034.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321034.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321034.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321038.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060c60] >[321038.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060c60] width 1280 pitch 5120 (/4 1280) >[321038.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321038.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321038.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321038.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321038.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321039.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321039.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321039.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[321039.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[321039.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eabb80] >[321039.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eabb80] width 1280 pitch 5120 (/4 1280) >[321061.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[321061.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[321061.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[321061.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[321061.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321061.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321061.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[321061.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[321062.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[321062.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[321062.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[321062.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[321062.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[321062.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[321062.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321062.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321062.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[321062.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[321062.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[321062.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[321063.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3facdc0] >[321063.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3facdc0] width 1280 pitch 5120 (/4 1280) >[321063.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[321063.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[321063.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4002c30] >[321063.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4002c30] width 1280 pitch 5120 (/4 1280) >[321063.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[321063.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[321063.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[321063.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[321063.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[321063.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[321065.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8440] >[321065.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8440] width 1280 pitch 5120 (/4 1280) >[321065.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[321065.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[321065.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[321065.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[321065.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[321065.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[321065.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[321065.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[321065.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca0d0] >[321065.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca0d0] width 1280 pitch 5120 (/4 1280) >[321065.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427a470] >[321065.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427a470] width 1280 pitch 5120 (/4 1280) >[321065.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321065.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321087.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321087.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321088.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4319c60] >[321088.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4319c60] width 1280 pitch 5120 (/4 1280) >[321088.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eab820] >[321088.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eab820] width 1280 pitch 5120 (/4 1280) >[321088.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[321088.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[321089.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[321089.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[321090.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40610f0] >[321090.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40610f0] width 1280 pitch 5120 (/4 1280) >[321090.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[321090.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[321090.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4319c60] >[321090.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4319c60] width 1280 pitch 5120 (/4 1280) >[321090.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[321090.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[321091.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[321091.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[321091.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff3dd0] >[321091.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff3dd0] width 1280 pitch 5120 (/4 1280) >[321091.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[321091.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[321098.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4128150] >[321098.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4128150] width 1280 pitch 5120 (/4 1280) >[321098.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321098.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321098.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[321098.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[321098.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321098.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321103.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4279ea0] >[321103.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4279ea0] width 1280 pitch 5120 (/4 1280) >[321103.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[321103.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[321103.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321103.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321103.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[321103.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[321116.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[321116.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[321116.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[321116.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[321116.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db440] >[321116.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db440] width 1280 pitch 5120 (/4 1280) >[321116.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4002c30] >[321116.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4002c30] width 1280 pitch 5120 (/4 1280) >[321147.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ff230] >[321147.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ff230] width 1280 pitch 5120 (/4 1280) >[321147.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[321147.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[321147.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[321147.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[321147.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[321147.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[321175.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321175.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321177.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cc4f0] >[321177.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cc4f0] width 1280 pitch 5120 (/4 1280) >[321177.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[321177.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[321177.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[321177.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[321205.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ae0b0] >[321205.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ae0b0] width 1280 pitch 5120 (/4 1280) >[321205.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419d920] >[321205.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419d920] width 1280 pitch 5120 (/4 1280) >[321205.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321205.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321205.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[321206.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[321206.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321206.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321207.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf7f40] >[321207.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf7f40] width 1280 pitch 5120 (/4 1280) >[321207.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321207.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321207.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[321207.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[321207.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f5c50] >[321207.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f5c50] width 1280 pitch 5120 (/4 1280) >[321208.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4002c30] >[321208.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4002c30] width 1280 pitch 5120 (/4 1280) >[321208.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415020] >[321208.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415020] width 1280 pitch 5120 (/4 1280) >[321208.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4002c30] >[321208.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4002c30] width 1280 pitch 5120 (/4 1280) >[321265.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4415150] >[321265.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4415150] width 1280 pitch 5120 (/4 1280) >[321265.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321265.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321265.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428fa50] >[321265.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428fa50] width 1280 pitch 5120 (/4 1280) >[321265.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[321265.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[321376.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321376.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321376.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321376.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429ece0] >[321376.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429ece0] width 1280 pitch 5120 (/4 1280) >[321378.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321378.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321378.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[321378.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[321378.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321378.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321378.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321378.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321378.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429fe90] >[321378.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429fe90] width 1280 pitch 5120 (/4 1280) >[321378.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321378.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321378.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429fe90] >[321378.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429fe90] width 1280 pitch 5120 (/4 1280) >[321378.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321378.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321378.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429fe90] >[321378.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429fe90] width 1280 pitch 5120 (/4 1280) >[321378.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321378.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321378.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4302810] >[321378.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4302810] width 1280 pitch 5120 (/4 1280) >[321379.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d270] >[321379.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d270] width 1280 pitch 5120 (/4 1280) >[321379.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[321379.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[321379.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f9b0] >[321379.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f9b0] width 1280 pitch 5120 (/4 1280) >[321379.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409b700] >[321379.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409b700] width 1280 pitch 5120 (/4 1280) >[321379.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a0ad0] >[321379.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a0ad0] width 1280 pitch 5120 (/4 1280) >[321379.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f5c50] >[321379.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f5c50] width 1280 pitch 5120 (/4 1280) >[321379.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4306cc0] >[321379.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4306cc0] width 1280 pitch 5120 (/4 1280) >[321379.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[321379.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[321379.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[321379.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[321379.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[321379.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[321379.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac200] >[321379.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac200] width 1280 pitch 5120 (/4 1280) >[321379.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[321379.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[321379.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[321379.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[321379.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[321379.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[321379.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4040f10] >[321379.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4040f10] width 1280 pitch 5120 (/4 1280) >[321379.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e44c00] >[321379.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e44c00] width 1280 pitch 5120 (/4 1280) >[321379.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4400c70] >[321379.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4400c70] width 1280 pitch 5120 (/4 1280) >[321379.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x429fe90] >[321379.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x429fe90] width 1280 pitch 5120 (/4 1280) >[321379.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4b2e0] >[321379.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4b2e0] width 1280 pitch 5120 (/4 1280) >[321379.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f5c50] >[321379.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f5c50] width 1280 pitch 5120 (/4 1280) >[321379.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[321379.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[321379.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[321379.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[321379.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d8710] >[321379.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d8710] width 1280 pitch 5120 (/4 1280) >[321478.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4482620] >[321478.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4482620] width 1280 pitch 5120 (/4 1280) >[321479.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409dcb0] >[321479.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409dcb0] width 1280 pitch 5120 (/4 1280) >[321479.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[321479.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[321479.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[321479.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[321486.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5410] >[321486.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5410] width 1280 pitch 5120 (/4 1280) >[321487.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414aff0] >[321487.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414aff0] width 1280 pitch 5120 (/4 1280) >[321487.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c8000] >[321487.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c8000] width 1280 pitch 5120 (/4 1280) >[321487.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414aff0] >[321487.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414aff0] width 1280 pitch 5120 (/4 1280) >[321679.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b66b0] >[321679.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b66b0] width 1280 pitch 5120 (/4 1280) >[321679.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b8af0] >[321679.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b8af0] width 1280 pitch 5120 (/4 1280) >[321679.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[321679.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[321680.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b66b0] >[321680.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b66b0] width 1280 pitch 5120 (/4 1280) >[321732.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44842e0] >[321732.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44842e0] width 1280 pitch 5120 (/4 1280) >[321733.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd400] >[321733.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd400] width 1280 pitch 5120 (/4 1280) >[321733.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4132620] >[321733.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4132620] width 1280 pitch 5120 (/4 1280) >[321733.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4318b00] >[321733.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4318b00] width 1280 pitch 5120 (/4 1280) >[321733.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f6850] >[321733.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f6850] width 1280 pitch 5120 (/4 1280) >[321734.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71e90] >[321734.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71e90] width 1280 pitch 5120 (/4 1280) >[321734.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[321734.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[321734.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f9050] >[321734.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f9050] width 1280 pitch 5120 (/4 1280) >[321734.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414aff0] >[321734.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414aff0] width 1280 pitch 5120 (/4 1280) >[321734.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406fa10] >[321734.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406fa10] width 1280 pitch 5120 (/4 1280) >[321734.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414aff0] >[321734.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414aff0] width 1280 pitch 5120 (/4 1280) >[321914.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c4570] >[321914.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c4570] width 1280 pitch 5120 (/4 1280) >[321914.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[321914.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[321916.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[321916.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322167.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322167.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322167.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[322167.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[322167.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322167.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322167.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[322167.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[322168.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322168.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322168.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[322168.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[322168.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322168.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322168.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[322168.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[322168.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322168.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322169.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[322169.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[322169.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf40c0] >[322169.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf40c0] width 1280 pitch 5120 (/4 1280) >[322169.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4409270] >[322169.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4409270] width 1280 pitch 5120 (/4 1280) >[322169.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a99f0] >[322169.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a99f0] width 1280 pitch 5120 (/4 1280) >[322169.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414aff0] >[322169.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414aff0] width 1280 pitch 5120 (/4 1280) >[322169.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a99f0] >[322169.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a99f0] width 1280 pitch 5120 (/4 1280) >[322172.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c28d00] >[322172.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c28d00] width 1280 pitch 5120 (/4 1280) >[322179.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114f970] >[322179.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114f970] width 1280 pitch 5120 (/4 1280) >[322179.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[322179.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[322179.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c4570] >[322179.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c4570] width 1280 pitch 5120 (/4 1280) >[322179.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c28d00] >[322179.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c28d00] width 1280 pitch 5120 (/4 1280) >[323846.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323846.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323846.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323846.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323846.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323846.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323846.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323846.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323846.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323846.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323846.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323846.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323846.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323846.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323846.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323846.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323846.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323846.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323846.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323847.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323847.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323847.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323847.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323847.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323847.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323847.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323847.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323847.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323847.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[323847.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[323847.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[323847.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[323847.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323847.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323847.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323847.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323847.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323847.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323847.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44e0740] >[323847.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44e0740] width 1280 pitch 5120 (/4 1280) >[323848.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323848.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323848.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323848.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323848.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323848.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323848.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323848.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323848.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323848.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323848.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323848.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323848.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323848.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323848.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323848.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323848.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323848.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323848.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323849.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448a650] >[323849.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448a650] width 1280 pitch 5120 (/4 1280) >[323849.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4206bb0] >[323849.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4206bb0] width 1280 pitch 5120 (/4 1280) >[323849.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[323849.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe8e0] >[323849.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe8e0] width 1280 pitch 5120 (/4 1280) >[323849.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44898f0] >[323849.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44898f0] width 1280 pitch 5120 (/4 1280) >[324088.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a2010] >[324088.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a2010] width 1280 pitch 5120 (/4 1280) >[324088.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3950] >[324088.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3950] width 1280 pitch 5120 (/4 1280) >[324215.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x447e8f0] >[324215.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x447e8f0] width 1280 pitch 5120 (/4 1280) >[324215.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324215.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324534.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324534.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324534.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324534.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324534.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324534.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324534.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324535.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324535.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324536.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324537.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324537.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324537.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324537.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324537.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324537.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324628.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324628.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324628.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324628.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324628.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ade40] >[324628.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ade40] width 1280 pitch 5120 (/4 1280) >[324629.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324629.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324629.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ade40] >[324629.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ade40] width 1280 pitch 5120 (/4 1280) >[324629.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324629.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324629.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9c70] >[324629.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9c70] width 1280 pitch 5120 (/4 1280) >[324629.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324629.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324630.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324630.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324630.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324630.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324630.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324630.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324630.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324631.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324631.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ade40] >[324631.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ade40] width 1280 pitch 5120 (/4 1280) >[324631.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324631.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324631.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9c70] >[324631.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9c70] width 1280 pitch 5120 (/4 1280) >[324690.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324690.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324691.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6de0] >[324691.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6de0] width 1280 pitch 5120 (/4 1280) >[324691.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6de0] >[324691.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6de0] width 1280 pitch 5120 (/4 1280) >[324691.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324691.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324695.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324695.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324709.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324709.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324709.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324709.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324709.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ade40] >[324709.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ade40] width 1280 pitch 5120 (/4 1280) >[324709.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324709.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324709.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ade40] >[324709.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ade40] width 1280 pitch 5120 (/4 1280) >[324710.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfde70] >[324710.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfde70] width 1280 pitch 5120 (/4 1280) >[324711.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324711.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324711.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[324711.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[324711.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6de0] >[324711.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6de0] width 1280 pitch 5120 (/4 1280) >[324711.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324711.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[324711.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[324711.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[324711.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a69a0] >[324711.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a69a0] width 1280 pitch 5120 (/4 1280) >[325363.870] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[325363.870] (II) RADEON(0): Printing DDC gathered Modelines: >[325363.870] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[325377.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325377.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325377.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5db0] >[325377.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5db0] width 1280 pitch 5120 (/4 1280) >[325377.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325377.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325377.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faac60] >[325377.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faac60] width 1280 pitch 5120 (/4 1280) >[325378.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325378.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325378.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faac60] >[325378.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faac60] width 1280 pitch 5120 (/4 1280) >[325378.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325378.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325378.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faac60] >[325378.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faac60] width 1280 pitch 5120 (/4 1280) >[325378.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325378.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325378.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[325378.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[325378.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5d30] >[325378.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5d30] width 1280 pitch 5120 (/4 1280) >[325378.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42a9180] >[325378.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42a9180] width 1280 pitch 5120 (/4 1280) >[325378.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5d30] >[325378.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5d30] width 1280 pitch 5120 (/4 1280) >[325399.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5db0] >[325399.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5db0] width 1280 pitch 5120 (/4 1280) >[325424.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325424.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325424.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325424.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325424.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325424.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325424.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325424.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325424.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325424.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325424.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325425.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325425.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4b60] >[325425.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4b60] width 1280 pitch 5120 (/4 1280) >[325425.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5d30] >[325425.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5d30] width 1280 pitch 5120 (/4 1280) >[325425.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6de0] >[325425.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6de0] width 1280 pitch 5120 (/4 1280) >[325425.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5d30] >[325425.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5d30] width 1280 pitch 5120 (/4 1280) >[325425.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6de0] >[325425.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6de0] width 1280 pitch 5120 (/4 1280) >[325430.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41188c0] >[325430.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41188c0] width 1280 pitch 5120 (/4 1280) >[325477.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a1090] >[325477.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a1090] width 1280 pitch 5120 (/4 1280) >[325478.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4461af0] >[325478.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4461af0] width 1280 pitch 5120 (/4 1280) >[325478.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a1090] >[325478.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a1090] width 1280 pitch 5120 (/4 1280) >[325479.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4118c60] >[325479.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4118c60] width 1280 pitch 5120 (/4 1280) >[325483.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3950] >[325483.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3950] width 1280 pitch 5120 (/4 1280) >[325498.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b69a0] >[325498.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b69a0] width 1280 pitch 5120 (/4 1280) >[325509.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f44d0] >[325509.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f44d0] width 1280 pitch 5120 (/4 1280) >[325509.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5b30] >[325509.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5b30] width 1280 pitch 5120 (/4 1280) >[325542.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a1090] >[325542.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a1090] width 1280 pitch 5120 (/4 1280) >[325603.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d6160] >[325603.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d6160] width 1280 pitch 5120 (/4 1280) >[325603.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fc290] >[325603.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fc290] width 1280 pitch 5120 (/4 1280) >[325614.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4000] >[325614.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4000] width 1280 pitch 5120 (/4 1280) >[325667.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325667.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325668.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325668.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325668.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325668.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325668.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9190] >[325668.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9190] width 1280 pitch 5120 (/4 1280) >[325668.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325668.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325668.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9190] >[325668.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9190] width 1280 pitch 5120 (/4 1280) >[325668.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325668.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325668.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41a9a70] >[325669.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41a9a70] width 1280 pitch 5120 (/4 1280) >[325669.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41018a0] >[325669.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41018a0] width 1280 pitch 5120 (/4 1280) >[325669.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325669.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325669.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41018a0] >[325669.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41018a0] width 1280 pitch 5120 (/4 1280) >[325669.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9190] >[325669.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9190] width 1280 pitch 5120 (/4 1280) >[325669.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41018a0] >[325669.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41018a0] width 1280 pitch 5120 (/4 1280) >[325669.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d9190] >[325669.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d9190] width 1280 pitch 5120 (/4 1280) >[325806.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fbbb0] >[325806.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fbbb0] width 1280 pitch 5120 (/4 1280) >[325806.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6e20] >[325806.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6e20] width 1280 pitch 5120 (/4 1280) >[325808.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[325808.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[325823.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d1310] >[325823.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d1310] width 1280 pitch 5120 (/4 1280) >[325824.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f92c0] >[325824.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f92c0] width 1280 pitch 5120 (/4 1280) >[325824.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4466920] >[325824.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4466920] width 1280 pitch 5120 (/4 1280) >[325824.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465a80] >[325824.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465a80] width 1280 pitch 5120 (/4 1280) >[325830.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325830.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325830.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465a80] >[325830.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465a80] width 1280 pitch 5120 (/4 1280) >[325831.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325831.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325831.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465a80] >[325831.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465a80] width 1280 pitch 5120 (/4 1280) >[325832.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325833.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325833.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325833.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325833.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325833.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325834.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325834.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325834.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325834.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325835.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325835.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325835.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ddac0] >[325835.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ddac0] width 1280 pitch 5120 (/4 1280) >[325835.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ddac0] >[325835.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ddac0] width 1280 pitch 5120 (/4 1280) >[325835.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[325835.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[325838.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ddac0] >[325838.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ddac0] width 1280 pitch 5120 (/4 1280) >[325838.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[325838.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[325838.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4466920] >[325838.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4466920] width 1280 pitch 5120 (/4 1280) >[325838.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6aa0] >[325838.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6aa0] width 1280 pitch 5120 (/4 1280) >[325838.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4466920] >[325838.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4466920] width 1280 pitch 5120 (/4 1280) >[325838.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f9b20] >[325838.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f9b20] width 1280 pitch 5120 (/4 1280) >[325839.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4466920] >[325839.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4466920] width 1280 pitch 5120 (/4 1280) >[325932.717] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[325932.717] (II) RADEON(0): Printing DDC gathered Modelines: >[325932.717] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[326532.550] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[326532.550] (II) RADEON(0): Printing DDC gathered Modelines: >[326532.550] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[326622.887] (II) RADEON(0): RADEONSaveScreen(2) >[326622.887] (II) RADEON(0): RADEONSaveScreen(0) >[346880.531] (II) RADEON(0): RADEONSaveScreen(1) >[346888.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4494e50] >[346888.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4494e50] width 1280 pitch 5120 (/4 1280) >[347109.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449b310] >[347109.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449b310] width 1280 pitch 5120 (/4 1280) >[347109.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449b310] >[347109.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449b310] width 1280 pitch 5120 (/4 1280) >[347113.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44994d0] >[347113.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44994d0] width 1280 pitch 5120 (/4 1280) >[347135.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f2bc0] >[347135.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f2bc0] width 1280 pitch 5120 (/4 1280) >[347342.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347342.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347342.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347342.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347342.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347342.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347342.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347342.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347342.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347342.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347342.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347342.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347342.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347342.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347342.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347342.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347342.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347342.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347343.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347343.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347343.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347343.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347343.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347343.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347343.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347343.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347343.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347343.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347343.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347343.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347343.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347343.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347343.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347343.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347344.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd560] >[347344.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd560] width 1280 pitch 5120 (/4 1280) >[347344.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab470] >[347344.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab470] width 1280 pitch 5120 (/4 1280) >[347344.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347344.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347345.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347345.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347345.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347345.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347345.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347345.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347345.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4119d60] >[347346.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4119d60] width 1280 pitch 5120 (/4 1280) >[347366.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347366.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347366.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347366.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347366.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347366.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347366.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347366.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347366.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347366.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347367.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347367.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347367.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347367.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347367.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410f480] >[347367.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410f480] width 1280 pitch 5120 (/4 1280) >[347367.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445f3e0] >[347367.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445f3e0] width 1280 pitch 5120 (/4 1280) >[347367.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347367.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347370.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410e090] >[347370.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410e090] width 1280 pitch 5120 (/4 1280) >[347370.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347370.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7e5c0] >[347382.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7e5c0] width 1280 pitch 5120 (/4 1280) >[347382.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347382.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347382.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347382.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347382.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347383.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347383.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347384.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347384.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347384.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347384.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347384.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347384.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347384.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347384.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347384.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347384.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347385.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347385.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347385.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347385.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347385.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347386.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347386.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347386.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347386.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347386.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347386.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347386.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347386.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347386.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347419.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347419.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347419.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347419.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347419.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347419.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347419.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347419.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347419.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347419.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347420.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347420.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347421.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347421.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347421.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd600] >[347421.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd600] width 1280 pitch 5120 (/4 1280) >[347421.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347421.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347421.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44dd600] >[347421.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44dd600] width 1280 pitch 5120 (/4 1280) >[347421.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7500] >[347421.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7500] width 1280 pitch 5120 (/4 1280) >[347479.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347479.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347479.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347480.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347480.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347480.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347480.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347480.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347480.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347480.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347480.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347480.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347480.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347480.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347480.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347480.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347480.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347480.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347480.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347480.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347480.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347480.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347480.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347480.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a7a0] >[347480.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a7a0] width 1280 pitch 5120 (/4 1280) >[347480.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347480.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347480.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347480.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347481.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347481.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347481.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347481.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347481.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347481.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347481.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347481.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347481.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347481.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347481.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347481.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347482.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347482.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347482.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4101c20] >[347482.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4101c20] width 1280 pitch 5120 (/4 1280) >[347482.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347482.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347482.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347482.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347482.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347482.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347482.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347482.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347483.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347483.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347483.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347483.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347509.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a890] >[347509.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a890] width 1280 pitch 5120 (/4 1280) >[347511.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347511.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347511.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347511.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347511.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347511.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347511.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347511.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347511.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347511.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347511.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347511.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347511.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347521.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347521.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347521.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347521.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347522.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347522.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347522.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347522.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347522.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a890] >[347522.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a890] width 1280 pitch 5120 (/4 1280) >[347522.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347522.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347523.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a890] >[347523.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a890] width 1280 pitch 5120 (/4 1280) >[347523.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ab2c0] >[347523.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ab2c0] width 1280 pitch 5120 (/4 1280) >[347523.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a890] >[347523.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a890] width 1280 pitch 5120 (/4 1280) >[347523.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347524.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347524.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x451a890] >[347524.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x451a890] width 1280 pitch 5120 (/4 1280) >[347524.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4517280] >[347524.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4517280] width 1280 pitch 5120 (/4 1280) >[347529.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347529.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347530.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f30c0] >[347530.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f30c0] width 1280 pitch 5120 (/4 1280) >[347530.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347530.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347530.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f30c0] >[347530.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f30c0] width 1280 pitch 5120 (/4 1280) >[347530.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347530.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347531.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f30c0] >[347531.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f30c0] width 1280 pitch 5120 (/4 1280) >[347531.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347531.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347531.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f30c0] >[347531.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f30c0] width 1280 pitch 5120 (/4 1280) >[347531.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347532.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347532.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465850] >[347532.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465850] width 1280 pitch 5120 (/4 1280) >[347532.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[347532.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[347532.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465850] >[347532.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465850] width 1280 pitch 5120 (/4 1280) >[347532.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347532.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347532.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465850] >[347532.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465850] width 1280 pitch 5120 (/4 1280) >[347532.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347532.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347532.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465850] >[347532.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465850] width 1280 pitch 5120 (/4 1280) >[347537.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4465850] >[347537.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4465850] width 1280 pitch 5120 (/4 1280) >[347554.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347554.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347554.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347554.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347554.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f0470] >[347554.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f0470] width 1280 pitch 5120 (/4 1280) >[347555.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f4df0] >[347555.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f4df0] width 1280 pitch 5120 (/4 1280) >[347558.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347558.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347558.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347558.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347559.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347559.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347559.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a6b40] >[347559.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a6b40] width 1280 pitch 5120 (/4 1280) >[347562.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f0470] >[347562.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f0470] width 1280 pitch 5120 (/4 1280) >[347562.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347562.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347571.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347571.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347571.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347571.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347571.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347572.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347572.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347572.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347576.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a3d10] >[347576.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a3d10] width 1280 pitch 5120 (/4 1280) >[347576.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347576.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347578.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347578.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347578.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347578.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347578.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347578.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347578.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347578.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347578.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347578.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347578.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347578.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347578.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347578.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347578.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347578.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347578.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347578.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347578.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347579.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347579.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a3d10] >[347579.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a3d10] width 1280 pitch 5120 (/4 1280) >[347579.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347579.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347579.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a3d10] >[347579.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a3d10] width 1280 pitch 5120 (/4 1280) >[347579.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347579.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347579.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f4df0] >[347579.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f4df0] width 1280 pitch 5120 (/4 1280) >[347579.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347579.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347579.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347579.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347579.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347579.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347579.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347579.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449cd90] >[347580.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449cd90] width 1280 pitch 5120 (/4 1280) >[347580.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a3d10] >[347580.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a3d10] width 1280 pitch 5120 (/4 1280) >[347580.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0910] >[347580.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0910] width 1280 pitch 5120 (/4 1280) >[347580.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f23e0] >[347580.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f23e0] width 1280 pitch 5120 (/4 1280) >[347580.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347580.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347580.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347580.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347580.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347597.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347597.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347597.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347597.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347597.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347597.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347597.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347597.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347597.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ece60] >[347597.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ece60] width 1280 pitch 5120 (/4 1280) >[347598.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347598.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347598.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347598.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347598.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d0e80] >[347598.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d0e80] width 1280 pitch 5120 (/4 1280) >[347598.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347598.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347598.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449cef0] >[347598.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449cef0] width 1280 pitch 5120 (/4 1280) >[347624.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a5eb0] >[347624.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a5eb0] width 1280 pitch 5120 (/4 1280) >[347998.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410da90] >[347998.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410da90] width 1280 pitch 5120 (/4 1280) >[348000.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a0100] >[348000.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a0100] width 1280 pitch 5120 (/4 1280) >[348000.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410d930] >[348000.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410d930] width 1280 pitch 5120 (/4 1280) >[348000.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434a280] >[348000.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434a280] width 1280 pitch 5120 (/4 1280) >[348150.468] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[348150.468] (II) RADEON(0): Printing DDC gathered Modelines: >[348150.468] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[348750.438] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[348750.438] (II) RADEON(0): Printing DDC gathered Modelines: >[348750.438] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[348840.902] (II) RADEON(0): RADEONSaveScreen(2) >[348840.902] (II) RADEON(0): RADEONSaveScreen(0) >[388832.354] (II) RADEON(0): RADEONSaveScreen(1) >[388841.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388841.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388842.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f5000] >[388842.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f5000] width 1280 pitch 5120 (/4 1280) >[388842.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f57c0] >[388842.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f57c0] width 1280 pitch 5120 (/4 1280) >[388843.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc5a0] >[388843.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc5a0] width 1280 pitch 5120 (/4 1280) >[388843.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388843.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388843.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc5a0] >[388843.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc5a0] width 1280 pitch 5120 (/4 1280) >[388843.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388843.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388843.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc5a0] >[388843.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc5a0] width 1280 pitch 5120 (/4 1280) >[388845.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388845.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388845.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc5a0] >[388845.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc5a0] width 1280 pitch 5120 (/4 1280) >[388848.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc5a0] >[388848.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc5a0] width 1280 pitch 5120 (/4 1280) >[388848.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f57c0] >[388848.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f57c0] width 1280 pitch 5120 (/4 1280) >[388848.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f5000] >[388848.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f5000] width 1280 pitch 5120 (/4 1280) >[388848.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f57c0] >[388848.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f57c0] width 1280 pitch 5120 (/4 1280) >[388848.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388848.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388849.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518dd0] >[388849.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518dd0] width 1280 pitch 5120 (/4 1280) >[388849.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f5000] >[388849.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f5000] width 1280 pitch 5120 (/4 1280) >[389154.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6640] >[389154.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6640] width 1280 pitch 5120 (/4 1280) >[389154.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f0cb0] >[389154.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f0cb0] width 1280 pitch 5120 (/4 1280) >[389171.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44de250] >[389171.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44de250] width 1280 pitch 5120 (/4 1280) >[389171.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a2f70] >[389171.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a2f70] width 1280 pitch 5120 (/4 1280) >[389180.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4348cd0] >[389180.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4348cd0] width 1280 pitch 5120 (/4 1280) >[389180.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345750] >[389180.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345750] width 1280 pitch 5120 (/4 1280) >[389191.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ff0d0] >[389191.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ff0d0] width 1280 pitch 5120 (/4 1280) >[389191.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d22b0] >[389191.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d22b0] width 1280 pitch 5120 (/4 1280) >[389280.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44af290] >[389280.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44af290] width 1280 pitch 5120 (/4 1280) >[389306.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44cf500] >[389306.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44cf500] width 1280 pitch 5120 (/4 1280) >[389336.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44c5080] >[389336.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44c5080] width 1280 pitch 5120 (/4 1280) >[389336.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ba1c0] >[389336.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ba1c0] width 1280 pitch 5120 (/4 1280) >[389381.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a2860] >[389381.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a2860] width 1280 pitch 5120 (/4 1280) >[389983.117] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[389983.117] (II) RADEON(0): Printing DDC gathered Modelines: >[389983.117] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[390072.898] (II) RADEON(0): RADEONSaveScreen(2) >[390072.898] (II) RADEON(0): RADEONSaveScreen(0) >[390481.767] (II) RADEON(0): RADEONSaveScreen(1) >[390526.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44cd9b0] >[390526.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44cd9b0] width 1280 pitch 5120 (/4 1280) >[390526.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390526.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390527.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390527.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390527.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390527.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390527.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390527.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390527.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390527.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390527.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390527.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390527.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390527.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390527.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390527.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390527.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390527.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390527.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390527.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390527.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390527.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390527.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41161e0] >[390527.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41161e0] width 1280 pitch 5120 (/4 1280) >[390527.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390527.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390527.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41161e0] >[390527.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41161e0] width 1280 pitch 5120 (/4 1280) >[390527.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390527.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390527.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390527.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390527.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390527.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390527.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390527.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390527.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390527.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390527.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390527.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390527.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390527.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390527.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390527.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390528.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44cd9b0] >[390528.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44cd9b0] width 1280 pitch 5120 (/4 1280) >[390528.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390528.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390528.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390528.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390529.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390529.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390529.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390529.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390529.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390529.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390529.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390529.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390533.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390533.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390566.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390566.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390566.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390566.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390566.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390566.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390566.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390566.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390566.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390566.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390566.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390566.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390566.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390566.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390566.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390566.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390566.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390566.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390566.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390566.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390566.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390566.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390566.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390566.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390566.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390566.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390566.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390566.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390566.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390566.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390566.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390566.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44adbc0] >[390566.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44adbc0] width 1280 pitch 5120 (/4 1280) >[390566.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390566.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390566.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390566.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390566.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390566.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390566.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390566.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390566.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390566.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390566.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390566.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390566.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ed8e0] >[390566.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ed8e0] width 1280 pitch 5120 (/4 1280) >[390566.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390566.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390566.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ed8e0] >[390566.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ed8e0] width 1280 pitch 5120 (/4 1280) >[390566.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390567.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390567.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390567.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390567.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390567.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390567.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390567.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390568.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390568.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390568.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae240] >[390568.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae240] width 1280 pitch 5120 (/4 1280) >[390569.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44c1de0] >[390569.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44c1de0] width 1280 pitch 5120 (/4 1280) >[390569.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b2df0] >[390569.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b2df0] width 1280 pitch 5120 (/4 1280) >[390584.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390584.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390584.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390584.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390584.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390584.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390584.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390584.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390584.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390584.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390585.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390585.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390585.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390585.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390585.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390585.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390585.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b4d00] >[390585.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b4d00] width 1280 pitch 5120 (/4 1280) >[390585.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390585.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390585.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44c1de0] >[390585.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44c1de0] width 1280 pitch 5120 (/4 1280) >[390585.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390585.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390585.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390585.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390585.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390585.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390585.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390586.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390586.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46147c0] >[390586.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46147c0] width 1280 pitch 5120 (/4 1280) >[390586.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4515cf0] >[390586.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4515cf0] width 1280 pitch 5120 (/4 1280) >[390586.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390586.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390586.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ac9f0] >[390586.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ac9f0] width 1280 pitch 5120 (/4 1280) >[390586.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bbde0] >[390586.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bbde0] width 1280 pitch 5120 (/4 1280) >[390586.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44fa8a0] >[390586.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44fa8a0] width 1280 pitch 5120 (/4 1280) >[390586.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6650] >[390586.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6650] width 1280 pitch 5120 (/4 1280) >[390587.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6650] >[390587.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6650] width 1280 pitch 5120 (/4 1280) >[390587.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6650] >[390587.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6650] width 1280 pitch 5120 (/4 1280) >[390587.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dbe60] >[390587.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dbe60] width 1280 pitch 5120 (/4 1280) >[390587.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4112a50] >[390587.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4112a50] width 1280 pitch 5120 (/4 1280) >[390587.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6650] >[390587.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6650] width 1280 pitch 5120 (/4 1280) >[390587.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41129e0] >[390587.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41129e0] width 1280 pitch 5120 (/4 1280) >[390587.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4127fc0] >[390587.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4127fc0] width 1280 pitch 5120 (/4 1280) >[390603.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b4f90] >[390603.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b4f90] width 1280 pitch 5120 (/4 1280) >[390605.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390605.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390799.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44c8e70] >[390799.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44c8e70] width 1280 pitch 5120 (/4 1280) >[390799.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b3d80] >[390799.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b3d80] width 1280 pitch 5120 (/4 1280) >[390820.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[390820.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[390822.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fef10] >[390822.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fef10] width 1280 pitch 5120 (/4 1280) >[390869.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b6110] >[390869.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b6110] width 1280 pitch 5120 (/4 1280) >[390869.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fef10] >[390869.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fef10] width 1280 pitch 5120 (/4 1280) >[390928.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x454a820] >[390928.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x454a820] width 1280 pitch 5120 (/4 1280) >[390928.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46101e0] >[390928.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46101e0] width 1280 pitch 5120 (/4 1280) >[391028.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4592fc0] >[391028.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4592fc0] width 1280 pitch 5120 (/4 1280) >[391048.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bae40] >[391048.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bae40] width 1280 pitch 5120 (/4 1280) >[391064.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4592fc0] >[391064.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4592fc0] width 1280 pitch 5120 (/4 1280) >[391314.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x452c510] >[391314.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x452c510] width 1280 pitch 5120 (/4 1280) >[391315.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b410] >[391315.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b410] width 1280 pitch 5120 (/4 1280) >[391323.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4534250] >[391323.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4534250] width 1280 pitch 5120 (/4 1280) >[391323.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b130] >[391323.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b130] width 1280 pitch 5120 (/4 1280) >[391328.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e40] >[391328.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e40] width 1280 pitch 5120 (/4 1280) >[391486.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bf480] >[391486.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bf480] width 1280 pitch 5120 (/4 1280) >[391486.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bf480] >[391486.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bf480] width 1280 pitch 5120 (/4 1280) >[391498.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4545000] >[391498.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4545000] width 1280 pitch 5120 (/4 1280) >[391499.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4588b60] >[391499.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4588b60] width 1280 pitch 5120 (/4 1280) >[391542.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4525aa0] >[391542.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4525aa0] width 1280 pitch 5120 (/4 1280) >[391542.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45243d0] >[391542.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45243d0] width 1280 pitch 5120 (/4 1280) >[391581.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464ab70] >[391581.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464ab70] width 1280 pitch 5120 (/4 1280) >[391691.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4545000] >[391691.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4545000] width 1280 pitch 5120 (/4 1280) >[391815.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4656bb0] >[391815.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4656bb0] width 1280 pitch 5120 (/4 1280) >[391815.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[391815.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[391976.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[391976.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[391976.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4656bb0] >[391976.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4656bb0] width 1280 pitch 5120 (/4 1280) >[392003.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392003.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392003.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392003.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392004.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392004.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392004.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392004.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[392004.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[392004.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392004.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392004.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[392004.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[392004.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392004.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392004.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[392004.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[392004.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392004.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392004.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392004.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392004.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392004.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392004.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392004.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392004.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392004.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392004.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392004.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392004.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[392004.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[392005.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392005.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392005.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392005.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392005.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392005.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392005.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392005.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392005.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392005.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392005.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[392005.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[392005.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a680] >[392005.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a680] width 1280 pitch 5120 (/4 1280) >[392005.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[392005.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[392005.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[392005.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[392005.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[392005.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[392070.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[392070.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[392086.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4496190] >[392086.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4496190] width 1280 pitch 5120 (/4 1280) >[392086.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1488680] >[392086.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1488680] width 1280 pitch 5120 (/4 1280) >[392087.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a05e0] >[392087.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a05e0] width 1280 pitch 5120 (/4 1280) >[392087.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44851f0] >[392087.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44851f0] width 1280 pitch 5120 (/4 1280) >[392088.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392088.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392089.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44851f0] >[392090.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44851f0] width 1280 pitch 5120 (/4 1280) >[392090.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392090.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392196.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392196.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392196.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392196.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392196.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392196.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392196.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392196.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392196.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392196.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392197.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392197.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392197.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340530] >[392197.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340530] width 1280 pitch 5120 (/4 1280) >[392197.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x455d250] >[392197.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x455d250] width 1280 pitch 5120 (/4 1280) >[392197.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f9460] >[392197.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f9460] width 1280 pitch 5120 (/4 1280) >[392197.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x455d250] >[392198.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x455d250] width 1280 pitch 5120 (/4 1280) >[392198.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43333e0] >[392198.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43333e0] width 1280 pitch 5120 (/4 1280) >[392200.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43403a0] >[392200.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43403a0] width 1280 pitch 5120 (/4 1280) >[392221.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392221.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392221.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392221.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392221.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392221.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392221.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392221.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392221.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392221.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392221.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392221.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392222.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392222.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392223.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392223.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392223.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6660] >[392223.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6660] width 1280 pitch 5120 (/4 1280) >[392223.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392223.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392223.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e6660] >[392223.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e6660] width 1280 pitch 5120 (/4 1280) >[392231.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4333e20] >[392231.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4333e20] width 1280 pitch 5120 (/4 1280) >[392231.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4333e20] >[392231.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4333e20] width 1280 pitch 5120 (/4 1280) >[392233.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4653140] >[392233.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4653140] width 1280 pitch 5120 (/4 1280) >[392293.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46bd270] >[392293.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46bd270] width 1280 pitch 5120 (/4 1280) >[392400.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392400.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392400.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392400.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392400.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[392400.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[392400.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392400.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392401.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392401.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392401.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4645db0] >[392401.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4645db0] width 1280 pitch 5120 (/4 1280) >[392401.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392401.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392401.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4645db0] >[392401.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4645db0] width 1280 pitch 5120 (/4 1280) >[392402.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392402.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392402.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46bd270] >[392402.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46bd270] width 1280 pitch 5120 (/4 1280) >[392402.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392402.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392402.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46bd270] >[392402.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46bd270] width 1280 pitch 5120 (/4 1280) >[392402.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392402.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392402.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46bd270] >[392402.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46bd270] width 1280 pitch 5120 (/4 1280) >[392404.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392404.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392417.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392417.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392420.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392420.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392420.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433ab20] >[392420.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433ab20] width 1280 pitch 5120 (/4 1280) >[392422.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4528b60] >[392422.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4528b60] width 1280 pitch 5120 (/4 1280) >[392422.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46477c0] >[392422.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46477c0] width 1280 pitch 5120 (/4 1280) >[392457.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46379e0] >[392457.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46379e0] width 1280 pitch 5120 (/4 1280) >[392638.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392638.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392639.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4535a40] >[392639.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4535a40] width 1280 pitch 5120 (/4 1280) >[392639.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637a80] >[392639.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637a80] width 1280 pitch 5120 (/4 1280) >[392639.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4535a40] >[392639.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4535a40] width 1280 pitch 5120 (/4 1280) >[392655.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4661560] >[392655.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4661560] width 1280 pitch 5120 (/4 1280) >[392655.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392655.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392655.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4664ab0] >[392655.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4664ab0] width 1280 pitch 5120 (/4 1280) >[392655.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b670] >[392655.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b670] width 1280 pitch 5120 (/4 1280) >[392671.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b670] >[392671.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b670] width 1280 pitch 5120 (/4 1280) >[392671.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392671.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392671.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392671.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392672.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e40] >[392672.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e40] width 1280 pitch 5120 (/4 1280) >[392701.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637e00] >[392701.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637e00] width 1280 pitch 5120 (/4 1280) >[392701.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392701.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392701.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637e00] >[392701.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637e00] width 1280 pitch 5120 (/4 1280) >[392701.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392701.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392701.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637e00] >[392701.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637e00] width 1280 pitch 5120 (/4 1280) >[392702.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392702.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392702.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637e00] >[392702.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637e00] width 1280 pitch 5120 (/4 1280) >[392702.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392702.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392702.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392702.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392702.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b670] >[392702.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b670] width 1280 pitch 5120 (/4 1280) >[392702.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392702.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392713.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449d970] >[392713.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449d970] width 1280 pitch 5120 (/4 1280) >[392713.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392713.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449d970] >[392713.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449d970] width 1280 pitch 5120 (/4 1280) >[392713.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392713.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449d970] >[392713.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449d970] width 1280 pitch 5120 (/4 1280) >[392713.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392713.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449d970] >[392713.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449d970] width 1280 pitch 5120 (/4 1280) >[392713.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392713.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392713.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461ab60] >[392713.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461ab60] width 1280 pitch 5120 (/4 1280) >[392713.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392713.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392713.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461ab60] >[392713.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461ab60] width 1280 pitch 5120 (/4 1280) >[392713.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392713.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392713.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433db30] >[392713.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433db30] width 1280 pitch 5120 (/4 1280) >[392714.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392714.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392714.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433db30] >[392714.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433db30] width 1280 pitch 5120 (/4 1280) >[392714.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392714.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392714.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433c570] >[392714.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433c570] width 1280 pitch 5120 (/4 1280) >[392714.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392714.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392714.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392714.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392714.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392714.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392714.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392714.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392714.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392714.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392714.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392714.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392714.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392714.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392714.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461ab60] >[392714.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461ab60] width 1280 pitch 5120 (/4 1280) >[392715.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433c570] >[392715.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433c570] width 1280 pitch 5120 (/4 1280) >[392715.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392715.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392715.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392715.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392715.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392715.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392715.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392725.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e40] >[392725.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e40] width 1280 pitch 5120 (/4 1280) >[392725.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4664ab0] >[392725.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4664ab0] width 1280 pitch 5120 (/4 1280) >[392725.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e40] >[392725.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e40] width 1280 pitch 5120 (/4 1280) >[392725.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4664ab0] >[392725.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4664ab0] width 1280 pitch 5120 (/4 1280) >[392726.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c1d0] >[392726.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c1d0] width 1280 pitch 5120 (/4 1280) >[392726.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4664ab0] >[392726.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4664ab0] width 1280 pitch 5120 (/4 1280) >[392726.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x455ff30] >[392726.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x455ff30] width 1280 pitch 5120 (/4 1280) >[392726.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392726.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392726.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457b1a0] >[392726.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457b1a0] width 1280 pitch 5120 (/4 1280) >[392726.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392726.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392731.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392731.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392732.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392732.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392732.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392732.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392732.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392732.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392732.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392732.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392732.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392732.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392732.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392732.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392732.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392732.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392733.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4786970] >[392733.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4786970] width 1280 pitch 5120 (/4 1280) >[392733.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392733.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392734.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392734.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392734.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392734.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392734.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433c570] >[392734.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433c570] width 1280 pitch 5120 (/4 1280) >[392734.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392734.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392734.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433c570] >[392734.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433c570] width 1280 pitch 5120 (/4 1280) >[392745.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c1d0] >[392745.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c1d0] width 1280 pitch 5120 (/4 1280) >[392745.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392745.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392745.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f90d0] >[392745.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f90d0] width 1280 pitch 5120 (/4 1280) >[392746.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392746.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392746.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4786970] >[392746.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4786970] width 1280 pitch 5120 (/4 1280) >[392746.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392746.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392746.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4786970] >[392746.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4786970] width 1280 pitch 5120 (/4 1280) >[392746.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392746.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392746.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4786970] >[392746.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4786970] width 1280 pitch 5120 (/4 1280) >[392746.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4337880] >[392746.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4337880] width 1280 pitch 5120 (/4 1280) >[392746.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780f60] >[392747.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780f60] width 1280 pitch 5120 (/4 1280) >[392747.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4629aa0] >[392747.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4629aa0] width 1280 pitch 5120 (/4 1280) >[392748.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392748.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392748.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457b1a0] >[392748.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457b1a0] width 1280 pitch 5120 (/4 1280) >[392748.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392748.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392748.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457b1a0] >[392748.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457b1a0] width 1280 pitch 5120 (/4 1280) >[392748.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433db30] >[392749.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433db30] width 1280 pitch 5120 (/4 1280) >[392762.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c9ae0] >[392762.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c9ae0] width 1280 pitch 5120 (/4 1280) >[392762.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43429d0] >[392762.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43429d0] width 1280 pitch 5120 (/4 1280) >[392776.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4561860] >[392776.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4561860] width 1280 pitch 5120 (/4 1280) >[392776.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46bd270] >[392776.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46bd270] width 1280 pitch 5120 (/4 1280) >[392776.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465f040] >[392776.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465f040] width 1280 pitch 5120 (/4 1280) >[392799.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4636c70] >[392799.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4636c70] width 1280 pitch 5120 (/4 1280) >[392799.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e40] >[392799.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e40] width 1280 pitch 5120 (/4 1280) >[392863.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392863.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392864.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331ce0] >[392864.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331ce0] width 1280 pitch 5120 (/4 1280) >[392864.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44c5000] >[392864.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44c5000] width 1280 pitch 5120 (/4 1280) >[393236.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x462e450] >[393236.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x462e450] width 1280 pitch 5120 (/4 1280) >[393236.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4637d30] >[393236.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4637d30] width 1280 pitch 5120 (/4 1280) >[393616.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45fff30] >[393616.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45fff30] width 1280 pitch 5120 (/4 1280) >[393616.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c820] >[393616.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c820] width 1280 pitch 5120 (/4 1280) >[393745.546] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[393745.546] (II) RADEON(0): Printing DDC gathered Modelines: >[393745.546] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[394345.292] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[394345.292] (II) RADEON(0): Printing DDC gathered Modelines: >[394345.292] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[394435.889] (II) RADEON(0): RADEONSaveScreen(2) >[394435.889] (II) RADEON(0): RADEONSaveScreen(0) >[442319.133] (II) RADEON(0): RADEONSaveScreen(1) >[442333.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442333.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442333.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442333.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442333.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442333.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442333.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442333.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442333.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442333.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442333.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442333.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442333.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442333.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442333.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442333.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442333.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442334.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442334.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442334.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442334.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442334.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442334.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442334.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442334.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442334.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442334.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442334.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442334.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442334.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442334.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442334.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569b40] >[442334.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569b40] width 1280 pitch 5120 (/4 1280) >[442334.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456b580] >[442334.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456b580] width 1280 pitch 5120 (/4 1280) >[442334.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46309d0] >[442334.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46309d0] width 1280 pitch 5120 (/4 1280) >[442334.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46678c0] >[442334.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46678c0] width 1280 pitch 5120 (/4 1280) >[442334.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456c930] >[442334.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456c930] width 1280 pitch 5120 (/4 1280) >[442334.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46678c0] >[442334.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46678c0] width 1280 pitch 5120 (/4 1280) >[442334.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456c930] >[442334.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456c930] width 1280 pitch 5120 (/4 1280) >[442334.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46678c0] >[442334.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46678c0] width 1280 pitch 5120 (/4 1280) >[442334.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456c930] >[442334.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456c930] width 1280 pitch 5120 (/4 1280) >[442334.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456acc0] >[442334.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456acc0] width 1280 pitch 5120 (/4 1280) >[442334.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4630c00] >[442334.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4630c00] width 1280 pitch 5120 (/4 1280) >[442334.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456dce0] >[442334.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456dce0] width 1280 pitch 5120 (/4 1280) >[442334.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456be40] >[442334.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456be40] width 1280 pitch 5120 (/4 1280) >[442334.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581140] >[442334.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581140] width 1280 pitch 5120 (/4 1280) >[442334.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46316f0] >[442334.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46316f0] width 1280 pitch 5120 (/4 1280) >[442334.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456cb60] >[442334.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456cb60] width 1280 pitch 5120 (/4 1280) >[442334.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46316f0] >[442334.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46316f0] width 1280 pitch 5120 (/4 1280) >[442334.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456cb60] >[442334.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456cb60] width 1280 pitch 5120 (/4 1280) >[442334.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46316f0] >[442335.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46316f0] width 1280 pitch 5120 (/4 1280) >[442335.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456cb60] >[442335.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456cb60] width 1280 pitch 5120 (/4 1280) >[442335.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46316f0] >[442335.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46316f0] width 1280 pitch 5120 (/4 1280) >[442335.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4667220] >[442335.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4667220] width 1280 pitch 5120 (/4 1280) >[442335.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456cfc0] >[442335.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456cfc0] width 1280 pitch 5120 (/4 1280) >[442335.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4667220] >[442335.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4667220] width 1280 pitch 5120 (/4 1280) >[442335.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456cfc0] >[442335.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456cfc0] width 1280 pitch 5120 (/4 1280) >[442335.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456c4d0] >[442335.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456c4d0] width 1280 pitch 5120 (/4 1280) >[442401.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410fc90] >[442401.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410fc90] width 1280 pitch 5120 (/4 1280) >[442431.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4682ee0] >[442431.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4682ee0] width 1280 pitch 5120 (/4 1280) >[442431.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4630340] >[442431.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4630340] width 1280 pitch 5120 (/4 1280) >[442559.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456bc10] >[442559.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456bc10] width 1280 pitch 5120 (/4 1280) >[442559.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4580880] >[442559.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4580880] width 1280 pitch 5120 (/4 1280) >[442559.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4677f50] >[442559.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4677f50] width 1280 pitch 5120 (/4 1280) >[442559.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45780f0] >[442559.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45780f0] width 1280 pitch 5120 (/4 1280) >[442570.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4691ed0] >[442570.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4691ed0] width 1280 pitch 5120 (/4 1280) >[442570.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4632410] >[442570.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4632410] width 1280 pitch 5120 (/4 1280) >[442682.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46834a0] >[442682.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46834a0] width 1280 pitch 5120 (/4 1280) >[442682.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4680c70] >[442682.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4680c70] width 1280 pitch 5120 (/4 1280) >[442771.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46834a0] >[442771.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46834a0] width 1280 pitch 5120 (/4 1280) >[442776.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776d70] >[442776.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776d70] width 1280 pitch 5120 (/4 1280) >[442776.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b98c90] >[442776.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b98c90] width 1280 pitch 5120 (/4 1280) >[442776.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776d70] >[442776.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776d70] width 1280 pitch 5120 (/4 1280) >[442776.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x469a7c0] >[442776.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x469a7c0] width 1280 pitch 5120 (/4 1280) >[442806.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c3590] >[442806.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c3590] width 1280 pitch 5120 (/4 1280) >[442806.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c3590] >[442806.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c3590] width 1280 pitch 5120 (/4 1280) >[442818.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c3590] >[442819.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c3590] width 1280 pitch 5120 (/4 1280) >[442819.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4580880] >[442819.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4580880] width 1280 pitch 5120 (/4 1280) >[443120.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b764d0] >[443121.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b764d0] width 1280 pitch 5120 (/4 1280) >[443121.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b77e10] >[443121.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b77e10] width 1280 pitch 5120 (/4 1280) >[443325.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47605f0] >[443325.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47605f0] width 1280 pitch 5120 (/4 1280) >[443325.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ffe90] >[443325.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ffe90] width 1280 pitch 5120 (/4 1280) >[443394.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476be60] >[443394.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476be60] width 1280 pitch 5120 (/4 1280) >[443817.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443817.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443817.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47820f0] >[443817.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47820f0] width 1280 pitch 5120 (/4 1280) >[443818.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443818.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443818.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47820f0] >[443818.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47820f0] width 1280 pitch 5120 (/4 1280) >[443818.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443818.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443818.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476be60] >[443819.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476be60] width 1280 pitch 5120 (/4 1280) >[443819.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752620] >[443819.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752620] width 1280 pitch 5120 (/4 1280) >[443819.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476be60] >[443819.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476be60] width 1280 pitch 5120 (/4 1280) >[443819.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443819.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443820.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752620] >[443820.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752620] width 1280 pitch 5120 (/4 1280) >[443820.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fecc0] >[443820.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fecc0] width 1280 pitch 5120 (/4 1280) >[443820.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47820f0] >[443820.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47820f0] width 1280 pitch 5120 (/4 1280) >[443820.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4665390] >[443820.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4665390] width 1280 pitch 5120 (/4 1280) >[443820.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443820.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443820.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752620] >[443820.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752620] width 1280 pitch 5120 (/4 1280) >[443821.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773510] >[443821.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773510] width 1280 pitch 5120 (/4 1280) >[443821.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752620] >[443821.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752620] width 1280 pitch 5120 (/4 1280) >[443824.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fecc0] >[443824.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fecc0] width 1280 pitch 5120 (/4 1280) >[443835.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4767630] >[443835.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4767630] width 1280 pitch 5120 (/4 1280) >[443835.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4769e00] >[443835.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4769e00] width 1280 pitch 5120 (/4 1280) >[443882.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752920] >[443882.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752920] width 1280 pitch 5120 (/4 1280) >[443882.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470a5c0] >[443882.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470a5c0] width 1280 pitch 5120 (/4 1280) >[443889.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752920] >[443889.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752920] width 1280 pitch 5120 (/4 1280) >[443889.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[443889.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[443920.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[443920.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[443920.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80240] >[443920.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80240] width 1280 pitch 5120 (/4 1280) >[443920.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[443920.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[443920.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80240] >[443920.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80240] width 1280 pitch 5120 (/4 1280) >[443920.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[443920.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[443920.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80240] >[443920.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80240] width 1280 pitch 5120 (/4 1280) >[443921.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b070] >[443921.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b070] width 1280 pitch 5120 (/4 1280) >[443921.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b670] >[443921.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b670] width 1280 pitch 5120 (/4 1280) >[443921.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[443921.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[443921.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c200] >[443921.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c200] width 1280 pitch 5120 (/4 1280) >[443921.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4726090] >[443921.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4726090] width 1280 pitch 5120 (/4 1280) >[443922.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47522c0] >[443922.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47522c0] width 1280 pitch 5120 (/4 1280) >[443922.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x462bbf0] >[443922.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x462bbf0] width 1280 pitch 5120 (/4 1280) >[443922.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4752920] >[443922.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4752920] width 1280 pitch 5120 (/4 1280) >[443922.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[443922.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444015.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4757e70] >[444015.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4757e70] width 1280 pitch 5120 (/4 1280) >[444015.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a5930] >[444015.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a5930] width 1280 pitch 5120 (/4 1280) >[444064.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b1510] >[444064.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b1510] width 1280 pitch 5120 (/4 1280) >[444064.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80240] >[444064.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80240] width 1280 pitch 5120 (/4 1280) >[444143.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4730360] >[444143.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4730360] width 1280 pitch 5120 (/4 1280) >[444143.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4679760] >[444143.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4679760] width 1280 pitch 5120 (/4 1280) >[444144.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b630] >[444144.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b630] width 1280 pitch 5120 (/4 1280) >[444144.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[444144.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444185.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80c80] >[444185.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80c80] width 1280 pitch 5120 (/4 1280) >[444185.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4679760] >[444185.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4679760] width 1280 pitch 5120 (/4 1280) >[444209.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448b340] >[444209.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448b340] width 1280 pitch 5120 (/4 1280) >[444209.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4717f10] >[444209.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4717f10] width 1280 pitch 5120 (/4 1280) >[444221.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720aa0] >[444221.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720aa0] width 1280 pitch 5120 (/4 1280) >[444221.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444221.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444221.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4757e70] >[444221.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4757e70] width 1280 pitch 5120 (/4 1280) >[444222.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448b340] >[444222.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448b340] width 1280 pitch 5120 (/4 1280) >[444270.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471d4f0] >[444270.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471d4f0] width 1280 pitch 5120 (/4 1280) >[444270.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fb810] >[444270.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fb810] width 1280 pitch 5120 (/4 1280) >[444320.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[444320.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[444672.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47134a0] >[444672.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47134a0] width 1280 pitch 5120 (/4 1280) >[444673.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444673.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444681.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4765f40] >[444681.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4765f40] width 1280 pitch 5120 (/4 1280) >[444681.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47278d0] >[444681.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47278d0] width 1280 pitch 5120 (/4 1280) >[444681.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444681.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444681.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444681.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444681.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444681.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444681.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444681.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444681.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444681.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444682.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444682.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444682.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444682.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444682.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444682.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444682.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444682.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444682.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444682.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444682.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444682.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444682.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720050] >[444682.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720050] width 1280 pitch 5120 (/4 1280) >[444682.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47134a0] >[444682.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47134a0] width 1280 pitch 5120 (/4 1280) >[444682.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444682.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444682.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[444682.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444682.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444682.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444682.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[444682.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444682.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444682.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444682.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444682.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444682.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444682.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444682.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f2b90] >[444682.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f2b90] width 1280 pitch 5120 (/4 1280) >[444682.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4719520] >[444682.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4719520] width 1280 pitch 5120 (/4 1280) >[444682.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444682.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444682.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444682.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711170] >[444682.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711170] width 1280 pitch 5120 (/4 1280) >[444682.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444682.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444686.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444686.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444686.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444686.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444686.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444686.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444686.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444686.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444686.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444686.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444686.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b862c0] >[444686.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b862c0] width 1280 pitch 5120 (/4 1280) >[444687.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444687.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444688.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47278d0] >[444688.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47278d0] width 1280 pitch 5120 (/4 1280) >[444688.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444688.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444688.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[444688.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444689.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4ce0] >[444689.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4ce0] width 1280 pitch 5120 (/4 1280) >[444689.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a8f70] >[444689.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a8f70] width 1280 pitch 5120 (/4 1280) >[444708.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4716470] >[444708.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4716470] width 1280 pitch 5120 (/4 1280) >[444714.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709250] >[444714.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709250] width 1280 pitch 5120 (/4 1280) >[444714.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444714.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444714.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c4ee0] >[444714.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c4ee0] width 1280 pitch 5120 (/4 1280) >[444714.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471eab0] >[444714.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471eab0] width 1280 pitch 5120 (/4 1280) >[444714.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444714.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444714.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444714.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444714.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444714.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444714.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4711410] >[444714.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4711410] width 1280 pitch 5120 (/4 1280) >[444714.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444714.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444714.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449c340] >[444714.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449c340] width 1280 pitch 5120 (/4 1280) >[444714.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709250] >[444714.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709250] width 1280 pitch 5120 (/4 1280) >[444714.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47099d0] >[444714.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47099d0] width 1280 pitch 5120 (/4 1280) >[444714.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444714.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444740.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b87570] >[444740.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b87570] width 1280 pitch 5120 (/4 1280) >[444741.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444741.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444741.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4741ff0] >[444741.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4741ff0] width 1280 pitch 5120 (/4 1280) >[444741.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444741.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444742.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444742.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444745.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444745.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444745.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444745.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444745.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444745.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444745.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444745.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444790.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444790.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444790.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d940] >[444790.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d940] width 1280 pitch 5120 (/4 1280) >[444790.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4712900] >[444790.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4712900] width 1280 pitch 5120 (/4 1280) >[444790.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444790.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444791.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444791.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444791.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d940] >[444791.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d940] width 1280 pitch 5120 (/4 1280) >[444791.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b87570] >[444791.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b87570] width 1280 pitch 5120 (/4 1280) >[444791.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4712900] >[444791.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4712900] width 1280 pitch 5120 (/4 1280) >[444791.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444791.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444791.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4741ff0] >[444791.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4741ff0] width 1280 pitch 5120 (/4 1280) >[444791.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4712900] >[444791.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4712900] width 1280 pitch 5120 (/4 1280) >[444791.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4950] >[444791.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4950] width 1280 pitch 5120 (/4 1280) >[444792.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715d50] >[444792.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715d50] width 1280 pitch 5120 (/4 1280) >[444792.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d940] >[444792.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d940] width 1280 pitch 5120 (/4 1280) >[444809.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f1ec0] >[444809.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f1ec0] width 1280 pitch 5120 (/4 1280) >[444809.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444809.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444809.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4721c30] >[444809.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4721c30] width 1280 pitch 5120 (/4 1280) >[444810.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444810.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444810.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4741ff0] >[444810.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4741ff0] width 1280 pitch 5120 (/4 1280) >[444810.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444810.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444810.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444810.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444810.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444811.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444811.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c4b0] >[444811.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c4b0] width 1280 pitch 5120 (/4 1280) >[444815.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444815.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444815.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d2420] >[444815.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d2420] width 1280 pitch 5120 (/4 1280) >[444827.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d2420] >[444827.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d2420] width 1280 pitch 5120 (/4 1280) >[444831.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb500] >[444831.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb500] width 1280 pitch 5120 (/4 1280) >[444831.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cb90] >[444831.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cb90] width 1280 pitch 5120 (/4 1280) >[444929.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fbf50] >[444929.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fbf50] width 1280 pitch 5120 (/4 1280) >[444929.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d5b30] >[444929.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d5b30] width 1280 pitch 5120 (/4 1280) >[444976.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e6700] >[444976.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e6700] width 1280 pitch 5120 (/4 1280) >[444977.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[444977.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[444977.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d44e0] >[444977.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d44e0] width 1280 pitch 5120 (/4 1280) >[444977.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6b350] >[444977.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6b350] width 1280 pitch 5120 (/4 1280) >[445188.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[445188.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[445189.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e6700] >[445189.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e6700] width 1280 pitch 5120 (/4 1280) >[445189.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[445189.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[445189.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e6700] >[445189.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e6700] width 1280 pitch 5120 (/4 1280) >[445189.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[445189.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[445190.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6b350] >[445190.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6b350] width 1280 pitch 5120 (/4 1280) >[445190.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[445190.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[445190.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6b350] >[445190.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6b350] width 1280 pitch 5120 (/4 1280) >[445190.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ea0d0] >[445190.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ea0d0] width 1280 pitch 5120 (/4 1280) >[445190.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6b350] >[445190.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6b350] width 1280 pitch 5120 (/4 1280) >[445212.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c94e0] >[445212.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c94e0] width 1280 pitch 5120 (/4 1280) >[445212.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c6890] >[445212.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c6890] width 1280 pitch 5120 (/4 1280) >[445233.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f8930] >[445233.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f8930] width 1280 pitch 5120 (/4 1280) >[445397.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36071a0] >[445397.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36071a0] width 1280 pitch 5120 (/4 1280) >[445397.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36071a0] >[445397.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36071a0] width 1280 pitch 5120 (/4 1280) >[445397.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f8930] >[445397.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f8930] width 1280 pitch 5120 (/4 1280) >[445397.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d44e0] >[445397.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d44e0] width 1280 pitch 5120 (/4 1280) >[445397.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36071a0] >[445397.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36071a0] width 1280 pitch 5120 (/4 1280) >[445397.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d9e00] >[445397.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d9e00] width 1280 pitch 5120 (/4 1280) >[445398.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d9e00] >[445398.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d9e00] width 1280 pitch 5120 (/4 1280) >[445398.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c9480] >[445398.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c9480] width 1280 pitch 5120 (/4 1280) >[445398.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5660] >[445398.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5660] width 1280 pitch 5120 (/4 1280) >[445398.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5660] >[445398.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5660] width 1280 pitch 5120 (/4 1280) >[445403.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d220] >[445403.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d220] width 1280 pitch 5120 (/4 1280) >[445404.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d220] >[445404.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d220] width 1280 pitch 5120 (/4 1280) >[445428.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1210] >[445428.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1210] width 1280 pitch 5120 (/4 1280) >[445449.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad10] >[445449.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad10] width 1280 pitch 5120 (/4 1280) >[445450.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d220] >[445450.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d220] width 1280 pitch 5120 (/4 1280) >[445450.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad10] >[445450.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad10] width 1280 pitch 5120 (/4 1280) >[445450.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d220] >[445450.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d220] width 1280 pitch 5120 (/4 1280) >[445450.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad10] >[445450.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad10] width 1280 pitch 5120 (/4 1280) >[445451.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d44e0] >[445451.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d44e0] width 1280 pitch 5120 (/4 1280) >[445451.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1210] >[445451.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1210] width 1280 pitch 5120 (/4 1280) >[445451.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d220] >[445451.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d220] width 1280 pitch 5120 (/4 1280) >[445451.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1210] >[445451.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1210] width 1280 pitch 5120 (/4 1280) >[445455.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad10] >[445455.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad10] width 1280 pitch 5120 (/4 1280) >[445489.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cbd50] >[445489.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cbd50] width 1280 pitch 5120 (/4 1280) >[445490.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad10] >[445490.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad10] width 1280 pitch 5120 (/4 1280) >[445490.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d8150] >[445490.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d8150] width 1280 pitch 5120 (/4 1280) >[445490.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cbd50] >[445490.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cbd50] width 1280 pitch 5120 (/4 1280) >[445490.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d8150] >[445490.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d8150] width 1280 pitch 5120 (/4 1280) >[445491.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d44e0] >[445491.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d44e0] width 1280 pitch 5120 (/4 1280) >[445491.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d44e0] >[445491.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d44e0] width 1280 pitch 5120 (/4 1280) >[445491.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d8150] >[445491.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d8150] width 1280 pitch 5120 (/4 1280) >[445617.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ce20] >[445617.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ce20] width 1280 pitch 5120 (/4 1280) >[445624.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445624.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445691.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b910] >[445691.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b910] width 1280 pitch 5120 (/4 1280) >[445691.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445691.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445691.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b910] >[445691.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b910] width 1280 pitch 5120 (/4 1280) >[445691.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445691.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445691.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b910] >[445691.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b910] width 1280 pitch 5120 (/4 1280) >[445692.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445692.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445692.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b910] >[445692.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b910] width 1280 pitch 5120 (/4 1280) >[445692.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445692.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445692.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7b910] >[445692.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7b910] width 1280 pitch 5120 (/4 1280) >[445692.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445692.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445693.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445693.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445693.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445693.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445693.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445693.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445693.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445693.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445732.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445732.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445733.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445733.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445733.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445733.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445733.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445733.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445733.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445733.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445733.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445733.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445733.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445733.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445734.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445734.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445734.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3580] >[445734.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3580] width 1280 pitch 5120 (/4 1280) >[445734.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d60b0] >[445734.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d60b0] width 1280 pitch 5120 (/4 1280) >[445734.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c7d50] >[445734.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c7d50] width 1280 pitch 5120 (/4 1280) >[445734.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d60b0] >[445734.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d60b0] width 1280 pitch 5120 (/4 1280) >[445734.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d3b0] >[445734.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d3b0] width 1280 pitch 5120 (/4 1280) >[445734.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e7990] >[445734.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e7990] width 1280 pitch 5120 (/4 1280) >[445786.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445786.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36075c0] >[445786.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36075c0] width 1280 pitch 5120 (/4 1280) >[445786.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445786.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36075c0] >[445786.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36075c0] width 1280 pitch 5120 (/4 1280) >[445786.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445786.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36075c0] >[445786.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36075c0] width 1280 pitch 5120 (/4 1280) >[445786.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445786.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445786.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445786.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445786.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445786.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445786.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230280] >[445786.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230280] width 1280 pitch 5120 (/4 1280) >[445787.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445787.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445787.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445787.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445787.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445788.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445788.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445788.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445788.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445788.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445788.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445788.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445788.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445788.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445788.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445788.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445788.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445788.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd590] >[445788.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd590] width 1280 pitch 5120 (/4 1280) >[445788.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231170] >[445788.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231170] width 1280 pitch 5120 (/4 1280) >[445788.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44db260] >[445788.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44db260] width 1280 pitch 5120 (/4 1280) >[445790.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440b1e0] >[445790.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440b1e0] width 1280 pitch 5120 (/4 1280) >[445790.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445790.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445790.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445790.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445790.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445790.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445790.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445790.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445790.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445790.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445790.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445790.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445790.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445790.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445790.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445791.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445791.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445791.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445791.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445791.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445791.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445791.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445791.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445791.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445791.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445791.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445791.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445791.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445791.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445791.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445791.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445791.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445791.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445791.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445791.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440b1e0] >[445791.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440b1e0] width 1280 pitch 5120 (/4 1280) >[445791.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440b1e0] >[445791.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440b1e0] width 1280 pitch 5120 (/4 1280) >[445791.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440b1e0] >[445791.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440b1e0] width 1280 pitch 5120 (/4 1280) >[445791.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445791.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445791.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445791.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445799.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445799.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445799.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445799.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445799.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445799.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445799.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445799.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445799.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445799.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445799.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445799.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445799.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445799.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445799.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445799.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445800.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445800.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445800.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445800.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445800.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445800.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445800.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445800.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445800.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445800.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4652420] >[445800.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4652420] width 1280 pitch 5120 (/4 1280) >[445800.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445800.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445801.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445801.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445801.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445801.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445801.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445801.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445801.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[445801.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[445801.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e6810] >[445801.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e6810] width 1280 pitch 5120 (/4 1280) >[445801.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445801.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445801.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445801.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445801.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445801.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445801.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445801.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445801.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445801.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445801.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445801.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445801.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340920] >[445801.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340920] width 1280 pitch 5120 (/4 1280) >[445801.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445801.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445801.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445801.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445801.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270290] >[445801.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270290] width 1280 pitch 5120 (/4 1280) >[445801.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445801.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445802.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445802.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445802.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f5190] >[445802.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f5190] width 1280 pitch 5120 (/4 1280) >[445802.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a740] >[445802.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a740] width 1280 pitch 5120 (/4 1280) >[445802.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[445802.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[445802.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464a1d0] >[445802.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464a1d0] width 1280 pitch 5120 (/4 1280) >[445809.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46594f0] >[445809.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46594f0] width 1280 pitch 5120 (/4 1280) >[445857.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445857.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445861.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa6c0] >[445861.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa6c0] width 1280 pitch 5120 (/4 1280) >[445874.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445874.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445874.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445874.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445874.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445874.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445874.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445874.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445874.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445874.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445874.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445874.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445874.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445874.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445874.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445874.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445874.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445874.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445874.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa6c0] >[445874.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa6c0] width 1280 pitch 5120 (/4 1280) >[445874.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445874.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445874.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa6c0] >[445874.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa6c0] width 1280 pitch 5120 (/4 1280) >[445875.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445875.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445875.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa6c0] >[445875.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa6c0] width 1280 pitch 5120 (/4 1280) >[445875.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x434b310] >[445875.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x434b310] width 1280 pitch 5120 (/4 1280) >[445875.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e4f50] >[445875.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e4f50] width 1280 pitch 5120 (/4 1280) >[445875.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445875.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445875.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445875.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445875.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445875.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445875.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445875.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445875.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445875.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445875.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445875.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445875.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445875.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445875.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445875.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445875.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cdf30] >[445875.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cdf30] width 1280 pitch 5120 (/4 1280) >[445875.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b45b10] >[445875.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b45b10] width 1280 pitch 5120 (/4 1280) >[445876.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445876.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445876.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445876.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445876.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607550] >[445876.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607550] width 1280 pitch 5120 (/4 1280) >[445876.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d6a0] >[445876.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d6a0] width 1280 pitch 5120 (/4 1280) >[445876.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445876.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445876.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445876.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445876.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445876.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445876.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445876.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445876.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445876.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445876.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445876.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445876.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445876.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445876.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445876.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445876.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445876.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445876.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445877.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445877.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445877.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445877.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d6a0] >[445877.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d6a0] width 1280 pitch 5120 (/4 1280) >[445877.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465b260] >[445877.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465b260] width 1280 pitch 5120 (/4 1280) >[445877.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607550] >[445877.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607550] width 1280 pitch 5120 (/4 1280) >[445877.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445877.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445877.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607550] >[445877.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607550] width 1280 pitch 5120 (/4 1280) >[445877.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[445877.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[445877.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445877.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445877.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d6a0] >[445877.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d6a0] width 1280 pitch 5120 (/4 1280) >[445877.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445877.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445877.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d6a0] >[445877.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d6a0] width 1280 pitch 5120 (/4 1280) >[445877.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[445877.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[445877.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428d6a0] >[445877.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428d6a0] width 1280 pitch 5120 (/4 1280) >[445879.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cf840] >[445879.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cf840] width 1280 pitch 5120 (/4 1280) >[445883.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x432df10] >[445883.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x432df10] width 1280 pitch 5120 (/4 1280) >[445889.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cab20] >[445889.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cab20] width 1280 pitch 5120 (/4 1280) >[445889.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x432e850] >[445889.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x432e850] width 1280 pitch 5120 (/4 1280) >[445889.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cab20] >[445889.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cab20] width 1280 pitch 5120 (/4 1280) >[445889.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e5a00] >[445889.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e5a00] width 1280 pitch 5120 (/4 1280) >[445889.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46dbd00] >[445889.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46dbd00] width 1280 pitch 5120 (/4 1280) >[445890.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e5a00] >[445890.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e5a00] width 1280 pitch 5120 (/4 1280) >[445890.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46dbd00] >[445890.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46dbd00] width 1280 pitch 5120 (/4 1280) >[445890.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cab20] >[445890.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cab20] width 1280 pitch 5120 (/4 1280) >[445890.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45da730] >[445890.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45da730] width 1280 pitch 5120 (/4 1280) >[445890.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e5a00] >[445890.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e5a00] width 1280 pitch 5120 (/4 1280) >[445890.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45da730] >[445890.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45da730] width 1280 pitch 5120 (/4 1280) >[445968.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d010] >[445968.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d010] width 1280 pitch 5120 (/4 1280) >[445968.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ee00] >[445968.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ee00] width 1280 pitch 5120 (/4 1280) >[445980.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36121a0] >[445980.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36121a0] width 1280 pitch 5120 (/4 1280) >[445980.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d3c60] >[445980.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d3c60] width 1280 pitch 5120 (/4 1280) >[445980.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36121a0] >[445981.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36121a0] width 1280 pitch 5120 (/4 1280) >[445981.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d3c60] >[445981.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d3c60] width 1280 pitch 5120 (/4 1280) >[445981.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36121a0] >[445981.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36121a0] width 1280 pitch 5120 (/4 1280) >[445981.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d3c60] >[445981.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d3c60] width 1280 pitch 5120 (/4 1280) >[445982.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36121a0] >[445982.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36121a0] width 1280 pitch 5120 (/4 1280) >[445983.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d3c60] >[445983.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d3c60] width 1280 pitch 5120 (/4 1280) >[445983.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36121a0] >[445984.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36121a0] width 1280 pitch 5120 (/4 1280) >[445984.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718a40] >[445984.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718a40] width 1280 pitch 5120 (/4 1280) >[445984.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4126ff0] >[445984.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4126ff0] width 1280 pitch 5120 (/4 1280) >[445984.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35de170] >[445984.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35de170] width 1280 pitch 5120 (/4 1280) >[445984.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[445984.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[446164.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45cdcf0] >[446164.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45cdcf0] width 1280 pitch 5120 (/4 1280) >[446164.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d3c60] >[446164.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d3c60] width 1280 pitch 5120 (/4 1280) >[446447.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3269b40] >[446447.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3269b40] width 1280 pitch 5120 (/4 1280) >[446447.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3269b40] >[446447.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3269b40] width 1280 pitch 5120 (/4 1280) >[446453.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d1b60] >[446453.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d1b60] width 1280 pitch 5120 (/4 1280) >[446453.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d16a0] >[446453.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d16a0] width 1280 pitch 5120 (/4 1280) >[446458.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45da280] >[446458.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45da280] width 1280 pitch 5120 (/4 1280) >[446458.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326d080] >[446458.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326d080] width 1280 pitch 5120 (/4 1280) >[446673.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3f80] >[446673.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3f80] width 1280 pitch 5120 (/4 1280) >[446673.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35eb540] >[446673.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35eb540] width 1280 pitch 5120 (/4 1280) >[446826.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f9a20] >[446826.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f9a20] width 1280 pitch 5120 (/4 1280) >[446826.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fa500] >[446826.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fa500] width 1280 pitch 5120 (/4 1280) >[446871.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f76a0] >[446871.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f76a0] width 1280 pitch 5120 (/4 1280) >[446871.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35edb20] >[446871.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35edb20] width 1280 pitch 5120 (/4 1280) >[447002.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326e400] >[447002.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326e400] width 1280 pitch 5120 (/4 1280) >[447002.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32569c0] >[447002.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32569c0] width 1280 pitch 5120 (/4 1280) >[447081.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[447081.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[447081.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8c80] >[447081.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8c80] width 1280 pitch 5120 (/4 1280) >[447151.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447151.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447151.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8c80] >[447151.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8c80] width 1280 pitch 5120 (/4 1280) >[447155.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447155.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447155.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8c80] >[447156.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8c80] width 1280 pitch 5120 (/4 1280) >[447156.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447156.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447156.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8c80] >[447156.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8c80] width 1280 pitch 5120 (/4 1280) >[447157.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47511b0] >[447157.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47511b0] width 1280 pitch 5120 (/4 1280) >[447157.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a170] >[447157.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a170] width 1280 pitch 5120 (/4 1280) >[447157.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447157.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447157.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447158.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447158.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447158.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447158.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447159.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447159.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447159.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261ab0] >[447159.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261ab0] width 1280 pitch 5120 (/4 1280) >[447159.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447159.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447159.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8c80] >[447159.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8c80] width 1280 pitch 5120 (/4 1280) >[447159.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447159.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447160.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447160.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447160.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4710a20] >[447160.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4710a20] width 1280 pitch 5120 (/4 1280) >[447161.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447161.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d180] >[447161.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d180] width 1280 pitch 5120 (/4 1280) >[447161.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447161.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447166.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ce60] >[447166.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ce60] width 1280 pitch 5120 (/4 1280) >[447197.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447197.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447197.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447197.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447197.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447197.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447198.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447198.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447198.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447198.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447198.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447198.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447198.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447198.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447199.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447199.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447199.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a170] >[447199.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a170] width 1280 pitch 5120 (/4 1280) >[447199.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447199.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447199.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a170] >[447199.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a170] width 1280 pitch 5120 (/4 1280) >[447199.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d4630] >[447199.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d4630] width 1280 pitch 5120 (/4 1280) >[447200.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447200.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447200.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47511b0] >[447200.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47511b0] width 1280 pitch 5120 (/4 1280) >[447201.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447201.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447201.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47511b0] >[447201.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47511b0] width 1280 pitch 5120 (/4 1280) >[447201.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447201.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447201.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47511b0] >[447201.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47511b0] width 1280 pitch 5120 (/4 1280) >[447202.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447202.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447202.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447202.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447202.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447202.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447202.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608830] >[447202.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608830] width 1280 pitch 5120 (/4 1280) >[447202.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447202.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447203.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6330] >[447203.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6330] width 1280 pitch 5120 (/4 1280) >[447203.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a170] >[447204.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a170] width 1280 pitch 5120 (/4 1280) >[447204.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308b870] >[447204.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308b870] width 1280 pitch 5120 (/4 1280) >[447204.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bad90] >[447204.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bad90] width 1280 pitch 5120 (/4 1280) >[447204.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261d90] >[447204.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261d90] width 1280 pitch 5120 (/4 1280) >[447250.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e0d0] >[447250.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e0d0] width 1280 pitch 5120 (/4 1280) >[447250.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee470] >[447250.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee470] width 1280 pitch 5120 (/4 1280) >[447449.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bfd30] >[447450.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bfd30] width 1280 pitch 5120 (/4 1280) >[447450.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447450.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447450.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447450.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447450.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bfd30] >[447451.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bfd30] width 1280 pitch 5120 (/4 1280) >[447451.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447451.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447451.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447451.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb710] >[447451.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb710] width 1280 pitch 5120 (/4 1280) >[447452.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447452.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447452.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214530] >[447452.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214530] width 1280 pitch 5120 (/4 1280) >[447452.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447452.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447452.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447452.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447452.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447452.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447452.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447452.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447452.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447452.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447452.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447452.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447452.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bfd30] >[447453.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bfd30] width 1280 pitch 5120 (/4 1280) >[447453.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214530] >[447453.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214530] width 1280 pitch 5120 (/4 1280) >[447453.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bfd30] >[447453.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bfd30] width 1280 pitch 5120 (/4 1280) >[447453.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447453.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4214620] >[447453.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4214620] width 1280 pitch 5120 (/4 1280) >[447453.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46eb960] >[447453.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46eb960] width 1280 pitch 5120 (/4 1280) >[447529.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d0be0] >[447529.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d0be0] width 1280 pitch 5120 (/4 1280) >[447529.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d0be0] >[447529.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d0be0] width 1280 pitch 5120 (/4 1280) >[447529.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d0be0] >[447529.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d0be0] width 1280 pitch 5120 (/4 1280) >[447529.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d5c10] >[447529.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d5c10] width 1280 pitch 5120 (/4 1280) >[447576.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46da290] >[447576.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46da290] width 1280 pitch 5120 (/4 1280) >[447602.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46da290] >[447602.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46da290] width 1280 pitch 5120 (/4 1280) >[447602.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257780] >[447602.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257780] width 1280 pitch 5120 (/4 1280) >[447602.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46da290] >[447602.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46da290] width 1280 pitch 5120 (/4 1280) >[447602.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257780] >[447602.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257780] width 1280 pitch 5120 (/4 1280) >[447602.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46da290] >[447602.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46da290] width 1280 pitch 5120 (/4 1280) >[447603.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d4470] >[447603.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d4470] width 1280 pitch 5120 (/4 1280) >[447603.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d4470] >[447603.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d4470] width 1280 pitch 5120 (/4 1280) >[447603.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x432d890] >[447603.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x432d890] width 1280 pitch 5120 (/4 1280) >[447603.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebbbe0] >[447603.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebbbe0] width 1280 pitch 5120 (/4 1280) >[447603.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46da290] >[447603.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46da290] width 1280 pitch 5120 (/4 1280) >[447646.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebc100] >[447646.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebc100] width 1280 pitch 5120 (/4 1280) >[447675.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x432f2c0] >[447675.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x432f2c0] width 1280 pitch 5120 (/4 1280) >[447679.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c5c0] >[447679.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c5c0] width 1280 pitch 5120 (/4 1280) >[447680.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35db6d0] >[447680.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35db6d0] width 1280 pitch 5120 (/4 1280) >[447770.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45dfcf0] >[447770.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45dfcf0] width 1280 pitch 5120 (/4 1280) >[447770.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f9040] >[447770.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f9040] width 1280 pitch 5120 (/4 1280) >[447777.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ccab0] >[447777.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ccab0] width 1280 pitch 5120 (/4 1280) >[447827.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45cc430] >[447827.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45cc430] width 1280 pitch 5120 (/4 1280) >[447828.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e9040] >[447828.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e9040] width 1280 pitch 5120 (/4 1280) >[447828.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e9040] >[447828.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e9040] width 1280 pitch 5120 (/4 1280) >[447828.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45cabb0] >[447828.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45cabb0] width 1280 pitch 5120 (/4 1280) >[447938.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45cabb0] >[447938.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45cabb0] width 1280 pitch 5120 (/4 1280) >[447939.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e9040] >[447939.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e9040] width 1280 pitch 5120 (/4 1280) >[447939.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325dcc0] >[447939.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325dcc0] width 1280 pitch 5120 (/4 1280) >[447939.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43284a0] >[447939.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43284a0] width 1280 pitch 5120 (/4 1280) >[448006.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f8030] >[448006.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f8030] width 1280 pitch 5120 (/4 1280) >[448006.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325cf20] >[448006.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325cf20] width 1280 pitch 5120 (/4 1280) >[448060.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3272050] >[448060.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3272050] width 1280 pitch 5120 (/4 1280) >[448060.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb910] >[448060.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb910] width 1280 pitch 5120 (/4 1280) >[448176.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f45d70] >[448176.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f45d70] width 1280 pitch 5120 (/4 1280) >[448176.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ebd60] >[448176.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ebd60] width 1280 pitch 5120 (/4 1280) >[448205.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3272050] >[448205.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3272050] width 1280 pitch 5120 (/4 1280) >[448205.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e4d20] >[448205.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e4d20] width 1280 pitch 5120 (/4 1280) >[448288.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c2fa0] >[448288.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c2fa0] width 1280 pitch 5120 (/4 1280) >[448288.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c2fa0] >[448288.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c2fa0] width 1280 pitch 5120 (/4 1280) >[448317.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e7020] >[448317.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e7020] width 1280 pitch 5120 (/4 1280) >[448317.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c2fa0] >[448317.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c2fa0] width 1280 pitch 5120 (/4 1280) >[448394.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fe410] >[448394.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fe410] width 1280 pitch 5120 (/4 1280) >[448395.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7b9f0] >[448395.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7b9f0] width 1280 pitch 5120 (/4 1280) >[448486.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325f1b0] >[448486.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325f1b0] width 1280 pitch 5120 (/4 1280) >[448486.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f8a60] >[448486.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f8a60] width 1280 pitch 5120 (/4 1280) >[448606.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ca070] >[448606.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ca070] width 1280 pitch 5120 (/4 1280) >[448606.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43280c0] >[448606.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43280c0] width 1280 pitch 5120 (/4 1280) >[448765.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43280c0] >[448765.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43280c0] width 1280 pitch 5120 (/4 1280) >[448765.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cc5f0] >[448765.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cc5f0] width 1280 pitch 5120 (/4 1280) >[448956.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ce5c0] >[448956.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ce5c0] width 1280 pitch 5120 (/4 1280) >[449025.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449025.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449025.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449025.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449026.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449026.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449060.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449060.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449070.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6860] >[449070.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6860] width 1280 pitch 5120 (/4 1280) >[449071.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449071.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449071.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6860] >[449071.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6860] width 1280 pitch 5120 (/4 1280) >[449071.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449071.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449071.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6860] >[449071.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6860] width 1280 pitch 5120 (/4 1280) >[449072.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449072.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449072.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6860] >[449072.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6860] width 1280 pitch 5120 (/4 1280) >[449072.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231cf0] >[449072.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231cf0] width 1280 pitch 5120 (/4 1280) >[449072.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233130] >[449072.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233130] width 1280 pitch 5120 (/4 1280) >[449072.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231cf0] >[449072.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231cf0] width 1280 pitch 5120 (/4 1280) >[449074.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449074.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449074.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449074.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449074.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449074.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449074.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449074.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449074.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449074.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449075.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449075.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449075.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449075.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449075.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449075.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449075.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449075.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449075.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449075.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449080.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449080.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449080.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449080.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449080.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449080.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449080.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449080.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449080.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9fe0] >[449080.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9fe0] width 1280 pitch 5120 (/4 1280) >[449081.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449081.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449081.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449082.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449082.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bec10] >[449082.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bec10] width 1280 pitch 5120 (/4 1280) >[449082.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ca0a0] >[449082.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ca0a0] width 1280 pitch 5120 (/4 1280) >[449082.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237550] >[449082.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237550] width 1280 pitch 5120 (/4 1280) >[449106.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9eb0] >[449106.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9eb0] width 1280 pitch 5120 (/4 1280) >[449106.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1160] >[449106.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1160] width 1280 pitch 5120 (/4 1280) >[449132.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9de0] >[449132.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9de0] width 1280 pitch 5120 (/4 1280) >[449157.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237c90] >[449157.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237c90] width 1280 pitch 5120 (/4 1280) >[449157.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237c90] >[449157.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237c90] width 1280 pitch 5120 (/4 1280) >[449162.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449162.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449182.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aac20] >[449182.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aac20] width 1280 pitch 5120 (/4 1280) >[449182.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aac20] >[449182.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aac20] width 1280 pitch 5120 (/4 1280) >[449182.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237c90] >[449182.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237c90] width 1280 pitch 5120 (/4 1280) >[449182.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd0e0] >[449182.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd0e0] width 1280 pitch 5120 (/4 1280) >[449221.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7da0] >[449221.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7da0] width 1280 pitch 5120 (/4 1280) >[449221.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a79b0] >[449221.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a79b0] width 1280 pitch 5120 (/4 1280) >[449238.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7400] >[449238.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7400] width 1280 pitch 5120 (/4 1280) >[449241.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c1c0] >[449241.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c1c0] width 1280 pitch 5120 (/4 1280) >[449242.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241c50] >[449242.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241c50] width 1280 pitch 5120 (/4 1280) >[449242.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32424c0] >[449242.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32424c0] width 1280 pitch 5120 (/4 1280) >[449242.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241c50] >[449242.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241c50] width 1280 pitch 5120 (/4 1280) >[449244.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c1c0] >[449244.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c1c0] width 1280 pitch 5120 (/4 1280) >[449244.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3245f60] >[449244.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3245f60] width 1280 pitch 5120 (/4 1280) >[449402.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32533a0] >[449402.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32533a0] width 1280 pitch 5120 (/4 1280) >[449402.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f9070] >[449402.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f9070] width 1280 pitch 5120 (/4 1280) >[449407.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449407.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449407.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea980] >[449407.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea980] width 1280 pitch 5120 (/4 1280) >[449407.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449407.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449408.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aadc0] >[449408.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aadc0] width 1280 pitch 5120 (/4 1280) >[449414.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f9070] >[449414.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f9070] width 1280 pitch 5120 (/4 1280) >[449414.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449414.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449414.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea980] >[449414.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea980] width 1280 pitch 5120 (/4 1280) >[449414.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449414.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449419.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3246990] >[449419.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3246990] width 1280 pitch 5120 (/4 1280) >[449420.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323f490] >[449420.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323f490] width 1280 pitch 5120 (/4 1280) >[449420.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449420.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449420.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449421.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449629.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326cb20] >[449629.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326cb20] width 1280 pitch 5120 (/4 1280) >[449629.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449629.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449629.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449629.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449629.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449629.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449629.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326cb20] >[449629.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326cb20] width 1280 pitch 5120 (/4 1280) >[449629.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449629.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449629.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326cb20] >[449629.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326cb20] width 1280 pitch 5120 (/4 1280) >[449630.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449630.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449630.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326cb20] >[449630.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326cb20] width 1280 pitch 5120 (/4 1280) >[449631.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449631.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449631.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449631.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449632.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449632.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449632.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea980] >[449632.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea980] width 1280 pitch 5120 (/4 1280) >[449632.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329cab0] >[449632.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329cab0] width 1280 pitch 5120 (/4 1280) >[449632.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea980] >[449632.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea980] width 1280 pitch 5120 (/4 1280) >[449632.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449632.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449633.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449633.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449633.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449633.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449634.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449634.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449634.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449634.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449634.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449634.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449635.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449635.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449635.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449635.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449635.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241270] >[449635.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241270] width 1280 pitch 5120 (/4 1280) >[449635.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449635.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449636.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431b900] >[449636.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431b900] width 1280 pitch 5120 (/4 1280) >[449636.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449636.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449636.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449636.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449637.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449637.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449638.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449638.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449638.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449638.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449638.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449638.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449638.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449638.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449638.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a78e0] >[449638.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a78e0] width 1280 pitch 5120 (/4 1280) >[449639.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449639.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449640.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c1c0] >[449640.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c1c0] width 1280 pitch 5120 (/4 1280) >[449640.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449640.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449640.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c1c0] >[449640.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c1c0] width 1280 pitch 5120 (/4 1280) >[449640.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326c1c0] >[449641.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326c1c0] width 1280 pitch 5120 (/4 1280) >[449641.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431b900] >[449641.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431b900] width 1280 pitch 5120 (/4 1280) >[449641.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449641.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449641.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431b900] >[449641.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431b900] width 1280 pitch 5120 (/4 1280) >[449642.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449642.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449642.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431b900] >[449642.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431b900] width 1280 pitch 5120 (/4 1280) >[449642.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a7290] >[449642.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a7290] width 1280 pitch 5120 (/4 1280) >[449642.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x431b900] >[449642.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x431b900] width 1280 pitch 5120 (/4 1280) >[449681.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449681.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449681.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449681.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449681.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449681.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449681.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449681.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449681.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449681.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449681.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4470e40] >[449681.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4470e40] width 1280 pitch 5120 (/4 1280) >[449681.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fd970] >[449681.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fd970] width 1280 pitch 5120 (/4 1280) >[449764.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ab1f0] >[449764.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ab1f0] width 1280 pitch 5120 (/4 1280) >[449764.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ab1f0] >[449764.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ab1f0] width 1280 pitch 5120 (/4 1280) >[449769.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449769.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449769.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aba40] >[449769.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aba40] width 1280 pitch 5120 (/4 1280) >[449769.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e4900] >[449769.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e4900] width 1280 pitch 5120 (/4 1280) >[449769.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4122190] >[449769.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4122190] width 1280 pitch 5120 (/4 1280) >[449786.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f92d0] >[449786.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f92d0] width 1280 pitch 5120 (/4 1280) >[449787.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a9170] >[449787.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a9170] width 1280 pitch 5120 (/4 1280) >[449801.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e99a0] >[449801.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e99a0] width 1280 pitch 5120 (/4 1280) >[449803.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e99a0] >[449803.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e99a0] width 1280 pitch 5120 (/4 1280) >[449803.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5c40] >[449803.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5c40] width 1280 pitch 5120 (/4 1280) >[449803.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f92d0] >[449803.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f92d0] width 1280 pitch 5120 (/4 1280) >[449846.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f92d0] >[449846.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f92d0] width 1280 pitch 5120 (/4 1280) >[449847.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e99a0] >[449847.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e99a0] width 1280 pitch 5120 (/4 1280) >[449890.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7e50] >[449890.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7e50] width 1280 pitch 5120 (/4 1280) >[449890.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f9250] >[449890.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f9250] width 1280 pitch 5120 (/4 1280) >[449955.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4699440] >[449955.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4699440] width 1280 pitch 5120 (/4 1280) >[450052.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1c00] >[450052.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1c00] width 1280 pitch 5120 (/4 1280) >[450052.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32919d0] >[450052.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32919d0] width 1280 pitch 5120 (/4 1280) >[450243.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450243.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450246.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450246.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450246.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450246.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450246.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450246.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450246.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450246.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450246.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450247.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450247.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450247.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450247.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450247.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450247.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450249.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450249.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450249.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0080] >[450249.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0080] width 1280 pitch 5120 (/4 1280) >[450250.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450250.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450250.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450250.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450250.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450250.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450266.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450266.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450266.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450266.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450266.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450266.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450266.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450266.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450266.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450266.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450267.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0080] >[450267.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0080] width 1280 pitch 5120 (/4 1280) >[450267.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450267.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450267.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450267.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450267.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450267.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450267.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450267.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450268.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450268.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450269.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450269.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450269.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450269.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450269.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450269.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450278.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450278.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450299.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450299.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450300.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450300.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450300.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4409990] >[450300.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4409990] width 1280 pitch 5120 (/4 1280) >[450300.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450300.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450301.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4409990] >[450301.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4409990] width 1280 pitch 5120 (/4 1280) >[450303.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450303.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450303.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450303.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450303.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450303.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450306.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450307.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450307.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450307.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450307.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450307.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450309.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4409990] >[450309.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4409990] width 1280 pitch 5120 (/4 1280) >[450309.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450309.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450309.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450309.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450309.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450309.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450310.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450310.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450310.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450310.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450362.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450362.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450362.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450362.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450362.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450362.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450362.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450362.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450362.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450362.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450363.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450363.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450363.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450363.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450363.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf030] >[450363.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf030] width 1280 pitch 5120 (/4 1280) >[450366.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450366.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450366.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450366.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450366.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450366.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450366.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450366.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450367.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450367.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450369.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ae050] >[450369.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ae050] width 1280 pitch 5120 (/4 1280) >[450369.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450369.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450369.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28ae050] >[450369.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28ae050] width 1280 pitch 5120 (/4 1280) >[450371.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450371.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450374.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450374.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450374.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450374.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450374.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450374.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450375.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450375.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450381.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450381.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450382.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3249590] >[450382.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3249590] width 1280 pitch 5120 (/4 1280) >[450382.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450382.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450382.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450382.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450383.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450383.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450383.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450383.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450383.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450383.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450383.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328410] >[450383.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328410] width 1280 pitch 5120 (/4 1280) >[450384.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450384.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450384.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3249590] >[450384.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3249590] width 1280 pitch 5120 (/4 1280) >[450384.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0e80] >[450384.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0e80] width 1280 pitch 5120 (/4 1280) >[450384.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450384.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450387.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450387.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450388.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0e80] >[450388.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0e80] width 1280 pitch 5120 (/4 1280) >[450388.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327fa80] >[450388.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327fa80] width 1280 pitch 5120 (/4 1280) >[450388.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32990d0] >[450388.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32990d0] width 1280 pitch 5120 (/4 1280) >[450389.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450389.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450389.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32912e0] >[450389.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32912e0] width 1280 pitch 5120 (/4 1280) >[450389.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450389.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450389.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b150] >[450389.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b150] width 1280 pitch 5120 (/4 1280) >[450389.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bd640] >[450389.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bd640] width 1280 pitch 5120 (/4 1280) >[450390.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b150] >[450390.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b150] width 1280 pitch 5120 (/4 1280) >[450390.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450390.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450390.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b150] >[450390.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b150] width 1280 pitch 5120 (/4 1280) >[450391.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d5950] >[450391.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d5950] width 1280 pitch 5120 (/4 1280) >[450392.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dbd0] >[450392.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dbd0] width 1280 pitch 5120 (/4 1280) >[450392.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251330] >[450392.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251330] width 1280 pitch 5120 (/4 1280) >[450416.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450416.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450420.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3280f80] >[450420.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3280f80] width 1280 pitch 5120 (/4 1280) >[450420.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3386ba0] >[450420.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3386ba0] width 1280 pitch 5120 (/4 1280) >[450422.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bc0d0] >[450422.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bc0d0] width 1280 pitch 5120 (/4 1280) >[450711.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3342180] >[450711.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3342180] width 1280 pitch 5120 (/4 1280) >[450732.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331e960] >[450733.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331e960] width 1280 pitch 5120 (/4 1280) >[450744.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe8480] >[450744.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe8480] width 1280 pitch 5120 (/4 1280) >[450761.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b6c0] >[450761.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b6c0] width 1280 pitch 5120 (/4 1280) >[450761.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe8480] >[450761.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe8480] width 1280 pitch 5120 (/4 1280) >[450769.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b6c0] >[450769.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b6c0] width 1280 pitch 5120 (/4 1280) >[450875.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3364470] >[450875.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3364470] width 1280 pitch 5120 (/4 1280) >[450876.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367750] >[450876.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367750] width 1280 pitch 5120 (/4 1280) >[450880.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367750] >[450880.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367750] width 1280 pitch 5120 (/4 1280) >[451073.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3376540] >[451073.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3376540] width 1280 pitch 5120 (/4 1280) >[451073.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f9f60] >[451073.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f9f60] width 1280 pitch 5120 (/4 1280) >[451073.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f9f60] >[451073.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f9f60] width 1280 pitch 5120 (/4 1280) >[451073.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fc40] >[451073.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fc40] width 1280 pitch 5120 (/4 1280) >[451073.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477e0d0] >[451073.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477e0d0] width 1280 pitch 5120 (/4 1280) >[451122.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe8390] >[451122.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe8390] width 1280 pitch 5120 (/4 1280) >[451122.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336f320] >[451122.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336f320] width 1280 pitch 5120 (/4 1280) >[451230.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3376540] >[451230.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3376540] width 1280 pitch 5120 (/4 1280) >[451231.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451231.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451231.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301080] >[451231.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301080] width 1280 pitch 5120 (/4 1280) >[451231.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451231.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451233.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3376540] >[451233.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3376540] width 1280 pitch 5120 (/4 1280) >[451234.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451234.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451234.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337ce50] >[451234.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337ce50] width 1280 pitch 5120 (/4 1280) >[451234.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451234.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451245.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337ce50] >[451245.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337ce50] width 1280 pitch 5120 (/4 1280) >[451245.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33613c0] >[451245.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33613c0] width 1280 pitch 5120 (/4 1280) >[451260.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33368b0] >[451260.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33368b0] width 1280 pitch 5120 (/4 1280) >[451260.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337ce50] >[451260.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337ce50] width 1280 pitch 5120 (/4 1280) >[451261.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301080] >[451261.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301080] width 1280 pitch 5120 (/4 1280) >[451261.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ea500] >[451261.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ea500] width 1280 pitch 5120 (/4 1280) >[451261.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336f320] >[451261.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336f320] width 1280 pitch 5120 (/4 1280) >[451261.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ea500] >[451261.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ea500] width 1280 pitch 5120 (/4 1280) >[451261.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336f320] >[451261.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336f320] width 1280 pitch 5120 (/4 1280) >[451262.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33613c0] >[451262.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33613c0] width 1280 pitch 5120 (/4 1280) >[451262.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33368b0] >[451262.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33368b0] width 1280 pitch 5120 (/4 1280) >[451262.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3376540] >[451262.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3376540] width 1280 pitch 5120 (/4 1280) >[451262.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451262.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451262.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33368b0] >[451262.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33368b0] width 1280 pitch 5120 (/4 1280) >[451262.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33acfa0] >[451262.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33acfa0] width 1280 pitch 5120 (/4 1280) >[451559.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33672d0] >[451559.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33672d0] width 1280 pitch 5120 (/4 1280) >[451581.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33156d0] >[451581.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33156d0] width 1280 pitch 5120 (/4 1280) >[451582.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f6b80] >[451582.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f6b80] width 1280 pitch 5120 (/4 1280) >[451600.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337aff0] >[451600.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337aff0] width 1280 pitch 5120 (/4 1280) >[451600.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46c29f0] >[451600.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46c29f0] width 1280 pitch 5120 (/4 1280) >[451629.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4980] >[451629.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4980] width 1280 pitch 5120 (/4 1280) >[451645.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4980] >[451645.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4980] width 1280 pitch 5120 (/4 1280) >[451647.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338eca0] >[451647.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338eca0] width 1280 pitch 5120 (/4 1280) >[451663.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338eca0] >[451663.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338eca0] width 1280 pitch 5120 (/4 1280) >[451952.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fd130] >[451952.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fd130] width 1280 pitch 5120 (/4 1280) >[451953.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34018c0] >[451953.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34018c0] width 1280 pitch 5120 (/4 1280) >[451953.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33895b0] >[451953.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33895b0] width 1280 pitch 5120 (/4 1280) >[451953.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdcf0] >[451953.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdcf0] width 1280 pitch 5120 (/4 1280) >[451957.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fcdd0] >[451957.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fcdd0] width 1280 pitch 5120 (/4 1280) >[451958.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34018c0] >[451958.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34018c0] width 1280 pitch 5120 (/4 1280) >[451958.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34018c0] >[451958.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34018c0] width 1280 pitch 5120 (/4 1280) >[452084.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33102d0] >[452084.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33102d0] width 1280 pitch 5120 (/4 1280) >[452084.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33102d0] >[452084.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33102d0] width 1280 pitch 5120 (/4 1280) >[452149.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359df0] >[452149.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359df0] width 1280 pitch 5120 (/4 1280) >[452149.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359df0] >[452149.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359df0] width 1280 pitch 5120 (/4 1280) >[452166.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db070] >[452166.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db070] width 1280 pitch 5120 (/4 1280) >[452166.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359890] >[452166.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359890] width 1280 pitch 5120 (/4 1280) >[452167.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406d50] >[452167.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406d50] width 1280 pitch 5120 (/4 1280) >[452185.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33912c0] >[452185.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33912c0] width 1280 pitch 5120 (/4 1280) >[452185.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ba440] >[452185.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ba440] width 1280 pitch 5120 (/4 1280) >[452186.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33495a0] >[452186.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33495a0] width 1280 pitch 5120 (/4 1280) >[452186.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a4f10] >[452186.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a4f10] width 1280 pitch 5120 (/4 1280) >[452186.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a4f10] >[452186.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a4f10] width 1280 pitch 5120 (/4 1280) >[452186.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4406cc0] >[452186.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4406cc0] width 1280 pitch 5120 (/4 1280) >[452188.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406d50] >[452189.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406d50] width 1280 pitch 5120 (/4 1280) >[452189.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dd40] >[452189.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dd40] width 1280 pitch 5120 (/4 1280) >[452189.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3e60] >[452189.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3e60] width 1280 pitch 5120 (/4 1280) >[452189.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406d50] >[452189.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406d50] width 1280 pitch 5120 (/4 1280) >[452190.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06f0] >[452190.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06f0] width 1280 pitch 5120 (/4 1280) >[452201.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d6cc0] >[452201.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d6cc0] width 1280 pitch 5120 (/4 1280) >[452229.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3432490] >[452229.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3432490] width 1280 pitch 5120 (/4 1280) >[452229.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db760] >[452229.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db760] width 1280 pitch 5120 (/4 1280) >[452239.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e18a0] >[452239.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e18a0] width 1280 pitch 5120 (/4 1280) >[452239.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34319f0] >[452239.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34319f0] width 1280 pitch 5120 (/4 1280) >[452259.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e6bb0] >[452259.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e6bb0] width 1280 pitch 5120 (/4 1280) >[452259.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3271b90] >[452259.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3271b90] width 1280 pitch 5120 (/4 1280) >[452344.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ed400] >[452344.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ed400] width 1280 pitch 5120 (/4 1280) >[452344.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357420] >[452344.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357420] width 1280 pitch 5120 (/4 1280) >[452471.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da640] >[452471.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da640] width 1280 pitch 5120 (/4 1280) >[452471.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34107d0] >[452471.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34107d0] width 1280 pitch 5120 (/4 1280) >[452477.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34104f0] >[452477.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34104f0] width 1280 pitch 5120 (/4 1280) >[452477.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34104f0] >[452477.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34104f0] width 1280 pitch 5120 (/4 1280) >[452486.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340c4f0] >[452486.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340c4f0] width 1280 pitch 5120 (/4 1280) >[452486.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e6610] >[452486.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e6610] width 1280 pitch 5120 (/4 1280) >[452492.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3412c20] >[452492.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3412c20] width 1280 pitch 5120 (/4 1280) >[452494.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3412c20] >[452494.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3412c20] width 1280 pitch 5120 (/4 1280) >[452500.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33be570] >[452500.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33be570] width 1280 pitch 5120 (/4 1280) >[452500.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33be570] >[452500.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33be570] width 1280 pitch 5120 (/4 1280) >[452503.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334fa90] >[452503.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334fa90] width 1280 pitch 5120 (/4 1280) >[452503.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340c4f0] >[452503.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340c4f0] width 1280 pitch 5120 (/4 1280) >[452579.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3401d00] >[452579.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3401d00] width 1280 pitch 5120 (/4 1280) >[452579.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eabd0] >[452579.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eabd0] width 1280 pitch 5120 (/4 1280) >[452596.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3401e70] >[452596.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3401e70] width 1280 pitch 5120 (/4 1280) >[452596.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1210] >[452596.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1210] width 1280 pitch 5120 (/4 1280) >[452673.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3412c20] >[452673.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3412c20] width 1280 pitch 5120 (/4 1280) >[452695.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3441f90] >[452695.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3441f90] width 1280 pitch 5120 (/4 1280) >[452697.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343d4a0] >[452697.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343d4a0] width 1280 pitch 5120 (/4 1280) >[452781.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de840] >[452781.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de840] width 1280 pitch 5120 (/4 1280) >[452781.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33585f0] >[452781.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33585f0] width 1280 pitch 5120 (/4 1280) >[452819.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447230] >[452819.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447230] width 1280 pitch 5120 (/4 1280) >[452819.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447230] >[452819.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447230] width 1280 pitch 5120 (/4 1280) >[452944.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346b730] >[452944.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346b730] width 1280 pitch 5120 (/4 1280) >[452944.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ba80] >[452944.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ba80] width 1280 pitch 5120 (/4 1280) >[452974.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346e730] >[452974.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346e730] width 1280 pitch 5120 (/4 1280) >[452974.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346e730] >[452974.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346e730] width 1280 pitch 5120 (/4 1280) >[452985.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3380830] >[452985.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3380830] width 1280 pitch 5120 (/4 1280) >[452985.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346ea00] >[452985.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346ea00] width 1280 pitch 5120 (/4 1280) >[452999.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33194d0] >[452999.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33194d0] width 1280 pitch 5120 (/4 1280) >[452999.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3380830] >[452999.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3380830] width 1280 pitch 5120 (/4 1280) >[453004.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3453e60] >[453004.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3453e60] width 1280 pitch 5120 (/4 1280) >[453004.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346ea00] >[453004.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346ea00] width 1280 pitch 5120 (/4 1280) >[453014.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3454360] >[453014.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3454360] width 1280 pitch 5120 (/4 1280) >[453014.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3453fc0] >[453014.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3453fc0] width 1280 pitch 5120 (/4 1280) >[453117.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3462a10] >[453117.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3462a10] width 1280 pitch 5120 (/4 1280) >[453117.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343bcb0] >[453117.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343bcb0] width 1280 pitch 5120 (/4 1280) >[453191.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470380] >[453191.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470380] width 1280 pitch 5120 (/4 1280) >[453191.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3463690] >[453191.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3463690] width 1280 pitch 5120 (/4 1280) >[453289.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470970] >[453289.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470970] width 1280 pitch 5120 (/4 1280) >[453289.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34707b0] >[453289.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34707b0] width 1280 pitch 5120 (/4 1280) >[453343.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34566d0] >[453343.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34566d0] width 1280 pitch 5120 (/4 1280) >[453343.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453343.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453343.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453343.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453343.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34566d0] >[453343.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34566d0] width 1280 pitch 5120 (/4 1280) >[453343.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453343.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453343.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34566d0] >[453343.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34566d0] width 1280 pitch 5120 (/4 1280) >[453343.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453343.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453343.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34566d0] >[453343.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34566d0] width 1280 pitch 5120 (/4 1280) >[453344.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453344.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453344.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34566d0] >[453344.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34566d0] width 1280 pitch 5120 (/4 1280) >[453344.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453344.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453398.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d33b0] >[453398.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d33b0] width 1280 pitch 5120 (/4 1280) >[453399.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3445230] >[453399.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3445230] width 1280 pitch 5120 (/4 1280) >[453476.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460990] >[453476.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460990] width 1280 pitch 5120 (/4 1280) >[453476.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345cfd0] >[453476.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345cfd0] width 1280 pitch 5120 (/4 1280) >[453590.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424120] >[453590.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424120] width 1280 pitch 5120 (/4 1280) >[453590.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34392e0] >[453590.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34392e0] width 1280 pitch 5120 (/4 1280) >[453664.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3436680] >[453664.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3436680] width 1280 pitch 5120 (/4 1280) >[453664.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3436680] >[453664.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3436680] width 1280 pitch 5120 (/4 1280) >[453720.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343b120] >[453720.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343b120] width 1280 pitch 5120 (/4 1280) >[453721.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3418550] >[453721.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3418550] width 1280 pitch 5120 (/4 1280) >[453722.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3455560] >[453722.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3455560] width 1280 pitch 5120 (/4 1280) >[453791.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ec8b0] >[453791.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ec8b0] width 1280 pitch 5120 (/4 1280) >[453791.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33932a0] >[453791.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33932a0] width 1280 pitch 5120 (/4 1280) >[453792.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a270] >[453792.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a270] width 1280 pitch 5120 (/4 1280) >[453792.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33932a0] >[453792.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33932a0] width 1280 pitch 5120 (/4 1280) >[453792.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3439130] >[453792.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3439130] width 1280 pitch 5120 (/4 1280) >[453792.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3439130] >[453792.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3439130] width 1280 pitch 5120 (/4 1280) >[453795.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344a830] >[453795.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344a830] width 1280 pitch 5120 (/4 1280) >[453795.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344a830] >[453795.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344a830] width 1280 pitch 5120 (/4 1280) >[453795.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3443490] >[453795.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3443490] width 1280 pitch 5120 (/4 1280) >[453795.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fd460] >[453795.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fd460] width 1280 pitch 5120 (/4 1280) >[453796.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344a830] >[453796.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344a830] width 1280 pitch 5120 (/4 1280) >[453796.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34238b0] >[453796.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34238b0] width 1280 pitch 5120 (/4 1280) >[453797.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fd460] >[453797.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fd460] width 1280 pitch 5120 (/4 1280) >[453797.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e1a0] >[453797.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e1a0] width 1280 pitch 5120 (/4 1280) >[453952.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340fa50] >[453952.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340fa50] width 1280 pitch 5120 (/4 1280) >[453955.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a6ad0] >[453955.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a6ad0] width 1280 pitch 5120 (/4 1280) >[453969.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a6ad0] >[453969.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a6ad0] width 1280 pitch 5120 (/4 1280) >[453970.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3443090] >[453970.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3443090] width 1280 pitch 5120 (/4 1280) >[453970.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3443090] >[453970.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3443090] width 1280 pitch 5120 (/4 1280) >[453972.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453972.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453973.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577160] >[453973.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577160] width 1280 pitch 5120 (/4 1280) >[453973.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[453973.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[453974.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453974.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453974.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577160] >[453974.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577160] width 1280 pitch 5120 (/4 1280) >[453974.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[453974.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[453975.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453975.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453975.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496b20] >[453975.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496b20] width 1280 pitch 5120 (/4 1280) >[453975.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3572820] >[453975.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3572820] width 1280 pitch 5120 (/4 1280) >[453975.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453975.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453975.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3572820] >[453975.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3572820] width 1280 pitch 5120 (/4 1280) >[453975.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453975.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453975.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496b20] >[453975.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496b20] width 1280 pitch 5120 (/4 1280) >[453975.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34288b0] >[453975.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34288b0] width 1280 pitch 5120 (/4 1280) >[453975.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496b20] >[453975.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496b20] width 1280 pitch 5120 (/4 1280) >[453975.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496b20] >[453975.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496b20] width 1280 pitch 5120 (/4 1280) >[453975.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[453975.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[453975.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496b20] >[453975.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496b20] width 1280 pitch 5120 (/4 1280) >[453976.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577160] >[453976.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577160] width 1280 pitch 5120 (/4 1280) >[453976.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577160] >[453976.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577160] width 1280 pitch 5120 (/4 1280) >[453976.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d36b0] >[453976.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d36b0] width 1280 pitch 5120 (/4 1280) >[453976.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[453976.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[453976.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400b00] >[453976.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400b00] width 1280 pitch 5120 (/4 1280) >[453976.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602b10] >[453976.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602b10] width 1280 pitch 5120 (/4 1280) >[453977.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453977.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453977.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453977.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453977.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4597780] >[453977.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4597780] width 1280 pitch 5120 (/4 1280) >[453977.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4537d70] >[453977.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4537d70] width 1280 pitch 5120 (/4 1280) >[453977.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4597780] >[453977.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4597780] width 1280 pitch 5120 (/4 1280) >[453977.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4537d70] >[453977.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4537d70] width 1280 pitch 5120 (/4 1280) >[453977.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4597780] >[453977.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4597780] width 1280 pitch 5120 (/4 1280) >[453977.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4537d70] >[453977.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4537d70] width 1280 pitch 5120 (/4 1280) >[453977.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4597780] >[453977.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4597780] width 1280 pitch 5120 (/4 1280) >[453977.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4537d70] >[453977.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4537d70] width 1280 pitch 5120 (/4 1280) >[453977.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4597780] >[453977.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4597780] width 1280 pitch 5120 (/4 1280) >[453979.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[453979.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[453980.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[453980.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[453980.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a14a20] >[453980.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a14a20] width 1280 pitch 5120 (/4 1280) >[453980.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[453980.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[453980.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a14a20] >[453980.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a14a20] width 1280 pitch 5120 (/4 1280) >[453980.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038c90] >[453980.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038c90] width 1280 pitch 5120 (/4 1280) >[453980.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a14a20] >[453980.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a14a20] width 1280 pitch 5120 (/4 1280) >[453980.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3020e60] >[453980.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3020e60] width 1280 pitch 5120 (/4 1280) >[453980.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a14a20] >[453980.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a14a20] width 1280 pitch 5120 (/4 1280) >[453980.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453980.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453980.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[453980.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[453980.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453980.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453980.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[453980.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[453980.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b090] >[453980.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b090] width 1280 pitch 5120 (/4 1280) >[453980.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[453980.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[453980.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b090] >[453980.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b090] width 1280 pitch 5120 (/4 1280) >[453981.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[453981.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[453981.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602b10] >[453981.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602b10] width 1280 pitch 5120 (/4 1280) >[453981.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400b00] >[453981.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400b00] width 1280 pitch 5120 (/4 1280) >[453981.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4537d70] >[453981.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4537d70] width 1280 pitch 5120 (/4 1280) >[453981.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[453981.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[453982.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x445c1b0] >[453982.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x445c1b0] width 1280 pitch 5120 (/4 1280) >[453983.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[453983.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[453986.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453986.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453987.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ac4b0] >[453987.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ac4b0] width 1280 pitch 5120 (/4 1280) >[453987.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453987.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453988.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ac4b0] >[453988.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ac4b0] width 1280 pitch 5120 (/4 1280) >[453988.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[453988.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[453988.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b090] >[453989.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b090] width 1280 pitch 5120 (/4 1280) >[453991.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ba710] >[453991.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ba710] width 1280 pitch 5120 (/4 1280) >[453991.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[453992.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[453992.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bf8b0] >[453993.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bf8b0] width 1280 pitch 5120 (/4 1280) >[453994.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45c0670] >[453994.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45c0670] width 1280 pitch 5120 (/4 1280) >[453994.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f25d0] >[453994.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f25d0] width 1280 pitch 5120 (/4 1280) >[453994.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4692cd0] >[453994.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4692cd0] width 1280 pitch 5120 (/4 1280) >[453994.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[453994.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[453999.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[453999.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[453999.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046430] >[453999.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046430] width 1280 pitch 5120 (/4 1280) >[453999.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[453999.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[453999.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046430] >[453999.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046430] width 1280 pitch 5120 (/4 1280) >[453999.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97c10] >[453999.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97c10] width 1280 pitch 5120 (/4 1280) >[453999.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046430] >[453999.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046430] width 1280 pitch 5120 (/4 1280) >[453999.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[453999.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[453999.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d846c0] >[453999.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d846c0] width 1280 pitch 5120 (/4 1280) >[454000.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[454000.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[454000.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[454000.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[454000.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e1c10] >[454000.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e1c10] width 1280 pitch 5120 (/4 1280) >[454000.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[454000.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[454000.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[454000.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[454000.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[454001.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[454001.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[454001.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[454001.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2ee90] >[454001.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2ee90] width 1280 pitch 5120 (/4 1280) >[454001.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3822b60] >[454001.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3822b60] width 1280 pitch 5120 (/4 1280) >[454003.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[454003.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[454013.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3463a70] >[454013.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3463a70] width 1280 pitch 5120 (/4 1280) >[454071.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454071.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454071.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454071.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454071.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454071.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454071.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454071.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454071.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454071.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454071.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454071.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454071.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454071.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454071.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454071.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454071.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454072.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454072.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454072.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454072.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454072.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454072.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41398c0] >[454072.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41398c0] width 1280 pitch 5120 (/4 1280) >[454072.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4473f50] >[454072.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4473f50] width 1280 pitch 5120 (/4 1280) >[454077.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a370] >[454077.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a370] width 1280 pitch 5120 (/4 1280) >[454077.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4cb0] >[454077.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4cb0] width 1280 pitch 5120 (/4 1280) >[454077.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a370] >[454077.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a370] width 1280 pitch 5120 (/4 1280) >[454077.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4cb0] >[454077.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4cb0] width 1280 pitch 5120 (/4 1280) >[454077.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a370] >[454077.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a370] width 1280 pitch 5120 (/4 1280) >[454077.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4cb0] >[454077.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4cb0] width 1280 pitch 5120 (/4 1280) >[454077.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a370] >[454077.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a370] width 1280 pitch 5120 (/4 1280) >[454077.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4cb0] >[454077.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4cb0] width 1280 pitch 5120 (/4 1280) >[454077.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8a370] >[454077.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8a370] width 1280 pitch 5120 (/4 1280) >[454077.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46f4cb0] >[454077.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46f4cb0] width 1280 pitch 5120 (/4 1280) >[454077.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[454077.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[454077.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4765b00] >[454077.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4765b00] width 1280 pitch 5120 (/4 1280) >[454077.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[454077.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[454077.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e95020] >[454078.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e95020] width 1280 pitch 5120 (/4 1280) >[454078.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40aa570] >[454078.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40aa570] width 1280 pitch 5120 (/4 1280) >[454078.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cd60] >[454078.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cd60] width 1280 pitch 5120 (/4 1280) >[454078.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47099d0] >[454078.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47099d0] width 1280 pitch 5120 (/4 1280) >[454078.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d2490] >[454078.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d2490] width 1280 pitch 5120 (/4 1280) >[454082.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4120570] >[454082.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4120570] width 1280 pitch 5120 (/4 1280) >[454083.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42192f0] >[454083.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42192f0] width 1280 pitch 5120 (/4 1280) >[454083.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12715a0] >[454083.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12715a0] width 1280 pitch 5120 (/4 1280) >[454083.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea8060] >[454083.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea8060] width 1280 pitch 5120 (/4 1280) >[454606.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d450] >[454606.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d450] width 1280 pitch 5120 (/4 1280) >[454606.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4716470] >[454606.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4716470] width 1280 pitch 5120 (/4 1280) >[454619.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[454619.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[454619.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[454619.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[454621.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d2490] >[454621.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d2490] width 1280 pitch 5120 (/4 1280) >[454621.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[454621.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[454621.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[454621.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[454621.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2593900] >[454621.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2593900] width 1280 pitch 5120 (/4 1280) >[454621.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[454621.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[454622.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2593900] >[454622.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2593900] width 1280 pitch 5120 (/4 1280) >[454622.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[454622.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[454622.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3440390] >[454622.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3440390] width 1280 pitch 5120 (/4 1280) >[454622.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[454622.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[454622.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d36b0] >[454622.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d36b0] width 1280 pitch 5120 (/4 1280) >[454622.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518a50] >[454622.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518a50] width 1280 pitch 5120 (/4 1280) >[454971.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025ce0] >[454971.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025ce0] width 1280 pitch 5120 (/4 1280) >[454971.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4cd40] >[454971.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4cd40] width 1280 pitch 5120 (/4 1280) >[454972.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025ce0] >[454972.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025ce0] width 1280 pitch 5120 (/4 1280) >[454972.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4cd40] >[454972.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4cd40] width 1280 pitch 5120 (/4 1280) >[454972.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025ce0] >[454972.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025ce0] width 1280 pitch 5120 (/4 1280) >[454972.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4cd40] >[454972.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4cd40] width 1280 pitch 5120 (/4 1280) >[454972.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[454973.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[454973.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[454973.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[454973.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e9ba0] >[454973.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e9ba0] width 1280 pitch 5120 (/4 1280) >[454974.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[454974.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[454974.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e9ba0] >[454974.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e9ba0] width 1280 pitch 5120 (/4 1280) >[454974.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[454974.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[454974.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46664d0] >[454974.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46664d0] width 1280 pitch 5120 (/4 1280) >[454975.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[454975.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[454975.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[454975.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[454975.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20abc80] >[454975.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20abc80] width 1280 pitch 5120 (/4 1280) >[454975.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[454975.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[454976.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3822b60] >[454976.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3822b60] width 1280 pitch 5120 (/4 1280) >[454976.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[454976.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[454976.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1514700] >[454976.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1514700] width 1280 pitch 5120 (/4 1280) >[454976.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[454977.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[454977.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x136c950] >[454977.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x136c950] width 1280 pitch 5120 (/4 1280) >[454977.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[454977.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[454977.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[454977.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[454977.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[454977.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[454977.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[454977.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[454977.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2467370] >[454977.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2467370] width 1280 pitch 5120 (/4 1280) >[455046.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400c000] >[455046.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400c000] width 1280 pitch 5120 (/4 1280) >[455046.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455046.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455047.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[455047.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[455047.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455047.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455047.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[455047.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[455047.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455047.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455048.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[455048.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[455048.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455048.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455048.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[455048.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[455048.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455048.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455048.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b06c0] >[455048.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b06c0] width 1280 pitch 5120 (/4 1280) >[455048.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a4b0] >[455048.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a4b0] width 1280 pitch 5120 (/4 1280) >[455050.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40218f0] >[455050.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40218f0] width 1280 pitch 5120 (/4 1280) >[455505.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455505.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455505.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[455505.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[455505.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455505.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455505.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[455505.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[455505.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455505.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455505.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[455505.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[455505.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455505.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455505.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[455505.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[455505.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[455505.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[455505.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[455505.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[455505.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[455505.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[455506.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046430] >[455506.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046430] width 1280 pitch 5120 (/4 1280) >[455506.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[455506.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[455506.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2340c20] >[455506.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2340c20] width 1280 pitch 5120 (/4 1280) >[455506.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44845a0] >[455506.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44845a0] width 1280 pitch 5120 (/4 1280) >[455506.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455506.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455506.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007d60] >[455506.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007d60] width 1280 pitch 5120 (/4 1280) >[455506.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455506.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455506.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007d60] >[455506.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007d60] width 1280 pitch 5120 (/4 1280) >[455506.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455506.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455506.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4007d60] >[455507.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4007d60] width 1280 pitch 5120 (/4 1280) >[455507.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9b1a0] >[455507.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9b1a0] width 1280 pitch 5120 (/4 1280) >[455507.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[455507.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[455507.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[455507.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[455507.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[455507.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[455507.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[455507.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[455507.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cd60] >[455507.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cd60] width 1280 pitch 5120 (/4 1280) >[455507.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[455507.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[455508.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x136c950] >[455508.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x136c950] width 1280 pitch 5120 (/4 1280) >[455508.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d2490] >[455508.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d2490] width 1280 pitch 5120 (/4 1280) >[455509.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[455509.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[455509.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455509.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455509.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455509.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455509.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455509.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455509.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455509.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455509.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455509.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455509.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455509.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455509.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455509.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455509.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455509.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455509.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455510.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455510.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455510.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455510.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455511.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f25d0] >[455511.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f25d0] width 1280 pitch 5120 (/4 1280) >[455511.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c7900] >[455511.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c7900] width 1280 pitch 5120 (/4 1280) >[455511.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4692cd0] >[455511.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4692cd0] width 1280 pitch 5120 (/4 1280) >[455511.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3849aa0] >[455511.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3849aa0] width 1280 pitch 5120 (/4 1280) >[455521.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cbb20] >[455521.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cbb20] width 1280 pitch 5120 (/4 1280) >[455521.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[455521.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[455522.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[455522.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[455522.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455522.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455522.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[455522.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[455523.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[455523.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[455523.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[455523.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[455524.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455524.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455524.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[455524.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[455524.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[455524.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[455579.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[455579.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[455579.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[455579.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[455579.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[455579.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[455579.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[455579.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[455580.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455580.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455580.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[455580.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[455580.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db910] >[455580.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db910] width 1280 pitch 5120 (/4 1280) >[455580.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[455580.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[455602.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a04f0] >[455602.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a04f0] width 1280 pitch 5120 (/4 1280) >[455602.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41fd030] >[455602.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41fd030] width 1280 pitch 5120 (/4 1280) >[455602.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343de90] >[455602.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343de90] width 1280 pitch 5120 (/4 1280) >[455602.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[455602.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[455602.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd2490] >[455602.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd2490] width 1280 pitch 5120 (/4 1280) >[455603.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dffff0] >[455603.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dffff0] width 1280 pitch 5120 (/4 1280) >[455603.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e2db0] >[455603.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e2db0] width 1280 pitch 5120 (/4 1280) >[455603.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460bf0] >[455603.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460bf0] width 1280 pitch 5120 (/4 1280) >[455604.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[455604.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[455604.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455604.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455604.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[455604.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[455604.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455604.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455604.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[455604.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[455604.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455604.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455604.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[455604.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[455604.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455604.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455604.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4454b50] >[455604.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4454b50] width 1280 pitch 5120 (/4 1280) >[455604.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455604.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455604.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455604.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455604.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455604.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455604.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455604.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455604.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455604.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[455604.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[455605.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3470420] >[455605.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3470420] width 1280 pitch 5120 (/4 1280) >[455605.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[455605.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[455605.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455605.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455606.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[455606.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[455606.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[455606.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[455611.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[455611.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[455611.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a460] >[455611.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a460] width 1280 pitch 5120 (/4 1280) >[455611.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[455611.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[455611.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a460] >[455611.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a460] width 1280 pitch 5120 (/4 1280) >[455612.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9ccf0] >[455612.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9ccf0] width 1280 pitch 5120 (/4 1280) >[455612.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45818d0] >[455612.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45818d0] width 1280 pitch 5120 (/4 1280) >[455630.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455630.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455630.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d2490] >[455630.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d2490] width 1280 pitch 5120 (/4 1280) >[455630.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[455630.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[455630.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d2490] >[455630.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d2490] width 1280 pitch 5120 (/4 1280) >[455631.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455631.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455631.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400b00] >[455631.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400b00] width 1280 pitch 5120 (/4 1280) >[455631.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413a970] >[455631.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413a970] width 1280 pitch 5120 (/4 1280) >[455631.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400b00] >[455631.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400b00] width 1280 pitch 5120 (/4 1280) >[455631.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d50] >[455631.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d50] width 1280 pitch 5120 (/4 1280) >[455631.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[455631.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[455631.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f25d0] >[455631.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f25d0] width 1280 pitch 5120 (/4 1280) >[455631.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[455631.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[455639.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[455639.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[455639.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ac4b0] >[455639.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ac4b0] width 1280 pitch 5120 (/4 1280) >[455639.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409ee40] >[455639.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409ee40] width 1280 pitch 5120 (/4 1280) >[455639.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ac4b0] >[455639.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ac4b0] width 1280 pitch 5120 (/4 1280) >[455649.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[455649.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[455665.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[455666.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[455667.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[455667.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[455667.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[455667.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[455667.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455667.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455672.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[455672.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[455672.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2340c20] >[455672.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2340c20] width 1280 pitch 5120 (/4 1280) >[455683.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c7900] >[455683.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c7900] width 1280 pitch 5120 (/4 1280) >[455683.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409ee40] >[455683.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409ee40] width 1280 pitch 5120 (/4 1280) >[455683.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4065880] >[455683.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4065880] width 1280 pitch 5120 (/4 1280) >[455683.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d720] >[455683.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d720] width 1280 pitch 5120 (/4 1280) >[455684.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455684.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455684.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[455684.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[455718.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[455718.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[455718.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdc2b0] >[455718.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdc2b0] width 1280 pitch 5120 (/4 1280) >[455718.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97c10] >[455718.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97c10] width 1280 pitch 5120 (/4 1280) >[455718.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[455718.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[455719.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[455719.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[455719.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2ee90] >[455719.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2ee90] width 1280 pitch 5120 (/4 1280) >[455719.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455719.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455719.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[455719.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[455747.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[455747.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[455747.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[455747.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[455747.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76b40] >[455747.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76b40] width 1280 pitch 5120 (/4 1280) >[455747.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cdde0] >[455747.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cdde0] width 1280 pitch 5120 (/4 1280) >[455750.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9b1a0] >[455750.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9b1a0] width 1280 pitch 5120 (/4 1280) >[455750.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400c000] >[455750.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400c000] width 1280 pitch 5120 (/4 1280) >[455750.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[455750.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[455750.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[455750.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[455787.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b090] >[455787.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b090] width 1280 pitch 5120 (/4 1280) >[455787.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e78f0] >[455787.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e78f0] width 1280 pitch 5120 (/4 1280) >[455794.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cba10] >[455794.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cba10] width 1280 pitch 5120 (/4 1280) >[455794.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406180] >[455794.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406180] width 1280 pitch 5120 (/4 1280) >[455794.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cba10] >[455794.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cba10] width 1280 pitch 5120 (/4 1280) >[455794.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406180] >[455794.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406180] width 1280 pitch 5120 (/4 1280) >[455794.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40cba10] >[455794.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40cba10] width 1280 pitch 5120 (/4 1280) >[455794.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406180] >[455794.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406180] width 1280 pitch 5120 (/4 1280) >[455794.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[455794.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[455794.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[455794.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[455794.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[455794.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[455794.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[455794.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[455794.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343aae0] >[455794.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343aae0] width 1280 pitch 5120 (/4 1280) >[455794.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[455794.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[455794.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a460] >[455794.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a460] width 1280 pitch 5120 (/4 1280) >[455794.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[455794.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[455794.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115a460] >[455794.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115a460] width 1280 pitch 5120 (/4 1280) >[455794.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[455794.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[455796.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455796.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[455796.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[455796.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be800] >[455796.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be800] width 1280 pitch 5120 (/4 1280) >[455807.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x454f430] >[455807.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x454f430] width 1280 pitch 5120 (/4 1280) >[455816.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282180] >[455816.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282180] width 1280 pitch 5120 (/4 1280) >[455816.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282180] >[455816.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282180] width 1280 pitch 5120 (/4 1280) >[455836.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45818d0] >[455836.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45818d0] width 1280 pitch 5120 (/4 1280) >[455854.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35762b0] >[455854.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35762b0] width 1280 pitch 5120 (/4 1280) >[455858.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45818d0] >[455858.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45818d0] width 1280 pitch 5120 (/4 1280) >[455859.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12898d0] >[455859.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12898d0] width 1280 pitch 5120 (/4 1280) >[455859.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3360920] >[455859.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3360920] width 1280 pitch 5120 (/4 1280) >[455859.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3360920] >[455859.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3360920] width 1280 pitch 5120 (/4 1280) >[455869.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455869.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455869.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455869.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455869.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455869.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455869.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[455869.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[455869.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[455869.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[455869.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[455869.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[455869.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d15c0] >[455869.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d15c0] width 1280 pitch 5120 (/4 1280) >[455869.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[455869.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[455869.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[455869.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[455869.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3f80] >[455869.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3f80] width 1280 pitch 5120 (/4 1280) >[455869.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[455869.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[455870.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455870.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[455870.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[455870.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2aa4a70] >[455870.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2aa4a70] width 1280 pitch 5120 (/4 1280) >[455882.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x115c8a0] >[455882.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x115c8a0] width 1280 pitch 5120 (/4 1280) >[455882.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a67270] >[455882.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a67270] width 1280 pitch 5120 (/4 1280) >[455889.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4106000] >[455889.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4106000] width 1280 pitch 5120 (/4 1280) >[455900.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409fd00] >[455900.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409fd00] width 1280 pitch 5120 (/4 1280) >[455900.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b170] >[455900.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b170] width 1280 pitch 5120 (/4 1280) >[455900.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409fd00] >[455900.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409fd00] width 1280 pitch 5120 (/4 1280) >[455900.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b170] >[455900.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b170] width 1280 pitch 5120 (/4 1280) >[455900.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409fd00] >[455900.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409fd00] width 1280 pitch 5120 (/4 1280) >[455900.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455900.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455900.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b4a0] >[455900.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b4a0] width 1280 pitch 5120 (/4 1280) >[455900.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455900.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455900.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b4a0] >[455900.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b4a0] width 1280 pitch 5120 (/4 1280) >[455900.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455900.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455900.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e9ba0] >[455900.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e9ba0] width 1280 pitch 5120 (/4 1280) >[455900.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455900.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455900.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e9ba0] >[455900.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e9ba0] width 1280 pitch 5120 (/4 1280) >[455900.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455900.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455900.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12e9ba0] >[455901.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12e9ba0] width 1280 pitch 5120 (/4 1280) >[455901.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[455901.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[455901.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[455901.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[455901.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[455901.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[455901.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[455901.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[455901.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231ca0] >[455901.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231ca0] width 1280 pitch 5120 (/4 1280) >[455901.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b75f0] >[455901.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b75f0] width 1280 pitch 5120 (/4 1280) >[455901.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[455901.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[455914.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407b090] >[455914.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407b090] width 1280 pitch 5120 (/4 1280) >[455914.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343f420] >[455914.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343f420] width 1280 pitch 5120 (/4 1280) >[455914.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[455914.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[455914.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42b5830] >[455914.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42b5830] width 1280 pitch 5120 (/4 1280) >[455977.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11aa9a0] >[455977.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11aa9a0] width 1280 pitch 5120 (/4 1280) >[455977.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455977.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455977.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11aa9a0] >[455977.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11aa9a0] width 1280 pitch 5120 (/4 1280) >[455977.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455977.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455977.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402dc0] >[455977.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402dc0] width 1280 pitch 5120 (/4 1280) >[455977.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43028b0] >[455977.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43028b0] width 1280 pitch 5120 (/4 1280) >[455977.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402dc0] >[455977.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402dc0] width 1280 pitch 5120 (/4 1280) >[455977.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43028b0] >[455977.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43028b0] width 1280 pitch 5120 (/4 1280) >[455977.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402dc0] >[455977.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402dc0] width 1280 pitch 5120 (/4 1280) >[455977.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43028b0] >[455977.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43028b0] width 1280 pitch 5120 (/4 1280) >[455977.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4402dc0] >[455977.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4402dc0] width 1280 pitch 5120 (/4 1280) >[455977.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43028b0] >[455977.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43028b0] width 1280 pitch 5120 (/4 1280) >[455979.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d37d0] >[455979.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d37d0] width 1280 pitch 5120 (/4 1280) >[455979.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475a2f0] >[455979.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475a2f0] width 1280 pitch 5120 (/4 1280) >[455979.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[455979.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[455979.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fbaf0] >[455979.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fbaf0] width 1280 pitch 5120 (/4 1280) >[455979.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455979.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455979.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455979.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455979.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4126eb0] >[455980.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4126eb0] width 1280 pitch 5120 (/4 1280) >[455980.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455980.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455980.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4126eb0] >[455980.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4126eb0] width 1280 pitch 5120 (/4 1280) >[455980.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455980.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455980.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4126eb0] >[455980.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4126eb0] width 1280 pitch 5120 (/4 1280) >[455980.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb110] >[455980.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb110] width 1280 pitch 5120 (/4 1280) >[455980.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cb10] >[455980.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cb10] width 1280 pitch 5120 (/4 1280) >[455980.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6990] >[455980.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6990] width 1280 pitch 5120 (/4 1280) >[455980.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6990] >[455980.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6990] width 1280 pitch 5120 (/4 1280) >[455980.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x462dfb0] >[455980.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x462dfb0] width 1280 pitch 5120 (/4 1280) >[455980.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6990] >[455980.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6990] width 1280 pitch 5120 (/4 1280) >[455980.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x462dfb0] >[455980.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x462dfb0] width 1280 pitch 5120 (/4 1280) >[455980.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6990] >[455980.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6990] width 1280 pitch 5120 (/4 1280) >[455980.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x462dfb0] >[455980.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x462dfb0] width 1280 pitch 5120 (/4 1280) >[455980.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b6990] >[455980.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b6990] width 1280 pitch 5120 (/4 1280) >[455981.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455981.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455981.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455981.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455981.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455981.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455981.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455981.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455981.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455981.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455981.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455981.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455981.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455981.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455981.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455981.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455981.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455981.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455982.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455982.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455982.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455982.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455982.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750ae0] >[455982.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750ae0] width 1280 pitch 5120 (/4 1280) >[455982.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455982.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455982.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455982.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455982.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455982.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455982.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455982.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455982.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5b70] >[455982.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5b70] width 1280 pitch 5120 (/4 1280) >[455983.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1352dc0] >[455983.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1352dc0] width 1280 pitch 5120 (/4 1280) >[455983.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455983.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455984.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455984.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455985.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29511f0] >[455985.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29511f0] width 1280 pitch 5120 (/4 1280) >[455985.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455985.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[455985.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c5a50] >[455985.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c5a50] width 1280 pitch 5120 (/4 1280) >[455985.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4499450] >[455985.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4499450] width 1280 pitch 5120 (/4 1280) >[455986.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[455986.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456001.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92170] >[456001.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92170] width 1280 pitch 5120 (/4 1280) >[456001.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4142140] >[456001.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4142140] width 1280 pitch 5120 (/4 1280) >[456013.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae9cd0] >[456013.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae9cd0] width 1280 pitch 5120 (/4 1280) >[456013.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda370] >[456013.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda370] width 1280 pitch 5120 (/4 1280) >[456013.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b6680] >[456013.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b6680] width 1280 pitch 5120 (/4 1280) >[456013.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda370] >[456013.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda370] width 1280 pitch 5120 (/4 1280) >[456014.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44b6680] >[456014.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44b6680] width 1280 pitch 5120 (/4 1280) >[456014.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda370] >[456014.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda370] width 1280 pitch 5120 (/4 1280) >[456014.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332eaf0] >[456014.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332eaf0] width 1280 pitch 5120 (/4 1280) >[456014.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324c720] >[456015.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324c720] width 1280 pitch 5120 (/4 1280) >[456015.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330e7e0] >[456015.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330e7e0] width 1280 pitch 5120 (/4 1280) >[456015.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f1d70] >[456015.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f1d70] width 1280 pitch 5120 (/4 1280) >[456016.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1190920] >[456016.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1190920] width 1280 pitch 5120 (/4 1280) >[456016.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[456016.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[456016.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1190920] >[456016.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1190920] width 1280 pitch 5120 (/4 1280) >[456021.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[456021.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[456022.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456022.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456022.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[456022.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[456023.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456023.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456023.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456023.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456023.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[456023.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[456048.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499980] >[456048.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499980] width 1280 pitch 5120 (/4 1280) >[456048.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456048.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456049.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499980] >[456049.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499980] width 1280 pitch 5120 (/4 1280) >[456049.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456049.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456049.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499980] >[456049.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499980] width 1280 pitch 5120 (/4 1280) >[456049.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456049.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456052.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[456052.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[456059.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a6a0] >[456059.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a6a0] width 1280 pitch 5120 (/4 1280) >[456059.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456059.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456059.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[456059.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[456059.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db910] >[456059.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db910] width 1280 pitch 5120 (/4 1280) >[456074.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[456074.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[456074.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456074.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456118.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456118.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456119.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456119.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456119.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403a6a0] >[456119.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403a6a0] width 1280 pitch 5120 (/4 1280) >[456119.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4065880] >[456119.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4065880] width 1280 pitch 5120 (/4 1280) >[456126.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[456126.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[456126.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456126.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456126.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[456126.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[456126.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456126.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456126.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[456126.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[456127.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456127.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456127.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459a350] >[456127.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459a350] width 1280 pitch 5120 (/4 1280) >[456127.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456127.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456127.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459a350] >[456127.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459a350] width 1280 pitch 5120 (/4 1280) >[456127.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456127.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456127.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459a350] >[456127.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459a350] width 1280 pitch 5120 (/4 1280) >[456127.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456127.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456140.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92170] >[456140.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92170] width 1280 pitch 5120 (/4 1280) >[456140.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499980] >[456140.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499980] width 1280 pitch 5120 (/4 1280) >[456175.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456175.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456176.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456176.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456176.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499980] >[456176.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499980] width 1280 pitch 5120 (/4 1280) >[456176.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456176.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456177.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456177.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456177.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92170] >[456177.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92170] width 1280 pitch 5120 (/4 1280) >[456183.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47362f0] >[456183.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47362f0] width 1280 pitch 5120 (/4 1280) >[456183.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47362f0] >[456183.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47362f0] width 1280 pitch 5120 (/4 1280) >[456183.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[456183.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[456183.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47362f0] >[456183.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47362f0] width 1280 pitch 5120 (/4 1280) >[456221.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92170] >[456221.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92170] width 1280 pitch 5120 (/4 1280) >[456221.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[456221.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[456222.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456222.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456222.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456222.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456222.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720f10] >[456222.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720f10] width 1280 pitch 5120 (/4 1280) >[456222.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456222.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456222.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f92a0] >[456222.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f92a0] width 1280 pitch 5120 (/4 1280) >[456222.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1151970] >[456222.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1151970] width 1280 pitch 5120 (/4 1280) >[456222.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2261e60] >[456222.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2261e60] width 1280 pitch 5120 (/4 1280) >[456222.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[456222.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[456226.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a0ff0] >[456226.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a0ff0] width 1280 pitch 5120 (/4 1280) >[456226.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456226.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456226.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec88d0] >[456226.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec88d0] width 1280 pitch 5120 (/4 1280) >[456226.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[456226.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[456227.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[456227.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[456227.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad240] >[456227.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad240] width 1280 pitch 5120 (/4 1280) >[456227.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[456227.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[456227.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7c170] >[456227.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7c170] width 1280 pitch 5120 (/4 1280) >[456229.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4120570] >[456229.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4120570] width 1280 pitch 5120 (/4 1280) >[456229.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[456229.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[456229.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456229.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456229.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46337c0] >[456229.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46337c0] width 1280 pitch 5120 (/4 1280) >[456230.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456230.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456230.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad240] >[456230.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad240] width 1280 pitch 5120 (/4 1280) >[456230.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456230.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456230.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cd60] >[456230.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cd60] width 1280 pitch 5120 (/4 1280) >[456232.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456232.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456232.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456232.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456232.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[456232.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[456232.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456232.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456239.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[456239.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[456239.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46337c0] >[456239.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46337c0] width 1280 pitch 5120 (/4 1280) >[456241.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456241.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456241.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456241.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456245.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[456246.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[456246.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456246.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456246.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414f50] >[456246.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414f50] width 1280 pitch 5120 (/4 1280) >[456246.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456246.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456246.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456246.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456246.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456246.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456246.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[456246.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[456246.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456246.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456247.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456247.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456247.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456247.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456255.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456255.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456256.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8130] >[456256.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8130] width 1280 pitch 5120 (/4 1280) >[456316.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456316.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456316.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456316.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456316.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456316.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456316.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456316.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456318.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[456318.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[456318.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[456318.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[456318.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456318.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456318.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[456318.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[456318.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2340c20] >[456318.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2340c20] width 1280 pitch 5120 (/4 1280) >[456318.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456318.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456321.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456321.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456321.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456321.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456321.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aac20] >[456321.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aac20] width 1280 pitch 5120 (/4 1280) >[456321.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456321.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456353.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[456353.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[456353.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[456353.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[456353.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40067e0] >[456353.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40067e0] width 1280 pitch 5120 (/4 1280) >[456354.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[456354.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[456441.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456441.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456441.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456441.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456441.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aac20] >[456441.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aac20] width 1280 pitch 5120 (/4 1280) >[456441.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[456441.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[456442.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[456442.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[456442.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[456442.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[456442.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456442.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456443.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505b30] >[456443.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505b30] width 1280 pitch 5120 (/4 1280) >[456443.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12a0780] >[456443.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12a0780] width 1280 pitch 5120 (/4 1280) >[456443.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cdd0] >[456443.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cdd0] width 1280 pitch 5120 (/4 1280) >[456443.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ae9cd0] >[456444.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ae9cd0] width 1280 pitch 5120 (/4 1280) >[456444.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1193750] >[456444.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1193750] width 1280 pitch 5120 (/4 1280) >[456496.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4538e70] >[456496.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4538e70] width 1280 pitch 5120 (/4 1280) >[456498.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f137a0] >[456498.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f137a0] width 1280 pitch 5120 (/4 1280) >[456524.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4538e70] >[456524.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4538e70] width 1280 pitch 5120 (/4 1280) >[456524.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[456524.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[456524.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[456524.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[456524.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344c8e0] >[456524.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344c8e0] width 1280 pitch 5120 (/4 1280) >[456524.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[456524.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[456524.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456524.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456524.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[456524.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[456524.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456524.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456531.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[456531.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[456531.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[456531.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[456532.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[456532.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[456532.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[456532.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[456532.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dffff0] >[456532.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dffff0] width 1280 pitch 5120 (/4 1280) >[456533.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[456533.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[456567.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456567.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456567.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456567.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456567.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[456567.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[456567.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[456567.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[456568.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[456568.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[456568.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456568.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456568.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456568.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456568.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344c8e0] >[456568.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344c8e0] width 1280 pitch 5120 (/4 1280) >[456583.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[456583.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[456584.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83840] >[456584.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83840] width 1280 pitch 5120 (/4 1280) >[456584.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[456584.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[456584.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8130] >[456584.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8130] width 1280 pitch 5120 (/4 1280) >[456584.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[456584.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[456584.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[456584.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[456595.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[456595.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[456596.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456596.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456596.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4444a20] >[456596.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4444a20] width 1280 pitch 5120 (/4 1280) >[456596.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c7900] >[456596.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c7900] width 1280 pitch 5120 (/4 1280) >[456596.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d0530] >[456596.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d0530] width 1280 pitch 5120 (/4 1280) >[456596.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad240] >[456596.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad240] width 1280 pitch 5120 (/4 1280) >[456612.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[456612.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[456612.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[456612.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[456612.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[456612.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[456612.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[456612.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[456612.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[456612.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[456612.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[456612.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[456612.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456612.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456612.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[456612.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[456613.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2340c20] >[456613.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2340c20] width 1280 pitch 5120 (/4 1280) >[456614.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[456614.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[456614.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[456614.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[456614.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ba60] >[456614.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ba60] width 1280 pitch 5120 (/4 1280) >[456616.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456616.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456620.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456620.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456620.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[456620.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[456620.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456620.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456665.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456665.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456665.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456665.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456665.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12190] >[456665.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12190] width 1280 pitch 5120 (/4 1280) >[456665.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456665.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456668.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456668.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456668.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344c8e0] >[456668.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344c8e0] width 1280 pitch 5120 (/4 1280) >[456674.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[456674.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[456674.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456674.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456674.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46337c0] >[456674.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46337c0] width 1280 pitch 5120 (/4 1280) >[456674.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1134b60] >[456674.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1134b60] width 1280 pitch 5120 (/4 1280) >[456688.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[456688.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[456688.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[456688.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[456688.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47362f0] >[456688.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47362f0] width 1280 pitch 5120 (/4 1280) >[456688.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[456688.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[456714.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[456714.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[456714.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[456714.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[456714.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406df20] >[456714.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406df20] width 1280 pitch 5120 (/4 1280) >[456715.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[456715.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[456715.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[456715.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[456715.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ba60] >[456715.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ba60] width 1280 pitch 5120 (/4 1280) >[456715.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[456715.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[456715.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ba60] >[456715.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ba60] width 1280 pitch 5120 (/4 1280) >[456715.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456715.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[456715.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[456716.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[456784.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f2700] >[456784.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f2700] width 1280 pitch 5120 (/4 1280) >[456790.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[456790.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[456790.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[456790.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[456791.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[456791.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[456791.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058610] >[456791.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058610] width 1280 pitch 5120 (/4 1280) >[456791.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[456791.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[456791.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058610] >[456791.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058610] width 1280 pitch 5120 (/4 1280) >[456791.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[456791.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[456792.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456792.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456792.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456792.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456792.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cd60] >[456792.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cd60] width 1280 pitch 5120 (/4 1280) >[456802.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ba60] >[456802.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ba60] width 1280 pitch 5120 (/4 1280) >[456803.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[456803.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[456803.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ba60] >[456803.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ba60] width 1280 pitch 5120 (/4 1280) >[456803.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[456803.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[456803.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x344c8e0] >[456803.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x344c8e0] width 1280 pitch 5120 (/4 1280) >[456803.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[456803.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[456826.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x204b1d0] >[456826.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x204b1d0] width 1280 pitch 5120 (/4 1280) >[456826.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[456826.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[456826.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f137a0] >[456826.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f137a0] width 1280 pitch 5120 (/4 1280) >[456826.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[456826.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[456826.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[456826.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[456827.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456827.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456827.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339c80] >[456827.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339c80] width 1280 pitch 5120 (/4 1280) >[456827.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[456827.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[456828.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[456828.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[456828.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[456828.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[456828.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35723a0] >[456829.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35723a0] width 1280 pitch 5120 (/4 1280) >[456829.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad240] >[456829.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad240] width 1280 pitch 5120 (/4 1280) >[456829.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[456829.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[456829.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4a80] >[456829.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4a80] width 1280 pitch 5120 (/4 1280) >[456829.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41da6c0] >[456829.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41da6c0] width 1280 pitch 5120 (/4 1280) >[456829.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[456829.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[456830.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[456830.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[456830.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[456830.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[456830.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12190] >[456830.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12190] width 1280 pitch 5120 (/4 1280) >[456830.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[456830.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[456841.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[456841.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[456842.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11c7900] >[456842.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11c7900] width 1280 pitch 5120 (/4 1280) >[456842.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[456842.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[456842.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2340c20] >[456842.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2340c20] width 1280 pitch 5120 (/4 1280) >[456872.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec88d0] >[456872.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec88d0] width 1280 pitch 5120 (/4 1280) >[456882.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a55c0] >[456882.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a55c0] width 1280 pitch 5120 (/4 1280) >[456882.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[456882.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[456902.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[456902.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[456902.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[456902.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[456902.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ffc80] >[456902.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ffc80] width 1280 pitch 5120 (/4 1280) >[456902.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[456902.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[456903.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[456903.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[456903.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420f1c0] >[456903.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420f1c0] width 1280 pitch 5120 (/4 1280) >[456903.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[456903.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[456903.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414f50] >[456903.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414f50] width 1280 pitch 5120 (/4 1280) >[456903.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[456903.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[456904.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456904.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456904.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[456904.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[456904.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3234bb0] >[456904.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3234bb0] width 1280 pitch 5120 (/4 1280) >[456936.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[456936.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[456936.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec88d0] >[456936.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec88d0] width 1280 pitch 5120 (/4 1280) >[456936.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[456936.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[456936.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec88d0] >[456936.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec88d0] width 1280 pitch 5120 (/4 1280) >[456937.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456937.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456937.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5570] >[456937.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5570] width 1280 pitch 5120 (/4 1280) >[456937.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[456937.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[456937.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4414f50] >[456937.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4414f50] width 1280 pitch 5120 (/4 1280) >[456938.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e2db0] >[456938.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e2db0] width 1280 pitch 5120 (/4 1280) >[456938.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460] >[456938.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1280 pitch 5120 (/4 1280) >[456938.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385a7d0] >[456938.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385a7d0] width 1280 pitch 5120 (/4 1280) >[456938.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f137a0] >[456938.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f137a0] width 1280 pitch 5120 (/4 1280) >[456940.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[456940.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[456941.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[456941.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[456942.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[456942.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[456942.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[456942.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[456942.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[456942.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[456952.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[456953.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[456953.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[456953.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[456953.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[456953.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[456953.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3270dd0] >[456953.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3270dd0] width 1280 pitch 5120 (/4 1280) >[456953.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[456953.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[457002.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d5a10] >[457002.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d5a10] width 1280 pitch 5120 (/4 1280) >[457002.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d5a10] >[457002.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d5a10] width 1280 pitch 5120 (/4 1280) >[457002.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720f10] >[457002.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720f10] width 1280 pitch 5120 (/4 1280) >[457002.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[457002.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[457053.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1151970] >[457053.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1151970] width 1280 pitch 5120 (/4 1280) >[457243.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457243.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457243.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457243.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457243.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457243.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457243.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457243.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457243.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457243.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457243.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457243.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457243.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457243.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457243.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457243.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[457243.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[457277.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457277.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457277.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457277.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457278.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240f940] >[457278.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240f940] width 1280 pitch 5120 (/4 1280) >[457278.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2050e80] >[457278.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2050e80] width 1280 pitch 5120 (/4 1280) >[457279.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[457279.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[457279.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c340] >[457279.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c340] width 1280 pitch 5120 (/4 1280) >[457279.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d2e0] >[457279.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d2e0] width 1280 pitch 5120 (/4 1280) >[457279.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460e8c0] >[457279.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460e8c0] width 1280 pitch 5120 (/4 1280) >[457279.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457279.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457279.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457279.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457279.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457279.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457279.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457279.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457279.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457279.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457279.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457279.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457279.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457279.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457279.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457279.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[457280.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[457280.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457280.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457280.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[457280.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[457280.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446fdf0] >[457280.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446fdf0] width 1280 pitch 5120 (/4 1280) >[457280.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a55c0] >[457280.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a55c0] width 1280 pitch 5120 (/4 1280) >[457280.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446fdf0] >[457280.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446fdf0] width 1280 pitch 5120 (/4 1280) >[457280.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097280] >[457280.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097280] width 1280 pitch 5120 (/4 1280) >[457280.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x446fdf0] >[457280.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x446fdf0] width 1280 pitch 5120 (/4 1280) >[457417.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[457417.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[457417.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[457417.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[457580.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[457580.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[457581.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[457581.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[457581.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e29a0] >[457581.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e29a0] width 1280 pitch 5120 (/4 1280) >[457582.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[457582.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[457582.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[457582.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[457582.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[457582.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[457586.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca6f0] >[457586.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca6f0] width 1280 pitch 5120 (/4 1280) >[457586.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e2db0] >[457586.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e2db0] width 1280 pitch 5120 (/4 1280) >[457586.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[457586.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[457586.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459a390] >[457586.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459a390] width 1280 pitch 5120 (/4 1280) >[457587.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[457587.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[457588.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7c170] >[457588.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7c170] width 1280 pitch 5120 (/4 1280) >[457589.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[457589.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[457589.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2261e60] >[457589.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2261e60] width 1280 pitch 5120 (/4 1280) >[457589.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[457589.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[457589.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2261e60] >[457589.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2261e60] width 1280 pitch 5120 (/4 1280) >[457625.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41da6c0] >[457625.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41da6c0] width 1280 pitch 5120 (/4 1280) >[457625.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[457625.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[457625.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41da6c0] >[457625.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41da6c0] width 1280 pitch 5120 (/4 1280) >[457625.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[457625.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[457625.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41da6c0] >[457625.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41da6c0] width 1280 pitch 5120 (/4 1280) >[457625.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[457625.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[457625.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[457625.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[457625.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097280] >[457625.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097280] width 1280 pitch 5120 (/4 1280) >[457625.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[457625.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[457625.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[457625.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[457625.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[457625.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[457625.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12190] >[457625.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12190] width 1280 pitch 5120 (/4 1280) >[457626.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[457626.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[457626.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457626.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457626.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[457626.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[457626.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457626.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457626.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[457626.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[457626.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457626.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457626.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[457626.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[457626.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457626.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457626.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[457626.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[457626.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457626.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457626.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[457626.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[457626.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457626.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4205b90] >[457626.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4205b90] width 1280 pitch 5120 (/4 1280) >[457626.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[457626.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[457627.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[457627.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[457627.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2261e60] >[457627.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2261e60] width 1280 pitch 5120 (/4 1280) >[457628.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[457628.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[457628.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457628.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457628.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[457628.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[457628.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457628.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457628.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[457628.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[457628.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457628.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457628.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b3a40] >[457628.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b3a40] width 1280 pitch 5120 (/4 1280) >[457628.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457628.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457628.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[457628.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[457628.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4618770] >[457628.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4618770] width 1280 pitch 5120 (/4 1280) >[457628.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[457628.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[457628.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4336f70] >[457628.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4336f70] width 1280 pitch 5120 (/4 1280) >[457628.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457628.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[457628.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[457628.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[457628.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[457632.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cfd60] >[457632.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cfd60] width 1280 pitch 5120 (/4 1280) >[457731.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[457731.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[457731.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406df20] >[457731.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406df20] width 1280 pitch 5120 (/4 1280) >[457731.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[457731.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[457731.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406df20] >[457731.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406df20] width 1280 pitch 5120 (/4 1280) >[457731.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[457731.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[457731.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406df20] >[457731.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406df20] width 1280 pitch 5120 (/4 1280) >[457731.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[457731.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[457731.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46275d0] >[457731.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46275d0] width 1280 pitch 5120 (/4 1280) >[457731.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[457731.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[457731.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46275d0] >[457731.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46275d0] width 1280 pitch 5120 (/4 1280) >[457731.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[457731.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[457731.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[457731.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[457731.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[457731.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[457731.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[457731.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[457731.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41c4da0] >[457731.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41c4da0] width 1280 pitch 5120 (/4 1280) >[457731.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3decd80] >[457731.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3decd80] width 1280 pitch 5120 (/4 1280) >[457732.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457732.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457732.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[457732.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[457732.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457732.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457732.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[457732.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[457732.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457732.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457732.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[457732.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[457732.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457732.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457732.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[457732.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[457732.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[457732.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[457733.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345a030] >[457733.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345a030] width 1280 pitch 5120 (/4 1280) >[457733.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1151970] >[457733.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1151970] width 1280 pitch 5120 (/4 1280) >[457733.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fbaf0] >[457733.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fbaf0] width 1280 pitch 5120 (/4 1280) >[457742.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457742.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d87a0] >[457742.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d87a0] width 1280 pitch 5120 (/4 1280) >[457742.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[457742.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[457774.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[457774.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[457775.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a72a0] >[457775.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a72a0] width 1280 pitch 5120 (/4 1280) >[457821.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585b70] >[457821.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585b70] width 1280 pitch 5120 (/4 1280) >[457821.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ae6a0] >[457821.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ae6a0] width 1280 pitch 5120 (/4 1280) >[457823.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35781f0] >[457823.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35781f0] width 1280 pitch 5120 (/4 1280) >[457823.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35781f0] >[457823.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35781f0] width 1280 pitch 5120 (/4 1280) >[457854.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45af230] >[457854.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45af230] width 1280 pitch 5120 (/4 1280) >[457854.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3578100] >[457854.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3578100] width 1280 pitch 5120 (/4 1280) >[457857.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a3040] >[457857.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a3040] width 1280 pitch 5120 (/4 1280) >[457857.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a3040] >[457857.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a3040] width 1280 pitch 5120 (/4 1280) >[457857.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357e4a0] >[457857.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357e4a0] width 1280 pitch 5120 (/4 1280) >[457857.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3568d10] >[457857.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3568d10] width 1280 pitch 5120 (/4 1280) >[457937.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3569530] >[457937.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3569530] width 1280 pitch 5120 (/4 1280) >[457938.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3569530] >[457938.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3569530] width 1280 pitch 5120 (/4 1280) >[457938.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3578670] >[457938.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3578670] width 1280 pitch 5120 (/4 1280) >[457938.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b788d0] >[457938.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b788d0] width 1280 pitch 5120 (/4 1280) >[457954.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f25d0] >[457954.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f25d0] width 1280 pitch 5120 (/4 1280) >[458115.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3592f00] >[458115.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3592f00] width 1280 pitch 5120 (/4 1280) >[458115.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595dc0] >[458115.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595dc0] width 1280 pitch 5120 (/4 1280) >[458117.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357e4e0] >[458117.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357e4e0] width 1280 pitch 5120 (/4 1280) >[458117.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bda0] >[458117.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bda0] width 1280 pitch 5120 (/4 1280) >[458118.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46a9610] >[458118.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46a9610] width 1280 pitch 5120 (/4 1280) >[458119.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03230] >[458119.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03230] width 1280 pitch 5120 (/4 1280) >[458128.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a490] >[458128.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a490] width 1280 pitch 5120 (/4 1280) >[458128.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda370] >[458128.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda370] width 1280 pitch 5120 (/4 1280) >[458129.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3565970] >[458129.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3565970] width 1280 pitch 5120 (/4 1280) >[458130.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35662f0] >[458130.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35662f0] width 1280 pitch 5120 (/4 1280) >[458168.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2b280] >[458168.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2b280] width 1280 pitch 5120 (/4 1280) >[458168.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[458168.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[458168.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2b280] >[458168.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2b280] width 1280 pitch 5120 (/4 1280) >[458168.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[458168.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[458169.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3565970] >[458169.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3565970] width 1280 pitch 5120 (/4 1280) >[458171.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7c170] >[458171.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7c170] width 1280 pitch 5120 (/4 1280) >[458234.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[458234.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[458234.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[458234.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[458234.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[458234.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[458234.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[458234.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[458234.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[458234.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[458234.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[458234.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[458235.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[458235.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[458235.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[458235.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[458235.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[458235.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[458235.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6d90] >[458235.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6d90] width 1280 pitch 5120 (/4 1280) >[458235.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03230] >[458235.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03230] width 1280 pitch 5120 (/4 1280) >[458235.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0450] >[458235.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0450] width 1280 pitch 5120 (/4 1280) >[458235.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e03230] >[458235.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e03230] width 1280 pitch 5120 (/4 1280) >[458236.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3463a60] >[458236.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3463a60] width 1280 pitch 5120 (/4 1280) >[458245.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[458245.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[458245.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2b280] >[458245.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2b280] width 1280 pitch 5120 (/4 1280) >[458245.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41f7850] >[458245.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41f7850] width 1280 pitch 5120 (/4 1280) >[458245.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2b280] >[458245.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2b280] width 1280 pitch 5120 (/4 1280) >[458245.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[458245.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[458245.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[458245.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[458245.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[458245.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[458245.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[458245.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[458245.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[458245.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[458245.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[458245.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[458245.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[458245.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[458245.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[458245.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[458246.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35662f0] >[458246.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35662f0] width 1280 pitch 5120 (/4 1280) >[458246.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4336f70] >[458246.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4336f70] width 1280 pitch 5120 (/4 1280) >[458246.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[458246.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[458246.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[458246.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[458246.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x151ce90] >[458246.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x151ce90] width 1280 pitch 5120 (/4 1280) >[458246.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458246.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458246.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458246.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458246.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458246.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458246.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac020] >[458246.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac020] width 1280 pitch 5120 (/4 1280) >[458246.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458246.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458246.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1151970] >[458246.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1151970] width 1280 pitch 5120 (/4 1280) >[458246.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[458246.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[458246.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[458246.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[458246.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45db0c0] >[458246.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45db0c0] width 1280 pitch 5120 (/4 1280) >[458246.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6d90] >[458246.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6d90] width 1280 pitch 5120 (/4 1280) >[458246.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097280] >[458246.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097280] width 1280 pitch 5120 (/4 1280) >[458246.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4097280] >[458246.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4097280] width 1280 pitch 5120 (/4 1280) >[458249.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80260] >[458249.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80260] width 1280 pitch 5120 (/4 1280) >[458249.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[458249.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[458250.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458250.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458250.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac020] >[458250.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac020] width 1280 pitch 5120 (/4 1280) >[458250.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac020] >[458250.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac020] width 1280 pitch 5120 (/4 1280) >[458250.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdf710] >[458250.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdf710] width 1280 pitch 5120 (/4 1280) >[458250.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac020] >[458250.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac020] width 1280 pitch 5120 (/4 1280) >[458251.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[458251.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[458320.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d36b0] >[458320.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d36b0] width 1280 pitch 5120 (/4 1280) >[458320.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[458320.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[458321.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d36b0] >[458321.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d36b0] width 1280 pitch 5120 (/4 1280) >[458321.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[458321.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[458321.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d36b0] >[458321.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d36b0] width 1280 pitch 5120 (/4 1280) >[458321.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[458321.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[458321.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4538e70] >[458321.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4538e70] width 1280 pitch 5120 (/4 1280) >[458322.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a490] >[458322.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a490] width 1280 pitch 5120 (/4 1280) >[458322.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[458322.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[458322.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a490] >[458322.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a490] width 1280 pitch 5120 (/4 1280) >[458322.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[458322.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[458322.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b14d0] >[458322.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b14d0] width 1280 pitch 5120 (/4 1280) >[458385.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[458385.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[458396.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35da330] >[458396.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35da330] width 1280 pitch 5120 (/4 1280) >[458607.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[458607.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[458607.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a50e40] >[458607.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a50e40] width 1280 pitch 5120 (/4 1280) >[458607.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46b3440] >[458607.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46b3440] width 1280 pitch 5120 (/4 1280) >[458607.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[458607.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[458611.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401e000] >[458611.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401e000] width 1280 pitch 5120 (/4 1280) >[458611.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423d9a0] >[458611.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423d9a0] width 1280 pitch 5120 (/4 1280) >[458611.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[458611.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[458611.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x423d9a0] >[458611.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x423d9a0] width 1280 pitch 5120 (/4 1280) >[458612.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[458612.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[458612.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[458612.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[459212.322] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[459212.322] (II) RADEON(0): Printing DDC gathered Modelines: >[459212.322] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[459302.936] (II) RADEON(0): RADEONSaveScreen(2) >[459302.940] (II) RADEON(0): RADEONSaveScreen(0) >[474823.920] (II) RADEON(0): RADEONSaveScreen(1) >[474829.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3025db0] >[474829.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3025db0] width 1280 pitch 5120 (/4 1280) >[474830.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[474830.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[474830.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffc580] >[474830.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffc580] width 1280 pitch 5120 (/4 1280) >[474830.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[474830.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[474831.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffc580] >[474831.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffc580] width 1280 pitch 5120 (/4 1280) >[474831.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[474831.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[474831.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[474831.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[474831.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4624960] >[474831.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4624960] width 1280 pitch 5120 (/4 1280) >[474831.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[474831.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[474832.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4624960] >[474832.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4624960] width 1280 pitch 5120 (/4 1280) >[474832.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[474832.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[474832.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[474832.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[474832.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4538e70] >[474832.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4538e70] width 1280 pitch 5120 (/4 1280) >[474832.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b27500] >[474832.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b27500] width 1280 pitch 5120 (/4 1280) >[474833.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[474833.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[474833.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[474833.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[474833.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03aa0] >[474833.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03aa0] width 1280 pitch 5120 (/4 1280) >[474833.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35da330] >[474833.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35da330] width 1280 pitch 5120 (/4 1280) >[474834.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[474834.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[474834.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4407d50] >[474834.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4407d50] width 1280 pitch 5120 (/4 1280) >[474834.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5ad0] >[474834.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5ad0] width 1280 pitch 5120 (/4 1280) >[474836.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80660] >[474836.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80660] width 1280 pitch 5120 (/4 1280) >[474837.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3515f30] >[474837.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3515f30] width 1280 pitch 5120 (/4 1280) >[474837.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[474837.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[474837.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[474837.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[474837.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[474837.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[474837.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[474837.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[474837.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[474837.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[474837.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[474837.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[474837.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a690] >[474837.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a690] width 1280 pitch 5120 (/4 1280) >[474837.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c240] >[474837.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c240] width 1280 pitch 5120 (/4 1280) >[474837.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[474837.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[474837.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025ce0] >[474837.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025ce0] width 1280 pitch 5120 (/4 1280) >[474837.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29953b0] >[474837.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29953b0] width 1280 pitch 5120 (/4 1280) >[474837.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3585f30] >[474837.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3585f30] width 1280 pitch 5120 (/4 1280) >[474837.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bda0] >[474837.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bda0] width 1280 pitch 5120 (/4 1280) >[474837.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4518a50] >[474837.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4518a50] width 1280 pitch 5120 (/4 1280) >[474837.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35662f0] >[474837.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35662f0] width 1280 pitch 5120 (/4 1280) >[474837.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[474837.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[474837.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35790e0] >[474837.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35790e0] width 1280 pitch 5120 (/4 1280) >[474837.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784070] >[474837.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784070] width 1280 pitch 5120 (/4 1280) >[474837.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474837.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474837.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784070] >[474837.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784070] width 1280 pitch 5120 (/4 1280) >[474837.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474837.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474837.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2784070] >[474837.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2784070] width 1280 pitch 5120 (/4 1280) >[474837.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474837.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474837.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[474838.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[474838.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474838.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474838.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[474838.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[474838.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474838.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474838.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f640] >[474838.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f640] width 1280 pitch 5120 (/4 1280) >[474838.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x408bae0] >[474838.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x408bae0] width 1280 pitch 5120 (/4 1280) >[474838.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[474838.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[474838.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[474838.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[474838.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[474838.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[474838.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[474838.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[474838.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[474838.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[474838.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[474838.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[474838.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[474838.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[474838.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[474838.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[474838.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[474838.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[474838.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609520] >[474838.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609520] width 1280 pitch 5120 (/4 1280) >[474838.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14ff040] >[474838.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14ff040] width 1280 pitch 5120 (/4 1280) >[474877.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dffff0] >[474877.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dffff0] width 1280 pitch 5120 (/4 1280) >[474893.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[474893.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[474893.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ac020] >[474893.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ac020] width 1280 pitch 5120 (/4 1280) >[474894.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da7370] >[474894.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da7370] width 1280 pitch 5120 (/4 1280) >[474894.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47099d0] >[474894.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47099d0] width 1280 pitch 5120 (/4 1280) >[475044.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ad70] >[475044.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ad70] width 1280 pitch 5120 (/4 1280) >[475044.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5ad0] >[475044.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5ad0] width 1280 pitch 5120 (/4 1280) >[475044.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736640] >[475045.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736640] width 1280 pitch 5120 (/4 1280) >[475045.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41da930] >[475045.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41da930] width 1280 pitch 5120 (/4 1280) >[475045.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b9440] >[475045.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b9440] width 1280 pitch 5120 (/4 1280) >[475045.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40513c0] >[475045.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40513c0] width 1280 pitch 5120 (/4 1280) >[475045.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479cd70] >[475045.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479cd70] width 1280 pitch 5120 (/4 1280) >[475045.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[475045.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[475045.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505b30] >[475045.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505b30] width 1280 pitch 5120 (/4 1280) >[475046.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da7370] >[475046.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da7370] width 1280 pitch 5120 (/4 1280) >[475046.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[475046.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[475046.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da7370] >[475046.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da7370] width 1280 pitch 5120 (/4 1280) >[475046.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[475046.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[475046.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da7370] >[475046.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da7370] width 1280 pitch 5120 (/4 1280) >[475332.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a55c0] >[475332.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a55c0] width 1280 pitch 5120 (/4 1280) >[475332.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[475332.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[475332.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40513c0] >[475332.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40513c0] width 1280 pitch 5120 (/4 1280) >[475332.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13b0c80] >[475332.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13b0c80] width 1280 pitch 5120 (/4 1280) >[475333.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d2fe0] >[475333.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d2fe0] width 1280 pitch 5120 (/4 1280) >[475333.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[475333.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[475333.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505b30] >[475333.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505b30] width 1280 pitch 5120 (/4 1280) >[475334.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[475334.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[475334.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720460] >[475334.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720460] width 1280 pitch 5120 (/4 1280) >[475334.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[475334.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[475345.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4120570] >[475345.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4120570] width 1280 pitch 5120 (/4 1280) >[475409.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x233eb30] >[475409.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x233eb30] width 1280 pitch 5120 (/4 1280) >[475409.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459a390] >[475409.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459a390] width 1280 pitch 5120 (/4 1280) >[475419.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee3df0] >[475419.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee3df0] width 1280 pitch 5120 (/4 1280) >[475680.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[475680.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[475680.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f34cc0] >[475680.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f34cc0] width 1280 pitch 5120 (/4 1280) >[475693.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427620] >[475693.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427620] width 1280 pitch 5120 (/4 1280) >[475693.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a9a0] >[475693.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a9a0] width 1280 pitch 5120 (/4 1280) >[475709.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475709.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475709.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475709.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475709.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475709.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475709.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475709.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475709.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475709.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475709.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475709.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475709.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475709.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475709.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475709.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475710.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475710.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475710.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475710.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475710.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475710.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475710.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475710.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475710.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475710.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475710.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475710.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475710.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475710.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475712.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475712.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475712.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475712.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475712.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475712.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475712.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475712.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475712.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475712.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475712.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475712.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475712.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475712.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475712.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475712.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475712.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2188190] >[475712.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2188190] width 1280 pitch 5120 (/4 1280) >[475712.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513320] >[475712.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513320] width 1280 pitch 5120 (/4 1280) >[475737.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433dfe0] >[475737.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433dfe0] width 1280 pitch 5120 (/4 1280) >[475953.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b2560] >[475953.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b2560] width 1280 pitch 5120 (/4 1280) >[475954.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44e40c0] >[475954.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44e40c0] width 1280 pitch 5120 (/4 1280) >[475956.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a7fb0] >[475956.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a7fb0] width 1280 pitch 5120 (/4 1280) >[475958.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ab370] >[475958.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ab370] width 1280 pitch 5120 (/4 1280) >[475970.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d05f0] >[475970.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d05f0] width 1280 pitch 5120 (/4 1280) >[476029.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9d10] >[476029.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9d10] width 1280 pitch 5120 (/4 1280) >[476029.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476029.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476108.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498010] >[476108.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498010] width 1280 pitch 5120 (/4 1280) >[476200.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476200.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476200.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476200.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476200.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476200.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476200.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476200.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476201.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ba010] >[476201.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ba010] width 1280 pitch 5120 (/4 1280) >[476201.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413b990] >[476201.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413b990] width 1280 pitch 5120 (/4 1280) >[476201.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ea180] >[476201.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ea180] width 1280 pitch 5120 (/4 1280) >[476201.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476201.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476203.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b95af0] >[476203.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b95af0] width 1280 pitch 5120 (/4 1280) >[476203.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413b990] >[476203.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413b990] width 1280 pitch 5120 (/4 1280) >[476203.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[476203.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[476205.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476205.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476206.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ea180] >[476206.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ea180] width 1280 pitch 5120 (/4 1280) >[476206.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476206.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476207.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ea180] >[476207.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ea180] width 1280 pitch 5120 (/4 1280) >[476207.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413b990] >[476207.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413b990] width 1280 pitch 5120 (/4 1280) >[476207.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4702570] >[476207.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4702570] width 1280 pitch 5120 (/4 1280) >[476222.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498010] >[476222.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498010] width 1280 pitch 5120 (/4 1280) >[476222.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498010] >[476222.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498010] width 1280 pitch 5120 (/4 1280) >[476222.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498010] >[476222.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498010] width 1280 pitch 5120 (/4 1280) >[476222.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ba010] >[476222.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ba010] width 1280 pitch 5120 (/4 1280) >[476223.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476223.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476223.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x413b990] >[476223.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x413b990] width 1280 pitch 5120 (/4 1280) >[476224.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476224.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476225.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476225.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476225.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34aa5e0] >[476225.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34aa5e0] width 1280 pitch 5120 (/4 1280) >[476225.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476225.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476232.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476232.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476232.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b95af0] >[476232.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b95af0] width 1280 pitch 5120 (/4 1280) >[476232.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ba010] >[476232.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ba010] width 1280 pitch 5120 (/4 1280) >[476232.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[476232.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[476232.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34aa5e0] >[476232.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34aa5e0] width 1280 pitch 5120 (/4 1280) >[476233.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c1ae0] >[476233.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c1ae0] width 1280 pitch 5120 (/4 1280) >[476233.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476233.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476233.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b8e10] >[476233.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b8e10] width 1280 pitch 5120 (/4 1280) >[476233.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4702570] >[476233.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4702570] width 1280 pitch 5120 (/4 1280) >[476233.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5540] >[476233.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5540] width 1280 pitch 5120 (/4 1280) >[476394.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42de1d0] >[476394.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42de1d0] width 1280 pitch 5120 (/4 1280) >[476394.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42de1d0] >[476394.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42de1d0] width 1280 pitch 5120 (/4 1280) >[476394.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42de1d0] >[476394.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42de1d0] width 1280 pitch 5120 (/4 1280) >[476394.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42de1d0] >[476394.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42de1d0] width 1280 pitch 5120 (/4 1280) >[476394.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a9a0] >[476394.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a9a0] width 1280 pitch 5120 (/4 1280) >[476394.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a9a0] >[476394.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a9a0] width 1280 pitch 5120 (/4 1280) >[476394.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0f60] >[476394.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0f60] width 1280 pitch 5120 (/4 1280) >[476394.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a9a0] >[476394.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a9a0] width 1280 pitch 5120 (/4 1280) >[476395.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476395.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476395.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476395.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476395.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476396.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476396.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476396.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476396.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476396.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb5c0] >[476396.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb5c0] width 1280 pitch 5120 (/4 1280) >[476396.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[476396.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[476455.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3479260] >[476455.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3479260] width 1280 pitch 5120 (/4 1280) >[477018.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477018.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477018.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477018.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477018.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477018.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477018.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477018.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477018.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477018.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477018.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477018.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477018.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477018.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477018.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477018.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477018.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477018.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477018.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477018.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477038.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477038.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477038.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477038.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477038.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477038.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477038.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477038.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477038.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477039.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477039.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477039.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477039.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477076.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9d10] >[477076.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9d10] width 1280 pitch 5120 (/4 1280) >[477076.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477076.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477076.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9d10] >[477076.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9d10] width 1280 pitch 5120 (/4 1280) >[477076.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477076.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477076.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477076.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477076.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477076.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477076.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477076.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477076.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477076.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477076.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d2690] >[477076.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d2690] width 1280 pitch 5120 (/4 1280) >[477076.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1201770] >[477076.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1201770] width 1280 pitch 5120 (/4 1280) >[477076.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3488d50] >[477076.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3488d50] width 1280 pitch 5120 (/4 1280) >[477076.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a10d0] >[477076.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a10d0] width 1280 pitch 5120 (/4 1280) >[477077.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[477077.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[477077.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bc920] >[477077.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bc920] width 1280 pitch 5120 (/4 1280) >[477077.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb5b0] >[477077.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb5b0] width 1280 pitch 5120 (/4 1280) >[477077.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34727b0] >[477077.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34727b0] width 1280 pitch 5120 (/4 1280) >[477077.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477077.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477077.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf540] >[477077.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf540] width 1280 pitch 5120 (/4 1280) >[477077.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9d10] >[477077.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9d10] width 1280 pitch 5120 (/4 1280) >[477077.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477077.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477077.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477077.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477077.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477077.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477077.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477077.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477077.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477077.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477077.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d2690] >[477077.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d2690] width 1280 pitch 5120 (/4 1280) >[477077.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477077.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477077.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0e40] >[477077.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0e40] width 1280 pitch 5120 (/4 1280) >[477078.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a10d0] >[477078.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a10d0] width 1280 pitch 5120 (/4 1280) >[477078.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0e40] >[477078.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0e40] width 1280 pitch 5120 (/4 1280) >[477078.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a10d0] >[477078.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a10d0] width 1280 pitch 5120 (/4 1280) >[477078.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0e40] >[477078.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0e40] width 1280 pitch 5120 (/4 1280) >[477078.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a10d0] >[477078.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a10d0] width 1280 pitch 5120 (/4 1280) >[477079.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0e40] >[477079.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0e40] width 1280 pitch 5120 (/4 1280) >[477079.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484c20] >[477079.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484c20] width 1280 pitch 5120 (/4 1280) >[477079.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1201770] >[477079.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1201770] width 1280 pitch 5120 (/4 1280) >[477079.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3471740] >[477079.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3471740] width 1280 pitch 5120 (/4 1280) >[477079.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1201770] >[477079.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1201770] width 1280 pitch 5120 (/4 1280) >[477079.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3471740] >[477079.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3471740] width 1280 pitch 5120 (/4 1280) >[477102.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477102.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477102.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477102.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477102.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477103.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477103.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477103.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477103.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477103.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477103.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489f60] >[477103.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489f60] width 1280 pitch 5120 (/4 1280) >[477103.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35acf90] >[477103.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35acf90] width 1280 pitch 5120 (/4 1280) >[477166.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347d530] >[477166.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347d530] width 1280 pitch 5120 (/4 1280) >[477190.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35233c0] >[477190.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35233c0] width 1280 pitch 5120 (/4 1280) >[477190.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35233c0] >[477190.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35233c0] width 1280 pitch 5120 (/4 1280) >[477190.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fff580] >[477190.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fff580] width 1280 pitch 5120 (/4 1280) >[477191.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5000170] >[477191.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5000170] width 1280 pitch 5120 (/4 1280) >[477422.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d3590] >[477422.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d3590] width 1280 pitch 5120 (/4 1280) >[477422.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f890] >[477422.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f890] width 1280 pitch 5120 (/4 1280) >[477430.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50145f0] >[477430.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50145f0] width 1280 pitch 5120 (/4 1280) >[477430.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3481f30] >[477431.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3481f30] width 1280 pitch 5120 (/4 1280) >[477431.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f890] >[477431.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f890] width 1280 pitch 5120 (/4 1280) >[477431.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42dd8f0] >[477431.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42dd8f0] width 1280 pitch 5120 (/4 1280) >[477431.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50145f0] >[477431.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50145f0] width 1280 pitch 5120 (/4 1280) >[477431.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42dd8f0] >[477431.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42dd8f0] width 1280 pitch 5120 (/4 1280) >[477432.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8d060] >[477432.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8d060] width 1280 pitch 5120 (/4 1280) >[477432.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f890] >[477432.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f890] width 1280 pitch 5120 (/4 1280) >[477433.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[477433.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[477433.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8d060] >[477433.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8d060] width 1280 pitch 5120 (/4 1280) >[477515.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e12b0] >[477515.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e12b0] width 1280 pitch 5120 (/4 1280) >[477515.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f9a0] >[477515.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f9a0] width 1280 pitch 5120 (/4 1280) >[477552.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351de40] >[477552.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351de40] width 1280 pitch 5120 (/4 1280) >[477552.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e79c0] >[477552.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e79c0] width 1280 pitch 5120 (/4 1280) >[477607.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f9a0] >[477607.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f9a0] width 1280 pitch 5120 (/4 1280) >[477607.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34edff0] >[477607.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34edff0] width 1280 pitch 5120 (/4 1280) >[477635.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f9a0] >[477635.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f9a0] width 1280 pitch 5120 (/4 1280) >[477732.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351f9a0] >[477732.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351f9a0] width 1280 pitch 5120 (/4 1280) >[477732.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f95300] >[477732.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f95300] width 1280 pitch 5120 (/4 1280) >[477796.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351cf10] >[477796.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351cf10] width 1280 pitch 5120 (/4 1280) >[477818.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d2d0] >[477818.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d2d0] width 1280 pitch 5120 (/4 1280) >[477818.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351cf10] >[477818.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351cf10] width 1280 pitch 5120 (/4 1280) >[477961.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3536c80] >[477961.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3536c80] width 1280 pitch 5120 (/4 1280) >[477962.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e81f0] >[477962.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e81f0] width 1280 pitch 5120 (/4 1280) >[478178.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f96ee0] >[478178.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f96ee0] width 1280 pitch 5120 (/4 1280) >[478245.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478245.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478245.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352ce80] >[478245.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352ce80] width 1280 pitch 5120 (/4 1280) >[478246.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fde5f0] >[478246.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fde5f0] width 1280 pitch 5120 (/4 1280) >[478246.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e81f0] >[478246.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e81f0] width 1280 pitch 5120 (/4 1280) >[478246.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478246.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478246.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e81f0] >[478246.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e81f0] width 1280 pitch 5120 (/4 1280) >[478260.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478260.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478261.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478261.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478261.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478261.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478261.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478261.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478261.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478261.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478261.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478261.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478261.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478261.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478261.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478261.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478261.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478261.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478261.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3538af0] >[478261.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3538af0] width 1280 pitch 5120 (/4 1280) >[478261.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044cf0] >[478262.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044cf0] width 1280 pitch 5120 (/4 1280) >[478262.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34edff0] >[478262.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34edff0] width 1280 pitch 5120 (/4 1280) >[478547.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa22a0] >[478547.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa22a0] width 1280 pitch 5120 (/4 1280) >[478547.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa22a0] >[478547.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa22a0] width 1280 pitch 5120 (/4 1280) >[478699.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478699.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478699.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046ae0] >[478699.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046ae0] width 1280 pitch 5120 (/4 1280) >[478726.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd5f10] >[478726.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd5f10] width 1280 pitch 5120 (/4 1280) >[478726.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd5f10] >[478726.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd5f10] width 1280 pitch 5120 (/4 1280) >[478726.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478726.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478726.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478726.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478726.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478726.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478726.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478726.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478726.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478726.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478726.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478726.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478726.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478727.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc6f60] >[478727.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc6f60] width 1280 pitch 5120 (/4 1280) >[478727.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[478727.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[478728.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3480400] >[478728.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3480400] width 1280 pitch 5120 (/4 1280) >[478728.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046ae0] >[478728.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046ae0] width 1280 pitch 5120 (/4 1280) >[478728.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046ae0] >[478728.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046ae0] width 1280 pitch 5120 (/4 1280) >[478728.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478728.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478728.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478728.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478728.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478728.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478728.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478728.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478728.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478728.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478728.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478728.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478728.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[478728.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[478728.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10] >[478728.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1280 pitch 5120 (/4 1280) >[478731.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x12dc950] >[478731.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x12dc950] width 1280 pitch 5120 (/4 1280) >[478732.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478732.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478732.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475e9e0] >[478732.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475e9e0] width 1280 pitch 5120 (/4 1280) >[478732.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[478732.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[478732.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[478732.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[478732.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4602360] >[478732.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4602360] width 1280 pitch 5120 (/4 1280) >[478732.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0e00] >[478732.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0e00] width 1280 pitch 5120 (/4 1280) >[478732.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[478732.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[478732.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f137a0] >[478732.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f137a0] width 1280 pitch 5120 (/4 1280) >[479127.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fca950] >[479127.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fca950] width 1280 pitch 5120 (/4 1280) >[479128.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46337c0] >[479128.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46337c0] width 1280 pitch 5120 (/4 1280) >[479151.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8130] >[479151.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8130] width 1280 pitch 5120 (/4 1280) >[479152.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411ec70] >[479152.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411ec70] width 1280 pitch 5120 (/4 1280) >[479152.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353e070] >[479152.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353e070] width 1280 pitch 5120 (/4 1280) >[479158.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46337c0] >[479158.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46337c0] width 1280 pitch 5120 (/4 1280) >[479163.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4660d10] >[479163.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4660d10] width 1280 pitch 5120 (/4 1280) >[479259.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a0ff0] >[479259.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a0ff0] width 1280 pitch 5120 (/4 1280) >[479260.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479260.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479348.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2261e60] >[479348.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2261e60] width 1280 pitch 5120 (/4 1280) >[479348.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479348.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479376.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a0ff0] >[479376.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a0ff0] width 1280 pitch 5120 (/4 1280) >[479376.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151fb0] >[479376.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151fb0] width 1280 pitch 5120 (/4 1280) >[479376.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505fc30] >[479376.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505fc30] width 1280 pitch 5120 (/4 1280) >[479376.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd5f10] >[479376.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd5f10] width 1280 pitch 5120 (/4 1280) >[479377.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479377.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479377.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fca950] >[479377.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fca950] width 1280 pitch 5120 (/4 1280) >[479377.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fdf350] >[479377.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fdf350] width 1280 pitch 5120 (/4 1280) >[479377.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479377.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479379.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd5f10] >[479379.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd5f10] width 1280 pitch 5120 (/4 1280) >[479385.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50952b0] >[479385.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50952b0] width 1280 pitch 5120 (/4 1280) >[479385.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b960] >[479385.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b960] width 1280 pitch 5120 (/4 1280) >[479385.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b960] >[479385.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b960] width 1280 pitch 5120 (/4 1280) >[479385.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509ae10] >[479385.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509ae10] width 1280 pitch 5120 (/4 1280) >[479386.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fdf350] >[479386.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fdf350] width 1280 pitch 5120 (/4 1280) >[479386.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479386.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479386.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fca950] >[479386.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fca950] width 1280 pitch 5120 (/4 1280) >[479386.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd7880] >[479386.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd7880] width 1280 pitch 5120 (/4 1280) >[479396.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479396.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479396.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b960] >[479396.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b960] width 1280 pitch 5120 (/4 1280) >[479396.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479396.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479397.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505fc30] >[479397.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505fc30] width 1280 pitch 5120 (/4 1280) >[479397.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479397.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479397.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479397.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479397.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fdf350] >[479397.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fdf350] width 1280 pitch 5120 (/4 1280) >[479397.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35723a0] >[479397.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35723a0] width 1280 pitch 5120 (/4 1280) >[479404.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b960] >[479404.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b960] width 1280 pitch 5120 (/4 1280) >[479404.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479404.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479404.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3adff60] >[479404.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3adff60] width 1280 pitch 5120 (/4 1280) >[479404.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479404.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479404.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479404.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479405.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd7880] >[479405.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd7880] width 1280 pitch 5120 (/4 1280) >[479405.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479405.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479405.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479405.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479460.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479460.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479460.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479460.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479460.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479460.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479460.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479460.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479460.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479460.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479460.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479460.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479460.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479460.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479460.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479460.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479460.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479460.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479460.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479460.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479460.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479460.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479460.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479460.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479464.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479464.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479465.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479465.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479465.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479465.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479465.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479465.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479465.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479465.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479465.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479465.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479465.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x355b7a0] >[479465.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x355b7a0] width 1280 pitch 5120 (/4 1280) >[479465.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420ab10] >[479465.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420ab10] width 1280 pitch 5120 (/4 1280) >[479465.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479465.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479465.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479465.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479465.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f91400] >[479465.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f91400] width 1280 pitch 5120 (/4 1280) >[479465.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fc200] >[479465.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fc200] width 1280 pitch 5120 (/4 1280) >[479465.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479465.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bf30] >[479465.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bf30] width 1280 pitch 5120 (/4 1280) >[479465.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44ae190] >[479465.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44ae190] width 1280 pitch 5120 (/4 1280) >[479517.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092bd0] >[479517.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092bd0] width 1280 pitch 5120 (/4 1280) >[479517.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4054eb0] >[479517.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4054eb0] width 1280 pitch 5120 (/4 1280) >[479630.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x502df00] >[479630.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x502df00] width 1280 pitch 5120 (/4 1280) >[479630.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x502f2f0] >[479630.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x502f2f0] width 1280 pitch 5120 (/4 1280) >[479632.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a470] >[479632.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a470] width 1280 pitch 5120 (/4 1280) >[479632.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5031180] >[479632.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5031180] width 1280 pitch 5120 (/4 1280) >[479632.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4319f60] >[479632.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4319f60] width 1280 pitch 5120 (/4 1280) >[479633.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5031180] >[479633.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5031180] width 1280 pitch 5120 (/4 1280) >[479633.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d760] >[479633.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d760] width 1280 pitch 5120 (/4 1280) >[479664.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5037f40] >[479664.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5037f40] width 1280 pitch 5120 (/4 1280) >[479664.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59e10] >[479664.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59e10] width 1280 pitch 5120 (/4 1280) >[479664.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479664.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479664.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479664.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479724.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd2a60] >[479724.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd2a60] width 1280 pitch 5120 (/4 1280) >[479725.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cb840] >[479725.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cb840] width 1280 pitch 5120 (/4 1280) >[479725.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46cb840] >[479725.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46cb840] width 1280 pitch 5120 (/4 1280) >[479725.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50318f0] >[479725.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50318f0] width 1280 pitch 5120 (/4 1280) >[479725.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061c30] >[479725.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061c30] width 1280 pitch 5120 (/4 1280) >[479726.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd45e0] >[479726.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd45e0] width 1280 pitch 5120 (/4 1280) >[479726.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061c30] >[479727.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061c30] width 1280 pitch 5120 (/4 1280) >[479727.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd45e0] >[479727.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd45e0] width 1280 pitch 5120 (/4 1280) >[479792.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508f210] >[479792.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508f210] width 1280 pitch 5120 (/4 1280) >[479792.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479792.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479792.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd45e0] >[479792.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd45e0] width 1280 pitch 5120 (/4 1280) >[479792.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479792.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479793.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd45e0] >[479793.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd45e0] width 1280 pitch 5120 (/4 1280) >[479793.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479793.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479793.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd45e0] >[479793.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd45e0] width 1280 pitch 5120 (/4 1280) >[479793.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd2a60] >[479793.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd2a60] width 1280 pitch 5120 (/4 1280) >[479793.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd2a60] >[479793.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd2a60] width 1280 pitch 5120 (/4 1280) >[479793.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8e880] >[479794.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8e880] width 1280 pitch 5120 (/4 1280) >[479794.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44add20] >[479794.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44add20] width 1280 pitch 5120 (/4 1280) >[479794.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aac850] >[479794.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aac850] width 1280 pitch 5120 (/4 1280) >[479794.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44add20] >[479794.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44add20] width 1280 pitch 5120 (/4 1280) >[479835.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fcd0] >[479835.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fcd0] width 1280 pitch 5120 (/4 1280) >[479836.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5065b90] >[479836.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5065b90] width 1280 pitch 5120 (/4 1280) >[479863.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479863.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479863.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479863.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479863.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479863.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479863.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479863.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479863.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479863.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479863.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479863.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479863.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479863.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479863.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb1820] >[479863.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb1820] width 1280 pitch 5120 (/4 1280) >[479863.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479863.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479863.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb1820] >[479863.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb1820] width 1280 pitch 5120 (/4 1280) >[479863.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479864.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479864.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb1820] >[479864.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb1820] width 1280 pitch 5120 (/4 1280) >[479864.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479864.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479864.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479864.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479864.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479864.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479864.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fafc80] >[479864.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fafc80] width 1280 pitch 5120 (/4 1280) >[479864.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479864.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479864.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0f10] >[479864.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0f10] width 1280 pitch 5120 (/4 1280) >[479865.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7200] >[479865.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7200] width 1280 pitch 5120 (/4 1280) >[479865.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6a30] >[479865.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6a30] width 1280 pitch 5120 (/4 1280) >[479865.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb71a0] >[479865.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb71a0] width 1280 pitch 5120 (/4 1280) >[479865.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7a70] >[479865.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7a70] width 1280 pitch 5120 (/4 1280) >[479865.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479865.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479865.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479865.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479865.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6a30] >[479865.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6a30] width 1280 pitch 5120 (/4 1280) >[479865.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479865.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479865.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6a30] >[479865.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6a30] width 1280 pitch 5120 (/4 1280) >[479865.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5a50] >[479865.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5a50] width 1280 pitch 5120 (/4 1280) >[479865.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5a50] >[479865.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5a50] width 1280 pitch 5120 (/4 1280) >[479866.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7a70] >[479866.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7a70] width 1280 pitch 5120 (/4 1280) >[479866.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7970] >[479866.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7970] width 1280 pitch 5120 (/4 1280) >[479866.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479866.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479867.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7970] >[479867.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7970] width 1280 pitch 5120 (/4 1280) >[479867.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479867.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479867.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7970] >[479867.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7970] width 1280 pitch 5120 (/4 1280) >[479867.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479867.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479867.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7970] >[479867.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7970] width 1280 pitch 5120 (/4 1280) >[479867.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479867.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479867.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7970] >[479867.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7970] width 1280 pitch 5120 (/4 1280) >[479867.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[479867.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[479912.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba250] >[479912.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba250] width 1280 pitch 5120 (/4 1280) >[479912.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba820] >[479912.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba820] width 1280 pitch 5120 (/4 1280) >[479917.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503d120] >[479917.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503d120] width 1280 pitch 5120 (/4 1280) >[479917.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479917.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479917.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479917.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479917.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479917.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479917.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479917.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479917.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479918.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479918.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479918.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479918.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479918.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479918.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479918.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479918.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479919.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479919.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479919.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479919.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479919.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479919.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479919.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479919.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479919.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479919.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479919.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479919.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479919.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479919.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479919.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479919.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479919.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479919.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479920.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479920.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479920.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479920.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479921.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479921.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479921.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479921.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479921.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479921.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479921.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479921.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479921.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479921.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479921.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479921.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479921.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479921.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479921.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479921.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479921.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479921.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479921.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479921.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479921.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479921.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479921.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479921.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479921.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479922.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479922.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479922.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e64e0] >[479922.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e64e0] width 1280 pitch 5120 (/4 1280) >[479943.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479943.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479953.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479953.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479986.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba450] >[479986.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba450] width 1280 pitch 5120 (/4 1280) >[479986.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479986.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479986.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a9270] >[479986.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a9270] width 1280 pitch 5120 (/4 1280) >[479986.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fc30] >[479986.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fc30] width 1280 pitch 5120 (/4 1280) >[479988.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500ea60] >[479988.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500ea60] width 1280 pitch 5120 (/4 1280) >[480169.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ce10] >[480169.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ce10] width 1280 pitch 5120 (/4 1280) >[480169.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5031f40] >[480169.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5031f40] width 1280 pitch 5120 (/4 1280) >[480322.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5088d40] >[480322.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5088d40] width 1280 pitch 5120 (/4 1280) >[480322.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50855c0] >[480322.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50855c0] width 1280 pitch 5120 (/4 1280) >[480330.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084300] >[480330.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084300] width 1280 pitch 5120 (/4 1280) >[480330.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5081800] >[480330.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5081800] width 1280 pitch 5120 (/4 1280) >[480339.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4660d10] >[480339.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4660d10] width 1280 pitch 5120 (/4 1280) >[480342.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5081d50] >[480342.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5081d50] width 1280 pitch 5120 (/4 1280) >[480343.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091350] >[480343.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091350] width 1280 pitch 5120 (/4 1280) >[480401.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5147460] >[480401.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5147460] width 1280 pitch 5120 (/4 1280) >[480403.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3480] >[480403.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3480] width 1280 pitch 5120 (/4 1280) >[480403.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5147460] >[480403.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5147460] width 1280 pitch 5120 (/4 1280) >[480410.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f5e0] >[480410.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f5e0] width 1280 pitch 5120 (/4 1280) >[480410.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5157e50] >[480410.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5157e50] width 1280 pitch 5120 (/4 1280) >[480413.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51744b0] >[480413.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51744b0] width 1280 pitch 5120 (/4 1280) >[480430.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c00] >[480430.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c00] width 1280 pitch 5120 (/4 1280) >[480488.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515c790] >[480488.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515c790] width 1280 pitch 5120 (/4 1280) >[480488.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ddad0] >[480488.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ddad0] width 1280 pitch 5120 (/4 1280) >[480488.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524f420] >[480488.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524f420] width 1280 pitch 5120 (/4 1280) >[480488.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515c790] >[480488.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515c790] width 1280 pitch 5120 (/4 1280) >[480488.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515be40] >[480488.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515be40] width 1280 pitch 5120 (/4 1280) >[480488.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515d6d0] >[480488.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515d6d0] width 1280 pitch 5120 (/4 1280) >[480488.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ddad0] >[480488.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ddad0] width 1280 pitch 5120 (/4 1280) >[480488.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515d6d0] >[480488.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515d6d0] width 1280 pitch 5120 (/4 1280) >[480488.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ddad0] >[480488.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ddad0] width 1280 pitch 5120 (/4 1280) >[480488.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3480] >[480488.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3480] width 1280 pitch 5120 (/4 1280) >[480488.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ddad0] >[480488.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ddad0] width 1280 pitch 5120 (/4 1280) >[480488.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3480] >[480488.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3480] width 1280 pitch 5120 (/4 1280) >[480488.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ddad0] >[480488.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ddad0] width 1280 pitch 5120 (/4 1280) >[480488.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3480] >[480488.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3480] width 1280 pitch 5120 (/4 1280) >[480502.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480502.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480518.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480518.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480518.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480518.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480669.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480669.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480669.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480669.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480669.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480669.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480670.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480670.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480670.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480670.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480670.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480670.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480670.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480670.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480671.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480671.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480671.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480671.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480671.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cc50] >[480671.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cc50] width 1280 pitch 5120 (/4 1280) >[480671.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x503a480] >[480671.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x503a480] width 1280 pitch 5120 (/4 1280) >[480671.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524f1b0] >[480671.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524f1b0] width 1280 pitch 5120 (/4 1280) >[480831.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x526b190] >[480831.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x526b190] width 1280 pitch 5120 (/4 1280) >[480831.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5178bc0] >[480831.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5178bc0] width 1280 pitch 5120 (/4 1280) >[480923.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480923.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480923.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[480923.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[480923.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[480923.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[480923.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480923.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480923.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[480923.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[480923.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[480923.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[480923.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480923.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480923.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480923.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480923.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480923.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480923.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480924.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480924.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480924.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480924.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480927.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480927.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[480928.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[480928.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[480929.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[480929.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[481533.693] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[481533.693] (II) RADEON(0): Printing DDC gathered Modelines: >[481533.693] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[481623.896] (II) RADEON(0): RADEONSaveScreen(2) >[481623.896] (II) RADEON(0): RADEONSaveScreen(0) >[485550.837] (II) RADEON(0): RADEONSaveScreen(1) >[485555.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[485555.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[485556.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34496c0] >[485556.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34496c0] width 1280 pitch 5120 (/4 1280) >[485556.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34496c0] >[485556.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34496c0] width 1280 pitch 5120 (/4 1280) >[485556.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34496c0] >[485556.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34496c0] width 1280 pitch 5120 (/4 1280) >[485556.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515c260] >[485556.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515c260] width 1280 pitch 5120 (/4 1280) >[485556.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[485556.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[485556.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091350] >[485556.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091350] width 1280 pitch 5120 (/4 1280) >[485557.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b4e0f0] >[485557.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b4e0f0] width 1280 pitch 5120 (/4 1280) >[485557.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5440] >[485557.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5440] width 1280 pitch 5120 (/4 1280) >[485562.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[485562.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[485563.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34496c0] >[485563.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34496c0] width 1280 pitch 5120 (/4 1280) >[485563.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091350] >[485563.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091350] width 1280 pitch 5120 (/4 1280) >[485563.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34496c0] >[485563.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34496c0] width 1280 pitch 5120 (/4 1280) >[485563.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091350] >[485563.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091350] width 1280 pitch 5120 (/4 1280) >[485565.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ac20] >[485565.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ac20] width 1280 pitch 5120 (/4 1280) >[485565.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091350] >[485565.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091350] width 1280 pitch 5120 (/4 1280) >[485565.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527bc20] >[485565.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527bc20] width 1280 pitch 5120 (/4 1280) >[485705.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515cec0] >[485705.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515cec0] width 1280 pitch 5120 (/4 1280) >[485705.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ceb80] >[485705.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ceb80] width 1280 pitch 5120 (/4 1280) >[485714.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34305a0] >[485714.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34305a0] width 1280 pitch 5120 (/4 1280) >[485792.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353c0e0] >[485792.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353c0e0] width 1280 pitch 5120 (/4 1280) >[485792.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8f60] >[485792.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8f60] width 1280 pitch 5120 (/4 1280) >[485829.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252ff0] >[485829.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252ff0] width 1280 pitch 5120 (/4 1280) >[485830.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252ff0] >[485830.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252ff0] width 1280 pitch 5120 (/4 1280) >[485839.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x516bd70] >[485839.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x516bd70] width 1280 pitch 5120 (/4 1280) >[485845.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x516bd70] >[485845.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x516bd70] width 1280 pitch 5120 (/4 1280) >[485868.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252ff0] >[485868.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252ff0] width 1280 pitch 5120 (/4 1280) >[485868.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5275b90] >[485868.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5275b90] width 1280 pitch 5120 (/4 1280) >[486124.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51643a0] >[486124.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51643a0] width 1280 pitch 5120 (/4 1280) >[486127.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51643a0] >[486127.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51643a0] width 1280 pitch 5120 (/4 1280) >[486727.882] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[486727.882] (II) RADEON(0): Printing DDC gathered Modelines: >[486727.882] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[486817.886] (II) RADEON(0): RADEONSaveScreen(2) >[486817.886] (II) RADEON(0): RADEONSaveScreen(0) >[489919.851] (II) RADEON(0): RADEONSaveScreen(1) >[489927.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489927.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489928.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489928.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489928.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489928.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489929.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489929.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489929.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489929.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489929.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489929.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489929.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489929.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489929.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489929.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489930.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489930.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489931.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489931.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489931.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489931.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489931.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489932.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489932.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489932.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489932.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489932.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489932.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9b60] >[489932.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9b60] width 1280 pitch 5120 (/4 1280) >[489932.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489932.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489932.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9b60] >[489932.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9b60] width 1280 pitch 5120 (/4 1280) >[489932.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513e7f0] >[489932.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513e7f0] width 1280 pitch 5120 (/4 1280) >[489946.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489946.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489946.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249d70] >[489946.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249d70] width 1280 pitch 5120 (/4 1280) >[489947.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489947.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489947.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249d70] >[489947.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249d70] width 1280 pitch 5120 (/4 1280) >[489947.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489947.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489947.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489947.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489947.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489947.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489947.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489947.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489947.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489947.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489947.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489947.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489947.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489947.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489947.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489947.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489948.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489948.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489948.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489948.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489948.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489948.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489948.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489948.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489948.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489948.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489948.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489948.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489948.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489948.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489948.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489948.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489948.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489948.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489948.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489948.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489948.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489948.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489948.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489948.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489948.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489948.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489948.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489948.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489948.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489948.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489948.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489948.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489948.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489951.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489951.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489951.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489951.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489951.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489951.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489951.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249d70] >[489951.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249d70] width 1280 pitch 5120 (/4 1280) >[489951.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489951.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489951.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249d70] >[489951.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249d70] width 1280 pitch 5120 (/4 1280) >[489951.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489951.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489951.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249d70] >[489951.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249d70] width 1280 pitch 5120 (/4 1280) >[489951.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5276c90] >[489951.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5276c90] width 1280 pitch 5120 (/4 1280) >[489951.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489951.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489951.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489951.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489951.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489951.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489952.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489952.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249a70] >[489952.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249a70] width 1280 pitch 5120 (/4 1280) >[489952.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489952.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489952.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489952.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489952.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489952.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489952.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489952.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489952.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489952.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489952.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489952.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489954.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489954.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489956.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5155630] >[489956.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5155630] width 1280 pitch 5120 (/4 1280) >[489956.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489956.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489956.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cee60] >[489956.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cee60] width 1280 pitch 5120 (/4 1280) >[489956.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3471670] >[489956.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3471670] width 1280 pitch 5120 (/4 1280) >[489956.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cee60] >[489956.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cee60] width 1280 pitch 5120 (/4 1280) >[489956.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248ff0] >[489956.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248ff0] width 1280 pitch 5120 (/4 1280) >[489957.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489957.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489957.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489957.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489957.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489957.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489957.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[489957.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[489957.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489957.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489958.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eccf0] >[489958.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eccf0] width 1280 pitch 5120 (/4 1280) >[489958.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489958.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489958.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3300] >[489958.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3300] width 1280 pitch 5120 (/4 1280) >[489958.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489958.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489958.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5159210] >[489958.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5159210] width 1280 pitch 5120 (/4 1280) >[489958.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489958.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489958.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5159210] >[489958.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5159210] width 1280 pitch 5120 (/4 1280) >[489961.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514d7c0] >[489961.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514d7c0] width 1280 pitch 5120 (/4 1280) >[489961.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489961.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[489963.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489963.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489964.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489964.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489964.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489964.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489964.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489964.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489964.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489964.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[489964.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[489965.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489965.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489971.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5161bb0] >[489971.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5161bb0] width 1280 pitch 5120 (/4 1280) >[489972.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489972.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489972.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5161bb0] >[489972.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5161bb0] width 1280 pitch 5120 (/4 1280) >[489972.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489972.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489972.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5161bb0] >[489972.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5161bb0] width 1280 pitch 5120 (/4 1280) >[489973.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[489973.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[489973.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5155630] >[489973.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5155630] width 1280 pitch 5120 (/4 1280) >[489973.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489973.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489973.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5155630] >[489973.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5155630] width 1280 pitch 5120 (/4 1280) >[489973.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x515af80] >[489973.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x515af80] width 1280 pitch 5120 (/4 1280) >[489973.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[489973.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[490003.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[490003.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[490015.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x526eb40] >[490015.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x526eb40] width 1280 pitch 5120 (/4 1280) >[490015.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5247480] >[490015.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5247480] width 1280 pitch 5120 (/4 1280) >[490016.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5279f20] >[490016.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5279f20] width 1280 pitch 5120 (/4 1280) >[490016.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42f0830] >[490016.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42f0830] width 1280 pitch 5120 (/4 1280) >[490016.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x526eb40] >[490016.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x526eb40] width 1280 pitch 5120 (/4 1280) >[490016.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5170f50] >[490016.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5170f50] width 1280 pitch 5120 (/4 1280) >[490016.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35321c0] >[490016.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35321c0] width 1280 pitch 5120 (/4 1280) >[490016.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5170f50] >[490016.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5170f50] width 1280 pitch 5120 (/4 1280) >[490017.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eccf0] >[490018.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eccf0] width 1280 pitch 5120 (/4 1280) >[490018.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eccf0] >[490018.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eccf0] width 1280 pitch 5120 (/4 1280) >[490018.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5279f20] >[490018.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5279f20] width 1280 pitch 5120 (/4 1280) >[490018.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eccf0] >[490018.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eccf0] width 1280 pitch 5120 (/4 1280) >[490018.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5279f20] >[490018.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5279f20] width 1280 pitch 5120 (/4 1280) >[490018.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5170f50] >[490018.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5170f50] width 1280 pitch 5120 (/4 1280) >[490020.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5170f50] >[490020.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5170f50] width 1280 pitch 5120 (/4 1280) >[490020.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x514e600] >[490020.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x514e600] width 1280 pitch 5120 (/4 1280) >[490020.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e5040] >[490020.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e5040] width 1280 pitch 5120 (/4 1280) >[490020.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e5040] >[490020.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e5040] width 1280 pitch 5120 (/4 1280) >[490020.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490020.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490020.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490020.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490020.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490020.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490020.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490020.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490020.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490020.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490020.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490020.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490021.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490021.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490021.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ab4f0] >[490021.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ab4f0] width 1280 pitch 5120 (/4 1280) >[490021.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502480] >[490021.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502480] width 1280 pitch 5120 (/4 1280) >[490021.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[490021.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[490021.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[490021.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[490021.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034fb0] >[490021.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034fb0] width 1280 pitch 5120 (/4 1280) >[490022.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[490022.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[490022.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[490022.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[490023.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[490023.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[490024.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41cdab0] >[490024.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41cdab0] width 1280 pitch 5120 (/4 1280) >[490025.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[490025.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[490025.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[490025.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[490025.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2218130] >[490025.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2218130] width 1280 pitch 5120 (/4 1280) >[490025.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40aa570] >[490025.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40aa570] width 1280 pitch 5120 (/4 1280) >[490026.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2218130] >[490026.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2218130] width 1280 pitch 5120 (/4 1280) >[490026.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40aa570] >[490026.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40aa570] width 1280 pitch 5120 (/4 1280) >[490099.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35762b0] >[490099.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35762b0] width 1280 pitch 5120 (/4 1280) >[490099.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490099.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490099.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19ab4f0] >[490099.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19ab4f0] width 1280 pitch 5120 (/4 1280) >[490100.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502480] >[490100.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502480] width 1280 pitch 5120 (/4 1280) >[490100.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4716470] >[490100.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4716470] width 1280 pitch 5120 (/4 1280) >[490100.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502480] >[490100.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502480] width 1280 pitch 5120 (/4 1280) >[490100.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4716470] >[490100.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4716470] width 1280 pitch 5120 (/4 1280) >[490100.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502480] >[490100.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502480] width 1280 pitch 5120 (/4 1280) >[490101.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[490101.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[490102.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x454f430] >[490102.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x454f430] width 1280 pitch 5120 (/4 1280) >[490102.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[490102.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[490102.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[490102.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[490103.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[490103.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[490103.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41cdab0] >[490103.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41cdab0] width 1280 pitch 5120 (/4 1280) >[490103.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[490103.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[490104.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[490104.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[490104.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d450] >[490104.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d450] width 1280 pitch 5120 (/4 1280) >[490104.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5b80] >[490104.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5b80] width 1280 pitch 5120 (/4 1280) >[490104.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409d450] >[490104.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409d450] width 1280 pitch 5120 (/4 1280) >[490104.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5b80] >[490104.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5b80] width 1280 pitch 5120 (/4 1280) >[490104.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[490104.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[490124.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[490124.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[490125.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6290] >[490125.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6290] width 1280 pitch 5120 (/4 1280) >[490125.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[490125.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[490125.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3267190] >[490125.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3267190] width 1280 pitch 5120 (/4 1280) >[490125.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11ac4b0] >[490125.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11ac4b0] width 1280 pitch 5120 (/4 1280) >[490125.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2ee90] >[490125.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2ee90] width 1280 pitch 5120 (/4 1280) >[490125.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[490125.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[490145.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e1c10] >[490145.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e1c10] width 1280 pitch 5120 (/4 1280) >[490146.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[490146.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[490146.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[490146.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[490146.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460bf0] >[490146.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460bf0] width 1280 pitch 5120 (/4 1280) >[490146.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[490147.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[490147.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460bf0] >[490147.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460bf0] width 1280 pitch 5120 (/4 1280) >[490147.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[490147.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[490148.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460bf0] >[490148.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460bf0] width 1280 pitch 5120 (/4 1280) >[490148.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[490148.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[490149.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7400] >[490149.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7400] width 1280 pitch 5120 (/4 1280) >[490149.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[490149.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[490149.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45e3450] >[490149.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45e3450] width 1280 pitch 5120 (/4 1280) >[490149.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1371da0] >[490149.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1371da0] width 1280 pitch 5120 (/4 1280) >[490149.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b990] >[490149.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b990] width 1280 pitch 5120 (/4 1280) >[490182.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490182.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490182.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[490182.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[490182.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490182.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490182.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[490182.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[490182.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490182.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490182.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[490182.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[490183.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490183.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490184.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[490184.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[490184.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490184.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490184.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3416500] >[490184.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3416500] width 1280 pitch 5120 (/4 1280) >[490184.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca890] >[490184.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca890] width 1280 pitch 5120 (/4 1280) >[490184.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[490184.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[490185.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11b5b80] >[490185.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11b5b80] width 1280 pitch 5120 (/4 1280) >[490185.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4497390] >[490185.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4497390] width 1280 pitch 5120 (/4 1280) >[490185.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[490185.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[490185.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a15ac0] >[490185.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a15ac0] width 1280 pitch 5120 (/4 1280) >[490185.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[490185.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[490186.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a15ac0] >[490186.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a15ac0] width 1280 pitch 5120 (/4 1280) >[490186.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[490186.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[490186.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a15ac0] >[490186.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a15ac0] width 1280 pitch 5120 (/4 1280) >[490186.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd8e0] >[490186.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd8e0] width 1280 pitch 5120 (/4 1280) >[490186.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42387b0] >[490186.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42387b0] width 1280 pitch 5120 (/4 1280) >[490186.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3515be0] >[490186.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3515be0] width 1280 pitch 5120 (/4 1280) >[490187.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bda0] >[490187.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bda0] width 1280 pitch 5120 (/4 1280) >[490187.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ec88d0] >[490187.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ec88d0] width 1280 pitch 5120 (/4 1280) >[490196.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1371da0] >[490196.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1371da0] width 1280 pitch 5120 (/4 1280) >[490196.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400c000] >[490196.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400c000] width 1280 pitch 5120 (/4 1280) >[490286.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[490286.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[490286.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45818d0] >[490286.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45818d0] width 1280 pitch 5120 (/4 1280) >[490300.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5058290] >[490300.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5058290] width 1280 pitch 5120 (/4 1280) >[490348.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58850] >[490348.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58850] width 1280 pitch 5120 (/4 1280) >[490349.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x128ce90] >[490349.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x128ce90] width 1280 pitch 5120 (/4 1280) >[490349.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46db890] >[490349.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46db890] width 1280 pitch 5120 (/4 1280) >[490349.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[490349.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[490458.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bec0] >[490458.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bec0] width 1280 pitch 5120 (/4 1280) >[490547.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df8640] >[490547.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df8640] width 1280 pitch 5120 (/4 1280) >[490547.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2311c10] >[490547.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2311c10] width 1280 pitch 5120 (/4 1280) >[490547.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f82da0] >[490547.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f82da0] width 1280 pitch 5120 (/4 1280) >[490547.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41e5040] >[490547.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41e5040] width 1280 pitch 5120 (/4 1280) >[490547.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5180] >[490547.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5180] width 1280 pitch 5120 (/4 1280) >[490548.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e92b0] >[490548.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e92b0] width 1280 pitch 5120 (/4 1280) >[490548.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x114b160] >[490548.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x114b160] width 1280 pitch 5120 (/4 1280) >[490548.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[490548.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[490548.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4eb0] >[490548.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4eb0] width 1280 pitch 5120 (/4 1280) >[490548.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[490548.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[490548.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41cdab0] >[490548.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41cdab0] width 1280 pitch 5120 (/4 1280) >[490548.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c15b10] >[490548.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c15b10] width 1280 pitch 5120 (/4 1280) >[490548.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aeaa0] >[490548.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aeaa0] width 1280 pitch 5120 (/4 1280) >[490565.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3592f00] >[490565.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3592f00] width 1280 pitch 5120 (/4 1280) >[490565.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400bdc0] >[490565.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400bdc0] width 1280 pitch 5120 (/4 1280) >[490565.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b27500] >[490565.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b27500] width 1280 pitch 5120 (/4 1280) >[490655.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490655.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490655.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7670] >[490655.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7670] width 1280 pitch 5120 (/4 1280) >[490655.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490655.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490655.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7670] >[490655.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7670] width 1280 pitch 5120 (/4 1280) >[490655.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490655.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490655.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7670] >[490655.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7670] width 1280 pitch 5120 (/4 1280) >[490655.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490655.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490655.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7670] >[490655.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7670] width 1280 pitch 5120 (/4 1280) >[490656.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490656.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490656.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee7670] >[490657.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee7670] width 1280 pitch 5120 (/4 1280) >[490657.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ef60] >[490657.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ef60] width 1280 pitch 5120 (/4 1280) >[490658.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1371da0] >[490658.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1371da0] width 1280 pitch 5120 (/4 1280) >[490658.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2a40] >[490658.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2a40] width 1280 pitch 5120 (/4 1280) >[490658.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b2dd0] >[490658.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b2dd0] width 1280 pitch 5120 (/4 1280) >[490658.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[490658.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[490775.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[490775.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[490775.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd69c0] >[490775.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd69c0] width 1280 pitch 5120 (/4 1280) >[490776.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490776.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490776.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490776.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490776.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490776.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490776.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490776.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490776.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490776.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490776.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490776.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490777.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490777.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490777.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d567d0] >[490777.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d567d0] width 1280 pitch 5120 (/4 1280) >[490777.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490778.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490778.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490778.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490778.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490778.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490778.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490778.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490778.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[490778.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[490779.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490779.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490779.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[490779.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[490779.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4054eb0] >[490779.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4054eb0] width 1280 pitch 5120 (/4 1280) >[490779.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9c50] >[490779.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9c50] width 1280 pitch 5120 (/4 1280) >[490779.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4054eb0] >[490779.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4054eb0] width 1280 pitch 5120 (/4 1280) >[490779.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x420bda0] >[490779.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x420bda0] width 1280 pitch 5120 (/4 1280) >[490779.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[490779.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[490780.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5d90] >[490780.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5d90] width 1280 pitch 5120 (/4 1280) >[490780.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34098a0] >[490780.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34098a0] width 1280 pitch 5120 (/4 1280) >[490781.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ba010] >[490781.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ba010] width 1280 pitch 5120 (/4 1280) >[490781.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[490781.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[490781.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[490781.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[490781.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[490781.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[490781.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[490781.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[490781.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[490781.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[490782.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[490782.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[490782.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[490782.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[490782.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[490782.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[490782.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc0b0] >[490782.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc0b0] width 1280 pitch 5120 (/4 1280) >[490782.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d15d0] >[490783.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d15d0] width 1280 pitch 5120 (/4 1280) >[490783.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1273a90] >[490783.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1273a90] width 1280 pitch 5120 (/4 1280) >[490783.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3489a80] >[490783.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3489a80] width 1280 pitch 5120 (/4 1280) >[490783.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4faffb0] >[490783.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4faffb0] width 1280 pitch 5120 (/4 1280) >[491375.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fef90] >[491375.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fef90] width 1280 pitch 5120 (/4 1280) >[492008.178] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[492008.178] (II) RADEON(0): Printing DDC gathered Modelines: >[492008.178] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[492332.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5155630] >[492332.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5155630] width 1280 pitch 5120 (/4 1280) >[492932.272] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[492932.272] (II) RADEON(0): Printing DDC gathered Modelines: >[492932.272] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[492936.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8070] >[492936.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8070] width 1280 pitch 5120 (/4 1280) >[493535.819] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[493535.819] (II) RADEON(0): Printing DDC gathered Modelines: >[493535.819] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[493697.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34da520] >[493697.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34da520] width 1280 pitch 5120 (/4 1280) >[493697.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11fd2f0] >[493697.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11fd2f0] width 1280 pitch 5120 (/4 1280) >[493745.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[493745.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[493745.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493745.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493745.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[493745.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[493746.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493746.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493746.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebda70] >[493746.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebda70] width 1280 pitch 5120 (/4 1280) >[493746.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493746.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493747.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3557930] >[493747.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3557930] width 1280 pitch 5120 (/4 1280) >[493747.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493747.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493747.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3557930] >[493747.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3557930] width 1280 pitch 5120 (/4 1280) >[493747.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493747.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493747.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3557930] >[493747.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3557930] width 1280 pitch 5120 (/4 1280) >[493747.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35af360] >[493747.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35af360] width 1280 pitch 5120 (/4 1280) >[493747.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ca890] >[493747.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ca890] width 1280 pitch 5120 (/4 1280) >[493747.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2ee90] >[493747.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2ee90] width 1280 pitch 5120 (/4 1280) >[493748.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2218130] >[493748.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2218130] width 1280 pitch 5120 (/4 1280) >[493748.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5275b90] >[493748.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5275b90] width 1280 pitch 5120 (/4 1280) >[493748.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[493748.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[493748.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5275b90] >[493748.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5275b90] width 1280 pitch 5120 (/4 1280) >[493749.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85af0] >[493749.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85af0] width 1280 pitch 5120 (/4 1280) >[493750.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5275b90] >[493750.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5275b90] width 1280 pitch 5120 (/4 1280) >[493751.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[493751.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[493751.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[493751.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[493751.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[493751.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[493751.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[493751.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[493751.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1187780] >[493751.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1187780] width 1280 pitch 5120 (/4 1280) >[493751.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493751.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493751.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[493751.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[493756.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[493756.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[493757.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[493757.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[493757.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[493757.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[493757.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[493757.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[493757.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[493757.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[493757.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400e2d0] >[493757.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400e2d0] width 1280 pitch 5120 (/4 1280) >[493757.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[493757.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[493757.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[493757.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[493757.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f945b0] >[493757.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f945b0] width 1280 pitch 5120 (/4 1280) >[493757.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eea80] >[493757.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eea80] width 1280 pitch 5120 (/4 1280) >[493757.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493757.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493757.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493757.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493757.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493757.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493757.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493757.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493758.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17da0] >[493758.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17da0] width 1280 pitch 5120 (/4 1280) >[493758.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46d7510] >[493758.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46d7510] width 1280 pitch 5120 (/4 1280) >[493759.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x134d850] >[493759.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x134d850] width 1280 pitch 5120 (/4 1280) >[493759.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d700] >[493759.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d700] width 1280 pitch 5120 (/4 1280) >[493759.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d23d50] >[493759.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d23d50] width 1280 pitch 5120 (/4 1280) >[493759.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493759.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493759.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493759.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493759.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493759.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493759.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493760.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493760.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493760.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493760.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493760.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40068b0] >[493760.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40068b0] width 1280 pitch 5120 (/4 1280) >[493760.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[493760.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[493767.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493767.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493767.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[493767.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[493767.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493767.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493768.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[493768.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[493768.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493768.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493768.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[493768.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[493768.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493768.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493768.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x122d540] >[493768.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x122d540] width 1280 pitch 5120 (/4 1280) >[493769.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e2ce10] >[493769.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e2ce10] width 1280 pitch 5120 (/4 1280) >[493769.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400c000] >[493769.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400c000] width 1280 pitch 5120 (/4 1280) >[493769.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[493769.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[493769.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[493769.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[493769.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e568e0] >[493769.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e568e0] width 1280 pitch 5120 (/4 1280) >[493769.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35938a0] >[493769.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35938a0] width 1280 pitch 5120 (/4 1280) >[493891.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[493891.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[493891.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477cea0] >[493891.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477cea0] width 1280 pitch 5120 (/4 1280) >[494113.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[494113.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[494113.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494113.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494113.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494113.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494114.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494114.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494114.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494114.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494114.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494114.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494114.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494114.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494114.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494114.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494114.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494114.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494114.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494114.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494114.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494114.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494114.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e3fd0] >[494114.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e3fd0] width 1280 pitch 5120 (/4 1280) >[494114.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443ccb0] >[494114.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443ccb0] width 1280 pitch 5120 (/4 1280) >[494115.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494115.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[494115.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[494115.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494115.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[494115.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[494115.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494115.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[494115.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[494115.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494115.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[494115.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[494115.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494115.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4497390] >[494115.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4497390] width 1280 pitch 5120 (/4 1280) >[494115.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bf6550] >[494115.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bf6550] width 1280 pitch 5120 (/4 1280) >[494116.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494116.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494116.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50439c0] >[494116.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50439c0] width 1280 pitch 5120 (/4 1280) >[494116.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494116.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494116.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50439c0] >[494116.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50439c0] width 1280 pitch 5120 (/4 1280) >[494116.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494116.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494116.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50439c0] >[494116.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50439c0] width 1280 pitch 5120 (/4 1280) >[494116.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494116.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494116.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50439c0] >[494116.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50439c0] width 1280 pitch 5120 (/4 1280) >[494116.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494116.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494116.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50439c0] >[494116.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50439c0] width 1280 pitch 5120 (/4 1280) >[494117.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494117.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494117.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218a840] >[494117.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218a840] width 1280 pitch 5120 (/4 1280) >[494117.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[494117.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[494117.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f85d60] >[494117.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f85d60] width 1280 pitch 5120 (/4 1280) >[494117.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42e1570] >[494117.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42e1570] width 1280 pitch 5120 (/4 1280) >[494117.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f85d60] >[494117.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f85d60] width 1280 pitch 5120 (/4 1280) >[494718.960] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[494718.960] (II) RADEON(0): Printing DDC gathered Modelines: >[494718.960] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[494808.890] (II) RADEON(0): RADEONSaveScreen(2) >[494808.890] (II) RADEON(0): RADEONSaveScreen(0) >[518636.126] (II) RADEON(0): RADEONSaveScreen(1) >[518656.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ba010] >[518656.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ba010] width 1280 pitch 5120 (/4 1280) >[518660.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e788e0] >[518660.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e788e0] width 1280 pitch 5120 (/4 1280) >[518661.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[518661.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[518661.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e788e0] >[518661.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e788e0] width 1280 pitch 5120 (/4 1280) >[518661.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[518661.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[518661.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e788e0] >[518661.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e788e0] width 1280 pitch 5120 (/4 1280) >[518661.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3a50] >[518661.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3a50] width 1280 pitch 5120 (/4 1280) >[518662.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e788e0] >[518662.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e788e0] width 1280 pitch 5120 (/4 1280) >[518662.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41ea180] >[518662.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41ea180] width 1280 pitch 5120 (/4 1280) >[518662.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[518662.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[518662.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd2490] >[518662.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd2490] width 1280 pitch 5120 (/4 1280) >[518662.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[518662.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[518662.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd2490] >[518662.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd2490] width 1280 pitch 5120 (/4 1280) >[518662.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[518662.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[518791.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4203980] >[518791.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4203980] width 1280 pitch 5120 (/4 1280) >[518791.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470f050] >[518791.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470f050] width 1280 pitch 5120 (/4 1280) >[518804.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9c50] >[518804.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9c50] width 1280 pitch 5120 (/4 1280) >[518804.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2ee90] >[518804.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2ee90] width 1280 pitch 5120 (/4 1280) >[518866.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5248cf0] >[518866.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5248cf0] width 1280 pitch 5120 (/4 1280) >[518866.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[518866.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[518895.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89070] >[518895.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89070] width 1280 pitch 5120 (/4 1280) >[519775.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519775.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519775.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519775.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519775.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519775.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519775.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519775.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519775.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519775.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519775.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519775.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519775.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519775.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519775.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519775.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519775.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519776.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519776.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519776.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519776.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519776.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519776.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519777.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519777.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519777.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519777.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519777.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519777.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519777.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519777.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519777.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519777.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519777.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519777.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519777.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519777.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519777.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519777.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519777.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519778.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519778.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519779.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519779.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519779.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519779.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519779.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519779.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519779.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519779.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519779.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519779.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519779.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519779.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519779.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519779.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519779.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519779.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519783.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519783.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519792.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[519792.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[519792.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519792.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519825.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519825.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519826.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519826.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519826.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114210] >[519826.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114210] width 1280 pitch 5120 (/4 1280) >[519826.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519826.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519826.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38cf0] >[519826.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38cf0] width 1280 pitch 5120 (/4 1280) >[519827.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519827.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519827.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519827.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519827.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525a620] >[519827.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525a620] width 1280 pitch 5120 (/4 1280) >[519827.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x414d2a0] >[519828.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x414d2a0] width 1280 pitch 5120 (/4 1280) >[519828.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[519828.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[519836.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[519836.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[519836.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[519836.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[519836.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e980] >[519836.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e980] width 1280 pitch 5120 (/4 1280) >[519837.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e67570] >[519837.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e67570] width 1280 pitch 5120 (/4 1280) >[519837.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e67570] >[519837.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e67570] width 1280 pitch 5120 (/4 1280) >[519840.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[519840.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[519840.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358f930] >[519840.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358f930] width 1280 pitch 5120 (/4 1280) >[519840.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e6f0] >[519840.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e6f0] width 1280 pitch 5120 (/4 1280) >[519840.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[519840.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[519840.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4c30] >[519840.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4c30] width 1280 pitch 5120 (/4 1280) >[519840.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[519840.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[519848.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ec2e0] >[519848.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ec2e0] width 1280 pitch 5120 (/4 1280) >[519848.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[519848.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[519848.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b345d0] >[519848.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b345d0] width 1280 pitch 5120 (/4 1280) >[519848.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[519848.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[519848.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b345d0] >[519848.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b345d0] width 1280 pitch 5120 (/4 1280) >[519856.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x448e0e0] >[519856.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x448e0e0] width 1280 pitch 5120 (/4 1280) >[519856.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf8550] >[519856.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf8550] width 1280 pitch 5120 (/4 1280) >[519856.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5261eb0] >[519856.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5261eb0] width 1280 pitch 5120 (/4 1280) >[519856.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf8550] >[519856.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf8550] width 1280 pitch 5120 (/4 1280) >[519856.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5261eb0] >[519856.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5261eb0] width 1280 pitch 5120 (/4 1280) >[519856.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[519856.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[519894.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[519894.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[519894.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[519894.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[519909.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[519909.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[519910.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c170] >[519910.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c170] width 1280 pitch 5120 (/4 1280) >[519938.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[519938.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[520085.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525cec0] >[520085.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525cec0] width 1280 pitch 5120 (/4 1280) >[520085.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520085.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520085.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525cec0] >[520085.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525cec0] width 1280 pitch 5120 (/4 1280) >[520085.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520085.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520085.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520085.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520085.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520085.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520085.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520085.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520085.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520085.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520085.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520085.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520085.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525cec0] >[520085.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525cec0] width 1280 pitch 5120 (/4 1280) >[520085.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520085.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520085.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525cec0] >[520085.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525cec0] width 1280 pitch 5120 (/4 1280) >[520086.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520086.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520086.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520086.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520086.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520087.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520087.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520087.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520087.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520087.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520087.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520087.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520087.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131560] >[520087.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131560] width 1280 pitch 5120 (/4 1280) >[520087.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520087.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520088.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520088.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520088.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520088.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520129.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520129.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520130.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520130.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520130.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520130.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520131.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520131.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520131.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520131.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520131.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520131.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520131.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520131.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520131.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520131.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520131.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520131.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[520131.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[520132.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525b030] >[520132.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525b030] width 1280 pitch 5120 (/4 1280) >[520132.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaf7b0] >[520132.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaf7b0] width 1280 pitch 5120 (/4 1280) >[520132.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525cec0] >[520132.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525cec0] width 1280 pitch 5120 (/4 1280) >[520132.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114760] >[520132.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114760] width 1280 pitch 5120 (/4 1280) >[520132.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[520132.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[520132.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131a10] >[520132.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131a10] width 1280 pitch 5120 (/4 1280) >[520132.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e207d0] >[520132.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e207d0] width 1280 pitch 5120 (/4 1280) >[520132.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520132.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520132.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520132.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520132.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520133.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520133.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520133.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520133.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520133.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520133.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b0d0] >[520133.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b0d0] width 1280 pitch 5120 (/4 1280) >[520133.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513b440] >[520133.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513b440] width 1280 pitch 5120 (/4 1280) >[520142.822] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[520142.822] (II) RADEON(0): Printing DDC gathered Modelines: >[520142.822] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[520149.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114760] >[520149.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114760] width 1280 pitch 5120 (/4 1280) >[520742.678] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[520742.678] (II) RADEON(0): Printing DDC gathered Modelines: >[520742.678] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[520832.893] (II) RADEON(0): RADEONSaveScreen(2) >[520832.893] (II) RADEON(0): RADEONSaveScreen(0) >[534381.257] (II) RADEON(0): RADEONSaveScreen(1) >[534385.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422dd30] >[534385.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422dd30] width 1280 pitch 5120 (/4 1280) >[534396.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402c270] >[534396.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402c270] width 1280 pitch 5120 (/4 1280) >[534419.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402c270] >[534419.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402c270] width 1280 pitch 5120 (/4 1280) >[534467.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130ba0] >[534467.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130ba0] width 1280 pitch 5120 (/4 1280) >[534467.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ebd70] >[534467.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ebd70] width 1280 pitch 5120 (/4 1280) >[534502.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed7c0] >[534502.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed7c0] width 1280 pitch 5120 (/4 1280) >[534502.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6be10] >[534502.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6be10] width 1280 pitch 5120 (/4 1280) >[534502.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6be10] >[534502.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6be10] width 1280 pitch 5120 (/4 1280) >[534502.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114cf0] >[534502.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114cf0] width 1280 pitch 5120 (/4 1280) >[534504.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6df0] >[534504.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6df0] width 1280 pitch 5120 (/4 1280) >[534505.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2536dc0] >[534505.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2536dc0] width 1280 pitch 5120 (/4 1280) >[534507.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114cf0] >[534507.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114cf0] width 1280 pitch 5120 (/4 1280) >[534594.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6daa0] >[534594.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6daa0] width 1280 pitch 5120 (/4 1280) >[534594.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9240] >[534594.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9240] width 1280 pitch 5120 (/4 1280) >[534594.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6daa0] >[534594.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6daa0] width 1280 pitch 5120 (/4 1280) >[534594.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9240] >[534594.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9240] width 1280 pitch 5120 (/4 1280) >[534608.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b70f70] >[534608.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b70f70] width 1280 pitch 5120 (/4 1280) >[534608.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6daa0] >[534608.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6daa0] width 1280 pitch 5120 (/4 1280) >[534611.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b7e2d0] >[534611.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b7e2d0] width 1280 pitch 5120 (/4 1280) >[534613.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52afed0] >[534613.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52afed0] width 1280 pitch 5120 (/4 1280) >[534613.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52afed0] >[534613.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52afed0] width 1280 pitch 5120 (/4 1280) >[534613.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b7e2d0] >[534614.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b7e2d0] width 1280 pitch 5120 (/4 1280) >[534614.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51464d0] >[534614.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51464d0] width 1280 pitch 5120 (/4 1280) >[534614.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df370] >[534614.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df370] width 1280 pitch 5120 (/4 1280) >[534614.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b08f0] >[534614.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b08f0] width 1280 pitch 5120 (/4 1280) >[534614.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df370] >[534614.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df370] width 1280 pitch 5120 (/4 1280) >[534615.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b08f0] >[534615.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b08f0] width 1280 pitch 5120 (/4 1280) >[534698.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528a480] >[534698.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528a480] width 1280 pitch 5120 (/4 1280) >[534699.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b4610] >[534699.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b4610] width 1280 pitch 5120 (/4 1280) >[534699.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534699.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534699.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bf390] >[534699.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bf390] width 1280 pitch 5120 (/4 1280) >[534703.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528a480] >[534704.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528a480] width 1280 pitch 5120 (/4 1280) >[534706.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528a480] >[534706.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528a480] width 1280 pitch 5120 (/4 1280) >[534719.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27bf390] >[534719.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27bf390] width 1280 pitch 5120 (/4 1280) >[534719.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52886d0] >[534719.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52886d0] width 1280 pitch 5120 (/4 1280) >[534719.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528a480] >[534719.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528a480] width 1280 pitch 5120 (/4 1280) >[534719.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5289480] >[534719.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5289480] width 1280 pitch 5120 (/4 1280) >[534721.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b33b0] >[534721.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b33b0] width 1280 pitch 5120 (/4 1280) >[534722.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b32e0] >[534722.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b32e0] width 1280 pitch 5120 (/4 1280) >[534722.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b32e0] >[534722.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b32e0] width 1280 pitch 5120 (/4 1280) >[534723.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285f00] >[534723.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285f00] width 1280 pitch 5120 (/4 1280) >[534754.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5318600] >[534754.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5318600] width 1280 pitch 5120 (/4 1280) >[534756.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e4700] >[534756.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e4700] width 1280 pitch 5120 (/4 1280) >[534756.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534756.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534756.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e4700] >[534756.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e4700] width 1280 pitch 5120 (/4 1280) >[534756.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534756.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534757.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528e320] >[534757.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528e320] width 1280 pitch 5120 (/4 1280) >[534757.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528e320] >[534757.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528e320] width 1280 pitch 5120 (/4 1280) >[534757.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528e320] >[534757.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528e320] width 1280 pitch 5120 (/4 1280) >[534757.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534757.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534757.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534757.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534757.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534757.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534757.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362ee0] >[534757.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362ee0] width 1280 pitch 5120 (/4 1280) >[534757.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534757.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534759.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e220] >[534759.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e220] width 1280 pitch 5120 (/4 1280) >[534761.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5318600] >[534761.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5318600] width 1280 pitch 5120 (/4 1280) >[534761.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4722bd0] >[534761.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4722bd0] width 1280 pitch 5120 (/4 1280) >[534762.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319d50] >[534762.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319d50] width 1280 pitch 5120 (/4 1280) >[534762.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4722bd0] >[534762.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4722bd0] width 1280 pitch 5120 (/4 1280) >[534763.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534763.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534763.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534763.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5368e30] >[534763.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5368e30] width 1280 pitch 5120 (/4 1280) >[534764.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536e8d0] >[534764.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536e8d0] width 1280 pitch 5120 (/4 1280) >[534765.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534765.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534765.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534765.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537b510] >[534765.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537b510] width 1280 pitch 5120 (/4 1280) >[534766.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53751a0] >[534766.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53751a0] width 1280 pitch 5120 (/4 1280) >[534766.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419e5f0] >[534766.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419e5f0] width 1280 pitch 5120 (/4 1280) >[534767.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536e8d0] >[534767.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536e8d0] width 1280 pitch 5120 (/4 1280) >[534767.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528e4e0] >[534767.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528e4e0] width 1280 pitch 5120 (/4 1280) >[534767.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b7f540] >[534767.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b7f540] width 1280 pitch 5120 (/4 1280) >[534771.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[534771.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[534771.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[534771.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[534772.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[534772.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[534772.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536ae10] >[534772.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536ae10] width 1280 pitch 5120 (/4 1280) >[534772.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[534772.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[534773.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[534773.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[534773.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[534773.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[534773.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536ae10] >[534773.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536ae10] width 1280 pitch 5120 (/4 1280) >[534774.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[534774.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[534776.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[534776.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[534776.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[534776.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[534776.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534776.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534776.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534776.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534776.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534776.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534776.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[534776.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[534776.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534776.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534777.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534777.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534777.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534777.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534777.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff6f0] >[534777.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff6f0] width 1280 pitch 5120 (/4 1280) >[534777.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[534777.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[534777.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff6f0] >[534777.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff6f0] width 1280 pitch 5120 (/4 1280) >[534777.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534777.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534777.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534777.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534778.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534778.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534778.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534778.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff4d0] >[534778.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff4d0] width 1280 pitch 5120 (/4 1280) >[534778.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5376680] >[534778.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5376680] width 1280 pitch 5120 (/4 1280) >[534778.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5376880] >[534778.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5376880] width 1280 pitch 5120 (/4 1280) >[534778.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338a90] >[534778.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338a90] width 1280 pitch 5120 (/4 1280) >[534778.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336020] >[534778.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336020] width 1280 pitch 5120 (/4 1280) >[534778.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338a90] >[534778.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338a90] width 1280 pitch 5120 (/4 1280) >[534778.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336020] >[534779.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336020] width 1280 pitch 5120 (/4 1280) >[534779.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338a90] >[534779.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338a90] width 1280 pitch 5120 (/4 1280) >[534779.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336020] >[534779.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336020] width 1280 pitch 5120 (/4 1280) >[534779.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338a90] >[534779.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338a90] width 1280 pitch 5120 (/4 1280) >[534779.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338a90] >[534779.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338a90] width 1280 pitch 5120 (/4 1280) >[534779.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5338ae0] >[534779.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5338ae0] width 1280 pitch 5120 (/4 1280) >[534779.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53358e0] >[534779.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53358e0] width 1280 pitch 5120 (/4 1280) >[534779.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53314a0] >[534779.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53314a0] width 1280 pitch 5120 (/4 1280) >[534779.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336130] >[534779.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336130] width 1280 pitch 5120 (/4 1280) >[534779.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534779.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534779.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534779.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534779.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534783.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534783.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534783.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534783.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534783.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336ae0] >[534783.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336ae0] width 1280 pitch 5120 (/4 1280) >[534783.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5336ae0] >[534783.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5336ae0] width 1280 pitch 5120 (/4 1280) >[534784.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0540] >[534784.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0540] width 1280 pitch 5120 (/4 1280) >[534784.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331440] >[534784.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331440] width 1280 pitch 5120 (/4 1280) >[534784.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0540] >[534784.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0540] width 1280 pitch 5120 (/4 1280) >[534785.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319d10] >[534785.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319d10] width 1280 pitch 5120 (/4 1280) >[534785.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53176d0] >[534785.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53176d0] width 1280 pitch 5120 (/4 1280) >[534785.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52886d0] >[534785.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52886d0] width 1280 pitch 5120 (/4 1280) >[534809.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b7f540] >[534809.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b7f540] width 1280 pitch 5120 (/4 1280) >[534819.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5420] >[534819.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5420] width 1280 pitch 5120 (/4 1280) >[534819.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b8cc0] >[534819.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b8cc0] width 1280 pitch 5120 (/4 1280) >[534819.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5376620] >[534819.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5376620] width 1280 pitch 5120 (/4 1280) >[534819.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83c90] >[534819.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83c90] width 1280 pitch 5120 (/4 1280) >[534820.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83c90] >[534820.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83c90] width 1280 pitch 5120 (/4 1280) >[534820.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528bdc0] >[534820.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528bdc0] width 1280 pitch 5120 (/4 1280) >[534820.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528bdc0] >[534820.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528bdc0] width 1280 pitch 5120 (/4 1280) >[534820.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52880b0] >[534820.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52880b0] width 1280 pitch 5120 (/4 1280) >[534820.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52880b0] >[534820.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52880b0] width 1280 pitch 5120 (/4 1280) >[534822.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528bdc0] >[534822.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528bdc0] width 1280 pitch 5120 (/4 1280) >[534822.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5376620] >[534822.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5376620] width 1280 pitch 5120 (/4 1280) >[534822.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83c90] >[534822.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83c90] width 1280 pitch 5120 (/4 1280) >[534822.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528bdc0] >[534822.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528bdc0] width 1280 pitch 5120 (/4 1280) >[534822.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5376620] >[534822.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5376620] width 1280 pitch 5120 (/4 1280) >[534836.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b6800] >[534836.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b6800] width 1280 pitch 5120 (/4 1280) >[534836.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52880b0] >[534836.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52880b0] width 1280 pitch 5120 (/4 1280) >[534836.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b6800] >[534836.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b6800] width 1280 pitch 5120 (/4 1280) >[534836.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83c90] >[534836.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83c90] width 1280 pitch 5120 (/4 1280) >[534852.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4e030] >[534852.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4e030] width 1280 pitch 5120 (/4 1280) >[534852.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4e030] >[534852.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4e030] width 1280 pitch 5120 (/4 1280) >[534852.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51102c0] >[534852.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51102c0] width 1280 pitch 5120 (/4 1280) >[534852.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4e030] >[534852.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4e030] width 1280 pitch 5120 (/4 1280) >[534867.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b0ed0] >[534867.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b0ed0] width 1280 pitch 5120 (/4 1280) >[534867.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3563160] >[534867.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3563160] width 1280 pitch 5120 (/4 1280) >[534867.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372410] >[534867.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372410] width 1280 pitch 5120 (/4 1280) >[534867.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3563160] >[534867.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3563160] width 1280 pitch 5120 (/4 1280) >[534873.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534873.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534873.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528fbb0] >[534873.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528fbb0] width 1280 pitch 5120 (/4 1280) >[534885.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533ed70] >[534885.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533ed70] width 1280 pitch 5120 (/4 1280) >[534885.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52880b0] >[534885.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52880b0] width 1280 pitch 5120 (/4 1280) >[534890.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533ed70] >[534890.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533ed70] width 1280 pitch 5120 (/4 1280) >[534890.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bfc80] >[534890.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bfc80] width 1280 pitch 5120 (/4 1280) >[534891.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b0ed0] >[534891.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b0ed0] width 1280 pitch 5120 (/4 1280) >[534891.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c3ed0] >[534891.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c3ed0] width 1280 pitch 5120 (/4 1280) >[534892.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c3ed0] >[534892.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c3ed0] width 1280 pitch 5120 (/4 1280) >[534892.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533ed70] >[534892.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533ed70] width 1280 pitch 5120 (/4 1280) >[534955.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c7df0] >[534955.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c7df0] width 1280 pitch 5120 (/4 1280) >[534955.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534955.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534956.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b73070] >[534956.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b73070] width 1280 pitch 5120 (/4 1280) >[534957.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5344a70] >[534957.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5344a70] width 1280 pitch 5120 (/4 1280) >[534957.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533f9d0] >[534957.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533f9d0] width 1280 pitch 5120 (/4 1280) >[534957.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534957.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534987.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9a80] >[534987.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9a80] width 1280 pitch 5120 (/4 1280) >[534987.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46041f0] >[534987.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46041f0] width 1280 pitch 5120 (/4 1280) >[534990.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373ed0] >[534990.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373ed0] width 1280 pitch 5120 (/4 1280) >[534990.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9a80] >[534990.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9a80] width 1280 pitch 5120 (/4 1280) >[534990.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ad60] >[534990.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ad60] width 1280 pitch 5120 (/4 1280) >[534990.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611e20] >[534990.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611e20] width 1280 pitch 5120 (/4 1280) >[534991.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534991.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534991.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5342340] >[534991.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5342340] width 1280 pitch 5120 (/4 1280) >[534992.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[534992.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[534992.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9a80] >[534992.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9a80] width 1280 pitch 5120 (/4 1280) >[534994.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9a80] >[534994.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9a80] width 1280 pitch 5120 (/4 1280) >[534994.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b0e70] >[534994.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b0e70] width 1280 pitch 5120 (/4 1280) >[534995.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[534995.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[534995.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534995.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534996.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373ed0] >[534996.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373ed0] width 1280 pitch 5120 (/4 1280) >[534997.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534997.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534997.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5343790] >[534997.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5343790] width 1280 pitch 5120 (/4 1280) >[534997.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52880b0] >[534997.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52880b0] width 1280 pitch 5120 (/4 1280) >[534997.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f990] >[534997.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f990] width 1280 pitch 5120 (/4 1280) >[534999.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9a80] >[534999.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9a80] width 1280 pitch 5120 (/4 1280) >[534999.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371d90] >[534999.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371d90] width 1280 pitch 5120 (/4 1280) >[534999.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611e20] >[534999.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611e20] width 1280 pitch 5120 (/4 1280) >[535000.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46041f0] >[535000.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46041f0] width 1280 pitch 5120 (/4 1280) >[535063.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53050d0] >[535063.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53050d0] width 1280 pitch 5120 (/4 1280) >[535115.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7fc0] >[535115.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7fc0] width 1280 pitch 5120 (/4 1280) >[535115.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535115.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535119.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ad170] >[535119.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ad170] width 1280 pitch 5120 (/4 1280) >[535119.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b8cc0] >[535119.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b8cc0] width 1280 pitch 5120 (/4 1280) >[535119.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c8070] >[535119.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c8070] width 1280 pitch 5120 (/4 1280) >[535119.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535119.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535184.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535184.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535184.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535184.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7fc0] >[535184.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7fc0] width 1280 pitch 5120 (/4 1280) >[535184.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7fc0] >[535184.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7fc0] width 1280 pitch 5120 (/4 1280) >[535184.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535184.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7fc0] >[535184.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7fc0] width 1280 pitch 5120 (/4 1280) >[535184.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5312fa0] >[535184.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5312fa0] width 1280 pitch 5120 (/4 1280) >[535185.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535185.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535185.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535185.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535185.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535185.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535185.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535186.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535186.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42bd6b0] >[535186.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42bd6b0] width 1280 pitch 5120 (/4 1280) >[535186.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[535186.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[535187.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535187.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535187.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535187.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535187.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535187.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535187.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535187.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535187.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535187.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535187.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535187.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535187.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14d1ac0] >[535187.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14d1ac0] width 1280 pitch 5120 (/4 1280) >[535187.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535187.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535187.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535187.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535187.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[535187.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[535187.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535187.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535187.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535187.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535187.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535187.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535187.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535187.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535187.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535188.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535188.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535188.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535188.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535188.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x533fff0] >[535188.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x533fff0] width 1280 pitch 5120 (/4 1280) >[535188.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7220] >[535188.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7220] width 1280 pitch 5120 (/4 1280) >[535251.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5950] >[535251.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5950] width 1280 pitch 5120 (/4 1280) >[535251.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535251.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535382.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535382.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535399.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534c440] >[535399.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534c440] width 1280 pitch 5120 (/4 1280) >[535399.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535399.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535399.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534c440] >[535399.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534c440] width 1280 pitch 5120 (/4 1280) >[535400.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535400.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535400.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534c440] >[535400.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534c440] width 1280 pitch 5120 (/4 1280) >[535400.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535400.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535400.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534c440] >[535400.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534c440] width 1280 pitch 5120 (/4 1280) >[535400.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535400.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535401.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534c440] >[535401.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534c440] width 1280 pitch 5120 (/4 1280) >[535401.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce070] >[535401.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce070] width 1280 pitch 5120 (/4 1280) >[535401.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5299df0] >[535401.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5299df0] width 1280 pitch 5120 (/4 1280) >[535401.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5340ae0] >[535401.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5340ae0] width 1280 pitch 5120 (/4 1280) >[535401.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce070] >[535401.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce070] width 1280 pitch 5120 (/4 1280) >[535401.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x106cb30] >[535401.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x106cb30] width 1280 pitch 5120 (/4 1280) >[535401.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5299df0] >[535401.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5299df0] width 1280 pitch 5120 (/4 1280) >[535405.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5340ae0] >[535405.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5340ae0] width 1280 pitch 5120 (/4 1280) >[535488.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535488.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535493.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535493.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535493.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535493.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535493.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535493.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535493.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535493.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535494.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535494.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535494.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535494.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535494.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535494.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535494.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535494.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7c90] >[535494.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7c90] width 1280 pitch 5120 (/4 1280) >[535494.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535494.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535494.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535494.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535494.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535494.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535494.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535494.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535494.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535494.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535494.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf2d20] >[535495.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf2d20] width 1280 pitch 5120 (/4 1280) >[535523.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535523.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535523.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535523.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535523.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535523.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535523.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535523.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535523.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535523.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535523.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535523.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535524.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535524.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535524.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535525.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535525.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535525.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535525.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535525.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535525.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535525.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535525.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535525.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535525.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535525.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535526.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535526.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535526.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535526.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535526.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53444d0] >[535526.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53444d0] width 1280 pitch 5120 (/4 1280) >[535526.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b9af60] >[535526.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b9af60] width 1280 pitch 5120 (/4 1280) >[535527.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6cd0] >[535527.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6cd0] width 1280 pitch 5120 (/4 1280) >[535527.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a7c90] >[535527.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a7c90] width 1280 pitch 5120 (/4 1280) >[535656.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535656.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535664.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535664.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535664.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535664.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535664.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535664.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535664.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535664.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535664.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535664.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535664.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535664.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535664.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535664.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535664.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535664.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535664.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535664.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535665.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535665.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535665.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535665.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535666.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535666.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535666.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535666.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535666.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535666.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535666.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535666.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535666.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535666.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535666.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535666.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535666.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535666.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535666.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535666.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535666.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535666.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535666.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535666.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535667.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535667.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535667.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535667.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535667.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bffc0] >[535667.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bffc0] width 1280 pitch 5120 (/4 1280) >[535667.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535667.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535667.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53041d0] >[535667.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53041d0] width 1280 pitch 5120 (/4 1280) >[535712.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b0350] >[535712.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b0350] width 1280 pitch 5120 (/4 1280) >[535712.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x529e210] >[535712.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x529e210] width 1280 pitch 5120 (/4 1280) >[535748.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535748.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535748.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535748.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535748.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535748.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535749.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535749.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535749.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535749.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535749.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535749.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535750.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535750.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535750.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535750.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535751.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535751.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535751.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535751.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535751.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535751.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535751.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535751.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535751.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535751.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535751.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535751.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535752.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535752.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535752.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535752.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535752.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535752.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535752.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535753.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535753.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535753.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535754.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535754.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535756.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535756.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535757.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535757.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535757.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535757.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535757.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535757.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535757.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535757.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535757.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535758.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535758.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535758.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535780.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535780.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535780.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535780.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535780.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535780.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535780.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535780.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535780.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535780.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535780.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535780.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535781.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535781.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535781.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535781.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535781.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535781.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535781.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535781.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535781.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535781.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535781.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535781.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535781.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535781.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535781.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535781.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535781.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535781.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535781.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535781.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535782.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535782.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535782.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535782.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535782.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535782.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535782.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535782.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535782.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x532f320] >[535782.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x532f320] width 1280 pitch 5120 (/4 1280) >[535782.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535782.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535782.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x532f320] >[535782.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x532f320] width 1280 pitch 5120 (/4 1280) >[535782.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535782.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535782.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535782.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535782.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535783.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535783.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535783.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535783.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x532f320] >[535783.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x532f320] width 1280 pitch 5120 (/4 1280) >[535783.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535783.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535783.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535783.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535783.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x532e150] >[535783.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x532e150] width 1280 pitch 5120 (/4 1280) >[535784.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535784.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535799.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535799.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535799.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535799.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535799.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535799.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535799.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535799.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535799.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535799.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535800.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535800.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535800.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535800.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535800.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535800.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535800.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535800.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535801.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535801.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535801.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535801.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535813.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[535813.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[535816.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff6f0] >[535816.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff6f0] width 1280 pitch 5120 (/4 1280) >[535816.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535816.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535816.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535816.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535816.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535816.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535862.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535862.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535862.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535862.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535864.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362840] >[535864.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362840] width 1280 pitch 5120 (/4 1280) >[535864.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535864.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535864.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362840] >[535864.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362840] width 1280 pitch 5120 (/4 1280) >[535865.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535865.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535865.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362840] >[535865.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362840] width 1280 pitch 5120 (/4 1280) >[535865.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f500] >[535865.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f500] width 1280 pitch 5120 (/4 1280) >[535865.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535865.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535866.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535866.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535866.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535866.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535866.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535866.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535866.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535867.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535867.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535867.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535867.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535867.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535867.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535867.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535868.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362840] >[535868.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362840] width 1280 pitch 5120 (/4 1280) >[535868.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535868.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535868.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535868.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535868.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[535868.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[535868.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535868.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535868.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[535868.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[535868.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535868.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535869.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535869.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535870.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535870.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535870.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535870.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535871.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff6f0] >[535871.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff6f0] width 1280 pitch 5120 (/4 1280) >[535871.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535871.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535872.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535872.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535872.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542b370] >[535872.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542b370] width 1280 pitch 5120 (/4 1280) >[535872.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ae170] >[535872.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ae170] width 1280 pitch 5120 (/4 1280) >[535872.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5317360] >[535872.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5317360] width 1280 pitch 5120 (/4 1280) >[535988.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee70] >[535988.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee70] width 1280 pitch 5120 (/4 1280) >[535988.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535988.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535989.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5317360] >[535989.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5317360] width 1280 pitch 5120 (/4 1280) >[535989.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535989.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535989.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535989.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535989.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535989.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535989.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535989.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535989.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535990.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535990.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535990.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535990.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3229960] >[535990.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3229960] width 1280 pitch 5120 (/4 1280) >[535990.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535991.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535991.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b180] >[535991.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b180] width 1280 pitch 5120 (/4 1280) >[535991.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535991.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535992.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535992.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535992.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5317360] >[535992.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5317360] width 1280 pitch 5120 (/4 1280) >[535992.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535992.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535992.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535992.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535992.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535992.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535992.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535992.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535992.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535992.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535993.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535993.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535993.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535993.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535993.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535993.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535994.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535994.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535994.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b180] >[535994.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b180] width 1280 pitch 5120 (/4 1280) >[535994.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535994.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535994.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535994.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535994.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535994.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535994.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535995.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535995.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[535995.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[535995.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[535995.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[535995.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535995.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535996.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535996.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535996.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535996.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535996.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535996.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535996.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535996.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535996.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535996.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535996.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535996.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535996.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535996.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535996.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535996.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535996.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535996.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535996.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535996.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535996.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535996.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535996.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535996.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535996.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535996.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535996.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535996.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535997.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535997.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535997.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535997.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535997.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535997.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535997.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535997.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535997.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535997.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535997.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535997.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535997.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535997.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535997.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa0750] >[535997.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa0750] width 1280 pitch 5120 (/4 1280) >[535997.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9850] >[535997.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9850] width 1280 pitch 5120 (/4 1280) >[535997.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa0750] >[535997.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa0750] width 1280 pitch 5120 (/4 1280) >[535997.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535997.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535997.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535997.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535997.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535997.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535997.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535997.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535997.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535997.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535998.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[535998.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[535998.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535998.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[535998.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[535998.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[535998.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535998.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535998.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b180] >[535998.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b180] width 1280 pitch 5120 (/4 1280) >[535998.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[535998.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[535999.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[535999.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[535999.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[535999.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[536000.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536000.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536009.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[536009.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[536009.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c780] >[536009.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c780] width 1280 pitch 5120 (/4 1280) >[536010.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[536010.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[536010.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa0750] >[536010.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa0750] width 1280 pitch 5120 (/4 1280) >[536010.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[536010.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[536010.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5317360] >[536010.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5317360] width 1280 pitch 5120 (/4 1280) >[536010.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[536010.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[536015.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[536015.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[536016.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4220] >[536016.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4220] width 1280 pitch 5120 (/4 1280) >[536016.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[536016.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[536016.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[536016.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[536017.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5317360] >[536017.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5317360] width 1280 pitch 5120 (/4 1280) >[536017.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b180] >[536017.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b180] width 1280 pitch 5120 (/4 1280) >[536017.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5348310] >[536017.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5348310] width 1280 pitch 5120 (/4 1280) >[536017.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[536017.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[536017.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[536017.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[536017.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa0750] >[536017.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa0750] width 1280 pitch 5120 (/4 1280) >[536017.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5372950] >[536018.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5372950] width 1280 pitch 5120 (/4 1280) >[536018.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b6dfe0] >[536018.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b6dfe0] width 1280 pitch 5120 (/4 1280) >[536023.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536023.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536029.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c0cb0] >[536029.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c0cb0] width 1280 pitch 5120 (/4 1280) >[536029.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ff6f0] >[536029.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ff6f0] width 1280 pitch 5120 (/4 1280) >[536037.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536037.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536037.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536037.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536037.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536037.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536037.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536037.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536037.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536037.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536037.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536037.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536037.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536038.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536038.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536038.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536038.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536038.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536038.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536038.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536038.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536038.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536038.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536038.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536038.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536038.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536038.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536038.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536038.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536038.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536038.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536038.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536038.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536038.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536038.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536038.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536038.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536040.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536040.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536040.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536040.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536040.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536040.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536040.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536040.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536040.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536040.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536040.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536040.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536040.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536040.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536041.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536041.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536041.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536041.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536041.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536043.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536043.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536043.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536043.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536043.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536043.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536043.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536043.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536043.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536043.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536043.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536043.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536043.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536043.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536043.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536043.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536043.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536043.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536043.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536043.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536044.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536044.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536044.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536044.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536044.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536044.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536044.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536044.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536044.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536044.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536044.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536044.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536044.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536044.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536044.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536044.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536044.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536044.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536044.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536044.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536044.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536044.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536044.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536044.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536044.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536044.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536045.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536045.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536045.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536045.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536045.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536045.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536045.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536045.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536045.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536045.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536045.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536045.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536045.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536045.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536046.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536046.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536046.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536046.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536046.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536046.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536046.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536046.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536046.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5395ac0] >[536047.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5395ac0] width 1280 pitch 5120 (/4 1280) >[536047.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536047.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536047.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bac60] >[536047.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bac60] width 1280 pitch 5120 (/4 1280) >[536047.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536047.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536047.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe8b0] >[536047.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe8b0] width 1280 pitch 5120 (/4 1280) >[536047.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bcf50] >[536047.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bcf50] width 1280 pitch 5120 (/4 1280) >[536052.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536052.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536052.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53313d0] >[536052.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53313d0] width 1280 pitch 5120 (/4 1280) >[536059.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a4edb0] >[536059.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a4edb0] width 1280 pitch 5120 (/4 1280) >[536059.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7fd0] >[536059.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7fd0] width 1280 pitch 5120 (/4 1280) >[536060.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331040] >[536060.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331040] width 1280 pitch 5120 (/4 1280) >[536060.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536060.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536061.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331040] >[536061.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331040] width 1280 pitch 5120 (/4 1280) >[536061.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536061.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536061.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331040] >[536061.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331040] width 1280 pitch 5120 (/4 1280) >[536061.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536061.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536061.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536061.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536062.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536062.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536062.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c0d10] >[536062.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c0d10] width 1280 pitch 5120 (/4 1280) >[536062.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536062.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536062.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536062.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536062.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53957f0] >[536062.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53957f0] width 1280 pitch 5120 (/4 1280) >[536062.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536062.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536062.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331040] >[536062.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331040] width 1280 pitch 5120 (/4 1280) >[536062.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536062.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536062.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536062.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536062.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536062.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536063.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536063.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536064.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536064.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536064.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536064.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536064.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5149060] >[536064.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5149060] width 1280 pitch 5120 (/4 1280) >[536064.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536064.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536064.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5331040] >[536064.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5331040] width 1280 pitch 5120 (/4 1280) >[536065.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528df70] >[536065.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528df70] width 1280 pitch 5120 (/4 1280) >[536069.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[536069.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[536070.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537a400] >[536070.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537a400] width 1280 pitch 5120 (/4 1280) >[536070.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537a3a0] >[536070.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537a3a0] width 1280 pitch 5120 (/4 1280) >[536070.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528ce60] >[536070.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528ce60] width 1280 pitch 5120 (/4 1280) >[536070.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5399a60] >[536070.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5399a60] width 1280 pitch 5120 (/4 1280) >[536070.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beaa0] >[536070.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beaa0] width 1280 pitch 5120 (/4 1280) >[536070.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b9d30] >[536070.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b9d30] width 1280 pitch 5120 (/4 1280) >[536070.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536070.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536071.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536071.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536071.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba220] >[536071.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba220] width 1280 pitch 5120 (/4 1280) >[536075.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536075.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536075.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536075.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536075.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b9ec0] >[536076.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b9ec0] width 1280 pitch 5120 (/4 1280) >[536076.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b060] >[536076.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b060] width 1280 pitch 5120 (/4 1280) >[536076.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b9ec0] >[536076.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b9ec0] width 1280 pitch 5120 (/4 1280) >[536076.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b9ec0] >[536076.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b9ec0] width 1280 pitch 5120 (/4 1280) >[536078.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b8e70] >[536078.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b8e70] width 1280 pitch 5120 (/4 1280) >[536078.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b8e70] >[536078.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b8e70] width 1280 pitch 5120 (/4 1280) >[536078.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b8e70] >[536079.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b8e70] width 1280 pitch 5120 (/4 1280) >[536079.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b7f40] >[536079.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b7f40] width 1280 pitch 5120 (/4 1280) >[536079.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53167a0] >[536079.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53167a0] width 1280 pitch 5120 (/4 1280) >[536079.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b7f40] >[536079.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b7f40] width 1280 pitch 5120 (/4 1280) >[536079.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52df260] >[536079.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52df260] width 1280 pitch 5120 (/4 1280) >[536079.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b7f40] >[536079.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b7f40] width 1280 pitch 5120 (/4 1280) >[536101.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b7f40] >[536101.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b7f40] width 1280 pitch 5120 (/4 1280) >[536104.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5950] >[536104.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5950] width 1280 pitch 5120 (/4 1280) >[536218.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5347c50] >[536218.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5347c50] width 1280 pitch 5120 (/4 1280) >[536218.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536218.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536218.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536218.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536218.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536218.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536218.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536218.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536218.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536218.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536219.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536219.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536219.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536219.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[536219.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[536219.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536219.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53796b0] >[536219.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53796b0] width 1280 pitch 5120 (/4 1280) >[536219.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536219.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536293.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[536293.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[536294.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df370] >[536294.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df370] width 1280 pitch 5120 (/4 1280) >[536295.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536295.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536295.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536295.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536295.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536295.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536296.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536296.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536296.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536296.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536296.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536296.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536296.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536296.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536297.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536297.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536297.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536297.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536297.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536297.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536298.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536298.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536298.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536298.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536298.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536298.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536298.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536298.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536298.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536298.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536298.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1497c20] >[536298.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1497c20] width 1280 pitch 5120 (/4 1280) >[536299.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35790e0] >[536299.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35790e0] width 1280 pitch 5120 (/4 1280) >[536299.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[536299.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[536299.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35790e0] >[536300.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35790e0] width 1280 pitch 5120 (/4 1280) >[536300.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[536300.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[536300.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35790e0] >[536300.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35790e0] width 1280 pitch 5120 (/4 1280) >[536300.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1156720] >[536300.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1156720] width 1280 pitch 5120 (/4 1280) >[536300.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ab2a0] >[536300.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ab2a0] width 1280 pitch 5120 (/4 1280) >[536301.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1156720] >[536301.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1156720] width 1280 pitch 5120 (/4 1280) >[536301.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18b90] >[536301.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18b90] width 1280 pitch 5120 (/4 1280) >[536301.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3517870] >[536301.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3517870] width 1280 pitch 5120 (/4 1280) >[536301.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x14f1bb0] >[536301.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x14f1bb0] width 1280 pitch 5120 (/4 1280) >[536301.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4624960] >[536301.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4624960] width 1280 pitch 5120 (/4 1280) >[536301.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b3f50] >[536301.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b3f50] width 1280 pitch 5120 (/4 1280) >[536301.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fc2f0] >[536301.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fc2f0] width 1280 pitch 5120 (/4 1280) >[536301.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b3f50] >[536301.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b3f50] width 1280 pitch 5120 (/4 1280) >[536301.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fc2f0] >[536301.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fc2f0] width 1280 pitch 5120 (/4 1280) >[536301.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b3f50] >[536301.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b3f50] width 1280 pitch 5120 (/4 1280) >[536301.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19fc2f0] >[536301.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19fc2f0] width 1280 pitch 5120 (/4 1280) >[536301.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b3f50] >[536301.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b3f50] width 1280 pitch 5120 (/4 1280) >[536302.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b3f50] >[536302.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b3f50] width 1280 pitch 5120 (/4 1280) >[536302.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[536302.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[536302.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[536302.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[536302.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536302.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536303.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b34f0] >[536303.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b34f0] width 1280 pitch 5120 (/4 1280) >[536303.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231ca0] >[536303.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231ca0] width 1280 pitch 5120 (/4 1280) >[536303.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1156720] >[536303.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1156720] width 1280 pitch 5120 (/4 1280) >[536303.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d77390] >[536303.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d77390] width 1280 pitch 5120 (/4 1280) >[536303.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2593900] >[536303.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2593900] width 1280 pitch 5120 (/4 1280) >[536303.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ab2a0] >[536303.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ab2a0] width 1280 pitch 5120 (/4 1280) >[536303.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b3220] >[536304.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b3220] width 1280 pitch 5120 (/4 1280) >[536304.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5950] >[536304.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5950] width 1280 pitch 5120 (/4 1280) >[536311.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52434e0] >[536311.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52434e0] width 1280 pitch 5120 (/4 1280) >[536311.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4624960] >[536311.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4624960] width 1280 pitch 5120 (/4 1280) >[536311.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2a40] >[536311.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2a40] width 1280 pitch 5120 (/4 1280) >[536311.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4624960] >[536311.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4624960] width 1280 pitch 5120 (/4 1280) >[536312.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2a40] >[536312.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2a40] width 1280 pitch 5120 (/4 1280) >[536639.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[536639.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[536639.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[536639.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[536639.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[536639.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[536639.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[536639.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[536639.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[536639.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[536641.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4736a60] >[536641.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4736a60] width 1280 pitch 5120 (/4 1280) >[536642.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371330] >[536642.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371330] width 1280 pitch 5120 (/4 1280) >[536642.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[536642.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[536642.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[536642.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[536642.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf9b0] >[536642.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf9b0] width 1280 pitch 5120 (/4 1280) >[536642.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[536642.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[536642.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5285d90] >[536642.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5285d90] width 1280 pitch 5120 (/4 1280) >[536642.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[536642.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[536643.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[536643.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[536643.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[536643.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[536643.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1231ca0] >[536643.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1231ca0] width 1280 pitch 5120 (/4 1280) >[536644.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b34f0] >[536644.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b34f0] width 1280 pitch 5120 (/4 1280) >[536644.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35da330] >[536644.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35da330] width 1280 pitch 5120 (/4 1280) >[536644.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[536644.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[536644.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df370] >[536644.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df370] width 1280 pitch 5120 (/4 1280) >[536644.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[536644.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[536645.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[536645.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[536645.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536645.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536646.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5136010] >[536646.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5136010] width 1280 pitch 5120 (/4 1280) >[536646.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[536646.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[536646.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5136010] >[536646.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5136010] width 1280 pitch 5120 (/4 1280) >[536646.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46286f0] >[536646.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46286f0] width 1280 pitch 5120 (/4 1280) >[536646.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5136010] >[536646.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5136010] width 1280 pitch 5120 (/4 1280) >[536646.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a8610] >[536646.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a8610] width 1280 pitch 5120 (/4 1280) >[536666.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3517870] >[536666.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3517870] width 1280 pitch 5120 (/4 1280) >[536674.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x421a740] >[536674.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x421a740] width 1280 pitch 5120 (/4 1280) >[536674.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412a3e0] >[536674.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412a3e0] width 1280 pitch 5120 (/4 1280) >[536675.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c1ab0] >[536675.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c1ab0] width 1280 pitch 5120 (/4 1280) >[536675.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b4020] >[536675.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b4020] width 1280 pitch 5120 (/4 1280) >[536690.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3512eb0] >[536690.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3512eb0] width 1280 pitch 5120 (/4 1280) >[536691.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c48f0] >[536691.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c48f0] width 1280 pitch 5120 (/4 1280) >[536710.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce8160] >[536710.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce8160] width 1280 pitch 5120 (/4 1280) >[536710.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[536710.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[536710.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1aaae50] >[536710.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1aaae50] width 1280 pitch 5120 (/4 1280) >[536710.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[536710.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[536711.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50344d0] >[536711.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50344d0] width 1280 pitch 5120 (/4 1280) >[536711.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18b90] >[536711.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18b90] width 1280 pitch 5120 (/4 1280) >[536711.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4765b00] >[536711.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4765b00] width 1280 pitch 5120 (/4 1280) >[536711.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ae550] >[536711.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ae550] width 1280 pitch 5120 (/4 1280) >[536712.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[536712.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[536713.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[536713.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[536713.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470f050] >[536713.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470f050] width 1280 pitch 5120 (/4 1280) >[536713.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ac140] >[536713.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ac140] width 1280 pitch 5120 (/4 1280) >[536725.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c48f0] >[536725.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c48f0] width 1280 pitch 5120 (/4 1280) >[536725.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x13d17a0] >[536725.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x13d17a0] width 1280 pitch 5120 (/4 1280) >[536769.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[536769.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[541513.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[541513.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ad7d0] >[541513.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ad7d0] width 1280 pitch 5120 (/4 1280) >[541513.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541513.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541513.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447c10] >[541513.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447c10] width 1280 pitch 5120 (/4 1280) >[541513.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541513.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541513.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447c10] >[541513.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447c10] width 1280 pitch 5120 (/4 1280) >[541513.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541513.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541513.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447c10] >[541513.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447c10] width 1280 pitch 5120 (/4 1280) >[541513.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541513.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541513.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447c10] >[541513.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447c10] width 1280 pitch 5120 (/4 1280) >[541513.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541513.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541513.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447c10] >[541514.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447c10] width 1280 pitch 5120 (/4 1280) >[541514.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32917d0] >[541514.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32917d0] width 1280 pitch 5120 (/4 1280) >[541514.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[541514.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[541514.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[541514.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[541514.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[541514.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[541514.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[541514.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[541514.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[541514.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[541514.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[541514.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[541514.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[541514.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[541514.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x410baf0] >[541514.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x410baf0] width 1280 pitch 5120 (/4 1280) >[541514.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[541514.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[541515.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51370e0] >[541515.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51370e0] width 1280 pitch 5120 (/4 1280) >[541515.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4087fd0] >[541515.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4087fd0] width 1280 pitch 5120 (/4 1280) >[541515.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19f9cd0] >[541515.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19f9cd0] width 1280 pitch 5120 (/4 1280) >[541516.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[541516.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[541516.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[541516.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[541517.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[541517.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[541517.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[541517.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[541517.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[541517.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[541517.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[541517.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[541517.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[541517.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[541517.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13700] >[541517.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13700] width 1280 pitch 5120 (/4 1280) >[541517.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5200] >[541517.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5200] width 1280 pitch 5120 (/4 1280) >[541517.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541517.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541517.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541517.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541517.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541518.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca870] >[541518.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca870] width 1280 pitch 5120 (/4 1280) >[541518.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338e850] >[541518.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338e850] width 1280 pitch 5120 (/4 1280) >[541522.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541522.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eefaf0] >[541522.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eefaf0] width 1280 pitch 5120 (/4 1280) >[541522.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[541522.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[541523.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541523.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x422fae0] >[541523.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x422fae0] width 1280 pitch 5120 (/4 1280) >[541523.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42316c0] >[541523.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42316c0] width 1280 pitch 5120 (/4 1280) >[541525.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541525.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541525.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541525.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541525.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541525.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541525.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541525.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541525.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541525.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541525.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541525.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541525.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541525.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541525.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541525.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541525.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541525.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541525.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541525.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541525.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541526.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541526.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541526.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541526.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541526.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541526.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541526.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541526.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541526.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541526.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541526.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541526.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541526.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541527.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440a150] >[541527.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440a150] width 1280 pitch 5120 (/4 1280) >[541527.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f6dc0] >[541527.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f6dc0] width 1280 pitch 5120 (/4 1280) >[541527.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52490b0] >[541527.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52490b0] width 1280 pitch 5120 (/4 1280) >[541527.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f6dc0] >[541527.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f6dc0] width 1280 pitch 5120 (/4 1280) >[541527.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4215d20] >[541527.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4215d20] width 1280 pitch 5120 (/4 1280) >[541528.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf8550] >[541528.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf8550] width 1280 pitch 5120 (/4 1280) >[541528.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb28d0] >[541528.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb28d0] width 1280 pitch 5120 (/4 1280) >[541533.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494da0] >[541533.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494da0] width 1280 pitch 5120 (/4 1280) >[541553.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541553.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541553.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541553.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541553.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541554.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541554.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541554.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541554.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541554.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541554.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541554.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541554.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541554.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541554.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541554.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541554.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541554.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541554.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541554.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541554.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541554.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541554.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fdad20] >[541555.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fdad20] width 1280 pitch 5120 (/4 1280) >[541555.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541555.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541555.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541555.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541555.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541555.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5373370] >[541555.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5373370] width 1280 pitch 5120 (/4 1280) >[541555.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541555.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541555.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541555.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541555.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541555.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541555.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541555.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541555.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541555.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541555.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541555.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541555.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541555.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541556.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541556.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541556.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bb5f0] >[541556.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bb5f0] width 1280 pitch 5120 (/4 1280) >[541906.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47050d0] >[541906.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47050d0] width 1280 pitch 5120 (/4 1280) >[541906.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d3da0] >[541906.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d3da0] width 1280 pitch 5120 (/4 1280) >[541906.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ae520] >[541906.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ae520] width 1280 pitch 5120 (/4 1280) >[541906.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d3da0] >[541906.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d3da0] width 1280 pitch 5120 (/4 1280) >[541906.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ae520] >[541906.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ae520] width 1280 pitch 5120 (/4 1280) >[541906.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d3da0] >[541906.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d3da0] width 1280 pitch 5120 (/4 1280) >[541907.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d3da0] >[541907.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d3da0] width 1280 pitch 5120 (/4 1280) >[541908.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541908.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541908.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d3da0] >[541908.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d3da0] width 1280 pitch 5120 (/4 1280) >[541908.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541908.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541908.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111910] >[541908.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111910] width 1280 pitch 5120 (/4 1280) >[541981.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x412a3e0] >[541981.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x412a3e0] width 1280 pitch 5120 (/4 1280) >[541983.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[541983.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[542020.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[542020.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[542395.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542395.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542395.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ddc0] >[542395.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ddc0] width 1280 pitch 5120 (/4 1280) >[542395.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542395.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542395.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ddc0] >[542395.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ddc0] width 1280 pitch 5120 (/4 1280) >[542395.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542395.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542395.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ddc0] >[542395.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ddc0] width 1280 pitch 5120 (/4 1280) >[542395.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542395.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542395.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542395.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542395.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ddc0] >[542395.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ddc0] width 1280 pitch 5120 (/4 1280) >[542395.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ddc0] >[542395.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ddc0] width 1280 pitch 5120 (/4 1280) >[542395.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d3260] >[542395.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d3260] width 1280 pitch 5120 (/4 1280) >[542395.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542395.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542395.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542395.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542395.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542396.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542396.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542396.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542396.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542396.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542396.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542396.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542396.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542396.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542396.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d3260] >[542396.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d3260] width 1280 pitch 5120 (/4 1280) >[542396.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d8910] >[542396.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d8910] width 1280 pitch 5120 (/4 1280) >[542396.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d3260] >[542396.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d3260] width 1280 pitch 5120 (/4 1280) >[542396.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542396.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542396.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542396.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542396.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542396.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[542396.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[542396.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542396.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542397.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542397.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542397.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542397.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542397.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a17f0] >[542397.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a17f0] width 1280 pitch 5120 (/4 1280) >[542397.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d2910] >[542397.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d2910] width 1280 pitch 5120 (/4 1280) >[542398.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4489df0] >[542398.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4489df0] width 1280 pitch 5120 (/4 1280) >[542398.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d8910] >[542398.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d8910] width 1280 pitch 5120 (/4 1280) >[542398.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d3260] >[542398.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d3260] width 1280 pitch 5120 (/4 1280) >[542398.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542398.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542398.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d3260] >[542398.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d3260] width 1280 pitch 5120 (/4 1280) >[542398.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[542398.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[542503.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44a4040] >[542503.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44a4040] width 1280 pitch 5120 (/4 1280) >[542505.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382820] >[542505.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382820] width 1280 pitch 5120 (/4 1280) >[542659.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5148520] >[542659.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5148520] width 1280 pitch 5120 (/4 1280) >[542659.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41d04d0] >[542659.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41d04d0] width 1280 pitch 5120 (/4 1280) >[543042.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543042.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543042.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543042.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543042.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543042.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543043.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543043.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543043.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543043.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543043.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543043.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543043.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543043.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543043.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543043.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d0670] >[543043.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d0670] width 1280 pitch 5120 (/4 1280) >[543044.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382980] >[543044.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382980] width 1280 pitch 5120 (/4 1280) >[543044.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543044.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543044.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543044.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543044.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543045.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543045.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543045.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543045.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543045.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543045.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543045.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543045.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543045.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543045.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543045.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543045.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543045.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543045.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051da0] >[543045.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051da0] width 1280 pitch 5120 (/4 1280) >[543045.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52eec30] >[543045.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52eec30] width 1280 pitch 5120 (/4 1280) >[543061.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543061.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543061.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bcce0] >[543061.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bcce0] width 1280 pitch 5120 (/4 1280) >[543146.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543146.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543146.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543146.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543146.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543146.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543146.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543146.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543146.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543146.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543146.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543146.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543146.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543146.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543146.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543146.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543146.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543146.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543146.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543146.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543147.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543147.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543147.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2421cc0] >[543147.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2421cc0] width 1280 pitch 5120 (/4 1280) >[543147.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a1b00] >[543147.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a1b00] width 1280 pitch 5120 (/4 1280) >[543147.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32770] >[543147.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32770] width 1280 pitch 5120 (/4 1280) >[543147.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a1b00] >[543147.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a1b00] width 1280 pitch 5120 (/4 1280) >[543147.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543147.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd1330] >[543147.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd1330] width 1280 pitch 5120 (/4 1280) >[543147.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf860] >[543147.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf860] width 1280 pitch 5120 (/4 1280) >[543164.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cda90] >[543164.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cda90] width 1280 pitch 5120 (/4 1280) >[543171.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d6930] >[543171.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d6930] width 1280 pitch 5120 (/4 1280) >[543171.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53010a0] >[543171.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53010a0] width 1280 pitch 5120 (/4 1280) >[543172.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bec0] >[543172.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bec0] width 1280 pitch 5120 (/4 1280) >[543172.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[543172.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[543173.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bec0] >[543173.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bec0] width 1280 pitch 5120 (/4 1280) >[543173.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fc130] >[543173.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fc130] width 1280 pitch 5120 (/4 1280) >[543174.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542cb60] >[543174.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542cb60] width 1280 pitch 5120 (/4 1280) >[543174.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bec0] >[543174.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bec0] width 1280 pitch 5120 (/4 1280) >[543191.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ca6e0] >[543191.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ca6e0] width 1280 pitch 5120 (/4 1280) >[543191.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53008f0] >[543191.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53008f0] width 1280 pitch 5120 (/4 1280) >[543192.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5352a50] >[543192.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5352a50] width 1280 pitch 5120 (/4 1280) >[543192.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4740] >[543192.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4740] width 1280 pitch 5120 (/4 1280) >[543192.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fda10] >[543192.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fda10] width 1280 pitch 5120 (/4 1280) >[543192.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2520] >[543192.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2520] width 1280 pitch 5120 (/4 1280) >[543199.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ca180] >[543199.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ca180] width 1280 pitch 5120 (/4 1280) >[543274.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ce330] >[543274.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ce330] width 1280 pitch 5120 (/4 1280) >[543274.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32970] >[543274.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32970] width 1280 pitch 5120 (/4 1280) >[543276.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543276.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543276.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543276.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543276.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543276.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28b9060] >[543276.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28b9060] width 1280 pitch 5120 (/4 1280) >[543276.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0ac0] >[543276.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0ac0] width 1280 pitch 5120 (/4 1280) >[543284.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ca4a0] >[543284.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ca4a0] width 1280 pitch 5120 (/4 1280) >[543426.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543426.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543426.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd12f0] >[543426.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd12f0] width 1280 pitch 5120 (/4 1280) >[543426.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543426.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543426.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543426.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543426.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543426.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543427.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543427.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543427.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543427.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543427.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543427.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543427.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543427.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543427.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543427.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543427.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543427.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0bc20] >[543428.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0bc20] width 1280 pitch 5120 (/4 1280) >[543428.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fd12f0] >[543428.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fd12f0] width 1280 pitch 5120 (/4 1280) >[543428.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543428.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543428.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543428.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543428.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543428.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543428.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543428.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543428.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4280] >[543428.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4280] width 1280 pitch 5120 (/4 1280) >[543428.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f2e40] >[543428.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f2e40] width 1280 pitch 5120 (/4 1280) >[543428.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b190] >[543428.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b190] width 1280 pitch 5120 (/4 1280) >[543428.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d5830] >[543428.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d5830] width 1280 pitch 5120 (/4 1280) >[543428.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0bc20] >[543428.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0bc20] width 1280 pitch 5120 (/4 1280) >[543493.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f0a00] >[543493.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f0a00] width 1280 pitch 5120 (/4 1280) >[543519.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54061d0] >[543519.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54061d0] width 1280 pitch 5120 (/4 1280) >[543519.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511bf50] >[543519.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511bf50] width 1280 pitch 5120 (/4 1280) >[543525.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f90b0] >[543525.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f90b0] width 1280 pitch 5120 (/4 1280) >[543542.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543542.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543542.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442c60] >[543542.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442c60] width 1280 pitch 5120 (/4 1280) >[543542.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5140680] >[543542.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5140680] width 1280 pitch 5120 (/4 1280) >[543543.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51194e0] >[543543.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51194e0] width 1280 pitch 5120 (/4 1280) >[543543.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543543.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543543.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5140680] >[543543.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5140680] width 1280 pitch 5120 (/4 1280) >[543543.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2a40] >[543543.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2a40] width 1280 pitch 5120 (/4 1280) >[543543.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543543.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543562.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456f50] >[543562.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456f50] width 1280 pitch 5120 (/4 1280) >[543562.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545cac0] >[543562.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545cac0] width 1280 pitch 5120 (/4 1280) >[543562.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[543562.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[543562.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[543562.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[543562.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[543562.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[543562.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543562.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543562.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[543563.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[543563.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543563.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543563.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[543563.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[543563.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543563.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543563.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4f0] >[543563.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4f0] width 1280 pitch 5120 (/4 1280) >[543563.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543563.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543563.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5452260] >[543563.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5452260] width 1280 pitch 5120 (/4 1280) >[543563.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543563.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543563.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5452260] >[543563.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5452260] width 1280 pitch 5120 (/4 1280) >[543563.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543563.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543563.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5452260] >[543563.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5452260] width 1280 pitch 5120 (/4 1280) >[543563.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54430d0] >[543563.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54430d0] width 1280 pitch 5120 (/4 1280) >[543563.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544fde0] >[543563.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544fde0] width 1280 pitch 5120 (/4 1280) >[543563.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[543563.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[543563.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543563.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543563.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50344d0] >[543563.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50344d0] width 1280 pitch 5120 (/4 1280) >[543563.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543563.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543563.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442c60] >[543563.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442c60] width 1280 pitch 5120 (/4 1280) >[543563.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543563.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543563.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442c60] >[543563.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442c60] width 1280 pitch 5120 (/4 1280) >[543563.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543563.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543563.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442c60] >[543563.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442c60] width 1280 pitch 5120 (/4 1280) >[543563.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[543563.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[543563.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543563.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543563.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5056530] >[543563.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5056530] width 1280 pitch 5120 (/4 1280) >[543563.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543563.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543563.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5056530] >[543563.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5056530] width 1280 pitch 5120 (/4 1280) >[543564.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543564.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543564.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5056530] >[543564.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5056530] width 1280 pitch 5120 (/4 1280) >[543564.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5457bb0] >[543564.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5457bb0] width 1280 pitch 5120 (/4 1280) >[543564.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456780] >[543564.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456780] width 1280 pitch 5120 (/4 1280) >[543564.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543564.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543564.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545cac0] >[543564.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545cac0] width 1280 pitch 5120 (/4 1280) >[543564.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543564.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543564.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545cac0] >[543564.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545cac0] width 1280 pitch 5120 (/4 1280) >[543564.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543564.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543564.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545cac0] >[543564.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545cac0] width 1280 pitch 5120 (/4 1280) >[543564.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543564.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543564.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[543564.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[543564.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543564.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543564.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543564.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543564.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9ac0] >[543564.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9ac0] width 1280 pitch 5120 (/4 1280) >[543565.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543565.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543565.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[543565.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[543565.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543565.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543565.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039a70] >[543565.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039a70] width 1280 pitch 5120 (/4 1280) >[543565.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543565.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543565.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d4250] >[543565.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d4250] width 1280 pitch 5120 (/4 1280) >[543565.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543565.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543565.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456f50] >[543565.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456f50] width 1280 pitch 5120 (/4 1280) >[543565.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x11a8120] >[543565.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x11a8120] width 1280 pitch 5120 (/4 1280) >[543565.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456f50] >[543565.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456f50] width 1280 pitch 5120 (/4 1280) >[543565.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511bf50] >[543565.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511bf50] width 1280 pitch 5120 (/4 1280) >[543565.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456f50] >[543565.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456f50] width 1280 pitch 5120 (/4 1280) >[543565.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54430d0] >[543565.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54430d0] width 1280 pitch 5120 (/4 1280) >[543565.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5457bb0] >[543565.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5457bb0] width 1280 pitch 5120 (/4 1280) >[543565.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456780] >[543565.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456780] width 1280 pitch 5120 (/4 1280) >[543565.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5457bb0] >[543565.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5457bb0] width 1280 pitch 5120 (/4 1280) >[543565.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456780] >[543565.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456780] width 1280 pitch 5120 (/4 1280) >[543565.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a12c30] >[543565.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a12c30] width 1280 pitch 5120 (/4 1280) >[543565.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456780] >[543565.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456780] width 1280 pitch 5120 (/4 1280) >[543565.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[543565.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[543565.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5456780] >[543565.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5456780] width 1280 pitch 5120 (/4 1280) >[543565.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[543565.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[543565.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543565.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543565.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a98b60] >[543565.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a98b60] width 1280 pitch 5120 (/4 1280) >[543565.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461bca0] >[543565.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461bca0] width 1280 pitch 5120 (/4 1280) >[543578.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544fde0] >[543578.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544fde0] width 1280 pitch 5120 (/4 1280) >[543578.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543578.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543578.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5140680] >[543578.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5140680] width 1280 pitch 5120 (/4 1280) >[543578.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5409a70] >[543578.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5409a70] width 1280 pitch 5120 (/4 1280) >[543589.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5457bb0] >[543589.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5457bb0] width 1280 pitch 5120 (/4 1280) >[543589.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5401fa0] >[543589.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5401fa0] width 1280 pitch 5120 (/4 1280) >[543607.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[543607.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[543656.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147b4d0] >[543656.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147b4d0] width 1280 pitch 5120 (/4 1280) >[543656.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3c60] >[543656.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3c60] width 1280 pitch 5120 (/4 1280) >[543656.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147b4d0] >[543656.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147b4d0] width 1280 pitch 5120 (/4 1280) >[543656.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3c60] >[543656.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3c60] width 1280 pitch 5120 (/4 1280) >[543656.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x147b4d0] >[543656.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x147b4d0] width 1280 pitch 5120 (/4 1280) >[543656.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3c60] >[543656.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3c60] width 1280 pitch 5120 (/4 1280) >[543656.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5457bb0] >[543656.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5457bb0] width 1280 pitch 5120 (/4 1280) >[543656.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5454f50] >[543656.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5454f50] width 1280 pitch 5120 (/4 1280) >[543656.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a8610] >[543656.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a8610] width 1280 pitch 5120 (/4 1280) >[543656.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2a40] >[543656.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2a40] width 1280 pitch 5120 (/4 1280) >[543656.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53813e0] >[543656.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53813e0] width 1280 pitch 5120 (/4 1280) >[543657.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4237210] >[543657.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4237210] width 1280 pitch 5120 (/4 1280) >[543657.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545f7e0] >[543657.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545f7e0] width 1280 pitch 5120 (/4 1280) >[543657.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[543657.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[543657.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5454bb0] >[543657.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5454bb0] width 1280 pitch 5120 (/4 1280) >[543657.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461bca0] >[543657.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461bca0] width 1280 pitch 5120 (/4 1280) >[543657.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513f2d0] >[543657.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513f2d0] width 1280 pitch 5120 (/4 1280) >[543657.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3100] >[543657.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3100] width 1280 pitch 5120 (/4 1280) >[543657.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3c60] >[543657.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3c60] width 1280 pitch 5120 (/4 1280) >[543658.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51486b0] >[543658.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51486b0] width 1280 pitch 5120 (/4 1280) >[543658.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f1270] >[543658.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f1270] width 1280 pitch 5120 (/4 1280) >[543658.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f90b0] >[543658.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f90b0] width 1280 pitch 5120 (/4 1280) >[543658.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f1270] >[543658.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f1270] width 1280 pitch 5120 (/4 1280) >[543658.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a5340] >[543658.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a5340] width 1280 pitch 5120 (/4 1280) >[543658.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442c60] >[543658.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442c60] width 1280 pitch 5120 (/4 1280) >[543658.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545d780] >[543658.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545d780] width 1280 pitch 5120 (/4 1280) >[543658.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545f7e0] >[543658.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545f7e0] width 1280 pitch 5120 (/4 1280) >[543658.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5454bb0] >[543658.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5454bb0] width 1280 pitch 5120 (/4 1280) >[543658.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461bca0] >[543658.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461bca0] width 1280 pitch 5120 (/4 1280) >[543658.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54560c0] >[543658.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54560c0] width 1280 pitch 5120 (/4 1280) >[543658.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[543658.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[543658.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513f2d0] >[543658.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513f2d0] width 1280 pitch 5120 (/4 1280) >[543659.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53813e0] >[543659.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53813e0] width 1280 pitch 5120 (/4 1280) >[543659.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f90b0] >[543659.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f90b0] width 1280 pitch 5120 (/4 1280) >[543662.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3100] >[543662.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3100] width 1280 pitch 5120 (/4 1280) >[543663.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53813e0] >[543664.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53813e0] width 1280 pitch 5120 (/4 1280) >[543698.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f1270] >[543698.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f1270] width 1280 pitch 5120 (/4 1280) >[543698.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5140680] >[543698.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5140680] width 1280 pitch 5120 (/4 1280) >[543702.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5455a30] >[543702.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5455a30] width 1280 pitch 5120 (/4 1280) >[543702.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3500c30] >[543702.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3500c30] width 1280 pitch 5120 (/4 1280) >[543702.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51486b0] >[543702.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51486b0] width 1280 pitch 5120 (/4 1280) >[543702.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4e50] >[543702.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4e50] width 1280 pitch 5120 (/4 1280) >[543739.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x513f2d0] >[543739.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x513f2d0] width 1280 pitch 5120 (/4 1280) >[543746.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2057ad0] >[543746.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2057ad0] width 1280 pitch 5120 (/4 1280) >[543747.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5455a30] >[543747.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5455a30] width 1280 pitch 5120 (/4 1280) >[543747.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5140680] >[543747.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5140680] width 1280 pitch 5120 (/4 1280) >[543906.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462140] >[543906.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462140] width 1280 pitch 5120 (/4 1280) >[543906.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462140] >[543906.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462140] width 1280 pitch 5120 (/4 1280) >[543906.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511bf50] >[543906.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511bf50] width 1280 pitch 5120 (/4 1280) >[543906.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462140] >[543906.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462140] width 1280 pitch 5120 (/4 1280) >[543906.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462140] >[543906.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462140] width 1280 pitch 5120 (/4 1280) >[543906.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536fd90] >[543906.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536fd90] width 1280 pitch 5120 (/4 1280) >[543907.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3100] >[543907.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3100] width 1280 pitch 5120 (/4 1280) >[543907.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462140] >[543907.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462140] width 1280 pitch 5120 (/4 1280) >[543907.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536fd90] >[543907.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536fd90] width 1280 pitch 5120 (/4 1280) >[543907.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a3100] >[543907.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a3100] width 1280 pitch 5120 (/4 1280) >[543907.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54063b0] >[543907.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54063b0] width 1280 pitch 5120 (/4 1280) >[543908.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5392ef0] >[543908.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5392ef0] width 1280 pitch 5120 (/4 1280) >[543950.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545c770] >[543950.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545c770] width 1280 pitch 5120 (/4 1280) >[543977.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c72c0] >[543977.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c72c0] width 1280 pitch 5120 (/4 1280) >[543977.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c9500] >[543977.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c9500] width 1280 pitch 5120 (/4 1280) >[543986.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[543986.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544012.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x541fc50] >[544012.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x541fc50] width 1280 pitch 5120 (/4 1280) >[544012.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544012.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544019.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c64a0] >[544019.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c64a0] width 1280 pitch 5120 (/4 1280) >[544019.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a38e0] >[544019.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a38e0] width 1280 pitch 5120 (/4 1280) >[544028.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544028.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544028.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544028.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544028.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544028.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544028.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544028.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544028.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544028.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544028.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544029.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544029.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544029.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544029.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544029.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544029.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544029.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544029.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544029.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544029.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544030.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544030.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544030.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544030.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544030.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544030.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544030.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544030.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544030.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544030.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544030.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544030.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544030.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544030.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544030.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544030.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544031.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea7b0] >[544031.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea7b0] width 1280 pitch 5120 (/4 1280) >[544031.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544031.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544031.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544031.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544031.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544031.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544031.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544031.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544031.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5452910] >[544031.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5452910] width 1280 pitch 5120 (/4 1280) >[544031.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544031.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544031.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a38e0] >[544031.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a38e0] width 1280 pitch 5120 (/4 1280) >[544031.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544031.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544031.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a38e0] >[544032.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a38e0] width 1280 pitch 5120 (/4 1280) >[544032.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544032.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544032.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544032.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544032.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544032.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544032.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a38e0] >[544032.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a38e0] width 1280 pitch 5120 (/4 1280) >[544032.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544032.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544032.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544032.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544032.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e6700] >[544032.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e6700] width 1280 pitch 5120 (/4 1280) >[544032.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544032.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544032.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544032.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544032.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544032.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5284630] >[544032.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5284630] width 1280 pitch 5120 (/4 1280) >[544032.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540fa50] >[544032.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540fa50] width 1280 pitch 5120 (/4 1280) >[544046.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544046.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544111.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544b820] >[544111.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544b820] width 1280 pitch 5120 (/4 1280) >[544111.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545a6a0] >[544111.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545a6a0] width 1280 pitch 5120 (/4 1280) >[544619.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544619.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544619.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544620.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544620.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544620.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544620.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544620.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544620.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fed0] >[544620.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fed0] width 1280 pitch 5120 (/4 1280) >[544620.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544620.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544620.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544620.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544620.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544620.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544620.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544620.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544620.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544620.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544620.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544620.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544620.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544620.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544621.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544621.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544621.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544621.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544621.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544621.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544621.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544621.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544621.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544621.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544621.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544621.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544621.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442870] >[544621.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442870] width 1280 pitch 5120 (/4 1280) >[544621.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fed0] >[544621.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fed0] width 1280 pitch 5120 (/4 1280) >[544621.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442870] >[544621.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442870] width 1280 pitch 5120 (/4 1280) >[544621.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[544621.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[544621.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544621.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544621.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[544621.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[544621.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544621.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544621.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[544621.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[544621.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544621.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544621.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544621.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544621.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545c320] >[544621.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545c320] width 1280 pitch 5120 (/4 1280) >[544621.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544621.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544621.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545c320] >[544621.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545c320] width 1280 pitch 5120 (/4 1280) >[544621.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x529b480] >[544621.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x529b480] width 1280 pitch 5120 (/4 1280) >[544621.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f0010] >[544621.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f0010] width 1280 pitch 5120 (/4 1280) >[544658.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545c320] >[544658.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545c320] width 1280 pitch 5120 (/4 1280) >[544658.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544658.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544658.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544658.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544658.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544658.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544658.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544658.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544658.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442870] >[544658.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442870] width 1280 pitch 5120 (/4 1280) >[544658.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544658.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544658.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442870] >[544658.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442870] width 1280 pitch 5120 (/4 1280) >[544658.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544658.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544658.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5442870] >[544658.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5442870] width 1280 pitch 5120 (/4 1280) >[544659.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544659.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544659.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544659.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544659.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544659.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544659.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544659.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544659.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544659.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544659.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544659.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544659.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544659.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544659.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544659.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544659.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544660.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544660.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544660.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544660.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544660.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544660.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544660.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544660.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8370] >[544661.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8370] width 1280 pitch 5120 (/4 1280) >[544661.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40849a0] >[544661.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40849a0] width 1280 pitch 5120 (/4 1280) >[544661.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544661.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544661.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544661.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544661.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544661.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544661.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544661.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544661.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544661.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544661.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544661.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544661.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544661.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544661.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544661.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544661.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52fb8c0] >[544661.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52fb8c0] width 1280 pitch 5120 (/4 1280) >[544661.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545c320] >[544661.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545c320] width 1280 pitch 5120 (/4 1280) >[544661.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[544661.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[544661.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544661.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544661.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544661.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544661.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[544661.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[544661.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[544661.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[544661.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544661.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544661.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5125760] >[544662.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5125760] width 1280 pitch 5120 (/4 1280) >[544662.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544662.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544662.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544662.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544662.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544662.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544662.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544662.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544662.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[544662.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[544662.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544662.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544662.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544662.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544662.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544662.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544662.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544662.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544662.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[544662.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[544662.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[544662.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[544662.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544662.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544662.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544662.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544662.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544662.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544662.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544662.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544662.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544662.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544662.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544662.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544662.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544662.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544662.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[544662.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[544662.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544662.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544662.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b2b0] >[544663.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b2b0] width 1280 pitch 5120 (/4 1280) >[544663.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5439bb0] >[544663.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5439bb0] width 1280 pitch 5120 (/4 1280) >[544663.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5439bb0] >[544663.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5439bb0] width 1280 pitch 5120 (/4 1280) >[544663.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b800] >[544663.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b800] width 1280 pitch 5120 (/4 1280) >[544663.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b800] >[544663.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b800] width 1280 pitch 5120 (/4 1280) >[544663.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544663.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544663.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544663.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544663.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544663.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544663.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[544663.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[544663.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[544663.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[544663.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c3c30] >[544663.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c3c30] width 1280 pitch 5120 (/4 1280) >[544663.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c51f0] >[544663.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c51f0] width 1280 pitch 5120 (/4 1280) >[544663.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b7c0] >[544663.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b7c0] width 1280 pitch 5120 (/4 1280) >[544663.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5414b80] >[544663.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5414b80] width 1280 pitch 5120 (/4 1280) >[544664.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b7c0] >[544664.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b7c0] width 1280 pitch 5120 (/4 1280) >[544664.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cb7b0] >[544664.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cb7b0] width 1280 pitch 5120 (/4 1280) >[544664.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cb7b0] >[544664.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cb7b0] width 1280 pitch 5120 (/4 1280) >[544664.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b7c0] >[544664.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b7c0] width 1280 pitch 5120 (/4 1280) >[544664.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cb7b0] >[544664.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cb7b0] width 1280 pitch 5120 (/4 1280) >[544664.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ce60] >[544664.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ce60] width 1280 pitch 5120 (/4 1280) >[544664.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7930] >[544664.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7930] width 1280 pitch 5120 (/4 1280) >[544664.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5436730] >[544664.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5436730] width 1280 pitch 5120 (/4 1280) >[544667.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540acf0] >[544667.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540acf0] width 1280 pitch 5120 (/4 1280) >[544667.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4151e70] >[544667.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4151e70] width 1280 pitch 5120 (/4 1280) >[544980.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5470b40] >[544980.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5470b40] width 1280 pitch 5120 (/4 1280) >[544980.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5470b40] >[544980.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5470b40] width 1280 pitch 5120 (/4 1280) >[545140.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5403e70] >[545140.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5403e70] width 1280 pitch 5120 (/4 1280) >[545140.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bdd30] >[545140.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bdd30] width 1280 pitch 5120 (/4 1280) >[545140.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5404ad0] >[545140.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5404ad0] width 1280 pitch 5120 (/4 1280) >[545141.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5404ad0] >[545141.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5404ad0] width 1280 pitch 5120 (/4 1280) >[545143.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f2d90] >[545143.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f2d90] width 1280 pitch 5120 (/4 1280) >[545143.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3408ef0] >[545143.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3408ef0] width 1280 pitch 5120 (/4 1280) >[545566.032] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[545566.032] (II) RADEON(0): Printing DDC gathered Modelines: >[545566.032] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[562800.439] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[562800.439] (II) RADEON(0): Printing DDC gathered Modelines: >[562800.439] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[562801.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562801.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562801.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562801.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562801.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562801.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562801.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562801.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562801.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562801.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562801.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562801.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562801.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562801.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562801.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562801.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562801.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562801.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562801.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562801.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562801.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562801.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562801.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562802.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562802.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562802.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562802.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562802.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562802.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562802.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562802.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562802.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562802.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562802.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562802.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562802.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562802.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562802.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562802.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562802.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562802.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562802.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562802.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562802.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562802.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562802.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562802.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562802.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562802.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562802.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562802.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562802.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562802.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562802.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562802.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562802.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562802.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562802.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562802.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562802.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562802.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562803.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562803.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562803.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cbd0] >[562803.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cbd0] width 1280 pitch 5120 (/4 1280) >[562803.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562803.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562803.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562803.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562803.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562804.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562804.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562804.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562804.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562804.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562804.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562804.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562804.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562804.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562804.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562804.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562804.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562804.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562804.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562804.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562804.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562804.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562804.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562804.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562804.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562804.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562805.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562805.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562805.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562805.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562805.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562805.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562805.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fbc70] >[562805.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fbc70] width 1280 pitch 5120 (/4 1280) >[562806.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562806.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562806.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562806.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562806.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562806.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562806.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562806.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562806.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562806.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562806.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562806.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562806.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562806.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562806.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562806.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562806.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dab80] >[562806.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dab80] width 1280 pitch 5120 (/4 1280) >[562806.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540d2b0] >[562806.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540d2b0] width 1280 pitch 5120 (/4 1280) >[562806.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562806.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[562806.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[562806.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562806.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562818.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e690] >[562818.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e690] width 1280 pitch 5120 (/4 1280) >[562823.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060dd0] >[562823.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060dd0] width 1280 pitch 5120 (/4 1280) >[562862.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4211a70] >[562862.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4211a70] width 1280 pitch 5120 (/4 1280) >[562958.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562958.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562958.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562958.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562958.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562958.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562958.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562958.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562958.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562958.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562958.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562958.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562958.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562958.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562958.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562958.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562959.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562959.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562959.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562959.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562959.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562959.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562959.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562959.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[562959.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[562959.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562959.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f5530] >[562959.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f5530] width 1280 pitch 5120 (/4 1280) >[562959.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562959.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562959.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562959.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562959.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562959.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562959.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562959.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562959.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562959.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[562959.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[562960.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562960.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562960.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[562960.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[562960.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562960.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562960.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[562960.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[562960.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562960.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562960.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[562960.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[562960.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562960.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562960.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[562960.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[562960.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562960.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562960.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[562960.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[562960.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562960.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562960.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562960.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562960.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562960.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562960.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562960.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562960.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562960.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562960.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562960.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562960.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562961.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562961.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562961.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562961.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5123030] >[562961.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5123030] width 1280 pitch 5120 (/4 1280) >[562961.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f5530] >[562961.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f5530] width 1280 pitch 5120 (/4 1280) >[562961.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562961.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562962.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562962.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562962.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[562962.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[562962.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[562962.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[562962.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d9a40] >[562962.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d9a40] width 1280 pitch 5120 (/4 1280) >[562962.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562962.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546cf90] >[562962.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546cf90] width 1280 pitch 5120 (/4 1280) >[562962.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562962.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[562971.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548bb20] >[562971.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548bb20] width 1280 pitch 5120 (/4 1280) >[563051.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5512110] >[563051.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5512110] width 1280 pitch 5120 (/4 1280) >[563052.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b800] >[563052.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b800] width 1280 pitch 5120 (/4 1280) >[563052.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44bd2b0] >[563052.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44bd2b0] width 1280 pitch 5120 (/4 1280) >[563052.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc0f0] >[563052.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc0f0] width 1280 pitch 5120 (/4 1280) >[563056.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545d0c0] >[563056.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545d0c0] width 1280 pitch 5120 (/4 1280) >[563056.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b800] >[563056.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b800] width 1280 pitch 5120 (/4 1280) >[563057.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545d0c0] >[563057.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545d0c0] width 1280 pitch 5120 (/4 1280) >[563057.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543b800] >[563057.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543b800] width 1280 pitch 5120 (/4 1280) >[563065.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546fe80] >[563065.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546fe80] width 1280 pitch 5120 (/4 1280) >[563075.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5512110] >[563075.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5512110] width 1280 pitch 5120 (/4 1280) >[563075.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cae80] >[563075.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cae80] width 1280 pitch 5120 (/4 1280) >[563246.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5512110] >[563246.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5512110] width 1280 pitch 5120 (/4 1280) >[563246.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e3c90] >[563246.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e3c90] width 1280 pitch 5120 (/4 1280) >[563257.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465870] >[563257.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465870] width 1280 pitch 5120 (/4 1280) >[563262.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465870] >[563262.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465870] width 1280 pitch 5120 (/4 1280) >[563262.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5491d60] >[563262.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5491d60] width 1280 pitch 5120 (/4 1280) >[563262.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5491d60] >[563262.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5491d60] width 1280 pitch 5120 (/4 1280) >[563262.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[563262.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[563262.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5491d60] >[563262.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5491d60] width 1280 pitch 5120 (/4 1280) >[563263.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465870] >[563263.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465870] width 1280 pitch 5120 (/4 1280) >[563267.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eaaae0] >[563267.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eaaae0] width 1280 pitch 5120 (/4 1280) >[563372.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563372.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563372.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563372.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563372.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563372.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563372.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563372.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563373.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563373.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563373.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563373.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563373.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563373.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563373.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563373.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff160] >[563373.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff160] width 1280 pitch 5120 (/4 1280) >[563373.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563373.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563373.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d89d0] >[563373.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d89d0] width 1280 pitch 5120 (/4 1280) >[563373.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d89d0] >[563373.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d89d0] width 1280 pitch 5120 (/4 1280) >[563373.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563373.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563373.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563373.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563373.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563373.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563373.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563373.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563373.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563373.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563373.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563373.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563374.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563374.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563374.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563374.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563395.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550d050] >[563395.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550d050] width 1280 pitch 5120 (/4 1280) >[563395.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d89d0] >[563395.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d89d0] width 1280 pitch 5120 (/4 1280) >[563396.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550d050] >[563396.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550d050] width 1280 pitch 5120 (/4 1280) >[563396.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550d050] >[563396.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550d050] width 1280 pitch 5120 (/4 1280) >[563396.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b740] >[563396.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b740] width 1280 pitch 5120 (/4 1280) >[563396.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550d050] >[563396.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550d050] width 1280 pitch 5120 (/4 1280) >[563397.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f3b60] >[563397.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f3b60] width 1280 pitch 5120 (/4 1280) >[563397.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563397.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563397.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c240] >[563397.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c240] width 1280 pitch 5120 (/4 1280) >[563397.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563397.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563433.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1630] >[563433.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1630] width 1280 pitch 5120 (/4 1280) >[563433.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[563433.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[563576.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a1ed0] >[563576.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a1ed0] width 1280 pitch 5120 (/4 1280) >[563576.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5503e20] >[563576.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5503e20] width 1280 pitch 5120 (/4 1280) >[572625.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572625.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572625.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5492cc0] >[572625.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5492cc0] width 1280 pitch 5120 (/4 1280) >[572625.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572625.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572625.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5492cc0] >[572625.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5492cc0] width 1280 pitch 5120 (/4 1280) >[572625.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572625.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572625.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5492cc0] >[572625.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5492cc0] width 1280 pitch 5120 (/4 1280) >[572625.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572625.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572625.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527910] >[572625.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527910] width 1280 pitch 5120 (/4 1280) >[572625.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a9500] >[572625.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a9500] width 1280 pitch 5120 (/4 1280) >[572625.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572625.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572625.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a9500] >[572625.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a9500] width 1280 pitch 5120 (/4 1280) >[572626.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b60] >[572626.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b60] width 1280 pitch 5120 (/4 1280) >[572626.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[572626.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[572626.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572626.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572626.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[572626.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[572626.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572626.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572626.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[572626.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[572626.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572626.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572627.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54941b0] >[572627.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54941b0] width 1280 pitch 5120 (/4 1280) >[572627.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0070] >[572627.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0070] width 1280 pitch 5120 (/4 1280) >[572627.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572627.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572627.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511d80] >[572627.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511d80] width 1280 pitch 5120 (/4 1280) >[572627.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493350] >[572627.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493350] width 1280 pitch 5120 (/4 1280) >[572628.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493350] >[572628.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493350] width 1280 pitch 5120 (/4 1280) >[572628.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572628.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55177f0] >[572628.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55177f0] width 1280 pitch 5120 (/4 1280) >[572628.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5496c60] >[572628.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5496c60] width 1280 pitch 5120 (/4 1280) >[572645.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527910] >[572645.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527910] width 1280 pitch 5120 (/4 1280) >[572645.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572645.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572645.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[572645.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[572645.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572646.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572652.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55276e0] >[572652.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55276e0] width 1280 pitch 5120 (/4 1280) >[572697.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493350] >[572697.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493350] width 1280 pitch 5120 (/4 1280) >[572697.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53df5a0] >[572697.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53df5a0] width 1280 pitch 5120 (/4 1280) >[572699.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5495450] >[572699.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5495450] width 1280 pitch 5120 (/4 1280) >[572699.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1390] >[572699.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1390] width 1280 pitch 5120 (/4 1280) >[572704.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55227a0] >[572704.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55227a0] width 1280 pitch 5120 (/4 1280) >[572706.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54941b0] >[572706.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54941b0] width 1280 pitch 5120 (/4 1280) >[572706.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53bfb90] >[572706.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53bfb90] width 1280 pitch 5120 (/4 1280) >[572706.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54941b0] >[572707.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54941b0] width 1280 pitch 5120 (/4 1280) >[572707.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5481ac0] >[572707.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5481ac0] width 1280 pitch 5120 (/4 1280) >[572722.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493580] >[572722.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493580] width 1280 pitch 5120 (/4 1280) >[572723.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e0ae0] >[572723.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e0ae0] width 1280 pitch 5120 (/4 1280) >[572723.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572723.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572724.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e0ae0] >[572724.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e0ae0] width 1280 pitch 5120 (/4 1280) >[572724.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e0c0] >[572724.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e0c0] width 1280 pitch 5120 (/4 1280) >[572724.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e0ae0] >[572724.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e0ae0] width 1280 pitch 5120 (/4 1280) >[572724.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ac250] >[572724.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ac250] width 1280 pitch 5120 (/4 1280) >[572724.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cae80] >[572724.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cae80] width 1280 pitch 5120 (/4 1280) >[572724.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bc840] >[572724.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bc840] width 1280 pitch 5120 (/4 1280) >[572724.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5503e20] >[572724.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5503e20] width 1280 pitch 5120 (/4 1280) >[572724.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53df5a0] >[572724.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53df5a0] width 1280 pitch 5120 (/4 1280) >[572724.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5503e20] >[572724.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5503e20] width 1280 pitch 5120 (/4 1280) >[572724.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cae80] >[572724.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cae80] width 1280 pitch 5120 (/4 1280) >[572724.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a8f10] >[572724.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a8f10] width 1280 pitch 5120 (/4 1280) >[572724.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cae80] >[572724.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cae80] width 1280 pitch 5120 (/4 1280) >[572724.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a8f10] >[572724.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a8f10] width 1280 pitch 5120 (/4 1280) >[572727.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e0ae0] >[572727.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e0ae0] width 1280 pitch 5120 (/4 1280) >[572729.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54970e0] >[572729.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54970e0] width 1280 pitch 5120 (/4 1280) >[572729.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54970e0] >[572729.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54970e0] width 1280 pitch 5120 (/4 1280) >[572729.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c380] >[572729.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c380] width 1280 pitch 5120 (/4 1280) >[572729.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x547cb00] >[572729.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x547cb00] width 1280 pitch 5120 (/4 1280) >[572746.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54970e0] >[572746.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54970e0] width 1280 pitch 5120 (/4 1280) >[572746.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55701a0] >[572746.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55701a0] width 1280 pitch 5120 (/4 1280) >[572749.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5481ac0] >[572749.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5481ac0] width 1280 pitch 5120 (/4 1280) >[572866.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572866.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572866.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572866.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572867.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572867.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572867.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572867.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572867.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572867.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572867.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572867.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572871.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572871.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572871.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572871.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572871.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572871.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572871.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572871.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572871.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572871.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572871.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572871.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572871.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572871.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572871.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572871.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572871.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572871.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572871.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540e2f0] >[572871.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540e2f0] width 1280 pitch 5120 (/4 1280) >[572871.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572871.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572871.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572871.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572871.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572871.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572871.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572871.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572871.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572871.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572871.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572871.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572871.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572871.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572871.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572871.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5576780] >[572871.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5576780] width 1280 pitch 5120 (/4 1280) >[572923.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572923.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572923.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552e2a0] >[572923.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552e2a0] width 1280 pitch 5120 (/4 1280) >[572923.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572923.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572924.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572924.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572924.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493120] >[572924.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493120] width 1280 pitch 5120 (/4 1280) >[572924.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572924.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572924.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493120] >[572924.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493120] width 1280 pitch 5120 (/4 1280) >[572924.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552d0f0] >[572924.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552d0f0] width 1280 pitch 5120 (/4 1280) >[572924.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572924.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572924.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552d0f0] >[572924.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552d0f0] width 1280 pitch 5120 (/4 1280) >[572924.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572924.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572924.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552d0f0] >[572924.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552d0f0] width 1280 pitch 5120 (/4 1280) >[572924.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572924.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572924.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572924.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572924.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572924.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572924.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572924.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572924.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572924.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572924.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572925.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572925.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572925.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572925.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572925.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572925.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55274b0] >[572925.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55274b0] width 1280 pitch 5120 (/4 1280) >[572925.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572925.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572925.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572925.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572925.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493120] >[572925.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493120] width 1280 pitch 5120 (/4 1280) >[572925.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572925.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572925.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493120] >[572925.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493120] width 1280 pitch 5120 (/4 1280) >[572925.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572925.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572925.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5493120] >[572925.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5493120] width 1280 pitch 5120 (/4 1280) >[572925.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[572925.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[572931.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b900] >[572931.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b900] width 1280 pitch 5120 (/4 1280) >[572931.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e81e0] >[572931.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e81e0] width 1280 pitch 5120 (/4 1280) >[572931.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552d0f0] >[572931.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552d0f0] width 1280 pitch 5120 (/4 1280) >[572932.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572932.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572934.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5575fe0] >[572934.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5575fe0] width 1280 pitch 5120 (/4 1280) >[572934.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e81e0] >[572934.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e81e0] width 1280 pitch 5120 (/4 1280) >[572938.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5480ed0] >[572938.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5480ed0] width 1280 pitch 5120 (/4 1280) >[572938.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552e2a0] >[572938.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552e2a0] width 1280 pitch 5120 (/4 1280) >[573070.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573070.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573070.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5301780] >[573070.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5301780] width 1280 pitch 5120 (/4 1280) >[573087.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573087.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573087.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573087.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573087.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573087.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573087.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573087.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573087.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573087.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573087.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573087.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573087.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573087.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573087.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573087.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573087.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573087.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573087.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573087.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573087.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573087.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573087.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573087.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573087.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573087.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573087.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573087.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573087.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573087.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573087.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573087.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573087.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573087.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573087.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573088.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573088.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573088.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573088.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573088.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573088.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573088.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573088.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573088.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573088.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573088.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573088.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573088.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573088.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573088.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573088.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573088.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573088.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573088.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573088.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573088.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573088.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573088.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573088.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573088.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573088.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573088.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573088.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573088.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573088.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573088.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573088.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573088.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573088.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573089.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573089.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573089.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573089.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573089.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573089.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573089.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573089.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554150] >[573090.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554150] width 1280 pitch 5120 (/4 1280) >[573090.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573090.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573090.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573090.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573090.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573090.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573090.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573090.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573090.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573090.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573090.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573090.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573090.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573090.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573090.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573090.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573090.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573090.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573090.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573090.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573090.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573090.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573090.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573090.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573091.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573091.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573091.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573091.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573091.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573091.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573091.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573091.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573091.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573091.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573091.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573092.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ffc0] >[573092.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ffc0] width 1280 pitch 5120 (/4 1280) >[573092.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573092.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573092.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573092.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573092.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573092.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573092.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573092.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573092.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573092.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573092.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573092.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573092.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573092.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[573092.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[573093.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573093.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573093.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573093.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573093.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fed0] >[573093.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fed0] width 1280 pitch 5120 (/4 1280) >[573093.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573093.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573093.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[573093.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[573093.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573093.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573093.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[573093.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[573093.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573093.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573093.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[573093.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[573093.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573093.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573093.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[573093.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[573093.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573093.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573093.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459480] >[573094.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459480] width 1280 pitch 5120 (/4 1280) >[573094.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573094.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573094.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573094.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573094.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573094.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573094.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573094.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573094.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573094.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573094.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573094.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573094.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573094.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573094.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554c40] >[573094.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554c40] width 1280 pitch 5120 (/4 1280) >[573094.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573094.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573094.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55289d0] >[573094.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55289d0] width 1280 pitch 5120 (/4 1280) >[573094.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573094.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573094.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573094.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573094.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5439700] >[573094.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5439700] width 1280 pitch 5120 (/4 1280) >[573094.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573094.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573094.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55283b0] >[573094.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55283b0] width 1280 pitch 5120 (/4 1280) >[573094.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51267c0] >[573094.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51267c0] width 1280 pitch 5120 (/4 1280) >[573094.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5439700] >[573094.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5439700] width 1280 pitch 5120 (/4 1280) >[573097.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573097.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573097.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573097.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573100.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558e390] >[573100.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558e390] width 1280 pitch 5120 (/4 1280) >[573114.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573114.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573114.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bff70] >[573114.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bff70] width 1280 pitch 5120 (/4 1280) >[573115.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bff70] >[573115.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bff70] width 1280 pitch 5120 (/4 1280) >[573115.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573115.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573115.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bff70] >[573115.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bff70] width 1280 pitch 5120 (/4 1280) >[573115.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573115.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573115.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bff70] >[573115.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bff70] width 1280 pitch 5120 (/4 1280) >[573115.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[573115.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[573115.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[573115.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[573115.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573115.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573115.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573115.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573115.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573116.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573116.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573116.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51296c0] >[573116.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51296c0] width 1280 pitch 5120 (/4 1280) >[573118.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543ad60] >[573118.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543ad60] width 1280 pitch 5120 (/4 1280) >[573118.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427e80] >[573118.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427e80] width 1280 pitch 5120 (/4 1280) >[573118.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573118.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573118.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543ac40] >[573118.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543ac40] width 1280 pitch 5120 (/4 1280) >[573119.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55331f0] >[573119.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55331f0] width 1280 pitch 5120 (/4 1280) >[573119.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bf8d0] >[573119.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bf8d0] width 1280 pitch 5120 (/4 1280) >[573121.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573121.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573122.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554be0] >[573122.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554be0] width 1280 pitch 5120 (/4 1280) >[573122.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6910] >[573122.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6910] width 1280 pitch 5120 (/4 1280) >[573123.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5422e70] >[573123.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5422e70] width 1280 pitch 5120 (/4 1280) >[573123.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554be0] >[573123.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554be0] width 1280 pitch 5120 (/4 1280) >[573123.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5422e70] >[573123.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5422e70] width 1280 pitch 5120 (/4 1280) >[573123.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554be0] >[573123.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554be0] width 1280 pitch 5120 (/4 1280) >[573123.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554fda0] >[573123.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554fda0] width 1280 pitch 5120 (/4 1280) >[573123.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c3280] >[573123.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c3280] width 1280 pitch 5120 (/4 1280) >[573134.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e96d0] >[573134.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e96d0] width 1280 pitch 5120 (/4 1280) >[573134.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573134.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573134.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573134.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573134.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573134.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573136.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573136.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573136.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e0f0] >[573136.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e0f0] width 1280 pitch 5120 (/4 1280) >[573136.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543ac40] >[573136.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543ac40] width 1280 pitch 5120 (/4 1280) >[573137.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573137.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573149.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573149.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573151.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543ac40] >[573151.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543ac40] width 1280 pitch 5120 (/4 1280) >[573156.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573156.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573168.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427800] >[573168.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427800] width 1280 pitch 5120 (/4 1280) >[573169.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543ac40] >[573169.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543ac40] width 1280 pitch 5120 (/4 1280) >[573169.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573169.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573169.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cff20] >[573169.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cff20] width 1280 pitch 5120 (/4 1280) >[573169.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5551800] >[573169.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5551800] width 1280 pitch 5120 (/4 1280) >[573169.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573169.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573169.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cfbf0] >[573169.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cfbf0] width 1280 pitch 5120 (/4 1280) >[573172.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573172.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573176.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573176.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573177.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cfbf0] >[573177.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cfbf0] width 1280 pitch 5120 (/4 1280) >[573178.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c1390] >[573178.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c1390] width 1280 pitch 5120 (/4 1280) >[573179.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5441380] >[573179.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5441380] width 1280 pitch 5120 (/4 1280) >[573192.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c1390] >[573192.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c1390] width 1280 pitch 5120 (/4 1280) >[573192.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e96d0] >[573192.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e96d0] width 1280 pitch 5120 (/4 1280) >[573192.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5301780] >[573192.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5301780] width 1280 pitch 5120 (/4 1280) >[573192.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e96d0] >[573192.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e96d0] width 1280 pitch 5120 (/4 1280) >[573193.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e94c0] >[573193.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e94c0] width 1280 pitch 5120 (/4 1280) >[573193.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573193.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573193.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e0f0] >[573193.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e0f0] width 1280 pitch 5120 (/4 1280) >[573193.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6820] >[573193.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6820] width 1280 pitch 5120 (/4 1280) >[573194.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5301780] >[573194.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5301780] width 1280 pitch 5120 (/4 1280) >[573194.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e96d0] >[573194.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e96d0] width 1280 pitch 5120 (/4 1280) >[573194.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573194.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573200.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0e60] >[573200.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0e60] width 1280 pitch 5120 (/4 1280) >[573200.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a5e60] >[573200.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a5e60] width 1280 pitch 5120 (/4 1280) >[573201.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573201.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573201.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4338b00] >[573201.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4338b00] width 1280 pitch 5120 (/4 1280) >[573201.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b4a0] >[573201.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b4a0] width 1280 pitch 5120 (/4 1280) >[573201.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573201.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573203.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573203.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573203.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5441300] >[573203.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5441300] width 1280 pitch 5120 (/4 1280) >[573216.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573216.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573216.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573216.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573216.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573216.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573216.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55761b0] >[573216.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55761b0] width 1280 pitch 5120 (/4 1280) >[573273.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558e670] >[573273.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558e670] width 1280 pitch 5120 (/4 1280) >[573273.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d56e0] >[573273.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d56e0] width 1280 pitch 5120 (/4 1280) >[573273.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573273.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573273.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543c270] >[573273.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543c270] width 1280 pitch 5120 (/4 1280) >[573276.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55629c0] >[573276.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55629c0] width 1280 pitch 5120 (/4 1280) >[573276.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573276.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573280.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555f640] >[573280.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555f640] width 1280 pitch 5120 (/4 1280) >[573280.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527c50] >[573280.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527c50] width 1280 pitch 5120 (/4 1280) >[573281.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a9240] >[573281.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a9240] width 1280 pitch 5120 (/4 1280) >[573281.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d6100] >[573281.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d6100] width 1280 pitch 5120 (/4 1280) >[573281.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554970] >[573281.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554970] width 1280 pitch 5120 (/4 1280) >[573281.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5554970] >[573281.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5554970] width 1280 pitch 5120 (/4 1280) >[573286.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a9240] >[573286.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a9240] width 1280 pitch 5120 (/4 1280) >[573286.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555f710] >[573286.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555f710] width 1280 pitch 5120 (/4 1280) >[573287.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527c50] >[573287.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527c50] width 1280 pitch 5120 (/4 1280) >[573287.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f9080] >[573287.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f9080] width 1280 pitch 5120 (/4 1280) >[573307.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527c50] >[573307.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527c50] width 1280 pitch 5120 (/4 1280) >[573320.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5527c50] >[573320.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5527c50] width 1280 pitch 5120 (/4 1280) >[573320.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5595990] >[573320.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5595990] width 1280 pitch 5120 (/4 1280) >[573327.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465870] >[573327.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465870] width 1280 pitch 5120 (/4 1280) >[573445.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573445.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573445.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573445.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573445.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573445.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573445.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573445.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573445.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573445.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573445.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573445.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573445.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573445.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573445.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52dee80] >[573445.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52dee80] width 1280 pitch 5120 (/4 1280) >[573445.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573445.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573445.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573445.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573445.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573445.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573445.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573445.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573445.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573445.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573445.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573445.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573445.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52dee80] >[573445.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52dee80] width 1280 pitch 5120 (/4 1280) >[573445.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573446.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573446.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5419650] >[573446.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5419650] width 1280 pitch 5120 (/4 1280) >[573446.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573446.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573446.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc2650] >[573446.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc2650] width 1280 pitch 5120 (/4 1280) >[573446.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573446.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573446.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc2650] >[573446.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc2650] width 1280 pitch 5120 (/4 1280) >[573446.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573446.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573446.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573446.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573446.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5419650] >[573446.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5419650] width 1280 pitch 5120 (/4 1280) >[573446.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573446.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573446.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52dee80] >[573446.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52dee80] width 1280 pitch 5120 (/4 1280) >[573446.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573446.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573446.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573446.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573446.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573446.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573446.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55949c0] >[573446.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55949c0] width 1280 pitch 5120 (/4 1280) >[573446.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e310] >[573446.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e310] width 1280 pitch 5120 (/4 1280) >[573446.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573446.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573446.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573446.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573446.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573446.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573446.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52dee80] >[573446.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52dee80] width 1280 pitch 5120 (/4 1280) >[573446.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573446.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573447.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573447.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573456.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573456.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573456.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573456.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573456.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f57c0] >[573456.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f57c0] width 1280 pitch 5120 (/4 1280) >[573456.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573456.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573456.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573456.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573457.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573457.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573457.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573457.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573457.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553a890] >[573457.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553a890] width 1280 pitch 5120 (/4 1280) >[573458.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573458.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573459.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573459.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573459.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573459.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573459.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573459.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573459.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573459.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573459.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573459.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573459.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573459.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573460.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573460.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573460.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573460.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573460.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573460.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573460.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f57c0] >[573460.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f57c0] width 1280 pitch 5120 (/4 1280) >[573460.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573460.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573461.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54509d0] >[573461.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54509d0] width 1280 pitch 5120 (/4 1280) >[573467.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573467.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573467.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f57c0] >[573467.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f57c0] width 1280 pitch 5120 (/4 1280) >[573467.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573467.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573467.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573467.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573468.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5599e10] >[573468.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5599e10] width 1280 pitch 5120 (/4 1280) >[573468.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573468.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573468.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54bb7a0] >[573468.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54bb7a0] width 1280 pitch 5120 (/4 1280) >[573469.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573469.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573469.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5532060] >[573469.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5532060] width 1280 pitch 5120 (/4 1280) >[573469.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e310] >[573469.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e310] width 1280 pitch 5120 (/4 1280) >[573469.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573469.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573469.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5451c50] >[573469.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5451c50] width 1280 pitch 5120 (/4 1280) >[573572.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b40b0] >[573572.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b40b0] width 1280 pitch 5120 (/4 1280) >[573753.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573753.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573753.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573753.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573753.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573753.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573753.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573754.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573754.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f00f0] >[573754.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f00f0] width 1280 pitch 5120 (/4 1280) >[573754.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573754.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573754.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573754.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573754.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573754.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573754.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573754.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573754.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573754.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573754.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573754.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573754.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573755.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573755.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573755.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573755.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573755.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573755.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573755.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573755.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573755.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573755.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f00f0] >[573755.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f00f0] width 1280 pitch 5120 (/4 1280) >[573755.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573755.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573755.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573755.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573755.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573755.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573755.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573755.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573755.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573755.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573755.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573755.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573755.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573755.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573755.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573755.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573755.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573755.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573755.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573755.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573755.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a22a0] >[573755.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a22a0] width 1280 pitch 5120 (/4 1280) >[573756.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5122770] >[573756.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5122770] width 1280 pitch 5120 (/4 1280) >[573756.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f00f0] >[573756.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f00f0] width 1280 pitch 5120 (/4 1280) >[573757.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5122770] >[573757.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5122770] width 1280 pitch 5120 (/4 1280) >[573757.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573757.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40869e0] >[573757.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40869e0] width 1280 pitch 5120 (/4 1280) >[573757.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55847c0] >[573757.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55847c0] width 1280 pitch 5120 (/4 1280) >[573768.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573768.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573772.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c3e0] >[573772.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c3e0] width 1280 pitch 5120 (/4 1280) >[573772.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573772.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573772.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee290] >[573772.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee290] width 1280 pitch 5120 (/4 1280) >[573772.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a63910] >[573773.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a63910] width 1280 pitch 5120 (/4 1280) >[573840.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573840.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573840.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573840.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573840.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573840.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573840.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573840.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573840.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573840.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573840.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573840.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573840.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573840.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573840.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573840.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573840.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573840.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573840.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573841.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573841.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573841.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573841.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573841.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573841.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573841.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573841.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54efe50] >[573841.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54efe50] width 1280 pitch 5120 (/4 1280) >[573841.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573841.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573841.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573841.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573841.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550d30] >[573841.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550d30] width 1280 pitch 5120 (/4 1280) >[573841.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573841.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573841.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573841.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573841.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573841.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573841.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573841.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573841.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573841.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573841.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573841.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573841.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573841.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573841.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573842.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573842.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573842.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573842.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573842.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573842.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573842.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573842.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573842.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573842.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573842.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573842.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573842.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573842.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573842.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573842.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573842.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573842.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573842.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573842.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573842.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5550000] >[573842.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5550000] width 1280 pitch 5120 (/4 1280) >[573842.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8660] >[573842.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8660] width 1280 pitch 5120 (/4 1280) >[573854.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573854.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573854.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573854.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573854.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573854.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573854.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573854.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573854.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573854.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573854.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573854.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573854.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573854.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573854.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573854.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425a40] >[573854.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425a40] width 1280 pitch 5120 (/4 1280) >[573854.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573854.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5122770] >[573855.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5122770] width 1280 pitch 5120 (/4 1280) >[573855.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cad0] >[573855.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cad0] width 1280 pitch 5120 (/4 1280) >[573855.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573855.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573855.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573855.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573855.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5459690] >[573855.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5459690] width 1280 pitch 5120 (/4 1280) >[573855.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573855.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573855.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573855.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573855.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425de0] >[573855.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425de0] width 1280 pitch 5120 (/4 1280) >[573855.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425a40] >[573855.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425a40] width 1280 pitch 5120 (/4 1280) >[573855.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bd80] >[573855.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bd80] width 1280 pitch 5120 (/4 1280) >[573855.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425a40] >[573855.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425a40] width 1280 pitch 5120 (/4 1280) >[573855.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bd80] >[573855.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bd80] width 1280 pitch 5120 (/4 1280) >[573855.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573855.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573855.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c7540] >[573855.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c7540] width 1280 pitch 5120 (/4 1280) >[573855.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573855.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573855.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c7540] >[573856.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c7540] width 1280 pitch 5120 (/4 1280) >[573856.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573856.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573856.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c7540] >[573856.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c7540] width 1280 pitch 5120 (/4 1280) >[573856.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573856.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573856.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8660] >[573856.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8660] width 1280 pitch 5120 (/4 1280) >[573856.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573856.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573856.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8660] >[573856.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8660] width 1280 pitch 5120 (/4 1280) >[573856.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543e040] >[573856.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543e040] width 1280 pitch 5120 (/4 1280) >[573887.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5d50] >[573887.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5d50] width 1280 pitch 5120 (/4 1280) >[573887.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8660] >[573887.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8660] width 1280 pitch 5120 (/4 1280) >[573890.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[573890.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[573890.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425a40] >[573890.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425a40] width 1280 pitch 5120 (/4 1280) >[573899.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[573899.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[573899.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573899.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573917.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573917.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573917.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573917.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573938.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3ae0] >[573938.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3ae0] width 1280 pitch 5120 (/4 1280) >[573938.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573938.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573946.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573946.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573946.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573946.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573946.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573946.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573946.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573946.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573946.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573946.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573946.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425830] >[573946.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425830] width 1280 pitch 5120 (/4 1280) >[573946.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425830] >[573946.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425830] width 1280 pitch 5120 (/4 1280) >[573946.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425830] >[573946.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425830] width 1280 pitch 5120 (/4 1280) >[573946.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573946.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425830] >[573946.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425830] width 1280 pitch 5120 (/4 1280) >[573946.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfda0] >[573946.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfda0] width 1280 pitch 5120 (/4 1280) >[573947.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573947.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573947.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55acfa0] >[573947.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55acfa0] width 1280 pitch 5120 (/4 1280) >[573947.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573947.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573947.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55acfa0] >[573947.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55acfa0] width 1280 pitch 5120 (/4 1280) >[573947.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573947.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573947.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55acfa0] >[573947.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55acfa0] width 1280 pitch 5120 (/4 1280) >[573947.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573947.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573947.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e0250] >[573947.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e0250] width 1280 pitch 5120 (/4 1280) >[573947.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573947.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573947.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e0250] >[573947.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e0250] width 1280 pitch 5120 (/4 1280) >[573948.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ed820] >[573948.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ed820] width 1280 pitch 5120 (/4 1280) >[573948.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573948.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573948.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bd80] >[573948.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bd80] width 1280 pitch 5120 (/4 1280) >[573949.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[573949.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[573949.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[573949.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[573950.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[573950.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[573950.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[573950.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[573950.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[573950.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[573950.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[573950.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[573950.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573950.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573950.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573950.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573950.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573950.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573950.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554dbd0] >[573950.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554dbd0] width 1280 pitch 5120 (/4 1280) >[573950.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[573950.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[573950.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[573950.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[573950.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573950.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573950.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[573950.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[573950.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573950.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573950.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[573950.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[573950.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573950.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573950.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[573950.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[573950.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[573950.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[573957.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573957.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573976.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573977.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573977.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573977.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573977.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573977.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573977.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573977.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573977.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573977.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573977.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573977.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573977.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573977.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573977.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573977.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573977.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573977.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573977.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573977.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573977.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573977.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573977.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573977.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573977.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573977.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573977.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573977.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573977.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573977.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573977.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573977.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573977.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573977.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573978.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573978.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573978.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573978.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573978.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573978.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573978.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573978.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573978.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573978.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573978.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573978.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573978.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573978.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573978.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573978.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573978.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573978.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573978.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573978.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573978.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559dc10] >[573978.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559dc10] width 1280 pitch 5120 (/4 1280) >[573978.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573978.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573978.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573978.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573978.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573978.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573978.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573978.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573978.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573978.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573978.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573978.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573979.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573979.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573979.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc3f0] >[573979.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc3f0] width 1280 pitch 5120 (/4 1280) >[573979.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573979.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573979.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fc0d0] >[573979.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fc0d0] width 1280 pitch 5120 (/4 1280) >[573979.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fa640] >[573979.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fa640] width 1280 pitch 5120 (/4 1280) >[573979.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573979.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[573980.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465610] >[573980.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465610] width 1280 pitch 5120 (/4 1280) >[573980.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55961f0] >[573980.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55961f0] width 1280 pitch 5120 (/4 1280) >[574008.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561b70] >[574008.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561b70] width 1280 pitch 5120 (/4 1280) >[574009.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574009.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574009.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fa640] >[574009.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fa640] width 1280 pitch 5120 (/4 1280) >[574009.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558e720] >[574009.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558e720] width 1280 pitch 5120 (/4 1280) >[574009.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574009.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574031.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55df0c0] >[574031.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55df0c0] width 1280 pitch 5120 (/4 1280) >[574031.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5594f10] >[574031.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5594f10] width 1280 pitch 5120 (/4 1280) >[574031.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f5f50] >[574031.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f5f50] width 1280 pitch 5120 (/4 1280) >[574031.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a3b0] >[574031.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a3b0] width 1280 pitch 5120 (/4 1280) >[574038.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aacd0] >[574038.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aacd0] width 1280 pitch 5120 (/4 1280) >[574038.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aba50] >[574038.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aba50] width 1280 pitch 5120 (/4 1280) >[574038.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aacd0] >[574038.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aacd0] width 1280 pitch 5120 (/4 1280) >[574038.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a1b20] >[574038.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a1b20] width 1280 pitch 5120 (/4 1280) >[574038.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558c420] >[574038.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558c420] width 1280 pitch 5120 (/4 1280) >[574038.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558e760] >[574038.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558e760] width 1280 pitch 5120 (/4 1280) >[574044.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558e760] >[574044.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558e760] width 1280 pitch 5120 (/4 1280) >[574048.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634990] >[574048.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634990] width 1280 pitch 5120 (/4 1280) >[574048.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a1b20] >[574048.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a1b20] width 1280 pitch 5120 (/4 1280) >[574055.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5630280] >[574055.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5630280] width 1280 pitch 5120 (/4 1280) >[574056.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e0d40] >[574056.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e0d40] width 1280 pitch 5120 (/4 1280) >[574056.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e0d40] >[574056.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e0d40] width 1280 pitch 5120 (/4 1280) >[574071.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f9480] >[574071.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f9480] width 1280 pitch 5120 (/4 1280) >[574071.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634c30] >[574071.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634c30] width 1280 pitch 5120 (/4 1280) >[574081.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f9480] >[574081.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f9480] width 1280 pitch 5120 (/4 1280) >[574081.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f9480] >[574081.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f9480] width 1280 pitch 5120 (/4 1280) >[574081.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634990] >[574082.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634990] width 1280 pitch 5120 (/4 1280) >[574082.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634990] >[574082.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634990] width 1280 pitch 5120 (/4 1280) >[574082.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562f8b0] >[574082.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562f8b0] width 1280 pitch 5120 (/4 1280) >[574082.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562f720] >[574082.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562f720] width 1280 pitch 5120 (/4 1280) >[574082.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56327e0] >[574082.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56327e0] width 1280 pitch 5120 (/4 1280) >[574082.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e0d40] >[574082.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e0d40] width 1280 pitch 5120 (/4 1280) >[574083.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a1b20] >[574083.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a1b20] width 1280 pitch 5120 (/4 1280) >[574083.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56368a0] >[574083.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56368a0] width 1280 pitch 5120 (/4 1280) >[574084.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2771e20] >[574084.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2771e20] width 1280 pitch 5120 (/4 1280) >[574084.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23d20] >[574084.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23d20] width 1280 pitch 5120 (/4 1280) >[574084.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23d20] >[574084.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23d20] width 1280 pitch 5120 (/4 1280) >[574084.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23d20] >[574084.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23d20] width 1280 pitch 5120 (/4 1280) >[574085.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c80170] >[574085.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c80170] width 1280 pitch 5120 (/4 1280) >[574085.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5465380] >[574085.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5465380] width 1280 pitch 5120 (/4 1280) >[574085.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5435290] >[574085.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5435290] width 1280 pitch 5120 (/4 1280) >[574096.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c7ea50] >[574096.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c7ea50] width 1280 pitch 5120 (/4 1280) >[574096.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574096.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574135.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e7d0] >[574135.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e7d0] width 1280 pitch 5120 (/4 1280) >[574135.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eed20] >[574135.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eed20] width 1280 pitch 5120 (/4 1280) >[574135.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574135.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574135.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1149a90] >[574135.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1149a90] width 1280 pitch 5120 (/4 1280) >[574139.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1149a90] >[574139.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1149a90] width 1280 pitch 5120 (/4 1280) >[574143.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e7d0] >[574143.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e7d0] width 1280 pitch 5120 (/4 1280) >[574147.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574147.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574149.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574149.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574149.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1149a90] >[574149.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1149a90] width 1280 pitch 5120 (/4 1280) >[574152.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5495e30] >[574152.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5495e30] width 1280 pitch 5120 (/4 1280) >[574152.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a9bf0] >[574152.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a9bf0] width 1280 pitch 5120 (/4 1280) >[574155.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56336d0] >[574155.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56336d0] width 1280 pitch 5120 (/4 1280) >[574155.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574155.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574156.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56336d0] >[574156.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56336d0] width 1280 pitch 5120 (/4 1280) >[574156.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23740] >[574156.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23740] width 1280 pitch 5120 (/4 1280) >[574156.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a2120] >[574156.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a2120] width 1280 pitch 5120 (/4 1280) >[574156.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574157.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574161.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574161.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574161.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f6570] >[574161.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f6570] width 1280 pitch 5120 (/4 1280) >[574162.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574162.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574162.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a2120] >[574162.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a2120] width 1280 pitch 5120 (/4 1280) >[574166.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e0770] >[574166.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e0770] width 1280 pitch 5120 (/4 1280) >[574166.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f6f20] >[574166.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f6f20] width 1280 pitch 5120 (/4 1280) >[574166.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574166.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574166.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a2120] >[574166.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a2120] width 1280 pitch 5120 (/4 1280) >[574170.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574170.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574170.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574170.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574171.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eed20] >[574171.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eed20] width 1280 pitch 5120 (/4 1280) >[574171.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e1b0] >[574171.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e1b0] width 1280 pitch 5120 (/4 1280) >[574171.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e7d0] >[574171.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e7d0] width 1280 pitch 5120 (/4 1280) >[574186.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eed20] >[574186.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eed20] width 1280 pitch 5120 (/4 1280) >[574187.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e1b0] >[574187.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e1b0] width 1280 pitch 5120 (/4 1280) >[574188.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574188.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574188.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574188.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574188.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574188.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574188.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2356f10] >[574188.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2356f10] width 1280 pitch 5120 (/4 1280) >[574188.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e1db0] >[574188.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e1db0] width 1280 pitch 5120 (/4 1280) >[574188.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eed20] >[574188.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eed20] width 1280 pitch 5120 (/4 1280) >[574190.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4680] >[574190.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4680] width 1280 pitch 5120 (/4 1280) >[574190.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562efc0] >[574190.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562efc0] width 1280 pitch 5120 (/4 1280) >[574196.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574196.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574197.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55489d0] >[574197.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55489d0] width 1280 pitch 5120 (/4 1280) >[574204.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562efc0] >[574204.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562efc0] width 1280 pitch 5120 (/4 1280) >[574204.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e1b0] >[574204.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e1b0] width 1280 pitch 5120 (/4 1280) >[574204.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4640] >[574204.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4640] width 1280 pitch 5120 (/4 1280) >[574204.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e1b0] >[574204.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e1b0] width 1280 pitch 5120 (/4 1280) >[574209.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c90] >[574209.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c90] width 1280 pitch 5120 (/4 1280) >[574213.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53287d0] >[574213.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53287d0] width 1280 pitch 5120 (/4 1280) >[574213.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1149a90] >[574213.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1149a90] width 1280 pitch 5120 (/4 1280) >[574254.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53287d0] >[574254.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53287d0] width 1280 pitch 5120 (/4 1280) >[574254.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635790] >[574254.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635790] width 1280 pitch 5120 (/4 1280) >[574254.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52f4640] >[574254.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52f4640] width 1280 pitch 5120 (/4 1280) >[574254.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c90] >[574254.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c90] width 1280 pitch 5120 (/4 1280) >[574307.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297c90] >[574307.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297c90] width 1280 pitch 5120 (/4 1280) >[574315.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562efc0] >[574315.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562efc0] width 1280 pitch 5120 (/4 1280) >[574335.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c90] >[574335.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c90] width 1280 pitch 5120 (/4 1280) >[574343.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297d70] >[574343.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297d70] width 1280 pitch 5120 (/4 1280) >[574358.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297d70] >[574358.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297d70] width 1280 pitch 5120 (/4 1280) >[574362.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c90] >[574362.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c90] width 1280 pitch 5120 (/4 1280) >[574402.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c90] >[574402.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c90] width 1280 pitch 5120 (/4 1280) >[574483.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635610] >[574483.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635610] width 1280 pitch 5120 (/4 1280) >[574488.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635610] >[574488.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635610] width 1280 pitch 5120 (/4 1280) >[574491.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647350] >[574492.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647350] width 1280 pitch 5120 (/4 1280) >[574492.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574492.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574492.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574492.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574492.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5327500] >[574492.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5327500] width 1280 pitch 5120 (/4 1280) >[574493.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574493.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574493.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574493.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574493.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574493.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574493.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5327fe0] >[574493.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5327fe0] width 1280 pitch 5120 (/4 1280) >[574494.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574494.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574494.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574494.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574494.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574494.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574494.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574494.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574499.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2356f10] >[574499.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2356f10] width 1280 pitch 5120 (/4 1280) >[574499.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a680] >[574499.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a680] width 1280 pitch 5120 (/4 1280) >[574499.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55488b0] >[574499.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55488b0] width 1280 pitch 5120 (/4 1280) >[574499.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e2e0] >[574499.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e2e0] width 1280 pitch 5120 (/4 1280) >[574508.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559e2e0] >[574508.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559e2e0] width 1280 pitch 5120 (/4 1280) >[574510.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c10] >[574510.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c10] width 1280 pitch 5120 (/4 1280) >[574510.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1149330] >[574510.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1149330] width 1280 pitch 5120 (/4 1280) >[574520.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574520.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574520.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5328420] >[574520.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5328420] width 1280 pitch 5120 (/4 1280) >[574520.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5647c10] >[574521.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5647c10] width 1280 pitch 5120 (/4 1280) >[574548.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635610] >[574548.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635610] width 1280 pitch 5120 (/4 1280) >[574550.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5328420] >[574551.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5328420] width 1280 pitch 5120 (/4 1280) >[574551.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5328420] >[574551.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5328420] width 1280 pitch 5120 (/4 1280) >[574552.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574552.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574553.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5645e20] >[574553.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5645e20] width 1280 pitch 5120 (/4 1280) >[574553.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574553.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574553.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5645e20] >[574553.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5645e20] width 1280 pitch 5120 (/4 1280) >[574558.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x562f000] >[574558.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x562f000] width 1280 pitch 5120 (/4 1280) >[574563.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574563.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574563.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd3a0] >[574563.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd3a0] width 1280 pitch 5120 (/4 1280) >[574563.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[574563.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[574563.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd3a0] >[574563.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd3a0] width 1280 pitch 5120 (/4 1280) >[574628.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[574628.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[574629.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dccc0] >[574629.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dccc0] width 1280 pitch 5120 (/4 1280) >[574629.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[574629.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[574629.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78ff0] >[574629.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78ff0] width 1280 pitch 5120 (/4 1280) >[574630.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54988b0] >[574630.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54988b0] width 1280 pitch 5120 (/4 1280) >[574630.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574630.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574632.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54988b0] >[574632.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54988b0] width 1280 pitch 5120 (/4 1280) >[574633.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd3a0] >[574633.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd3a0] width 1280 pitch 5120 (/4 1280) >[574633.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54988b0] >[574633.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54988b0] width 1280 pitch 5120 (/4 1280) >[574633.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd3a0] >[574633.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd3a0] width 1280 pitch 5120 (/4 1280) >[574634.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5698630] >[574634.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5698630] width 1280 pitch 5120 (/4 1280) >[574635.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ccf70] >[574635.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ccf70] width 1280 pitch 5120 (/4 1280) >[574647.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574647.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574647.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dccc0] >[574647.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dccc0] width 1280 pitch 5120 (/4 1280) >[574647.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba880] >[574647.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba880] width 1280 pitch 5120 (/4 1280) >[574647.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b120] >[574647.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b120] width 1280 pitch 5120 (/4 1280) >[574651.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8f0] >[574651.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8f0] width 1280 pitch 5120 (/4 1280) >[574651.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460b120] >[574651.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460b120] width 1280 pitch 5120 (/4 1280) >[574651.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574651.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574651.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[574651.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[574654.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574654.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574655.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[574655.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[574655.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[574655.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[574655.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a280] >[574655.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a280] width 1280 pitch 5120 (/4 1280) >[574655.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4273950] >[574655.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4273950] width 1280 pitch 5120 (/4 1280) >[574655.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5658870] >[574655.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5658870] width 1280 pitch 5120 (/4 1280) >[574655.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[574655.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[574655.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574655.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574659.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574659.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574659.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54988b0] >[574659.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54988b0] width 1280 pitch 5120 (/4 1280) >[574660.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[574660.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[574660.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574660.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574660.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9980] >[574660.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9980] width 1280 pitch 5120 (/4 1280) >[574660.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97270] >[574660.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97270] width 1280 pitch 5120 (/4 1280) >[574663.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52714f0] >[574663.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52714f0] width 1280 pitch 5120 (/4 1280) >[574687.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f900] >[574687.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f900] width 1280 pitch 5120 (/4 1280) >[574687.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2b50] >[574687.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2b50] width 1280 pitch 5120 (/4 1280) >[574688.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425830] >[574688.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425830] width 1280 pitch 5120 (/4 1280) >[574688.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fee40] >[574688.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fee40] width 1280 pitch 5120 (/4 1280) >[574689.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fee40] >[574689.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fee40] width 1280 pitch 5120 (/4 1280) >[574689.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574689.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574689.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574689.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574689.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ec6b0] >[574689.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ec6b0] width 1280 pitch 5120 (/4 1280) >[574692.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574692.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574706.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f900] >[574706.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f900] width 1280 pitch 5120 (/4 1280) >[574706.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[574706.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[574706.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f900] >[574706.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f900] width 1280 pitch 5120 (/4 1280) >[574706.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[574706.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[574707.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574707.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574707.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574707.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574707.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574707.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574707.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574707.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574708.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[574708.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[574708.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f900] >[574708.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f900] width 1280 pitch 5120 (/4 1280) >[574709.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f900] >[574709.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f900] width 1280 pitch 5120 (/4 1280) >[574709.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574709.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574709.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574709.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574709.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574709.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574709.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574709.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574717.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574717.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574717.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574717.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574717.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574717.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574717.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574717.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574717.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574717.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574717.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574717.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574717.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574717.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574717.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574717.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574718.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574718.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574718.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574718.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574718.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574718.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574718.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574718.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574718.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574718.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574719.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574719.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574719.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574719.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a12a0] >[574719.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a12a0] width 1280 pitch 5120 (/4 1280) >[574720.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574720.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574720.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574720.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574720.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574720.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574720.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574720.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574720.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574720.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574720.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574720.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574720.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574720.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574720.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544cd50] >[574720.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544cd50] width 1280 pitch 5120 (/4 1280) >[574720.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574720.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574720.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[574720.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[574724.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5472dd0] >[574724.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5472dd0] width 1280 pitch 5120 (/4 1280) >[574724.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[574724.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[574724.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574724.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574724.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574724.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574724.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574724.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574724.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574724.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574724.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2e80] >[574724.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2e80] width 1280 pitch 5120 (/4 1280) >[574724.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574724.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574724.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd220] >[574724.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd220] width 1280 pitch 5120 (/4 1280) >[574724.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a87c0] >[574724.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a87c0] width 1280 pitch 5120 (/4 1280) >[574765.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574765.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574765.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574765.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574765.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574765.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574765.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574765.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574765.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d04a0] >[574765.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d04a0] width 1280 pitch 5120 (/4 1280) >[574765.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5346870] >[574765.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5346870] width 1280 pitch 5120 (/4 1280) >[574768.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574768.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574769.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574769.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574769.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574769.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574769.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574769.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574769.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6a0] >[574769.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6a0] width 1280 pitch 5120 (/4 1280) >[574769.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50207c0] >[574769.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50207c0] width 1280 pitch 5120 (/4 1280) >[574781.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55df5e0] >[574781.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55df5e0] width 1280 pitch 5120 (/4 1280) >[574781.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55df440] >[574781.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55df440] width 1280 pitch 5120 (/4 1280) >[574781.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574782.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574782.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[574782.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[574782.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a540] >[574782.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a540] width 1280 pitch 5120 (/4 1280) >[574784.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5649d40] >[574784.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5649d40] width 1280 pitch 5120 (/4 1280) >[574812.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5649b00] >[574812.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5649b00] width 1280 pitch 5120 (/4 1280) >[574812.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55394c0] >[574812.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55394c0] width 1280 pitch 5120 (/4 1280) >[574813.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574813.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574813.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5657410] >[574813.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5657410] width 1280 pitch 5120 (/4 1280) >[574814.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55394c0] >[574814.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55394c0] width 1280 pitch 5120 (/4 1280) >[574814.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574814.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574815.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f8fd0] >[574815.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f8fd0] width 1280 pitch 5120 (/4 1280) >[574815.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574815.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574816.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574816.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574816.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574816.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574816.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5524a00] >[574816.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5524a00] width 1280 pitch 5120 (/4 1280) >[574816.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56436c0] >[574816.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56436c0] width 1280 pitch 5120 (/4 1280) >[574818.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574818.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574820.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fd3a0] >[574820.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fd3a0] width 1280 pitch 5120 (/4 1280) >[574820.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56435a0] >[574820.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56435a0] width 1280 pitch 5120 (/4 1280) >[574820.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574820.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574820.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561fe50] >[574820.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561fe50] width 1280 pitch 5120 (/4 1280) >[574827.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574827.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574830.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[574830.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[574831.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561fe50] >[574831.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561fe50] width 1280 pitch 5120 (/4 1280) >[574831.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55394c0] >[574831.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55394c0] width 1280 pitch 5120 (/4 1280) >[574831.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574831.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574831.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0fd0] >[574831.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0fd0] width 1280 pitch 5120 (/4 1280) >[574831.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0480] >[574831.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0480] width 1280 pitch 5120 (/4 1280) >[574831.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0fd0] >[574831.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0fd0] width 1280 pitch 5120 (/4 1280) >[574832.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0480] >[574832.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0480] width 1280 pitch 5120 (/4 1280) >[574834.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[574834.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[574834.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563e080] >[574834.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563e080] width 1280 pitch 5120 (/4 1280) >[574835.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56217e0] >[574835.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56217e0] width 1280 pitch 5120 (/4 1280) >[574835.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0480] >[574835.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0480] width 1280 pitch 5120 (/4 1280) >[574835.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564b490] >[574835.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564b490] width 1280 pitch 5120 (/4 1280) >[574839.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56438b0] >[574839.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56438b0] width 1280 pitch 5120 (/4 1280) >[574839.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0480] >[574839.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0480] width 1280 pitch 5120 (/4 1280) >[574839.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56217e0] >[574839.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56217e0] width 1280 pitch 5120 (/4 1280) >[574839.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ca4d0] >[574839.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ca4d0] width 1280 pitch 5120 (/4 1280) >[574840.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[574840.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[574840.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564b530] >[574840.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564b530] width 1280 pitch 5120 (/4 1280) >[574840.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8bb0] >[574840.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8bb0] width 1280 pitch 5120 (/4 1280) >[574840.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574840.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574842.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574842.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574842.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5643630] >[574842.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5643630] width 1280 pitch 5120 (/4 1280) >[574843.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5657410] >[574843.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5657410] width 1280 pitch 5120 (/4 1280) >[574843.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574843.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574843.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x568f780] >[574843.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x568f780] width 1280 pitch 5120 (/4 1280) >[574843.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574843.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574854.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a0480] >[574854.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a0480] width 1280 pitch 5120 (/4 1280) >[574854.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52939f0] >[574854.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52939f0] width 1280 pitch 5120 (/4 1280) >[574854.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574854.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574854.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5657410] >[574854.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5657410] width 1280 pitch 5120 (/4 1280) >[574855.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4273c60] >[574855.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4273c60] width 1280 pitch 5120 (/4 1280) >[574855.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574855.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574855.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5657410] >[574855.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5657410] width 1280 pitch 5120 (/4 1280) >[574855.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574855.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574857.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574857.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574857.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[574857.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[574857.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574857.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574857.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574857.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574858.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5657410] >[574858.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5657410] width 1280 pitch 5120 (/4 1280) >[574858.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574858.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574858.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ca4d0] >[574858.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ca4d0] width 1280 pitch 5120 (/4 1280) >[574858.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5643630] >[574858.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5643630] width 1280 pitch 5120 (/4 1280) >[574863.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574863.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574863.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[574863.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[574863.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561f910] >[574863.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561f910] width 1280 pitch 5120 (/4 1280) >[574863.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[574863.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[574864.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574864.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574864.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574864.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574864.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574864.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574864.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574864.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574865.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574865.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574865.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2b50] >[574865.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2b50] width 1280 pitch 5120 (/4 1280) >[574865.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574865.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574865.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56525b0] >[574865.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56525b0] width 1280 pitch 5120 (/4 1280) >[574866.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574866.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574866.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574866.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574866.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a80d0] >[574866.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a80d0] width 1280 pitch 5120 (/4 1280) >[574866.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d2b90] >[574866.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d2b90] width 1280 pitch 5120 (/4 1280) >[574870.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574870.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574870.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574870.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574871.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574871.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574871.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574871.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574871.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5643630] >[574871.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5643630] width 1280 pitch 5120 (/4 1280) >[574871.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ddc60] >[574871.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ddc60] width 1280 pitch 5120 (/4 1280) >[574872.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ddc60] >[574872.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ddc60] width 1280 pitch 5120 (/4 1280) >[574872.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[574872.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[574872.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf6e0] >[574872.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf6e0] width 1280 pitch 5120 (/4 1280) >[574872.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574872.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574935.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574935.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574935.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dce10] >[574935.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dce10] width 1280 pitch 5120 (/4 1280) >[574936.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56e2e00] >[574936.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56e2e00] width 1280 pitch 5120 (/4 1280) >[574936.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56e2e00] >[574936.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56e2e00] width 1280 pitch 5120 (/4 1280) >[574936.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dce10] >[574936.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dce10] width 1280 pitch 5120 (/4 1280) >[574936.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574936.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574951.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5654490] >[574952.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5654490] width 1280 pitch 5120 (/4 1280) >[574960.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574960.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574961.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dce10] >[574961.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dce10] width 1280 pitch 5120 (/4 1280) >[574962.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574962.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574966.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574966.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574966.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dce10] >[574966.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dce10] width 1280 pitch 5120 (/4 1280) >[574976.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5654490] >[574976.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5654490] width 1280 pitch 5120 (/4 1280) >[574976.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5654490] >[574976.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5654490] width 1280 pitch 5120 (/4 1280) >[574976.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574976.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574976.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574976.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574978.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5655a90] >[574978.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5655a90] width 1280 pitch 5120 (/4 1280) >[574978.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5651270] >[574978.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5651270] width 1280 pitch 5120 (/4 1280) >[574978.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574978.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574978.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574978.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574979.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dce10] >[574979.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dce10] width 1280 pitch 5120 (/4 1280) >[574979.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574979.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574979.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574979.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574979.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574979.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574980.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5654490] >[574980.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5654490] width 1280 pitch 5120 (/4 1280) >[574980.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574980.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574980.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574980.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574980.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5655a90] >[574980.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5655a90] width 1280 pitch 5120 (/4 1280) >[574980.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574980.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574980.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5670e50] >[574980.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5670e50] width 1280 pitch 5120 (/4 1280) >[574981.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[574981.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[574981.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d5080] >[574981.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d5080] width 1280 pitch 5120 (/4 1280) >[574990.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574990.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574990.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5655a90] >[574990.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5655a90] width 1280 pitch 5120 (/4 1280) >[574990.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ee4b0] >[574990.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ee4b0] width 1280 pitch 5120 (/4 1280) >[574990.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5655a90] >[574990.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5655a90] width 1280 pitch 5120 (/4 1280) >[574991.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5607b40] >[574991.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5607b40] width 1280 pitch 5120 (/4 1280) >[574991.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5694e10] >[574991.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5694e10] width 1280 pitch 5120 (/4 1280) >[574991.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f34f0] >[574991.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f34f0] width 1280 pitch 5120 (/4 1280) >[574991.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5694e10] >[574991.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5694e10] width 1280 pitch 5120 (/4 1280) >[574992.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608eb0] >[574992.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608eb0] width 1280 pitch 5120 (/4 1280) >[574992.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5694e10] >[574992.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5694e10] width 1280 pitch 5120 (/4 1280) >[574992.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f23c0] >[574992.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f23c0] width 1280 pitch 5120 (/4 1280) >[574992.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[574992.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[574992.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f23c0] >[574992.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f23c0] width 1280 pitch 5120 (/4 1280) >[574993.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574993.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574993.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bfa40] >[574993.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bfa40] width 1280 pitch 5120 (/4 1280) >[574993.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f3ab0] >[574993.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f3ab0] width 1280 pitch 5120 (/4 1280) >[575001.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f23c0] >[575001.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f23c0] width 1280 pitch 5120 (/4 1280) >[575001.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5694e10] >[575001.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5694e10] width 1280 pitch 5120 (/4 1280) >[575001.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a6a0] >[575001.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a6a0] width 1280 pitch 5120 (/4 1280) >[575001.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5654c00] >[575001.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5654c00] width 1280 pitch 5120 (/4 1280) >[575002.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef500] >[575002.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef500] width 1280 pitch 5120 (/4 1280) >[575002.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56eeec0] >[575002.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56eeec0] width 1280 pitch 5120 (/4 1280) >[575002.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a23bb0] >[575002.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a23bb0] width 1280 pitch 5120 (/4 1280) >[575002.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56eed10] >[575002.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56eed10] width 1280 pitch 5120 (/4 1280) >[575022.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5694e10] >[575022.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5694e10] width 1280 pitch 5120 (/4 1280) >[575028.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5670950] >[575028.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5670950] width 1280 pitch 5120 (/4 1280) >[575028.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5670950] >[575028.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5670950] width 1280 pitch 5120 (/4 1280) >[575028.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef970] >[575028.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef970] width 1280 pitch 5120 (/4 1280) >[575029.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f1490] >[575029.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f1490] width 1280 pitch 5120 (/4 1280) >[575029.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef970] >[575029.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef970] width 1280 pitch 5120 (/4 1280) >[575029.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef970] >[575029.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef970] width 1280 pitch 5120 (/4 1280) >[575029.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56e1a60] >[575029.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56e1a60] width 1280 pitch 5120 (/4 1280) >[575123.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f3720] >[575123.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f3720] width 1280 pitch 5120 (/4 1280) >[575123.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f4d00] >[575123.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f4d00] width 1280 pitch 5120 (/4 1280) >[575352.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575352.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575352.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[575352.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[575352.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575352.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575352.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[575352.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[575352.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575352.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575352.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575352.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575352.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f1490] >[575352.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f1490] width 1280 pitch 5120 (/4 1280) >[575352.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575352.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575352.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55960f0] >[575352.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55960f0] width 1280 pitch 5120 (/4 1280) >[575352.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575352.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575352.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f1490] >[575352.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f1490] width 1280 pitch 5120 (/4 1280) >[575352.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575352.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575352.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f1490] >[575352.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f1490] width 1280 pitch 5120 (/4 1280) >[575353.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5522e80] >[575353.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5522e80] width 1280 pitch 5120 (/4 1280) >[575487.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575487.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575487.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[575487.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[575487.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575487.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575487.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[575487.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[575488.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56532d0] >[575488.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56532d0] width 1280 pitch 5120 (/4 1280) >[575488.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f4c80] >[575488.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f4c80] width 1280 pitch 5120 (/4 1280) >[575488.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56532d0] >[575488.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56532d0] width 1280 pitch 5120 (/4 1280) >[575488.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f4c80] >[575488.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f4c80] width 1280 pitch 5120 (/4 1280) >[575488.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56532d0] >[575488.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56532d0] width 1280 pitch 5120 (/4 1280) >[575489.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f4c80] >[575489.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f4c80] width 1280 pitch 5120 (/4 1280) >[575489.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56532d0] >[575489.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56532d0] width 1280 pitch 5120 (/4 1280) >[575490.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575490.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575490.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575490.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575490.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[575490.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[575490.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575490.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575490.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575490.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575499.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5640590] >[575499.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5640590] width 1280 pitch 5120 (/4 1280) >[575499.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eac2d0] >[575499.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eac2d0] width 1280 pitch 5120 (/4 1280) >[575516.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[575516.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[575656.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8ad0] >[575656.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8ad0] width 1280 pitch 5120 (/4 1280) >[575656.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575656.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575656.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56561c0] >[575656.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56561c0] width 1280 pitch 5120 (/4 1280) >[575656.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575656.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575656.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56561c0] >[575656.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56561c0] width 1280 pitch 5120 (/4 1280) >[575656.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575656.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575656.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56561c0] >[575656.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56561c0] width 1280 pitch 5120 (/4 1280) >[575656.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575656.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575656.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56561c0] >[575656.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56561c0] width 1280 pitch 5120 (/4 1280) >[575656.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575656.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575656.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56561c0] >[575656.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56561c0] width 1280 pitch 5120 (/4 1280) >[575657.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[575657.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[575657.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[575657.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[575657.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[575657.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[575657.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549b460] >[575657.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549b460] width 1280 pitch 5120 (/4 1280) >[575657.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f1490] >[575657.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f1490] width 1280 pitch 5120 (/4 1280) >[575657.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef310] >[575657.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef310] width 1280 pitch 5120 (/4 1280) >[575657.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621e70] >[575657.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621e70] width 1280 pitch 5120 (/4 1280) >[575657.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef050] >[575657.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef050] width 1280 pitch 5120 (/4 1280) >[575657.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b0a60] >[575657.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b0a60] width 1280 pitch 5120 (/4 1280) >[575657.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575657.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575657.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575657.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575657.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575657.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575657.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575657.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575657.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575658.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575658.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575658.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575658.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575658.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575658.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5603f80] >[575658.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5603f80] width 1280 pitch 5120 (/4 1280) >[575658.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575658.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575658.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575658.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575658.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575658.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[575658.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[575658.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[575659.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56ef050] >[575659.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56ef050] width 1280 pitch 5120 (/4 1280) >[575799.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621e70] >[575799.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621e70] width 1280 pitch 5120 (/4 1280) >[575799.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[575799.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576421.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[576421.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[576421.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576421.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576421.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576421.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576421.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576421.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576421.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576421.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576421.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576421.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576421.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576421.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576421.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576421.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576421.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576421.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576421.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576421.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576422.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576422.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576422.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[576422.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[576422.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576422.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576422.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[576422.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[576422.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576422.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576422.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[576422.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[576422.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576422.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576422.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[576422.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[576422.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576422.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576422.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[576422.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[576422.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576422.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576422.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576422.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576422.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576422.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576422.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576422.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576422.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576422.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576422.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576422.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576422.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576422.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576422.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576422.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576422.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576422.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576423.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576423.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576423.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576423.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576423.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78150] >[576423.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78150] width 1280 pitch 5120 (/4 1280) >[576424.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576424.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576424.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576424.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576424.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576424.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576425.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[576425.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[576425.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[576425.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[576425.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fbca0] >[576425.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fbca0] width 1280 pitch 5120 (/4 1280) >[576425.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f17c0] >[576425.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f17c0] width 1280 pitch 5120 (/4 1280) >[576426.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576426.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576426.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576426.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576426.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576426.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576426.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576426.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576426.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576426.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576426.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576426.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576426.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576426.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576426.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576426.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576426.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576426.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576426.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576426.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576427.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576427.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576427.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576427.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576427.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576427.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576427.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f6710] >[576427.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f6710] width 1280 pitch 5120 (/4 1280) >[576427.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576427.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576428.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576428.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576428.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576428.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576428.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576428.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576428.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576428.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576428.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576428.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576428.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576428.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576428.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576428.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576428.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55512b0] >[576428.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55512b0] width 1280 pitch 5120 (/4 1280) >[576428.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576428.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576431.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543dc40] >[576431.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543dc40] width 1280 pitch 5120 (/4 1280) >[576431.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576431.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576432.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576432.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576432.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576432.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576432.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576432.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576432.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536750] >[576432.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536750] width 1280 pitch 5120 (/4 1280) >[576432.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b73f0] >[576432.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b73f0] width 1280 pitch 5120 (/4 1280) >[576432.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536750] >[576432.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536750] width 1280 pitch 5120 (/4 1280) >[576432.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f280] >[576432.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f280] width 1280 pitch 5120 (/4 1280) >[576432.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f280] >[576432.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f280] width 1280 pitch 5120 (/4 1280) >[576432.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f280] >[576432.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f280] width 1280 pitch 5120 (/4 1280) >[576432.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576432.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576432.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f280] >[576432.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f280] width 1280 pitch 5120 (/4 1280) >[576433.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576433.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576434.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576434.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576434.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6850] >[576434.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6850] width 1280 pitch 5120 (/4 1280) >[576434.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[576434.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[576434.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6850] >[576434.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6850] width 1280 pitch 5120 (/4 1280) >[576434.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4054a20] >[576434.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4054a20] width 1280 pitch 5120 (/4 1280) >[576449.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576449.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576451.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576451.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576472.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576473.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576498.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2420] >[576498.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2420] width 1280 pitch 5120 (/4 1280) >[576498.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536710] >[576498.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536710] width 1280 pitch 5120 (/4 1280) >[576498.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576498.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576498.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576498.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576498.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576498.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576498.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576498.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576498.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576498.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576500.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576500.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576500.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576500.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576500.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576500.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576500.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5293ae0] >[576501.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5293ae0] width 1280 pitch 5120 (/4 1280) >[576501.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576501.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576502.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42fee80] >[576502.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42fee80] width 1280 pitch 5120 (/4 1280) >[576502.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ccf90] >[576502.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ccf90] width 1280 pitch 5120 (/4 1280) >[576502.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f3f90] >[576502.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f3f90] width 1280 pitch 5120 (/4 1280) >[576610.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576610.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576610.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576610.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576610.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576610.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576610.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576610.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576610.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576611.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700370] >[576611.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700370] width 1280 pitch 5120 (/4 1280) >[576611.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576611.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576611.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700370] >[576611.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700370] width 1280 pitch 5120 (/4 1280) >[576611.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576611.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576611.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700370] >[576611.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700370] width 1280 pitch 5120 (/4 1280) >[576611.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576611.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576611.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700370] >[576611.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700370] width 1280 pitch 5120 (/4 1280) >[576611.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576611.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576612.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576612.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576612.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576612.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576613.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5604550] >[576613.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5604550] width 1280 pitch 5120 (/4 1280) >[576613.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576613.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576613.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576613.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576613.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576613.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576613.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576613.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576613.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576613.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576613.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2420] >[576613.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2420] width 1280 pitch 5120 (/4 1280) >[576613.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2420] >[576613.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2420] width 1280 pitch 5120 (/4 1280) >[576613.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576613.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576613.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576613.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576613.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576613.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576613.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576613.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576613.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576702.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608410] >[576702.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608410] width 1280 pitch 5120 (/4 1280) >[576702.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576702.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576703.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576703.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576704.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576704.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576704.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576704.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576705.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576705.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576705.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576705.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576705.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576705.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576705.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576705.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576705.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[576705.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[576817.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576817.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576817.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576817.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576836.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576836.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576836.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576836.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576836.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576836.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576836.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576836.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576836.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576836.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576836.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576836.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576836.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576836.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576836.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576837.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576837.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576837.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576837.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576837.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576837.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576837.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576837.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576837.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576837.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576837.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576837.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576837.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576837.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576837.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576837.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576837.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576837.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576884.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576884.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576884.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576884.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576904.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576904.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576927.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576927.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576927.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576927.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576927.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576927.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576927.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576927.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576927.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576927.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576927.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576927.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576927.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576927.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576927.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576927.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576927.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576927.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576927.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576927.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576927.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576928.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576928.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576928.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576928.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576928.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576928.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576928.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576928.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576928.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576928.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576928.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576928.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576928.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576928.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576928.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576928.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576928.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576928.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576928.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576938.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576938.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576938.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576938.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576940.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576940.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576947.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576947.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576951.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576951.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576951.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[576951.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[576956.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576956.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576956.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576956.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576956.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576956.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576956.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576956.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576956.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576956.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576956.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576956.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576956.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576957.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[576957.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[576957.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576957.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576965.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f9cb0] >[576965.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f9cb0] width 1280 pitch 5120 (/4 1280) >[576965.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f9cb0] >[576965.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f9cb0] width 1280 pitch 5120 (/4 1280) >[576965.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f9cb0] >[576965.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f9cb0] width 1280 pitch 5120 (/4 1280) >[576966.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576966.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576966.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576966.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576967.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592a6c0] >[576967.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592a6c0] width 1280 pitch 5120 (/4 1280) >[576967.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f9cb0] >[576967.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f9cb0] width 1280 pitch 5120 (/4 1280) >[576967.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592a6c0] >[576967.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592a6c0] width 1280 pitch 5120 (/4 1280) >[576967.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f9cb0] >[576967.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f9cb0] width 1280 pitch 5120 (/4 1280) >[576967.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576967.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576967.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576967.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576967.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576967.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576967.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576967.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576967.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576967.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576968.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576968.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576968.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f53b0] >[576968.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f53b0] width 1280 pitch 5120 (/4 1280) >[576968.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576968.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545e590] >[576968.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545e590] width 1280 pitch 5120 (/4 1280) >[576968.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[576968.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[576974.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576974.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576974.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[576974.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[576976.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576976.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576982.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[576982.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[576982.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[576982.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[576982.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[576982.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[576982.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576982.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576982.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576982.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576982.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576982.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576982.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576982.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576982.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[576982.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[576982.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576982.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[576986.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576986.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576986.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576986.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576986.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[576986.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[576986.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576986.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576986.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576986.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576986.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576986.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576986.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576986.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576986.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576986.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[576986.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[576986.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[576986.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[576998.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[576998.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[576998.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[576998.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[577002.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5700430] >[577002.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5700430] width 1280 pitch 5120 (/4 1280) >[577011.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f37c0] >[577011.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f37c0] width 1280 pitch 5120 (/4 1280) >[577014.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dfe020] >[577014.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dfe020] width 1280 pitch 5120 (/4 1280) >[577014.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[577014.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[577014.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608880] >[577014.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608880] width 1280 pitch 5120 (/4 1280) >[577014.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f6c80] >[577014.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f6c80] width 1280 pitch 5120 (/4 1280) >[578675.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5941480] >[578675.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5941480] width 1280 pitch 5120 (/4 1280) >[578675.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44d4d60] >[578675.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44d4d60] width 1280 pitch 5120 (/4 1280) >[578681.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[578681.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[578681.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[578681.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[578681.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[578681.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[578681.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[578681.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[578682.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[578682.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[578682.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[578682.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[578682.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a65e0] >[578682.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a65e0] width 1280 pitch 5120 (/4 1280) >[578682.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[578682.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[578682.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0d720] >[578683.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0d720] width 1280 pitch 5120 (/4 1280) >[578683.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5249490] >[578683.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5249490] width 1280 pitch 5120 (/4 1280) >[578683.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59304f0] >[578683.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59304f0] width 1280 pitch 5120 (/4 1280) >[578683.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593f9d0] >[578683.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593f9d0] width 1280 pitch 5120 (/4 1280) >[578683.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59304f0] >[578683.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59304f0] width 1280 pitch 5120 (/4 1280) >[578692.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593f9d0] >[578692.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593f9d0] width 1280 pitch 5120 (/4 1280) >[578859.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578859.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578859.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578859.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578859.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578859.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578859.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578859.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578859.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578859.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578859.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578859.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578859.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578859.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578859.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578859.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578859.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578860.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578860.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578860.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578860.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578860.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578860.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578860.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578860.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578860.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578860.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578860.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578860.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578860.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578860.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578860.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578860.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578860.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578861.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578861.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578861.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578861.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578861.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578861.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578861.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578861.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ae00] >[578862.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ae00] width 1280 pitch 5120 (/4 1280) >[578862.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578862.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578862.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578862.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578862.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ccd0] >[578862.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ccd0] width 1280 pitch 5120 (/4 1280) >[578862.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578862.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578862.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578862.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578862.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578862.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578862.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578862.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578862.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578862.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a1a0] >[578862.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a1a0] width 1280 pitch 5120 (/4 1280) >[578862.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b320] >[578862.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b320] width 1280 pitch 5120 (/4 1280) >[578864.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672360] >[578864.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672360] width 1280 pitch 5120 (/4 1280) >[578882.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5646c30] >[578882.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5646c30] width 1280 pitch 5120 (/4 1280) >[578884.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f4c0] >[578884.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f4c0] width 1280 pitch 5120 (/4 1280) >[578998.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578998.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578998.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578998.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578998.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[578999.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f050] >[578999.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f050] width 1280 pitch 5120 (/4 1280) >[578999.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[578999.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581532.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581532.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581532.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581532.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581533.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581533.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581533.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581533.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581533.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581533.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581533.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581533.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581533.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581533.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581533.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581533.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581534.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581534.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581534.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581534.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581534.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581534.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581534.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581534.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581534.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581534.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581534.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581534.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581534.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581534.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581534.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581534.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581535.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581535.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581535.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581535.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581535.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dfa0] >[581535.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dfa0] width 1280 pitch 5120 (/4 1280) >[581535.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dfa0] >[581535.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dfa0] width 1280 pitch 5120 (/4 1280) >[581535.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dfa0] >[581535.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dfa0] width 1280 pitch 5120 (/4 1280) >[581535.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581535.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581535.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581535.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581535.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581535.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581535.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581535.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581535.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581535.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581535.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581535.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581535.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581535.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581535.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581535.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581535.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581535.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581535.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581536.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581536.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581536.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581536.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581536.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581536.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581536.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581536.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581536.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581536.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581536.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581536.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581536.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581536.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581536.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581536.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581536.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581536.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581536.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581536.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581536.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581536.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581536.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581536.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581536.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581537.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581537.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581537.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581537.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581537.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581537.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581537.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5444fc0] >[581537.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5444fc0] width 1280 pitch 5120 (/4 1280) >[581537.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581537.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581537.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581537.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581537.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581537.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581537.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581537.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581537.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581537.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432930] >[581537.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432930] width 1280 pitch 5120 (/4 1280) >[581537.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581537.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581538.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581538.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581538.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581538.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581538.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581538.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581538.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581538.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581538.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581538.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581538.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581538.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581538.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[581538.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[581538.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581538.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581539.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c4d0] >[581539.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c4d0] width 1280 pitch 5120 (/4 1280) >[581539.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53f1460] >[581539.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53f1460] width 1280 pitch 5120 (/4 1280) >[581540.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5562be0] >[581540.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5562be0] width 1280 pitch 5120 (/4 1280) >[581540.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581540.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581540.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581540.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581540.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5498280] >[581540.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5498280] width 1280 pitch 5120 (/4 1280) >[581541.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5673340] >[581541.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5673340] width 1280 pitch 5120 (/4 1280) >[581541.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5671480] >[581541.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5671480] width 1280 pitch 5120 (/4 1280) >[581541.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581541.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581541.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581541.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5673430] >[581541.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5673430] width 1280 pitch 5120 (/4 1280) >[581541.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438f10] >[581541.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438f10] width 1280 pitch 5120 (/4 1280) >[581544.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581544.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581548.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[581548.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[581548.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[581548.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[581548.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[581548.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[581549.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581549.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581549.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5497870] >[581549.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5497870] width 1280 pitch 5120 (/4 1280) >[581549.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581549.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581602.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581602.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581602.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dd20] >[581602.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dd20] width 1280 pitch 5120 (/4 1280) >[581603.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581603.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581603.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dd20] >[581603.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dd20] width 1280 pitch 5120 (/4 1280) >[581603.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dd20] >[581603.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dd20] width 1280 pitch 5120 (/4 1280) >[581603.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dd20] >[581603.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dd20] width 1280 pitch 5120 (/4 1280) >[581603.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590dd20] >[581603.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590dd20] width 1280 pitch 5120 (/4 1280) >[581603.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6d90] >[581603.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6d90] width 1280 pitch 5120 (/4 1280) >[581603.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581603.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581603.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6d90] >[581603.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6d90] width 1280 pitch 5120 (/4 1280) >[581603.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581603.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581603.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581603.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581603.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581603.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581603.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581604.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581604.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581604.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581604.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6d90] >[581604.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6d90] width 1280 pitch 5120 (/4 1280) >[581604.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581604.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581604.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6d90] >[581604.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6d90] width 1280 pitch 5120 (/4 1280) >[581604.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581604.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581604.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581604.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581604.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581604.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581604.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581604.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581604.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57051c0] >[581604.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57051c0] width 1280 pitch 5120 (/4 1280) >[581604.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581604.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581604.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581604.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581604.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581604.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581604.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581604.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581604.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581604.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581604.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581604.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581604.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250b2e0] >[581604.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250b2e0] width 1280 pitch 5120 (/4 1280) >[581604.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8eb0] >[581605.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8eb0] width 1280 pitch 5120 (/4 1280) >[581652.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b28f0] >[581652.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b28f0] width 1280 pitch 5120 (/4 1280) >[581652.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5915010] >[581652.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5915010] width 1280 pitch 5120 (/4 1280) >[581654.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581654.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581654.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581654.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581654.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581654.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581654.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581654.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581654.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581654.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581654.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581654.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581654.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581654.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581654.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581654.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581654.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581654.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581654.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581654.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581654.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581654.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581654.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949ec0] >[581654.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949ec0] width 1280 pitch 5120 (/4 1280) >[581655.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581655.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581655.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581655.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581655.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581655.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581655.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581655.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581655.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581655.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581655.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581655.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581655.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581655.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581655.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581655.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581655.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581655.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581655.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949ec0] >[581655.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949ec0] width 1280 pitch 5120 (/4 1280) >[581655.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949ec0] >[581655.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949ec0] width 1280 pitch 5120 (/4 1280) >[581655.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581656.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581656.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581656.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581656.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581656.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581656.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949ec0] >[581656.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949ec0] width 1280 pitch 5120 (/4 1280) >[581656.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581656.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581656.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590fdf0] >[581656.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590fdf0] width 1280 pitch 5120 (/4 1280) >[581656.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56745c0] >[581656.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56745c0] width 1280 pitch 5120 (/4 1280) >[581656.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bcd40] >[581656.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bcd40] width 1280 pitch 5120 (/4 1280) >[581656.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2056700] >[581656.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2056700] width 1280 pitch 5120 (/4 1280) >[581658.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581658.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581658.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581658.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581658.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581658.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581658.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581658.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581658.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581658.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581658.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581658.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581658.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581658.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581658.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581658.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581658.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581658.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581658.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581658.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581658.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581658.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581658.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581658.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581658.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581658.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581658.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581658.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581658.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581658.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581658.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581658.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581658.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581658.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581658.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581659.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581659.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581659.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581659.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581659.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581659.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581659.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581659.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581659.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581659.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581659.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581659.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581659.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581659.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581659.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581662.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581662.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581666.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[581666.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[581666.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[581666.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[581732.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581732.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581732.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581733.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581733.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581733.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581733.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7bb0] >[581733.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7bb0] width 1280 pitch 5120 (/4 1280) >[581733.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5905250] >[581734.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5905250] width 1280 pitch 5120 (/4 1280) >[581734.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528cfb0] >[581734.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528cfb0] width 1280 pitch 5120 (/4 1280) >[581734.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56828c0] >[581734.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56828c0] width 1280 pitch 5120 (/4 1280) >[581734.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ccf0] >[581734.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ccf0] width 1280 pitch 5120 (/4 1280) >[581734.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56828c0] >[581734.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56828c0] width 1280 pitch 5120 (/4 1280) >[581735.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56828c0] >[581735.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56828c0] width 1280 pitch 5120 (/4 1280) >[581735.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56828c0] >[581735.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56828c0] width 1280 pitch 5120 (/4 1280) >[581878.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c2290] >[581878.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c2290] width 1280 pitch 5120 (/4 1280) >[581878.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6d90] >[581878.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6d90] width 1280 pitch 5120 (/4 1280) >[582125.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582125.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582125.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582125.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582125.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582125.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582125.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ed10] >[582125.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ed10] width 1280 pitch 5120 (/4 1280) >[582125.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582125.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582125.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582125.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582125.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582125.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582125.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582125.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582125.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582125.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582125.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582125.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582125.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582125.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582126.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582126.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582126.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582126.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582126.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582126.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582126.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582126.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582126.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582126.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582126.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x440fb20] >[582126.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x440fb20] width 1280 pitch 5120 (/4 1280) >[582126.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582126.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582126.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c4dd0] >[582126.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c4dd0] width 1280 pitch 5120 (/4 1280) >[582126.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582127.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582127.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582127.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582127.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582127.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582127.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582127.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582127.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582127.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582127.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582127.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582127.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582127.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582127.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582127.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582128.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582128.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c4dd0] >[582129.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c4dd0] width 1280 pitch 5120 (/4 1280) >[582129.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c4dd0] >[582129.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c4dd0] width 1280 pitch 5120 (/4 1280) >[582129.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c4dd0] >[582129.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c4dd0] width 1280 pitch 5120 (/4 1280) >[582129.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d1960] >[582129.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d1960] width 1280 pitch 5120 (/4 1280) >[582129.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d1960] >[582129.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d1960] width 1280 pitch 5120 (/4 1280) >[582129.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2f20] >[582129.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2f20] width 1280 pitch 5120 (/4 1280) >[582129.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582129.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582129.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582129.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582129.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582130.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582130.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582130.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582130.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582130.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582130.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582130.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582133.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582133.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582133.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ed10] >[582133.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ed10] width 1280 pitch 5120 (/4 1280) >[582133.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582133.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582134.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ed10] >[582134.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ed10] width 1280 pitch 5120 (/4 1280) >[582134.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c4dd0] >[582134.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c4dd0] width 1280 pitch 5120 (/4 1280) >[582134.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ed10] >[582134.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ed10] width 1280 pitch 5120 (/4 1280) >[582134.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d1960] >[582134.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d1960] width 1280 pitch 5120 (/4 1280) >[582134.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582135.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582135.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d1960] >[582135.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d1960] width 1280 pitch 5120 (/4 1280) >[582135.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582135.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582136.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582136.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582136.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582136.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582136.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2090] >[582136.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2090] width 1280 pitch 5120 (/4 1280) >[582136.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c06d0] >[582136.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c06d0] width 1280 pitch 5120 (/4 1280) >[582798.683] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[582798.683] (II) RADEON(0): Printing DDC gathered Modelines: >[582798.683] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[603276.572] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[603276.572] (II) RADEON(0): Printing DDC gathered Modelines: >[603276.572] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[603282.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58fc160] >[603282.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58fc160] width 1280 pitch 5120 (/4 1280) >[603282.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f0c60] >[603282.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f0c60] width 1280 pitch 5120 (/4 1280) >[603377.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x589d0a0] >[603377.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x589d0a0] width 1280 pitch 5120 (/4 1280) >[603377.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5956270] >[603377.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5956270] width 1280 pitch 5120 (/4 1280) >[603378.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603378.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603378.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58f9c00] >[603378.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58f9c00] width 1280 pitch 5120 (/4 1280) >[603378.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603378.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603378.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949b60] >[603378.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949b60] width 1280 pitch 5120 (/4 1280) >[603378.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603378.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603379.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949b60] >[603379.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949b60] width 1280 pitch 5120 (/4 1280) >[603379.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603379.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603380.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603380.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603380.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603380.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603380.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603380.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603380.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603380.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603383.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603383.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603383.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603383.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592dc10] >[603383.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592dc10] width 1280 pitch 5120 (/4 1280) >[603390.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603390.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603390.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603390.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603390.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603391.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603392.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603392.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603392.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603392.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603392.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[603392.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[603392.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603392.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603392.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[603392.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[603409.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603409.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603409.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603409.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603409.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c25a0] >[603409.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c25a0] width 1280 pitch 5120 (/4 1280) >[603409.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603409.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603409.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949b60] >[603409.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949b60] width 1280 pitch 5120 (/4 1280) >[603409.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603409.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603409.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603409.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603409.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603410.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603410.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603410.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603410.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603410.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603410.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603410.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603410.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603410.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603410.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603410.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603410.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603410.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603410.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603410.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603410.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603410.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603410.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603410.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603410.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603410.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603410.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603410.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603410.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603410.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603410.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603410.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603410.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603410.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603410.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603410.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603410.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603410.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603410.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603410.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603410.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603410.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603410.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603410.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603411.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5427330] >[603411.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5427330] width 1280 pitch 5120 (/4 1280) >[603411.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a8190] >[603411.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a8190] width 1280 pitch 5120 (/4 1280) >[603411.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x589d0a0] >[603411.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x589d0a0] width 1280 pitch 5120 (/4 1280) >[603411.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbe10] >[603411.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbe10] width 1280 pitch 5120 (/4 1280) >[603412.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603412.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603412.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42ea810] >[603412.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42ea810] width 1280 pitch 5120 (/4 1280) >[603412.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603412.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603412.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603412.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603412.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603412.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603412.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603412.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603412.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635640] >[603412.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635640] width 1280 pitch 5120 (/4 1280) >[603412.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603412.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603412.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5432b20] >[603412.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5432b20] width 1280 pitch 5120 (/4 1280) >[603412.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ff2f0] >[603412.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ff2f0] width 1280 pitch 5120 (/4 1280) >[603413.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426de0] >[603413.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426de0] width 1280 pitch 5120 (/4 1280) >[603413.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ff2f0] >[603413.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ff2f0] width 1280 pitch 5120 (/4 1280) >[603413.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592f400] >[603413.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592f400] width 1280 pitch 5120 (/4 1280) >[603413.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ff2f0] >[603413.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ff2f0] width 1280 pitch 5120 (/4 1280) >[603413.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592f400] >[603413.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592f400] width 1280 pitch 5120 (/4 1280) >[603413.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ff2f0] >[603413.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ff2f0] width 1280 pitch 5120 (/4 1280) >[603413.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f2ac0] >[603413.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f2ac0] width 1280 pitch 5120 (/4 1280) >[603413.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603413.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603414.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603414.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603415.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603415.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a85d0] >[603415.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a85d0] width 1280 pitch 5120 (/4 1280) >[603415.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[603415.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[603415.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949b60] >[603415.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949b60] width 1280 pitch 5120 (/4 1280) >[603415.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808980] >[603415.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808980] width 1280 pitch 5120 (/4 1280) >[603416.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[603416.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[603416.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603416.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603416.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[603416.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[603417.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603417.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603418.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[603418.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[603418.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cefd0] >[603418.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cefd0] width 1280 pitch 5120 (/4 1280) >[603418.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[603418.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[603418.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b5b10] >[603418.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b5b10] width 1280 pitch 5120 (/4 1280) >[603418.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596f420] >[603418.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596f420] width 1280 pitch 5120 (/4 1280) >[603586.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eaf90] >[603586.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eaf90] width 1280 pitch 5120 (/4 1280) >[603586.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f0e80] >[603586.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f0e80] width 1280 pitch 5120 (/4 1280) >[603586.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eaf90] >[603586.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eaf90] width 1280 pitch 5120 (/4 1280) >[603586.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f0e80] >[603586.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f0e80] width 1280 pitch 5120 (/4 1280) >[603586.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eaf90] >[603586.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eaf90] width 1280 pitch 5120 (/4 1280) >[603586.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f0e80] >[603586.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f0e80] width 1280 pitch 5120 (/4 1280) >[603586.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eaf90] >[603586.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eaf90] width 1280 pitch 5120 (/4 1280) >[603586.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f0e80] >[603586.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f0e80] width 1280 pitch 5120 (/4 1280) >[603586.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42eaf90] >[603586.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42eaf90] width 1280 pitch 5120 (/4 1280) >[603586.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[603587.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[603587.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[603587.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[603587.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[603587.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[603587.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[603587.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[603587.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5577bc0] >[603587.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5577bc0] width 1280 pitch 5120 (/4 1280) >[603587.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[603587.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[603587.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426de0] >[603587.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426de0] width 1280 pitch 5120 (/4 1280) >[603587.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fa7c0] >[603587.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fa7c0] width 1280 pitch 5120 (/4 1280) >[603587.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426de0] >[603587.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426de0] width 1280 pitch 5120 (/4 1280) >[603587.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d4b50] >[603587.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d4b50] width 1280 pitch 5120 (/4 1280) >[603587.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426de0] >[603587.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426de0] width 1280 pitch 5120 (/4 1280) >[603587.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52d4b50] >[603587.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52d4b50] width 1280 pitch 5120 (/4 1280) >[603587.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426de0] >[603587.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426de0] width 1280 pitch 5120 (/4 1280) >[603587.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603587.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603587.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603587.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603587.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603587.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603587.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603587.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603587.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603587.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603587.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603587.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603587.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5910b50] >[603587.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5910b50] width 1280 pitch 5120 (/4 1280) >[603587.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603587.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603587.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603587.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603587.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603587.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603587.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603587.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603587.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be120] >[603587.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be120] width 1280 pitch 5120 (/4 1280) >[603587.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603587.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603587.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be120] >[603587.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be120] width 1280 pitch 5120 (/4 1280) >[603587.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58a7f70] >[603587.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58a7f70] width 1280 pitch 5120 (/4 1280) >[603657.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603657.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603696.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564a5a0] >[603696.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564a5a0] width 1280 pitch 5120 (/4 1280) >[603696.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dda80] >[603696.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dda80] width 1280 pitch 5120 (/4 1280) >[603696.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5704d00] >[603696.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5704d00] width 1280 pitch 5120 (/4 1280) >[603696.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597af70] >[603696.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597af70] width 1280 pitch 5120 (/4 1280) >[603707.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553af60] >[603707.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553af60] width 1280 pitch 5120 (/4 1280) >[603707.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c7d70] >[603707.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c7d70] width 1280 pitch 5120 (/4 1280) >[603823.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567d7d0] >[603823.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567d7d0] width 1280 pitch 5120 (/4 1280) >[603823.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5888c00] >[603823.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5888c00] width 1280 pitch 5120 (/4 1280) >[603910.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5901a60] >[603910.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5901a60] width 1280 pitch 5120 (/4 1280) >[603910.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5674000] >[603910.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5674000] width 1280 pitch 5120 (/4 1280) >[603922.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45af730] >[603922.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45af730] width 1280 pitch 5120 (/4 1280) >[603923.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e1ce0] >[603923.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e1ce0] width 1280 pitch 5120 (/4 1280) >[604370.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c1c50] >[604370.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c1c50] width 1280 pitch 5120 (/4 1280) >[604370.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c1a50] >[604370.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c1a50] width 1280 pitch 5120 (/4 1280) >[604520.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604520.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604520.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604520.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604520.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604520.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7120] >[604520.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7120] width 1280 pitch 5120 (/4 1280) >[604520.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604520.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59aa6e0] >[604521.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59aa6e0] width 1280 pitch 5120 (/4 1280) >[604521.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59aa500] >[604521.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59aa500] width 1280 pitch 5120 (/4 1280) >[604521.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604521.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604521.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604521.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7fb0] >[604521.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7fb0] width 1280 pitch 5120 (/4 1280) >[604522.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7ed0] >[604522.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7ed0] width 1280 pitch 5120 (/4 1280) >[604523.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cae0] >[604523.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cae0] width 1280 pitch 5120 (/4 1280) >[604523.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604523.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604523.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604523.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604523.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604523.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604523.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604523.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604523.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604523.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604523.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604523.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604523.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604523.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604523.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604523.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604523.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604523.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604523.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604523.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604523.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604524.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604524.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604524.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e84d0] >[604524.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e84d0] width 1280 pitch 5120 (/4 1280) >[604567.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461be60] >[604567.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461be60] width 1280 pitch 5120 (/4 1280) >[604568.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cae0] >[604568.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cae0] width 1280 pitch 5120 (/4 1280) >[604568.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461be60] >[604568.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461be60] width 1280 pitch 5120 (/4 1280) >[604568.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cae0] >[604568.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cae0] width 1280 pitch 5120 (/4 1280) >[604569.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461be60] >[604569.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461be60] width 1280 pitch 5120 (/4 1280) >[604570.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cae0] >[604570.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cae0] width 1280 pitch 5120 (/4 1280) >[604570.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563c510] >[604570.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563c510] width 1280 pitch 5120 (/4 1280) >[604570.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c37c0] >[604570.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c37c0] width 1280 pitch 5120 (/4 1280) >[604570.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563c510] >[604570.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563c510] width 1280 pitch 5120 (/4 1280) >[604716.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a78a0] >[604716.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a78a0] width 1280 pitch 5120 (/4 1280) >[604716.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a8250] >[604716.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a8250] width 1280 pitch 5120 (/4 1280) >[604742.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988cb0] >[604742.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988cb0] width 1280 pitch 5120 (/4 1280) >[604742.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988060] >[604742.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988060] width 1280 pitch 5120 (/4 1280) >[604884.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604884.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604884.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604884.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604884.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604884.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604884.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604884.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604884.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604884.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604884.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604884.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604884.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604884.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604884.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604884.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604884.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604884.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604884.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604884.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604884.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604884.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604884.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604884.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604884.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604884.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604884.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604884.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604885.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604885.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604885.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604885.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604885.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604885.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604885.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604885.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604886.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604886.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604886.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604886.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604886.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604886.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7d40] >[604886.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7d40] width 1280 pitch 5120 (/4 1280) >[604886.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604886.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604887.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[604887.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604887.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604887.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604887.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604887.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604888.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604888.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52ced10] >[604888.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52ced10] width 1280 pitch 5120 (/4 1280) >[604943.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604943.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604943.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604943.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604943.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604943.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604943.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604943.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604943.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604944.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604944.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604944.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604945.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604945.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604945.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604945.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604945.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604945.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604946.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604946.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604947.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604947.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604948.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7690] >[604948.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7690] width 1280 pitch 5120 (/4 1280) >[604948.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604948.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604948.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594c110] >[604948.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594c110] width 1280 pitch 5120 (/4 1280) >[604948.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9bf0] >[604948.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9bf0] width 1280 pitch 5120 (/4 1280) >[604948.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5295c50] >[604948.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5295c50] width 1280 pitch 5120 (/4 1280) >[605088.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x568e970] >[605088.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x568e970] width 1280 pitch 5120 (/4 1280) >[605088.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cf6f0] >[605088.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cf6f0] width 1280 pitch 5120 (/4 1280) >[605099.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605099.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x540c860] >[605099.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x540c860] width 1280 pitch 5120 (/4 1280) >[605099.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[605099.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[605100.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605100.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605100.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605100.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605100.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605100.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605100.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605100.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605100.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605100.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605100.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605100.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605100.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605100.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605100.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605100.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605100.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605100.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605101.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605101.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605101.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605101.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605101.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605101.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605101.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605101.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605101.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605101.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605101.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605101.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605101.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605101.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605101.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605101.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605101.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605101.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605101.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605101.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605102.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605102.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605102.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605102.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605102.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605102.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605102.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605102.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605102.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605102.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605102.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605102.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605104.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605104.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605105.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605105.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605105.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605105.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605129.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605129.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605129.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605129.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605129.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eb2e0] >[605129.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eb2e0] width 1280 pitch 5120 (/4 1280) >[605129.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605129.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605129.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eb2e0] >[605130.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eb2e0] width 1280 pitch 5120 (/4 1280) >[605132.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605132.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605132.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55eb2e0] >[605132.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55eb2e0] width 1280 pitch 5120 (/4 1280) >[605132.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605132.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605132.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605132.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605132.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605133.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605133.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605133.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605134.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605134.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605135.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605135.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605135.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605135.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605135.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605135.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605137.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x599a090] >[605137.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x599a090] width 1280 pitch 5120 (/4 1280) >[605137.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605137.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605137.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605137.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605137.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x599a090] >[605137.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x599a090] width 1280 pitch 5120 (/4 1280) >[605137.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605137.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605139.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605139.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605139.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605139.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605139.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605139.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605139.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605139.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605139.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605139.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605139.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x599a090] >[605139.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x599a090] width 1280 pitch 5120 (/4 1280) >[605139.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56f52a0] >[605139.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56f52a0] width 1280 pitch 5120 (/4 1280) >[605141.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605141.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605141.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605141.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605142.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55302a0] >[605142.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55302a0] width 1280 pitch 5120 (/4 1280) >[605142.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605142.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605142.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605142.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605142.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605142.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605142.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605142.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605142.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605142.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605144.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605144.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605144.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc280] >[605144.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc280] width 1280 pitch 5120 (/4 1280) >[605144.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605144.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605144.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc280] >[605144.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc280] width 1280 pitch 5120 (/4 1280) >[605144.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605144.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605144.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53dc280] >[605145.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53dc280] width 1280 pitch 5120 (/4 1280) >[605156.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605156.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605157.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605157.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605157.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605157.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605157.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605157.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605158.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605158.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605162.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605162.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605169.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7db0] >[605169.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7db0] width 1280 pitch 5120 (/4 1280) >[605169.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605170.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605170.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605170.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605170.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605170.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605170.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605170.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605170.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605170.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605171.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605171.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605171.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605171.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605171.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605171.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605172.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605172.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605172.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605172.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605172.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605172.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605172.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605172.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605172.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605172.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605172.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605172.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605173.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605173.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605173.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605173.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605173.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605173.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605173.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605173.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605173.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605173.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605173.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605173.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605173.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605173.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605173.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605173.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605173.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605173.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605174.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605174.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605174.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605174.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605174.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605174.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605174.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605174.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605174.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605174.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605174.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605174.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605174.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605174.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605174.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605174.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605174.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605174.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605175.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605175.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605175.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605175.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605175.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605175.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605175.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605175.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605175.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605175.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605175.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605175.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605175.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605175.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605175.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605175.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605176.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605176.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605177.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605177.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605178.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605178.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605178.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605178.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605178.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605178.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605178.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605178.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605178.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605178.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605178.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605178.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605178.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605178.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605178.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605178.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605178.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605178.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605178.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605178.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605178.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605179.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605179.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605179.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605179.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605179.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605179.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605179.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605179.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605179.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605179.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605179.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605180.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605180.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605180.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5425fa0] >[605180.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5425fa0] width 1280 pitch 5120 (/4 1280) >[605180.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605180.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605180.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605180.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605180.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605180.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605181.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605181.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605181.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605181.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605181.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605181.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605181.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605181.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605181.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605181.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605182.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605182.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605182.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605182.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ba7f0] >[605182.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ba7f0] width 1280 pitch 5120 (/4 1280) >[605182.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605182.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605182.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605182.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605182.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605182.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605182.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ceff0] >[605182.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ceff0] width 1280 pitch 5120 (/4 1280) >[605182.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605182.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605184.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539b000] >[605184.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539b000] width 1280 pitch 5120 (/4 1280) >[605185.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605185.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605185.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605185.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605185.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605185.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605185.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605185.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925ee0] >[605185.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925ee0] width 1280 pitch 5120 (/4 1280) >[605185.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be510] >[605185.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be510] width 1280 pitch 5120 (/4 1280) >[605186.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605186.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4980] >[605186.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4980] width 1280 pitch 5120 (/4 1280) >[605186.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605186.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605195.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605195.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605301.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605301.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605301.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605301.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605301.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605301.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605302.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605302.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605302.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605302.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605302.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605302.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605302.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605302.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605304.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605304.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605304.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605304.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605304.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x449aff0] >[605304.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x449aff0] width 1280 pitch 5120 (/4 1280) >[605304.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b8fd0] >[605304.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b8fd0] width 1280 pitch 5120 (/4 1280) >[605304.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605304.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605447.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605447.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605447.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605447.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605447.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605447.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605447.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605447.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605447.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605447.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605447.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605447.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605447.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605447.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605447.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605447.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605447.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605447.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605447.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605447.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5953e80] >[605448.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5953e80] width 1280 pitch 5120 (/4 1280) >[605448.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482460] >[605448.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482460] width 1280 pitch 5120 (/4 1280) >[605448.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5953e80] >[605448.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5953e80] width 1280 pitch 5120 (/4 1280) >[605448.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482460] >[605448.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482460] width 1280 pitch 5120 (/4 1280) >[605448.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5953e80] >[605448.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5953e80] width 1280 pitch 5120 (/4 1280) >[605448.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605448.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605448.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605448.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605448.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605448.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605448.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605448.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605448.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605448.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605448.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605449.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605449.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605449.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605449.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605449.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605449.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605449.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605449.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605449.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605449.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605449.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605449.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605449.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605449.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605449.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605449.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53527e0] >[605449.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53527e0] width 1280 pitch 5120 (/4 1280) >[605449.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb6c0] >[605449.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb6c0] width 1280 pitch 5120 (/4 1280) >[605449.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605449.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605449.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[605449.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[605450.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979020] >[605450.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979020] width 1280 pitch 5120 (/4 1280) >[605450.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be7b0] >[605450.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be7b0] width 1280 pitch 5120 (/4 1280) >[605450.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482460] >[605450.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482460] width 1280 pitch 5120 (/4 1280) >[605450.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be7b0] >[605450.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be7b0] width 1280 pitch 5120 (/4 1280) >[605450.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[605450.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[605450.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605450.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925530] >[605450.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925530] width 1280 pitch 5120 (/4 1280) >[605450.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360c130] >[605450.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360c130] width 1280 pitch 5120 (/4 1280) >[605796.037] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[605796.037] (II) RADEON(0): Printing DDC gathered Modelines: >[605796.037] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[606395.810] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[606395.810] (II) RADEON(0): Printing DDC gathered Modelines: >[606395.810] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[606485.931] (II) RADEON(0): RADEONSaveScreen(2) >[606485.936] (II) RADEON(0): RADEONSaveScreen(0) >[614692.543] (II) RADEON(0): RADEONSaveScreen(1) >[614709.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597ce40] >[614709.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597ce40] width 1280 pitch 5120 (/4 1280) >[614711.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53be7b0] >[614711.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53be7b0] width 1280 pitch 5120 (/4 1280) >[614711.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e54ca0] >[614711.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e54ca0] width 1280 pitch 5120 (/4 1280) >[614711.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591ae10] >[614711.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591ae10] width 1280 pitch 5120 (/4 1280) >[614712.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537a830] >[614712.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537a830] width 1280 pitch 5120 (/4 1280) >[614712.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53beb40] >[614712.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53beb40] width 1280 pitch 5120 (/4 1280) >[614712.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53bba00] >[614712.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53bba00] width 1280 pitch 5120 (/4 1280) >[614716.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4082ac0] >[614716.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4082ac0] width 1280 pitch 5120 (/4 1280) >[614725.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e74c0] >[614725.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e74c0] width 1280 pitch 5120 (/4 1280) >[614725.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979020] >[614725.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979020] width 1280 pitch 5120 (/4 1280) >[614728.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c15ec0] >[614728.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c15ec0] width 1280 pitch 5120 (/4 1280) >[614728.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5941a40] >[614728.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5941a40] width 1280 pitch 5120 (/4 1280) >[614810.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e74c0] >[614810.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e74c0] width 1280 pitch 5120 (/4 1280) >[614810.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925150] >[614810.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925150] width 1280 pitch 5120 (/4 1280) >[614852.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x539d900] >[614852.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x539d900] width 1280 pitch 5120 (/4 1280) >[614872.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b03d0] >[614872.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b03d0] width 1280 pitch 5120 (/4 1280) >[615140.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b03d0] >[615140.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b03d0] width 1280 pitch 5120 (/4 1280) >[615142.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925150] >[615142.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925150] width 1280 pitch 5120 (/4 1280) >[615144.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53346f0] >[615144.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53346f0] width 1280 pitch 5120 (/4 1280) >[615144.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5394a90] >[615144.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5394a90] width 1280 pitch 5120 (/4 1280) >[615250.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53346f0] >[615250.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53346f0] width 1280 pitch 5120 (/4 1280) >[615250.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53346f0] >[615250.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53346f0] width 1280 pitch 5120 (/4 1280) >[615253.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5369f70] >[615253.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5369f70] width 1280 pitch 5120 (/4 1280) >[615308.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x535b260] >[615308.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x535b260] width 1280 pitch 5120 (/4 1280) >[615308.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x535b260] >[615308.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x535b260] width 1280 pitch 5120 (/4 1280) >[615308.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x535b260] >[615308.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x535b260] width 1280 pitch 5120 (/4 1280) >[615308.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x535b260] >[615309.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x535b260] width 1280 pitch 5120 (/4 1280) >[615517.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9270] >[615517.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9270] width 1280 pitch 5120 (/4 1280) >[615517.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b9270] >[615517.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b9270] width 1280 pitch 5120 (/4 1280) >[615748.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ecb30] >[615748.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ecb30] width 1280 pitch 5120 (/4 1280) >[615748.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53587b0] >[615748.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53587b0] width 1280 pitch 5120 (/4 1280) >[615809.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cd3c0] >[615809.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cd3c0] width 1280 pitch 5120 (/4 1280) >[615809.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5325660] >[615809.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5325660] width 1280 pitch 5120 (/4 1280) >[615812.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584f420] >[615812.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584f420] width 1280 pitch 5120 (/4 1280) >[615835.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ee290] >[615835.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ee290] width 1280 pitch 5120 (/4 1280) >[615836.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ee290] >[615836.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ee290] width 1280 pitch 5120 (/4 1280) >[615890.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58522d0] >[615890.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58522d0] width 1280 pitch 5120 (/4 1280) >[615890.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58522d0] >[615891.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58522d0] width 1280 pitch 5120 (/4 1280) >[616587.133] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[616587.156] (II) RADEON(0): Printing DDC gathered Modelines: >[616587.157] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[616676.917] (II) RADEON(0): RADEONSaveScreen(2) >[616676.922] (II) RADEON(0): RADEONSaveScreen(0) >[650259.977] (II) RADEON(0): RADEONSaveScreen(1) >[650949.887] (II) RADEON(0): RADEONSaveScreen(2) >[650949.887] (II) RADEON(0): RADEONSaveScreen(0) >[651389.436] (II) RADEON(0): RADEONSaveScreen(1) >[651408.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886220] >[651408.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886220] width 1280 pitch 5120 (/4 1280) >[651411.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2080] >[651411.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2080] width 1280 pitch 5120 (/4 1280) >[651411.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58884c0] >[651411.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58884c0] width 1280 pitch 5120 (/4 1280) >[651471.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58eb240] >[651471.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58eb240] width 1280 pitch 5120 (/4 1280) >[651471.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bc350] >[651471.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bc350] width 1280 pitch 5120 (/4 1280) >[652071.831] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[652071.831] (II) RADEON(0): Printing DDC gathered Modelines: >[652071.831] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[652161.903] (II) RADEON(0): RADEONSaveScreen(2) >[652161.903] (II) RADEON(0): RADEONSaveScreen(0) >[653868.978] (II) RADEON(0): RADEONSaveScreen(1) >[653889.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653889.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653889.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58173c0] >[653889.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58173c0] width 1280 pitch 5120 (/4 1280) >[653889.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653889.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653889.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58173c0] >[653889.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58173c0] width 1280 pitch 5120 (/4 1280) >[653889.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653889.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653889.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58173c0] >[653889.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58173c0] width 1280 pitch 5120 (/4 1280) >[653889.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653890.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653890.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58173c0] >[653890.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58173c0] width 1280 pitch 5120 (/4 1280) >[653890.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653890.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653890.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58173c0] >[653890.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58173c0] width 1280 pitch 5120 (/4 1280) >[653890.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2540] >[653890.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2540] width 1280 pitch 5120 (/4 1280) >[653890.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653890.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653890.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653890.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653890.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653890.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653890.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653890.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653890.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653890.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653890.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653890.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653890.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653890.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653890.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653890.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653890.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653890.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653890.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58170e0] >[653890.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58170e0] width 1280 pitch 5120 (/4 1280) >[653890.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653890.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653890.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581ff60] >[653890.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581ff60] width 1280 pitch 5120 (/4 1280) >[653890.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653890.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653890.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581ff60] >[653890.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581ff60] width 1280 pitch 5120 (/4 1280) >[653890.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653890.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653891.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581ff60] >[653891.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581ff60] width 1280 pitch 5120 (/4 1280) >[653891.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58548e0] >[653891.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58548e0] width 1280 pitch 5120 (/4 1280) >[653891.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58170e0] >[653891.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58170e0] width 1280 pitch 5120 (/4 1280) >[653891.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653891.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653891.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d2540] >[653891.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d2540] width 1280 pitch 5120 (/4 1280) >[653892.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56533a0] >[653892.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56533a0] width 1280 pitch 5120 (/4 1280) >[653892.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56533a0] >[653892.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56533a0] width 1280 pitch 5120 (/4 1280) >[653892.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56533a0] >[653892.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56533a0] width 1280 pitch 5120 (/4 1280) >[653892.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56533a0] >[653892.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56533a0] width 1280 pitch 5120 (/4 1280) >[653892.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56533a0] >[653892.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56533a0] width 1280 pitch 5120 (/4 1280) >[653892.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd490] >[653892.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd490] width 1280 pitch 5120 (/4 1280) >[653892.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582a8b0] >[653892.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582a8b0] width 1280 pitch 5120 (/4 1280) >[653892.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8cf0] >[653892.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8cf0] width 1280 pitch 5120 (/4 1280) >[653892.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582a8b0] >[653892.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582a8b0] width 1280 pitch 5120 (/4 1280) >[653892.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8cf0] >[653892.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8cf0] width 1280 pitch 5120 (/4 1280) >[653892.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582a8b0] >[653892.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582a8b0] width 1280 pitch 5120 (/4 1280) >[653892.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8cf0] >[653892.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8cf0] width 1280 pitch 5120 (/4 1280) >[653892.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582a8b0] >[653892.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582a8b0] width 1280 pitch 5120 (/4 1280) >[653892.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8cf0] >[653892.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8cf0] width 1280 pitch 5120 (/4 1280) >[653892.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582a8b0] >[653892.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582a8b0] width 1280 pitch 5120 (/4 1280) >[653892.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821400] >[653892.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821400] width 1280 pitch 5120 (/4 1280) >[653892.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653892.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653892.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821400] >[653892.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821400] width 1280 pitch 5120 (/4 1280) >[653892.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653892.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653892.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821400] >[653892.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821400] width 1280 pitch 5120 (/4 1280) >[653892.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5820fd0] >[653892.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5820fd0] width 1280 pitch 5120 (/4 1280) >[653905.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821400] >[653905.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821400] width 1280 pitch 5120 (/4 1280) >[653915.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5814d10] >[653915.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5814d10] width 1280 pitch 5120 (/4 1280) >[653951.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d260] >[653951.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d260] width 1280 pitch 5120 (/4 1280) >[654259.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b73500] >[654259.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b73500] width 1280 pitch 5120 (/4 1280) >[654259.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654259.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654279.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ead0] >[654279.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ead0] width 1280 pitch 5120 (/4 1280) >[654279.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654279.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654279.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ead0] >[654279.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ead0] width 1280 pitch 5120 (/4 1280) >[654279.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654279.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654279.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ead0] >[654279.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ead0] width 1280 pitch 5120 (/4 1280) >[654279.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654279.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654279.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ead0] >[654279.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ead0] width 1280 pitch 5120 (/4 1280) >[654279.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654279.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654283.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654283.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654283.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654283.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654283.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654283.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654283.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654283.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654283.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654283.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654284.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654284.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654284.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654284.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654284.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654284.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654284.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654284.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654284.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654284.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654284.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654284.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654284.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654284.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654284.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654284.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654284.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654284.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654285.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654285.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654285.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654285.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654289.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654289.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654289.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654289.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654289.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654289.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654289.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654289.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654289.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654289.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654289.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654289.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654290.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573cb90] >[654290.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573cb90] width 1280 pitch 5120 (/4 1280) >[654290.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654290.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654290.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654290.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654290.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573c820] >[654291.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573c820] width 1280 pitch 5120 (/4 1280) >[654291.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573a7e0] >[654291.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573a7e0] width 1280 pitch 5120 (/4 1280) >[654291.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573ad00] >[654291.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573ad00] width 1280 pitch 5120 (/4 1280) >[654291.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573fc50] >[654291.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573fc50] width 1280 pitch 5120 (/4 1280) >[654305.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5740310] >[654305.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5740310] width 1280 pitch 5120 (/4 1280) >[654479.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654479.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654479.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654479.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654479.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654479.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654479.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654479.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654479.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654480.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654480.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654480.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654480.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654480.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654480.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5743090] >[654480.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5743090] width 1280 pitch 5120 (/4 1280) >[654480.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5742ca0] >[654480.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5742ca0] width 1280 pitch 5120 (/4 1280) >[654480.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57421c0] >[654480.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57421c0] width 1280 pitch 5120 (/4 1280) >[654480.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57421c0] >[654480.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57421c0] width 1280 pitch 5120 (/4 1280) >[654480.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57421c0] >[654480.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57421c0] width 1280 pitch 5120 (/4 1280) >[654480.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654480.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57421c0] >[654480.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57421c0] width 1280 pitch 5120 (/4 1280) >[654480.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654480.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654481.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654481.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654482.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654482.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654483.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654483.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654483.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654483.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654483.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654483.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654483.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654483.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654483.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654483.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654483.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654483.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654483.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654483.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654483.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654483.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654483.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654483.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654484.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654484.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654484.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654484.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654484.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654484.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654484.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x568aac0] >[654485.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x568aac0] width 1280 pitch 5120 (/4 1280) >[654485.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654485.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654485.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654485.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654485.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654485.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654485.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654485.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654485.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654485.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654485.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654485.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654485.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654485.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954220] >[654485.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954220] width 1280 pitch 5120 (/4 1280) >[654486.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba550] >[654486.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba550] width 1280 pitch 5120 (/4 1280) >[654486.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654486.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654486.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654486.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654486.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654486.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654486.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654486.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654486.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a3250] >[654486.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a3250] width 1280 pitch 5120 (/4 1280) >[654486.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x568aac0] >[654486.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x568aac0] width 1280 pitch 5120 (/4 1280) >[654489.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27b2770] >[654489.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27b2770] width 1280 pitch 5120 (/4 1280) >[654501.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591e8a0] >[654501.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591e8a0] width 1280 pitch 5120 (/4 1280) >[654506.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654506.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654506.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654506.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654506.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654506.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654506.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654506.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654506.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654506.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654506.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654506.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654506.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654506.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654506.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654506.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654506.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654507.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654507.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654507.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be4c0] >[654507.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be4c0] width 1280 pitch 5120 (/4 1280) >[654507.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654507.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654507.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654507.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654507.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654507.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[654507.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[654507.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572a320] >[654507.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572a320] width 1280 pitch 5120 (/4 1280) >[654508.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57472b0] >[654508.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57472b0] width 1280 pitch 5120 (/4 1280) >[654508.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654508.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654508.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654508.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654508.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654508.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654508.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654508.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654508.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654508.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654508.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654508.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654508.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654508.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654508.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654508.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654508.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654508.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654508.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654509.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654509.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654509.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654509.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654509.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654509.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654509.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654509.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654509.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654509.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654509.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654509.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654509.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654509.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654509.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654509.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654509.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654509.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654509.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654509.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654509.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654510.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724bc0] >[654510.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724bc0] width 1280 pitch 5120 (/4 1280) >[654510.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582aab0] >[654510.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582aab0] width 1280 pitch 5120 (/4 1280) >[654510.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00e30] >[654510.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00e30] width 1280 pitch 5120 (/4 1280) >[654510.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654510.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654510.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654510.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654510.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654510.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654510.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654510.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654510.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654510.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654510.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654510.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654510.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654510.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654510.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654510.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654510.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b6d50] >[654510.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b6d50] width 1280 pitch 5120 (/4 1280) >[654510.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654510.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654511.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654511.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654511.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654511.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654516.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654516.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654517.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654517.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654517.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5924800] >[654517.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5924800] width 1280 pitch 5120 (/4 1280) >[654517.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654517.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654517.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654517.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654517.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654517.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654518.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58837d0] >[654518.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58837d0] width 1280 pitch 5120 (/4 1280) >[654519.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ae170] >[654519.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ae170] width 1280 pitch 5120 (/4 1280) >[654519.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5934df0] >[654519.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5934df0] width 1280 pitch 5120 (/4 1280) >[654519.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597cba0] >[654519.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597cba0] width 1280 pitch 5120 (/4 1280) >[654524.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573f760] >[654524.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573f760] width 1280 pitch 5120 (/4 1280) >[654527.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58dfea0] >[654527.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58dfea0] width 1280 pitch 5120 (/4 1280) >[654527.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654527.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654536.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654536.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654576.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654576.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654576.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654576.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654576.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654576.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654576.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654577.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654577.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654577.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654577.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654577.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654577.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654577.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654577.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654577.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654577.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654577.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654577.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654577.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654577.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654577.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654577.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59518f0] >[654577.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59518f0] width 1280 pitch 5120 (/4 1280) >[654578.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5900920] >[654578.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5900920] width 1280 pitch 5120 (/4 1280) >[654578.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58488a0] >[654578.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58488a0] width 1280 pitch 5120 (/4 1280) >[654578.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52cf6f0] >[654578.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52cf6f0] width 1280 pitch 5120 (/4 1280) >[654580.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654580.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59520e0] >[654580.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59520e0] width 1280 pitch 5120 (/4 1280) >[654580.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50203f0] >[654580.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50203f0] width 1280 pitch 5120 (/4 1280) >[654581.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5928760] >[654581.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5928760] width 1280 pitch 5120 (/4 1280) >[654588.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ca80] >[654588.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ca80] width 1280 pitch 5120 (/4 1280) >[654589.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573bf00] >[654589.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573bf00] width 1280 pitch 5120 (/4 1280) >[654595.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcea40] >[654595.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcea40] width 1280 pitch 5120 (/4 1280) >[654595.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcea40] >[654595.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcea40] width 1280 pitch 5120 (/4 1280) >[654596.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e78a0] >[654596.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e78a0] width 1280 pitch 5120 (/4 1280) >[654596.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e5e20] >[654596.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e5e20] width 1280 pitch 5120 (/4 1280) >[654598.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59447d0] >[654598.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59447d0] width 1280 pitch 5120 (/4 1280) >[654599.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59912d0] >[654599.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59912d0] width 1280 pitch 5120 (/4 1280) >[654600.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc84f0] >[654600.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc84f0] width 1280 pitch 5120 (/4 1280) >[654600.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59912d0] >[654600.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59912d0] width 1280 pitch 5120 (/4 1280) >[654601.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59447d0] >[654601.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59447d0] width 1280 pitch 5120 (/4 1280) >[654601.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5619ef0] >[654601.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5619ef0] width 1280 pitch 5120 (/4 1280) >[654902.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x599e440] >[654902.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x599e440] width 1280 pitch 5120 (/4 1280) >[654902.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1decfb0] >[654902.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1decfb0] width 1280 pitch 5120 (/4 1280) >[655052.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcdae0] >[655052.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcdae0] width 1280 pitch 5120 (/4 1280) >[655052.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40efea0] >[655052.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40efea0] width 1280 pitch 5120 (/4 1280) >[655163.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b26290] >[655163.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b26290] width 1280 pitch 5120 (/4 1280) >[655169.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5746720] >[655169.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5746720] width 1280 pitch 5120 (/4 1280) >[655169.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580adb0] >[655169.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580adb0] width 1280 pitch 5120 (/4 1280) >[655196.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a94d20] >[655196.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a94d20] width 1280 pitch 5120 (/4 1280) >[655289.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56832c0] >[655289.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56832c0] width 1280 pitch 5120 (/4 1280) >[655311.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56832c0] >[655312.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56832c0] width 1280 pitch 5120 (/4 1280) >[655944.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655944.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655944.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56832c0] >[655944.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56832c0] width 1280 pitch 5120 (/4 1280) >[655945.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5920980] >[655945.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5920980] width 1280 pitch 5120 (/4 1280) >[655945.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56832c0] >[655945.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56832c0] width 1280 pitch 5120 (/4 1280) >[655946.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655946.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655946.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909ec0] >[655946.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909ec0] width 1280 pitch 5120 (/4 1280) >[655946.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655946.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655946.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909ec0] >[655946.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909ec0] width 1280 pitch 5120 (/4 1280) >[655946.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655946.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655946.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909ec0] >[655946.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909ec0] width 1280 pitch 5120 (/4 1280) >[655947.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655947.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655947.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590d320] >[655947.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590d320] width 1280 pitch 5120 (/4 1280) >[655947.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909ec0] >[655947.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909ec0] width 1280 pitch 5120 (/4 1280) >[655947.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590d320] >[655947.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590d320] width 1280 pitch 5120 (/4 1280) >[655947.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909ec0] >[655947.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909ec0] width 1280 pitch 5120 (/4 1280) >[655947.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598fb40] >[655947.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598fb40] width 1280 pitch 5120 (/4 1280) >[655980.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655980.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655980.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655980.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655980.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655980.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655980.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655980.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655980.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655980.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655980.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655980.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655980.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655980.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655980.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655980.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655980.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655980.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655980.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655980.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655980.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655980.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655980.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655980.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655981.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655981.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655981.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655981.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655981.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655981.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655981.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655981.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655981.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655981.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655981.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655981.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655981.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655981.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655981.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655981.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655981.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655985.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655985.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655986.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655986.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655986.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655986.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655987.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655987.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655987.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655987.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655987.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655987.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655987.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655987.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655987.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655987.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655987.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655987.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655987.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655987.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655987.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655987.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655987.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655987.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655987.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655988.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655988.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655988.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655988.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655988.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655988.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655988.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655988.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655988.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655988.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655988.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655989.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655989.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655989.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655989.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655989.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655989.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655989.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655989.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655989.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655989.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655989.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655989.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655989.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655989.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655989.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655989.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655989.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655989.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655989.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655989.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[655989.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[655989.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655989.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655989.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655989.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655989.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655989.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655989.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655989.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655989.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655989.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655989.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655990.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655990.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655990.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655990.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655990.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655990.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655990.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655999.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655999.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[655999.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[655999.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655999.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655999.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655999.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655999.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655999.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655999.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655999.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655999.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[655999.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[655999.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[655999.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[655999.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656000.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656000.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656000.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656000.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656000.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656000.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656000.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656000.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656000.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656000.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656000.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656000.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656001.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656001.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656001.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656001.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656001.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656001.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656001.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656001.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656001.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656002.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656002.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656002.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656002.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656002.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656002.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656003.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656003.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656003.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656003.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656003.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656003.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656003.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656003.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656003.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656003.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656004.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656004.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656004.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656004.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656004.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656004.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656004.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656004.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656004.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656004.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656005.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656005.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656005.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656005.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656005.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656006.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656006.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656006.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656006.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038840] >[656006.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038840] width 1280 pitch 5120 (/4 1280) >[656006.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656006.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656009.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656009.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656009.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656009.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656010.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656010.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656010.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656010.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656010.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656010.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656010.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656010.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656010.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656010.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656010.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656010.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656010.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656010.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656010.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656010.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038840] >[656010.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038840] width 1280 pitch 5120 (/4 1280) >[656010.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656010.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656011.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038840] >[656011.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038840] width 1280 pitch 5120 (/4 1280) >[656011.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656011.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656011.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038840] >[656011.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038840] width 1280 pitch 5120 (/4 1280) >[656011.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656011.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656011.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038840] >[656011.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038840] width 1280 pitch 5120 (/4 1280) >[656011.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656011.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656011.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656011.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656011.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656011.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656011.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656011.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656011.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656011.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656011.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656011.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656011.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656011.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656011.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656011.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656011.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656012.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656012.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea130] >[656012.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea130] width 1280 pitch 5120 (/4 1280) >[656012.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656012.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656012.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656012.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656012.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656012.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656012.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656012.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656012.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656012.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656012.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656012.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656012.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656012.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656012.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656012.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656012.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656012.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656013.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656013.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656013.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58827c0] >[656013.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58827c0] width 1280 pitch 5120 (/4 1280) >[656016.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656016.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656016.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656016.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656016.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656017.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656017.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656017.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656017.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656017.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58159b0] >[656017.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58159b0] width 1280 pitch 5120 (/4 1280) >[656018.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656018.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656018.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656018.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656018.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656018.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656018.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656018.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656018.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656019.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656019.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656019.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656019.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656019.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656019.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656019.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656019.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656019.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656019.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656019.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656019.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656019.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656019.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656019.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656019.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656020.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5999ef0] >[656020.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5999ef0] width 1280 pitch 5120 (/4 1280) >[656020.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656020.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656020.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656020.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656021.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5999ef0] >[656021.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5999ef0] width 1280 pitch 5120 (/4 1280) >[656021.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[656021.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[656022.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656022.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656022.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656022.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656023.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656024.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656024.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5999ef0] >[656024.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5999ef0] width 1280 pitch 5120 (/4 1280) >[656024.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656024.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656024.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656025.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656025.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[656025.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[656025.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656025.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656025.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656025.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656027.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656027.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656034.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57260a0] >[656034.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57260a0] width 1280 pitch 5120 (/4 1280) >[656034.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c36e0] >[656034.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c36e0] width 1280 pitch 5120 (/4 1280) >[656034.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656034.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656034.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c36e0] >[656034.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c36e0] width 1280 pitch 5120 (/4 1280) >[656034.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656034.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656034.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c36e0] >[656034.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c36e0] width 1280 pitch 5120 (/4 1280) >[656034.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656034.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656034.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c36e0] >[656034.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c36e0] width 1280 pitch 5120 (/4 1280) >[656034.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656034.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656034.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656034.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656034.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656034.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656034.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656034.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656034.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[656034.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[656034.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ed30] >[656034.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ed30] width 1280 pitch 5120 (/4 1280) >[656035.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c36e0] >[656035.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c36e0] width 1280 pitch 5120 (/4 1280) >[656035.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785f00] >[656035.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785f00] width 1280 pitch 5120 (/4 1280) >[656035.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785f00] >[656035.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785f00] width 1280 pitch 5120 (/4 1280) >[656035.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785ea0] >[656035.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785ea0] width 1280 pitch 5120 (/4 1280) >[656035.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785350] >[656035.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785350] width 1280 pitch 5120 (/4 1280) >[656035.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785f00] >[656035.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785f00] width 1280 pitch 5120 (/4 1280) >[656035.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785350] >[656035.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785350] width 1280 pitch 5120 (/4 1280) >[656035.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785350] >[656035.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785350] width 1280 pitch 5120 (/4 1280) >[656035.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785ea0] >[656035.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785ea0] width 1280 pitch 5120 (/4 1280) >[656035.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785350] >[656035.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785350] width 1280 pitch 5120 (/4 1280) >[656036.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785410] >[656036.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785410] width 1280 pitch 5120 (/4 1280) >[656036.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5785ea0] >[656036.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5785ea0] width 1280 pitch 5120 (/4 1280) >[656043.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57860a0] >[656043.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57860a0] width 1280 pitch 5120 (/4 1280) >[656044.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f98e0] >[656044.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f98e0] width 1280 pitch 5120 (/4 1280) >[656044.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5808df0] >[656044.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5808df0] width 1280 pitch 5120 (/4 1280) >[656044.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4309e90] >[656045.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4309e90] width 1280 pitch 5120 (/4 1280) >[656045.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b010] >[656045.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b010] width 1280 pitch 5120 (/4 1280) >[656045.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581a580] >[656045.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581a580] width 1280 pitch 5120 (/4 1280) >[656046.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cbcdd0] >[656046.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cbcdd0] width 1280 pitch 5120 (/4 1280) >[656046.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656046.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656046.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5458f60] >[656046.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5458f60] width 1280 pitch 5120 (/4 1280) >[656046.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5907340] >[656046.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5907340] width 1280 pitch 5120 (/4 1280) >[656148.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582d3b0] >[656148.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582d3b0] width 1280 pitch 5120 (/4 1280) >[656148.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5789360] >[656148.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5789360] width 1280 pitch 5120 (/4 1280) >[656162.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656162.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656162.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656162.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656162.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57437f0] >[656163.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57437f0] width 1280 pitch 5120 (/4 1280) >[656163.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656163.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656163.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57437f0] >[656163.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57437f0] width 1280 pitch 5120 (/4 1280) >[656163.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57437f0] >[656163.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57437f0] width 1280 pitch 5120 (/4 1280) >[656163.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656163.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656163.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57437f0] >[656163.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57437f0] width 1280 pitch 5120 (/4 1280) >[656167.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ea7d0] >[656167.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ea7d0] width 1280 pitch 5120 (/4 1280) >[656168.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656168.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57882a0] >[656168.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57882a0] width 1280 pitch 5120 (/4 1280) >[656168.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc1e0] >[656168.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc1e0] width 1280 pitch 5120 (/4 1280) >[656169.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656169.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656169.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4c40] >[656169.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4c40] width 1280 pitch 5120 (/4 1280) >[656190.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5782f90] >[656190.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5782f90] width 1280 pitch 5120 (/4 1280) >[656201.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656201.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656208.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ae9f0] >[656208.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ae9f0] width 1280 pitch 5120 (/4 1280) >[656209.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656209.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656209.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656209.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656209.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656209.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656209.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656209.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656209.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656209.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656210.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656210.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656210.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656210.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656211.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656211.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656212.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656212.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656213.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656213.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656213.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656213.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656213.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ec80] >[656213.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ec80] width 1280 pitch 5120 (/4 1280) >[656214.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656214.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656214.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be490] >[656214.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be490] width 1280 pitch 5120 (/4 1280) >[656214.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656214.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656214.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x535a520] >[656214.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x535a520] width 1280 pitch 5120 (/4 1280) >[656214.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786ab0] >[656214.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786ab0] width 1280 pitch 5120 (/4 1280) >[656245.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ae9f0] >[656245.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ae9f0] width 1280 pitch 5120 (/4 1280) >[656245.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656245.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656246.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ae9f0] >[656246.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ae9f0] width 1280 pitch 5120 (/4 1280) >[656246.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ba590] >[656246.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ba590] width 1280 pitch 5120 (/4 1280) >[656246.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4290] >[656246.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4290] width 1280 pitch 5120 (/4 1280) >[656246.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656246.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656246.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ba590] >[656246.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ba590] width 1280 pitch 5120 (/4 1280) >[656246.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656246.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656246.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ba590] >[656246.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ba590] width 1280 pitch 5120 (/4 1280) >[656246.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656246.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656246.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ba590] >[656246.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ba590] width 1280 pitch 5120 (/4 1280) >[656246.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656246.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656246.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ba590] >[656246.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ba590] width 1280 pitch 5120 (/4 1280) >[656246.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656246.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656246.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4290] >[656246.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4290] width 1280 pitch 5120 (/4 1280) >[656246.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656246.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656246.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4290] >[656246.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4290] width 1280 pitch 5120 (/4 1280) >[656246.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656246.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656246.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4290] >[656246.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4290] width 1280 pitch 5120 (/4 1280) >[656246.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656246.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4290] >[656247.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4290] width 1280 pitch 5120 (/4 1280) >[656247.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656247.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656247.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656247.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656247.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656248.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656248.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656248.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656248.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656253.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bb3b0] >[656253.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bb3b0] width 1280 pitch 5120 (/4 1280) >[656254.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bb4c0] >[656254.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bb4c0] width 1280 pitch 5120 (/4 1280) >[656254.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bb3b0] >[656254.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bb3b0] width 1280 pitch 5120 (/4 1280) >[656255.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5741160] >[656255.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5741160] width 1280 pitch 5120 (/4 1280) >[656255.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c2a50] >[656255.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c2a50] width 1280 pitch 5120 (/4 1280) >[656257.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656257.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656257.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656257.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656257.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656258.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3fe0] >[656258.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3fe0] width 1280 pitch 5120 (/4 1280) >[656258.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be4c0] >[656258.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be4c0] width 1280 pitch 5120 (/4 1280) >[656264.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b62d0] >[656264.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b62d0] width 1280 pitch 5120 (/4 1280) >[656264.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656264.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656264.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656264.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656264.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656264.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656264.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656264.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656265.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656265.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656265.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656265.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656266.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656266.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656266.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656266.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656266.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656266.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656266.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656266.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656266.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656266.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656266.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656266.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656266.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656266.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19c0f40] >[656266.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19c0f40] width 1280 pitch 5120 (/4 1280) >[656267.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656267.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656267.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b5070] >[656267.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b5070] width 1280 pitch 5120 (/4 1280) >[656267.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bf930] >[656267.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bf930] width 1280 pitch 5120 (/4 1280) >[656268.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bef40] >[656268.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bef40] width 1280 pitch 5120 (/4 1280) >[656268.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575a210] >[656268.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575a210] width 1280 pitch 5120 (/4 1280) >[656268.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bfdb0] >[656268.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bfdb0] width 1280 pitch 5120 (/4 1280) >[656268.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bfdb0] >[656268.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bfdb0] width 1280 pitch 5120 (/4 1280) >[656268.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bfdb0] >[656268.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bfdb0] width 1280 pitch 5120 (/4 1280) >[656268.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bfdb0] >[656268.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bfdb0] width 1280 pitch 5120 (/4 1280) >[656268.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575b1d0] >[656268.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575b1d0] width 1280 pitch 5120 (/4 1280) >[656268.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575b1d0] >[656268.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575b1d0] width 1280 pitch 5120 (/4 1280) >[656268.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5759a80] >[656268.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5759a80] width 1280 pitch 5120 (/4 1280) >[656268.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575b1d0] >[656268.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575b1d0] width 1280 pitch 5120 (/4 1280) >[656273.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5756000] >[656273.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5756000] width 1280 pitch 5120 (/4 1280) >[656273.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656273.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656273.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5756000] >[656273.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5756000] width 1280 pitch 5120 (/4 1280) >[656273.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575d030] >[656273.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575d030] width 1280 pitch 5120 (/4 1280) >[656273.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5756000] >[656273.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5756000] width 1280 pitch 5120 (/4 1280) >[656275.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575ae70] >[656275.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575ae70] width 1280 pitch 5120 (/4 1280) >[656275.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5756000] >[656275.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5756000] width 1280 pitch 5120 (/4 1280) >[656395.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5736ff0] >[656395.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5736ff0] width 1280 pitch 5120 (/4 1280) >[656449.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a35620] >[656449.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a35620] width 1280 pitch 5120 (/4 1280) >[656457.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a35620] >[656457.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a35620] width 1280 pitch 5120 (/4 1280) >[656523.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b6ff0] >[656523.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b6ff0] width 1280 pitch 5120 (/4 1280) >[656523.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53399d0] >[656523.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53399d0] width 1280 pitch 5120 (/4 1280) >[656525.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b6b190] >[656525.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b6b190] width 1280 pitch 5120 (/4 1280) >[656556.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5397e00] >[656556.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5397e00] width 1280 pitch 5120 (/4 1280) >[656556.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786d00] >[656556.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786d00] width 1280 pitch 5120 (/4 1280) >[656561.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5397e00] >[656561.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5397e00] width 1280 pitch 5120 (/4 1280) >[656561.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656561.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656561.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656561.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656561.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656562.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656562.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656562.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9550] >[656562.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9550] width 1280 pitch 5120 (/4 1280) >[656565.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786730] >[656565.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786730] width 1280 pitch 5120 (/4 1280) >[656565.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656565.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656587.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57bb2c0] >[656587.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57bb2c0] width 1280 pitch 5120 (/4 1280) >[656621.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a741d0] >[656621.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a741d0] width 1280 pitch 5120 (/4 1280) >[656621.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be430] >[656621.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be430] width 1280 pitch 5120 (/4 1280) >[656624.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786180] >[656624.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786180] width 1280 pitch 5120 (/4 1280) >[656624.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a741d0] >[656624.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a741d0] width 1280 pitch 5120 (/4 1280) >[656624.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be430] >[656624.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be430] width 1280 pitch 5120 (/4 1280) >[656625.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a741d0] >[656625.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a741d0] width 1280 pitch 5120 (/4 1280) >[656628.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5776810] >[656628.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5776810] width 1280 pitch 5120 (/4 1280) >[656628.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57864f0] >[656628.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57864f0] width 1280 pitch 5120 (/4 1280) >[656628.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5776810] >[656628.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5776810] width 1280 pitch 5120 (/4 1280) >[656630.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656630.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656630.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be430] >[656630.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be430] width 1280 pitch 5120 (/4 1280) >[656630.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656630.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656630.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57be430] >[656630.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57be430] width 1280 pitch 5120 (/4 1280) >[656630.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656630.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656630.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5786680] >[656630.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5786680] width 1280 pitch 5120 (/4 1280) >[656630.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874540] >[656630.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874540] width 1280 pitch 5120 (/4 1280) >[656633.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59158c0] >[656633.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59158c0] width 1280 pitch 5120 (/4 1280) >[656633.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2029480] >[656633.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2029480] width 1280 pitch 5120 (/4 1280) >[656675.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586f430] >[656675.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586f430] width 1280 pitch 5120 (/4 1280) >[656676.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a41f0] >[656676.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a41f0] width 1280 pitch 5120 (/4 1280) >[656676.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2029410] >[656676.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2029410] width 1280 pitch 5120 (/4 1280) >[656676.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x311c210] >[656676.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x311c210] width 1280 pitch 5120 (/4 1280) >[656751.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586faa0] >[656751.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586faa0] width 1280 pitch 5120 (/4 1280) >[656755.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5755170] >[656755.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5755170] width 1280 pitch 5120 (/4 1280) >[656755.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2029a10] >[656755.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2029a10] width 1280 pitch 5120 (/4 1280) >[656772.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f7c0] >[656772.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f7c0] width 1280 pitch 5120 (/4 1280) >[656772.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f7c0] >[656772.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f7c0] width 1280 pitch 5120 (/4 1280) >[656772.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f7c0] >[656772.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f7c0] width 1280 pitch 5120 (/4 1280) >[656772.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f7c0] >[656772.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f7c0] width 1280 pitch 5120 (/4 1280) >[656772.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cdc10] >[656772.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cdc10] width 1280 pitch 5120 (/4 1280) >[656772.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656772.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656772.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cdc10] >[656772.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cdc10] width 1280 pitch 5120 (/4 1280) >[656773.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656773.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656773.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cdc10] >[656773.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cdc10] width 1280 pitch 5120 (/4 1280) >[656773.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656773.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656773.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cdc10] >[656773.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cdc10] width 1280 pitch 5120 (/4 1280) >[656773.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656773.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656773.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cdc10] >[656773.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cdc10] width 1280 pitch 5120 (/4 1280) >[656773.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579f690] >[656773.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579f690] width 1280 pitch 5120 (/4 1280) >[656774.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb00] >[656774.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb00] width 1280 pitch 5120 (/4 1280) >[656774.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656774.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656775.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938c40] >[656775.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938c40] width 1280 pitch 5120 (/4 1280) >[656775.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57513e0] >[656775.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57513e0] width 1280 pitch 5120 (/4 1280) >[656793.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221bbb0] >[656793.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221bbb0] width 1280 pitch 5120 (/4 1280) >[656823.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5828df0] >[656823.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5828df0] width 1280 pitch 5120 (/4 1280) >[656826.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5828e70] >[656826.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5828e70] width 1280 pitch 5120 (/4 1280) >[656863.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58390] >[656863.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58390] width 1280 pitch 5120 (/4 1280) >[656863.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58650] >[656863.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58650] width 1280 pitch 5120 (/4 1280) >[656951.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866680] >[656951.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866680] width 1280 pitch 5120 (/4 1280) >[656951.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656951.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656952.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656952.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656953.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656953.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656961.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656961.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656961.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656961.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656962.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656962.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656962.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656962.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656962.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656962.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656962.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656962.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656962.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656962.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656962.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656962.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656962.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656962.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656963.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656963.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656963.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656963.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656963.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656963.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656965.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656965.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656971.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656971.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656971.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656971.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656971.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656971.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656971.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656971.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656971.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656971.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656971.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656971.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656972.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656972.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[656972.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[656972.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656972.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[656972.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[656972.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[656972.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[656973.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fe880] >[656973.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fe880] width 1280 pitch 5120 (/4 1280) >[656984.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fe880] >[656984.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fe880] width 1280 pitch 5120 (/4 1280) >[657020.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657020.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657020.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657020.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657020.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657020.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657020.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57961e0] >[657020.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57961e0] width 1280 pitch 5120 (/4 1280) >[657020.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657020.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657020.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586e040] >[657020.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586e040] width 1280 pitch 5120 (/4 1280) >[657020.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657020.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657020.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753d10] >[657020.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753d10] width 1280 pitch 5120 (/4 1280) >[657020.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753d10] >[657020.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753d10] width 1280 pitch 5120 (/4 1280) >[657020.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586e040] >[657020.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586e040] width 1280 pitch 5120 (/4 1280) >[657020.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753d10] >[657020.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753d10] width 1280 pitch 5120 (/4 1280) >[657020.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753d10] >[657020.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753d10] width 1280 pitch 5120 (/4 1280) >[657020.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797930] >[657020.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797930] width 1280 pitch 5120 (/4 1280) >[657020.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753d10] >[657020.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753d10] width 1280 pitch 5120 (/4 1280) >[657020.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657020.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586e040] >[657020.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586e040] width 1280 pitch 5120 (/4 1280) >[657020.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57965a0] >[657020.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57965a0] width 1280 pitch 5120 (/4 1280) >[657043.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c600] >[657043.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c600] width 1280 pitch 5120 (/4 1280) >[657043.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574fe90] >[657043.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574fe90] width 1280 pitch 5120 (/4 1280) >[657043.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657043.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657043.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657043.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657043.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657043.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657043.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657043.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657043.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657043.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657043.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657043.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657043.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657043.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657044.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657044.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657044.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657044.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657044.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657044.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657044.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657044.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657044.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657044.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657044.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657044.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657044.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657045.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657045.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657045.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657045.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657045.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657045.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657045.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657045.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657045.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657045.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657045.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657045.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657045.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572ceb0] >[657045.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572ceb0] width 1280 pitch 5120 (/4 1280) >[657046.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657046.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657046.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657046.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657046.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657046.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657046.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657046.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657046.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657046.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657046.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4748080] >[657046.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4748080] width 1280 pitch 5120 (/4 1280) >[657046.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657046.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657046.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657046.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657046.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657046.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657046.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657046.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657046.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657046.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657046.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657046.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657046.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657046.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657046.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657046.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657047.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657047.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657047.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577bf40] >[657047.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577bf40] width 1280 pitch 5120 (/4 1280) >[657047.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a6b70] >[657047.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a6b70] width 1280 pitch 5120 (/4 1280) >[657055.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5828cb0] >[657055.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5828cb0] width 1280 pitch 5120 (/4 1280) >[657057.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[657057.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[657057.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[657057.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[657057.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[657057.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[657057.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657057.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657057.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[657057.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[657057.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[657057.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[657057.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[657057.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[657057.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[657057.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[657057.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[657057.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[657057.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657057.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657057.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[657057.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[657057.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[657057.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[657057.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[657057.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[657057.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[657057.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[657058.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e0ff0] >[657058.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e0ff0] width 1280 pitch 5120 (/4 1280) >[657058.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657058.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657058.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657058.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657058.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[657058.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[657058.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[657058.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[657058.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[657058.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[657058.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[657058.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[657058.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[657058.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[657059.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657059.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657059.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[657059.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[657059.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[657059.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[657059.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[657059.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[657059.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657059.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657059.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7ca0] >[657059.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7ca0] width 1280 pitch 5120 (/4 1280) >[657060.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x564f800] >[657060.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x564f800] width 1280 pitch 5120 (/4 1280) >[657060.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657060.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657060.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[657060.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[657060.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cb40] >[657060.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cb40] width 1280 pitch 5120 (/4 1280) >[657060.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657060.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657060.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[657060.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[657060.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657060.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657060.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2900] >[657060.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2900] width 1280 pitch 5120 (/4 1280) >[657060.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657060.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657060.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7ca0] >[657060.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7ca0] width 1280 pitch 5120 (/4 1280) >[657060.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657060.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657060.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[657060.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[657060.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a740e0] >[657060.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a740e0] width 1280 pitch 5120 (/4 1280) >[657060.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[657060.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[657060.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5f40] >[657060.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5f40] width 1280 pitch 5120 (/4 1280) >[657060.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573d040] >[657060.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573d040] width 1280 pitch 5120 (/4 1280) >[657060.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x542edb0] >[657060.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x542edb0] width 1280 pitch 5120 (/4 1280) >[657060.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573d040] >[657060.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573d040] width 1280 pitch 5120 (/4 1280) >[657060.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cb40] >[657060.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cb40] width 1280 pitch 5120 (/4 1280) >[657060.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657060.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657060.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cb40] >[657060.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cb40] width 1280 pitch 5120 (/4 1280) >[657060.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2900] >[657060.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2900] width 1280 pitch 5120 (/4 1280) >[657060.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cb40] >[657060.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cb40] width 1280 pitch 5120 (/4 1280) >[657060.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b7ca0] >[657060.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b7ca0] width 1280 pitch 5120 (/4 1280) >[657060.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x592cb40] >[657060.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x592cb40] width 1280 pitch 5120 (/4 1280) >[657060.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[657060.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[657062.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657062.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657063.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a75030] >[657063.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a75030] width 1280 pitch 5120 (/4 1280) >[657063.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657063.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657063.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[657063.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[657063.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657063.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657064.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657064.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657064.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5790710] >[657064.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5790710] width 1280 pitch 5120 (/4 1280) >[657064.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657064.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657064.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57906e0] >[657064.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57906e0] width 1280 pitch 5120 (/4 1280) >[657064.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea3d20] >[657064.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea3d20] width 1280 pitch 5120 (/4 1280) >[657117.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a1a80] >[657117.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a1a80] width 1280 pitch 5120 (/4 1280) >[657117.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d820] >[657117.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d820] width 1280 pitch 5120 (/4 1280) >[657342.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959930] >[657342.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959930] width 1280 pitch 5120 (/4 1280) >[657342.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657342.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657343.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657343.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657343.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657343.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657344.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657344.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657344.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657344.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5754cc0] >[657345.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5754cc0] width 1280 pitch 5120 (/4 1280) >[657345.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[657345.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[657345.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[657345.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[657345.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[657345.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[657345.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657345.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657345.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657346.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657346.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657346.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657346.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657346.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657346.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[657346.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[657346.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[657346.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[657346.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[657346.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[657346.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866920] >[657346.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866920] width 1280 pitch 5120 (/4 1280) >[657346.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[657346.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[657346.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5774e60] >[657346.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5774e60] width 1280 pitch 5120 (/4 1280) >[657346.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657346.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657346.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f54e0] >[657346.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f54e0] width 1280 pitch 5120 (/4 1280) >[657347.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f54e0] >[657347.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f54e0] width 1280 pitch 5120 (/4 1280) >[657347.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5670] >[657347.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5670] width 1280 pitch 5120 (/4 1280) >[657347.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5600] >[657347.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5600] width 1280 pitch 5120 (/4 1280) >[657347.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657347.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58662e0] >[657347.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58662e0] width 1280 pitch 5120 (/4 1280) >[657347.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5615600] >[657347.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5615600] width 1280 pitch 5120 (/4 1280) >[657352.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872bd0] >[657352.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872bd0] width 1280 pitch 5120 (/4 1280) >[657352.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872d80] >[657352.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872d80] width 1280 pitch 5120 (/4 1280) >[657352.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657352.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657352.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657352.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657352.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657352.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5250] >[657352.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5250] width 1280 pitch 5120 (/4 1280) >[657352.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872d80] >[657352.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872d80] width 1280 pitch 5120 (/4 1280) >[657352.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f56f0] >[657352.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f56f0] width 1280 pitch 5120 (/4 1280) >[657353.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a22560] >[657353.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a22560] width 1280 pitch 5120 (/4 1280) >[657353.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552ae80] >[657353.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552ae80] width 1280 pitch 5120 (/4 1280) >[657354.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632340] >[657354.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632340] width 1280 pitch 5120 (/4 1280) >[657354.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578f8f0] >[657354.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578f8f0] width 1280 pitch 5120 (/4 1280) >[657354.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f50c0] >[657354.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f50c0] width 1280 pitch 5120 (/4 1280) >[657361.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2773790] >[657361.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2773790] width 1280 pitch 5120 (/4 1280) >[657361.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a22560] >[657361.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a22560] width 1280 pitch 5120 (/4 1280) >[657362.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57245a0] >[657362.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57245a0] width 1280 pitch 5120 (/4 1280) >[657362.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371520] >[657362.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371520] width 1280 pitch 5120 (/4 1280) >[657362.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a9d6b0] >[657362.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a9d6b0] width 1280 pitch 5120 (/4 1280) >[657362.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371520] >[657362.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371520] width 1280 pitch 5120 (/4 1280) >[657363.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a9d6b0] >[657363.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a9d6b0] width 1280 pitch 5120 (/4 1280) >[657363.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8d00] >[657364.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8d00] width 1280 pitch 5120 (/4 1280) >[657364.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d3d0] >[657364.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d3d0] width 1280 pitch 5120 (/4 1280) >[657364.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5962b40] >[657364.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5962b40] width 1280 pitch 5120 (/4 1280) >[657364.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b8d00] >[657364.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b8d00] width 1280 pitch 5120 (/4 1280) >[657375.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a9d6b0] >[657375.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a9d6b0] width 1280 pitch 5120 (/4 1280) >[657375.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a64c0] >[657375.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a64c0] width 1280 pitch 5120 (/4 1280) >[657472.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33e50] >[657472.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33e50] width 1280 pitch 5120 (/4 1280) >[657472.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33570] >[657472.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33570] width 1280 pitch 5120 (/4 1280) >[657478.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4470] >[657478.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4470] width 1280 pitch 5120 (/4 1280) >[657482.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaea20] >[657482.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaea20] width 1280 pitch 5120 (/4 1280) >[657482.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bd0de0] >[657482.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bd0de0] width 1280 pitch 5120 (/4 1280) >[657482.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33490] >[657482.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33490] width 1280 pitch 5120 (/4 1280) >[657487.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaf0a0] >[657487.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaf0a0] width 1280 pitch 5120 (/4 1280) >[657487.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcf040] >[657487.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcf040] width 1280 pitch 5120 (/4 1280) >[657488.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcf360] >[657488.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcf360] width 1280 pitch 5120 (/4 1280) >[657488.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4250] >[657488.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4250] width 1280 pitch 5120 (/4 1280) >[657488.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4250] >[657488.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4250] width 1280 pitch 5120 (/4 1280) >[657488.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33490] >[657488.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33490] width 1280 pitch 5120 (/4 1280) >[657488.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33490] >[657488.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33490] width 1280 pitch 5120 (/4 1280) >[657492.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657492.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657494.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab9cd0] >[657494.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab9cd0] width 1280 pitch 5120 (/4 1280) >[657495.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7020] >[657495.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7020] width 1280 pitch 5120 (/4 1280) >[657495.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c070] >[657495.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c070] width 1280 pitch 5120 (/4 1280) >[657495.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7020] >[657495.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7020] width 1280 pitch 5120 (/4 1280) >[657498.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab9f90] >[657498.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab9f90] width 1280 pitch 5120 (/4 1280) >[657498.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2e1d0] >[657498.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2e1d0] width 1280 pitch 5120 (/4 1280) >[657498.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33490] >[657498.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33490] width 1280 pitch 5120 (/4 1280) >[657498.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657498.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657498.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f2dd0] >[657498.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f2dd0] width 1280 pitch 5120 (/4 1280) >[657498.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2e630] >[657498.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2e630] width 1280 pitch 5120 (/4 1280) >[657498.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657498.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657498.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2e630] >[657498.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2e630] width 1280 pitch 5120 (/4 1280) >[657498.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f2dd0] >[657498.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f2dd0] width 1280 pitch 5120 (/4 1280) >[657498.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657498.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657498.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f2dd0] >[657498.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f2dd0] width 1280 pitch 5120 (/4 1280) >[657498.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657498.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657500.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33490] >[657500.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33490] width 1280 pitch 5120 (/4 1280) >[657500.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30ef0] >[657500.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30ef0] width 1280 pitch 5120 (/4 1280) >[657500.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30ef0] >[657500.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30ef0] width 1280 pitch 5120 (/4 1280) >[657500.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4330] >[657500.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4330] width 1280 pitch 5120 (/4 1280) >[657500.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30ef0] >[657500.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30ef0] width 1280 pitch 5120 (/4 1280) >[657500.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4330] >[657500.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4330] width 1280 pitch 5120 (/4 1280) >[657500.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30ef0] >[657500.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30ef0] width 1280 pitch 5120 (/4 1280) >[657500.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30ef0] >[657500.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30ef0] width 1280 pitch 5120 (/4 1280) >[657500.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4140] >[657500.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4140] width 1280 pitch 5120 (/4 1280) >[657500.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa4330] >[657500.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa4330] width 1280 pitch 5120 (/4 1280) >[657500.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5750b00] >[657500.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5750b00] width 1280 pitch 5120 (/4 1280) >[657500.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5ad0] >[657500.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5ad0] width 1280 pitch 5120 (/4 1280) >[657500.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57996f0] >[657500.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57996f0] width 1280 pitch 5120 (/4 1280) >[657548.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33a30] >[657548.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33a30] width 1280 pitch 5120 (/4 1280) >[657548.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33a30] >[657548.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33a30] width 1280 pitch 5120 (/4 1280) >[657636.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657636.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657639.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657639.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657655.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aade10] >[657655.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aade10] width 1280 pitch 5120 (/4 1280) >[657656.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aade10] >[657656.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aade10] width 1280 pitch 5120 (/4 1280) >[657656.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657656.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657656.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ceb0] >[657656.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ceb0] width 1280 pitch 5120 (/4 1280) >[657890.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aade10] >[657890.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aade10] width 1280 pitch 5120 (/4 1280) >[657890.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aade10] >[657890.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aade10] width 1280 pitch 5120 (/4 1280) >[657890.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657890.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657890.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aade10] >[657890.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aade10] width 1280 pitch 5120 (/4 1280) >[657890.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657890.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657891.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadd10] >[657891.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadd10] width 1280 pitch 5120 (/4 1280) >[657891.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872d80] >[657891.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872d80] width 1280 pitch 5120 (/4 1280) >[657892.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4309e20] >[657892.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4309e20] width 1280 pitch 5120 (/4 1280) >[657892.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5872d80] >[657892.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5872d80] width 1280 pitch 5120 (/4 1280) >[657892.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f2f60] >[657892.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f2f60] width 1280 pitch 5120 (/4 1280) >[657892.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ed0b0] >[657892.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ed0b0] width 1280 pitch 5120 (/4 1280) >[657892.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584cc90] >[657892.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584cc90] width 1280 pitch 5120 (/4 1280) >[657900.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4188c50] >[657900.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4188c50] width 1280 pitch 5120 (/4 1280) >[657900.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aad700] >[657900.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aad700] width 1280 pitch 5120 (/4 1280) >[657900.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aad700] >[657900.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aad700] width 1280 pitch 5120 (/4 1280) >[657900.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33340] >[657900.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33340] width 1280 pitch 5120 (/4 1280) >[657901.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8330] >[657901.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8330] width 1280 pitch 5120 (/4 1280) >[657901.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f81d0] >[657901.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f81d0] width 1280 pitch 5120 (/4 1280) >[657902.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7cee0] >[657902.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7cee0] width 1280 pitch 5120 (/4 1280) >[657902.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8330] >[657902.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8330] width 1280 pitch 5120 (/4 1280) >[657902.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a8010] >[657902.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a8010] width 1280 pitch 5120 (/4 1280) >[657902.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33340] >[657902.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33340] width 1280 pitch 5120 (/4 1280) >[657909.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5798c80] >[657909.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5798c80] width 1280 pitch 5120 (/4 1280) >[657909.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5798c80] >[657909.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5798c80] width 1280 pitch 5120 (/4 1280) >[657918.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724af0] >[657918.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724af0] width 1280 pitch 5120 (/4 1280) >[657918.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5724af0] >[657918.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5724af0] width 1280 pitch 5120 (/4 1280) >[657930.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aae5d0] >[657930.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aae5d0] width 1280 pitch 5120 (/4 1280) >[657932.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadbf0] >[657932.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadbf0] width 1280 pitch 5120 (/4 1280) >[657932.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657932.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657932.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657932.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657932.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657932.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657932.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657932.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657932.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657932.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657932.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657932.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657932.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657932.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657932.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657932.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657932.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657932.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657932.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657932.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a430] >[657933.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a430] width 1280 pitch 5120 (/4 1280) >[657933.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c900] >[657933.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c900] width 1280 pitch 5120 (/4 1280) >[657933.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadbf0] >[657933.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadbf0] width 1280 pitch 5120 (/4 1280) >[657933.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadbf0] >[657933.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadbf0] width 1280 pitch 5120 (/4 1280) >[657933.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c900] >[657933.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c900] width 1280 pitch 5120 (/4 1280) >[657933.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aae5d0] >[657933.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aae5d0] width 1280 pitch 5120 (/4 1280) >[657933.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aae5d0] >[657933.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aae5d0] width 1280 pitch 5120 (/4 1280) >[657933.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aae5d0] >[657933.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aae5d0] width 1280 pitch 5120 (/4 1280) >[657933.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657933.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657933.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aae5d0] >[657933.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aae5d0] width 1280 pitch 5120 (/4 1280) >[657934.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c900] >[657934.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c900] width 1280 pitch 5120 (/4 1280) >[657934.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aadbf0] >[657934.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aadbf0] width 1280 pitch 5120 (/4 1280) >[657934.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c900] >[657934.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c900] width 1280 pitch 5120 (/4 1280) >[657934.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f690] >[657934.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f690] width 1280 pitch 5120 (/4 1280) >[657934.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8bd80] >[657934.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8bd80] width 1280 pitch 5120 (/4 1280) >[657934.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[657934.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[657935.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657935.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657935.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657935.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657935.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b88350] >[657936.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b88350] width 1280 pitch 5120 (/4 1280) >[657936.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657936.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657936.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657936.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657936.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657936.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657936.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657936.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657936.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657936.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657936.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657936.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765430] >[657936.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765430] width 1280 pitch 5120 (/4 1280) >[657942.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed10] >[657942.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed10] width 1280 pitch 5120 (/4 1280) >[657954.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b80590] >[657954.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b80590] width 1280 pitch 5120 (/4 1280) >[657955.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5520] >[657955.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5520] width 1280 pitch 5120 (/4 1280) >[657955.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b80590] >[657955.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b80590] width 1280 pitch 5120 (/4 1280) >[657956.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5520] >[657956.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5520] width 1280 pitch 5120 (/4 1280) >[657956.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b80590] >[657956.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b80590] width 1280 pitch 5120 (/4 1280) >[657957.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5520] >[657957.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5520] width 1280 pitch 5120 (/4 1280) >[657957.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b80590] >[657957.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b80590] width 1280 pitch 5120 (/4 1280) >[663837.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663837.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663837.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663837.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663837.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663837.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663837.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663837.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663837.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59633a0] >[663837.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59633a0] width 1280 pitch 5120 (/4 1280) >[663837.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663837.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663838.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663838.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663838.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58685f0] >[663838.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58685f0] width 1280 pitch 5120 (/4 1280) >[663838.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663838.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663838.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20594e0] >[663838.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20594e0] width 1280 pitch 5120 (/4 1280) >[663838.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663838.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663838.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663838.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663838.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59633a0] >[663839.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59633a0] width 1280 pitch 5120 (/4 1280) >[663839.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58685f0] >[663839.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58685f0] width 1280 pitch 5120 (/4 1280) >[663839.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20594e0] >[663839.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20594e0] width 1280 pitch 5120 (/4 1280) >[663839.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58685f0] >[663839.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58685f0] width 1280 pitch 5120 (/4 1280) >[663839.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20594e0] >[663839.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20594e0] width 1280 pitch 5120 (/4 1280) >[663839.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b1390] >[663839.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b1390] width 1280 pitch 5120 (/4 1280) >[663839.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20594e0] >[663839.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20594e0] width 1280 pitch 5120 (/4 1280) >[663839.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b1390] >[663839.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b1390] width 1280 pitch 5120 (/4 1280) >[663839.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59633a0] >[663839.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59633a0] width 1280 pitch 5120 (/4 1280) >[663839.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59633a0] >[663839.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59633a0] width 1280 pitch 5120 (/4 1280) >[663839.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663839.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663840.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663840.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663840.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5721d20] >[663840.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5721d20] width 1280 pitch 5120 (/4 1280) >[663840.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abb850] >[663840.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abb850] width 1280 pitch 5120 (/4 1280) >[663841.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5826410] >[663841.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5826410] width 1280 pitch 5120 (/4 1280) >[663841.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59633a0] >[663841.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59633a0] width 1280 pitch 5120 (/4 1280) >[663841.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576de80] >[663841.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576de80] width 1280 pitch 5120 (/4 1280) >[663841.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30620] >[663841.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30620] width 1280 pitch 5120 (/4 1280) >[663841.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abb850] >[663841.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abb850] width 1280 pitch 5120 (/4 1280) >[663843.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[663843.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[663843.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663843.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663843.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791900] >[663843.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791900] width 1280 pitch 5120 (/4 1280) >[663844.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663844.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663844.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791830] >[663844.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791830] width 1280 pitch 5120 (/4 1280) >[663845.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c3c0] >[663845.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c3c0] width 1280 pitch 5120 (/4 1280) >[663845.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c3c0] >[663845.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c3c0] width 1280 pitch 5120 (/4 1280) >[663845.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c3c0] >[663845.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c3c0] width 1280 pitch 5120 (/4 1280) >[663845.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c3c0] >[663845.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c3c0] width 1280 pitch 5120 (/4 1280) >[663845.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663845.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663845.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663845.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[663845.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[663849.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5728df0] >[663849.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5728df0] width 1280 pitch 5120 (/4 1280) >[663849.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791830] >[663849.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791830] width 1280 pitch 5120 (/4 1280) >[663850.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c570] >[663850.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c570] width 1280 pitch 5120 (/4 1280) >[663850.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57913a0] >[663850.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57913a0] width 1280 pitch 5120 (/4 1280) >[663850.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c570] >[663850.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c570] width 1280 pitch 5120 (/4 1280) >[663850.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57913a0] >[663850.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57913a0] width 1280 pitch 5120 (/4 1280) >[663851.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791c00] >[663851.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791c00] width 1280 pitch 5120 (/4 1280) >[663851.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c570] >[663851.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c570] width 1280 pitch 5120 (/4 1280) >[663851.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598c570] >[663851.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598c570] width 1280 pitch 5120 (/4 1280) >[663851.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56856f0] >[663851.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56856f0] width 1280 pitch 5120 (/4 1280) >[663853.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a0700] >[663853.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a0700] width 1280 pitch 5120 (/4 1280) >[663861.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574f480] >[663861.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574f480] width 1280 pitch 5120 (/4 1280) >[664296.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b733b0] >[664296.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b733b0] width 1280 pitch 5120 (/4 1280) >[664296.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7aca0] >[664296.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7aca0] width 1280 pitch 5120 (/4 1280) >[664305.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[664305.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[664310.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b76ec0] >[664310.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b76ec0] width 1280 pitch 5120 (/4 1280) >[664310.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b733b0] >[664310.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b733b0] width 1280 pitch 5120 (/4 1280) >[664310.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5870e20] >[664310.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5870e20] width 1280 pitch 5120 (/4 1280) >[664310.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5870e20] >[664310.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5870e20] width 1280 pitch 5120 (/4 1280) >[664360.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b73e00] >[664360.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b73e00] width 1280 pitch 5120 (/4 1280) >[664362.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b75380] >[664362.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b75380] width 1280 pitch 5120 (/4 1280) >[664380.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b73e00] >[664380.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b73e00] width 1280 pitch 5120 (/4 1280) >[664402.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b663f0] >[664402.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b663f0] width 1280 pitch 5120 (/4 1280) >[664406.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7b4e0] >[664406.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7b4e0] width 1280 pitch 5120 (/4 1280) >[664424.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b896e0] >[664424.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b896e0] width 1280 pitch 5120 (/4 1280) >[664424.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b663f0] >[664424.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b663f0] width 1280 pitch 5120 (/4 1280) >[664474.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c0440] >[664474.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c0440] width 1280 pitch 5120 (/4 1280) >[664491.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573f360] >[664491.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573f360] width 1280 pitch 5120 (/4 1280) >[664497.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58bb800] >[664497.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58bb800] width 1280 pitch 5120 (/4 1280) >[664497.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b9f80] >[664497.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b9f80] width 1280 pitch 5120 (/4 1280) >[664502.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827380] >[664502.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827380] width 1280 pitch 5120 (/4 1280) >[664503.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a77370] >[664503.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a77370] width 1280 pitch 5120 (/4 1280) >[664504.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827380] >[664504.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827380] width 1280 pitch 5120 (/4 1280) >[664504.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a77370] >[664504.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a77370] width 1280 pitch 5120 (/4 1280) >[664505.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5755040] >[664505.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5755040] width 1280 pitch 5120 (/4 1280) >[664505.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573f360] >[664505.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573f360] width 1280 pitch 5120 (/4 1280) >[664617.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90550] >[664617.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90550] width 1280 pitch 5120 (/4 1280) >[664617.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b500] >[664617.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b500] width 1280 pitch 5120 (/4 1280) >[664626.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc8da0] >[664626.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc8da0] width 1280 pitch 5120 (/4 1280) >[664626.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53686f0] >[664626.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53686f0] width 1280 pitch 5120 (/4 1280) >[664629.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc8da0] >[664629.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc8da0] width 1280 pitch 5120 (/4 1280) >[664630.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5450] >[664630.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5450] width 1280 pitch 5120 (/4 1280) >[664632.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5450] >[664632.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5450] width 1280 pitch 5120 (/4 1280) >[664632.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61fc0] >[664632.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61fc0] width 1280 pitch 5120 (/4 1280) >[664632.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc8da0] >[664632.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc8da0] width 1280 pitch 5120 (/4 1280) >[664642.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5450] >[664642.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5450] width 1280 pitch 5120 (/4 1280) >[664644.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53686f0] >[664644.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53686f0] width 1280 pitch 5120 (/4 1280) >[664679.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61fc0] >[664679.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61fc0] width 1280 pitch 5120 (/4 1280) >[664681.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc8da0] >[664681.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc8da0] width 1280 pitch 5120 (/4 1280) >[664681.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a916c0] >[664681.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a916c0] width 1280 pitch 5120 (/4 1280) >[664681.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b667c0] >[664681.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b667c0] width 1280 pitch 5120 (/4 1280) >[664683.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61fc0] >[664683.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61fc0] width 1280 pitch 5120 (/4 1280) >[664685.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53686f0] >[664685.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53686f0] width 1280 pitch 5120 (/4 1280) >[664685.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53686f0] >[664685.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53686f0] width 1280 pitch 5120 (/4 1280) >[664697.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14e30] >[664697.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14e30] width 1280 pitch 5120 (/4 1280) >[664697.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14e30] >[664697.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14e30] width 1280 pitch 5120 (/4 1280) >[664709.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598de40] >[664709.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598de40] width 1280 pitch 5120 (/4 1280) >[664709.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578ced0] >[664710.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578ced0] width 1280 pitch 5120 (/4 1280) >[664714.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578cc60] >[664714.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578cc60] width 1280 pitch 5120 (/4 1280) >[664715.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x578cc60] >[664715.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x578cc60] width 1280 pitch 5120 (/4 1280) >[664716.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b51f60] >[664716.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b51f60] width 1280 pitch 5120 (/4 1280) >[664717.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59536d0] >[664717.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59536d0] width 1280 pitch 5120 (/4 1280) >[664717.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59536d0] >[664717.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59536d0] width 1280 pitch 5120 (/4 1280) >[664717.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96c40] >[664717.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96c40] width 1280 pitch 5120 (/4 1280) >[664718.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[664718.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[664718.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8ac0] >[664718.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8ac0] width 1280 pitch 5120 (/4 1280) >[664718.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96c40] >[664718.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96c40] width 1280 pitch 5120 (/4 1280) >[664718.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582dfe0] >[664718.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582dfe0] width 1280 pitch 5120 (/4 1280) >[664718.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59536d0] >[664718.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59536d0] width 1280 pitch 5120 (/4 1280) >[664719.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582dfe0] >[664719.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582dfe0] width 1280 pitch 5120 (/4 1280) >[664719.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56259a0] >[664719.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56259a0] width 1280 pitch 5120 (/4 1280) >[664719.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96c40] >[664719.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96c40] width 1280 pitch 5120 (/4 1280) >[664720.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eadac0] >[664720.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eadac0] width 1280 pitch 5120 (/4 1280) >[664721.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b85ef0] >[664721.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b85ef0] width 1280 pitch 5120 (/4 1280) >[664721.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827c70] >[664721.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827c70] width 1280 pitch 5120 (/4 1280) >[664721.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x568c2f0] >[664721.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x568c2f0] width 1280 pitch 5120 (/4 1280) >[664721.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90ac0] >[664721.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90ac0] width 1280 pitch 5120 (/4 1280) >[664722.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b632a0] >[664722.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b632a0] width 1280 pitch 5120 (/4 1280) >[664722.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b632a0] >[664722.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b632a0] width 1280 pitch 5120 (/4 1280) >[664722.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b632a0] >[664722.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b632a0] width 1280 pitch 5120 (/4 1280) >[664722.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57922c0] >[664722.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57922c0] width 1280 pitch 5120 (/4 1280) >[664722.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664722.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664723.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664723.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664723.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3e7a0] >[664723.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3e7a0] width 1280 pitch 5120 (/4 1280) >[664724.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5760e10] >[664724.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5760e10] width 1280 pitch 5120 (/4 1280) >[664724.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61fc0] >[664724.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61fc0] width 1280 pitch 5120 (/4 1280) >[664724.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b648e0] >[664724.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b648e0] width 1280 pitch 5120 (/4 1280) >[664730.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664730.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664731.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b648e0] >[664731.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b648e0] width 1280 pitch 5120 (/4 1280) >[664731.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a916c0] >[664731.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a916c0] width 1280 pitch 5120 (/4 1280) >[664731.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664731.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664731.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa5450] >[664731.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa5450] width 1280 pitch 5120 (/4 1280) >[664732.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96a20] >[664732.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96a20] width 1280 pitch 5120 (/4 1280) >[664732.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96a20] >[664732.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96a20] width 1280 pitch 5120 (/4 1280) >[664732.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664732.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664733.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96a20] >[664733.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96a20] width 1280 pitch 5120 (/4 1280) >[664734.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664734.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664734.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b91f50] >[664734.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b91f50] width 1280 pitch 5120 (/4 1280) >[664734.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x573e370] >[664734.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x573e370] width 1280 pitch 5120 (/4 1280) >[664739.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b33920] >[664739.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b33920] width 1280 pitch 5120 (/4 1280) >[664739.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3fa20] >[664739.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3fa20] width 1280 pitch 5120 (/4 1280) >[664762.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54770c0] >[664762.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54770c0] width 1280 pitch 5120 (/4 1280) >[664762.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a59380] >[664762.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a59380] width 1280 pitch 5120 (/4 1280) >[664861.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56050b0] >[664861.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56050b0] width 1280 pitch 5120 (/4 1280) >[664861.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[664861.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[664862.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3fef0] >[664862.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3fef0] width 1280 pitch 5120 (/4 1280) >[664896.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[664896.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[664896.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56050b0] >[664896.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56050b0] width 1280 pitch 5120 (/4 1280) >[664896.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3fef0] >[664896.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3fef0] width 1280 pitch 5120 (/4 1280) >[664896.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56050b0] >[664896.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56050b0] width 1280 pitch 5120 (/4 1280) >[664896.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56050b0] >[664896.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56050b0] width 1280 pitch 5120 (/4 1280) >[664897.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a370] >[664897.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a370] width 1280 pitch 5120 (/4 1280) >[664898.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3fef0] >[664898.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3fef0] width 1280 pitch 5120 (/4 1280) >[665188.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3fef0] >[665188.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3fef0] width 1280 pitch 5120 (/4 1280) >[665188.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56050b0] >[665188.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56050b0] width 1280 pitch 5120 (/4 1280) >[665192.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43500] >[665192.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43500] width 1280 pitch 5120 (/4 1280) >[665234.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b85ec0] >[665234.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b85ec0] width 1280 pitch 5120 (/4 1280) >[665246.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a370] >[665246.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a370] width 1280 pitch 5120 (/4 1280) >[665247.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7e00] >[665247.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7e00] width 1280 pitch 5120 (/4 1280) >[665248.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571d410] >[665248.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571d410] width 1280 pitch 5120 (/4 1280) >[665248.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7e00] >[665248.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7e00] width 1280 pitch 5120 (/4 1280) >[665248.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571d410] >[665248.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571d410] width 1280 pitch 5120 (/4 1280) >[665248.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd7e00] >[665248.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd7e00] width 1280 pitch 5120 (/4 1280) >[665248.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571d410] >[665248.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571d410] width 1280 pitch 5120 (/4 1280) >[665249.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bceae0] >[665249.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bceae0] width 1280 pitch 5120 (/4 1280) >[665249.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b85ee0] >[665249.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b85ee0] width 1280 pitch 5120 (/4 1280) >[665249.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bceae0] >[665249.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bceae0] width 1280 pitch 5120 (/4 1280) >[665249.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b85ee0] >[665249.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b85ee0] width 1280 pitch 5120 (/4 1280) >[665249.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bceae0] >[665249.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bceae0] width 1280 pitch 5120 (/4 1280) >[665250.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a370] >[665250.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a370] width 1280 pitch 5120 (/4 1280) >[665250.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b1130] >[665250.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b1130] width 1280 pitch 5120 (/4 1280) >[665250.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a370] >[665250.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a370] width 1280 pitch 5120 (/4 1280) >[665250.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b1130] >[665250.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b1130] width 1280 pitch 5120 (/4 1280) >[665250.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a370] >[665250.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a370] width 1280 pitch 5120 (/4 1280) >[665252.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[665252.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[665252.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[665252.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[665252.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[665252.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[665252.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[665252.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[665252.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[665252.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[665252.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[665252.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[665253.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[665253.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[665253.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[665253.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[665253.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[665253.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[665253.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572c340] >[665253.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572c340] width 1280 pitch 5120 (/4 1280) >[665253.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b15e0] >[665253.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b15e0] width 1280 pitch 5120 (/4 1280) >[665337.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665337.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665338.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a79120] >[665338.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a79120] width 1280 pitch 5120 (/4 1280) >[665362.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac6640] >[665362.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac6640] width 1280 pitch 5120 (/4 1280) >[665412.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665412.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665412.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665412.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665412.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665412.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665412.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665412.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665412.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665412.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665412.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665412.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665412.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665412.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665412.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665412.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665412.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665412.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665412.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665413.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665413.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8b1f0] >[665413.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8b1f0] width 1280 pitch 5120 (/4 1280) >[665413.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665413.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665414.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665414.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665414.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665414.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665414.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665414.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665414.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665414.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665414.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665414.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665414.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665415.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665415.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665415.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665415.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665415.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665415.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665415.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665415.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665415.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665415.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665415.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665415.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665415.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665415.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97860] >[665415.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97860] width 1280 pitch 5120 (/4 1280) >[665415.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57904b0] >[665415.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57904b0] width 1280 pitch 5120 (/4 1280) >[665421.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b13f0] >[665421.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b13f0] width 1280 pitch 5120 (/4 1280) >[665421.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8a940] >[665421.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8a940] width 1280 pitch 5120 (/4 1280) >[665426.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665426.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665426.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac91e0] >[665426.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac91e0] width 1280 pitch 5120 (/4 1280) >[665432.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x572cff0] >[665432.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x572cff0] width 1280 pitch 5120 (/4 1280) >[665483.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x532f610] >[665483.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x532f610] width 1280 pitch 5120 (/4 1280) >[665483.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595a760] >[665483.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595a760] width 1280 pitch 5120 (/4 1280) >[665485.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abc7e0] >[665485.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abc7e0] width 1280 pitch 5120 (/4 1280) >[665485.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5720880] >[665485.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5720880] width 1280 pitch 5120 (/4 1280) >[665488.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665488.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665489.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5a50] >[665489.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5a50] width 1280 pitch 5120 (/4 1280) >[665489.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b854d0] >[665489.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b854d0] width 1280 pitch 5120 (/4 1280) >[665503.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6dde0] >[665503.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6dde0] width 1280 pitch 5120 (/4 1280) >[665590.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac5200] >[665590.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac5200] width 1280 pitch 5120 (/4 1280) >[665590.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac5200] >[665590.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac5200] width 1280 pitch 5120 (/4 1280) >[665659.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6e7d0] >[665659.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6e7d0] width 1280 pitch 5120 (/4 1280) >[665659.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a73600] >[665659.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a73600] width 1280 pitch 5120 (/4 1280) >[665721.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b9ca20] >[665721.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b9ca20] width 1280 pitch 5120 (/4 1280) >[665721.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b9a120] >[665721.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b9a120] width 1280 pitch 5120 (/4 1280) >[665887.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba5230] >[665887.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba5230] width 1280 pitch 5120 (/4 1280) >[665887.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[665887.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[665887.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665887.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665887.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[665887.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[665887.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665888.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665888.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[665888.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[665888.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665888.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665889.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[665889.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[665889.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665889.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665889.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35400] >[665889.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35400] width 1280 pitch 5120 (/4 1280) >[665889.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665889.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665889.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35400] >[665889.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35400] width 1280 pitch 5120 (/4 1280) >[665889.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240] >[665890.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1280 pitch 5120 (/4 1280) >[665890.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35400] >[665890.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35400] width 1280 pitch 5120 (/4 1280) >[665890.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[665890.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[665890.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba5230] >[665890.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba5230] width 1280 pitch 5120 (/4 1280) >[665890.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8e760] >[665890.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8e760] width 1280 pitch 5120 (/4 1280) >[665890.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8e760] >[665890.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8e760] width 1280 pitch 5120 (/4 1280) >[668948.334] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[668948.347] (II) RADEON(0): Printing DDC gathered Modelines: >[668948.347] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[694738.119] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[694738.128] (II) RADEON(0): Printing DDC gathered Modelines: >[694738.128] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[694740.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528cdc0] >[694740.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528cdc0] width 1280 pitch 5120 (/4 1280) >[694740.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694740.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694741.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6b770] >[694741.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6b770] width 1280 pitch 5120 (/4 1280) >[694741.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694741.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694741.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6b770] >[694742.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6b770] width 1280 pitch 5120 (/4 1280) >[694742.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694742.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694742.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6b770] >[694742.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6b770] width 1280 pitch 5120 (/4 1280) >[694743.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694743.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694743.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694743.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694743.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528cdc0] >[694743.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528cdc0] width 1280 pitch 5120 (/4 1280) >[694743.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b5bd70] >[694743.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b5bd70] width 1280 pitch 5120 (/4 1280) >[694743.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e8e70] >[694743.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e8e70] width 1280 pitch 5120 (/4 1280) >[694745.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac9970] >[694745.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac9970] width 1280 pitch 5120 (/4 1280) >[694745.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694745.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694745.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b434a0] >[694745.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b434a0] width 1280 pitch 5120 (/4 1280) >[694745.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694745.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694745.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b434a0] >[694745.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b434a0] width 1280 pitch 5120 (/4 1280) >[694745.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694745.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694746.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b434a0] >[694746.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b434a0] width 1280 pitch 5120 (/4 1280) >[694746.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694746.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694746.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b434a0] >[694746.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b434a0] width 1280 pitch 5120 (/4 1280) >[694746.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694747.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694747.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694747.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694747.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcafe0] >[694747.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcafe0] width 1280 pitch 5120 (/4 1280) >[694747.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b2a00] >[694747.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b2a00] width 1280 pitch 5120 (/4 1280) >[694747.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6b770] >[694747.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6b770] width 1280 pitch 5120 (/4 1280) >[694945.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8a00] >[694945.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8a00] width 1280 pitch 5120 (/4 1280) >[694945.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b44090] >[694945.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b44090] width 1280 pitch 5120 (/4 1280) >[694981.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b2fc0] >[694981.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b2fc0] width 1280 pitch 5120 (/4 1280) >[694981.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b17a30] >[694981.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b17a30] width 1280 pitch 5120 (/4 1280) >[694986.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b2fc0] >[694986.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b2fc0] width 1280 pitch 5120 (/4 1280) >[694986.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b45e0] >[694986.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b45e0] width 1280 pitch 5120 (/4 1280) >[694996.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f78f0] >[694996.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f78f0] width 1280 pitch 5120 (/4 1280) >[695994.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695994.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695994.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695994.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695994.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695994.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695994.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695994.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695994.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695994.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695994.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695994.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695994.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695995.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695995.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695995.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695995.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695995.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695995.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695995.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695995.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695996.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695996.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[695996.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[695996.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[695996.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[695996.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696046.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696046.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696048.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696048.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[696049.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[696049.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[696049.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[696049.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[696049.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[696049.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25e80] >[696049.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25e80] width 1280 pitch 5120 (/4 1280) >[696049.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba3950] >[696049.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba3950] width 1280 pitch 5120 (/4 1280) >[696049.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696049.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b60420] >[696049.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b60420] width 1280 pitch 5120 (/4 1280) >[696049.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba3950] >[696049.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba3950] width 1280 pitch 5120 (/4 1280) >[696049.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba3950] >[696049.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba3950] width 1280 pitch 5120 (/4 1280) >[696049.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b26080] >[696049.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b26080] width 1280 pitch 5120 (/4 1280) >[696049.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba3950] >[696049.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba3950] width 1280 pitch 5120 (/4 1280) >[696049.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94370] >[696049.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94370] width 1280 pitch 5120 (/4 1280) >[696052.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a942a0] >[696052.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a942a0] width 1280 pitch 5120 (/4 1280) >[696103.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c53190] >[696103.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c53190] width 1280 pitch 5120 (/4 1280) >[696103.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696103.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696103.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c53190] >[696103.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c53190] width 1280 pitch 5120 (/4 1280) >[696103.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696103.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696103.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c53190] >[696103.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c53190] width 1280 pitch 5120 (/4 1280) >[696103.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696103.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696103.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c53190] >[696103.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c53190] width 1280 pitch 5120 (/4 1280) >[696103.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696103.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696103.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c53190] >[696103.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c53190] width 1280 pitch 5120 (/4 1280) >[696103.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696103.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696105.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696105.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696105.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696105.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696105.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696106.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696106.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696106.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696106.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3c1a0] >[696106.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3c1a0] width 1280 pitch 5120 (/4 1280) >[696106.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54060] >[696106.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54060] width 1280 pitch 5120 (/4 1280) >[696106.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54060] >[696106.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54060] width 1280 pitch 5120 (/4 1280) >[696106.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54220] >[696106.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54220] width 1280 pitch 5120 (/4 1280) >[696106.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54260] >[696106.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54260] width 1280 pitch 5120 (/4 1280) >[696106.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54060] >[696106.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54060] width 1280 pitch 5120 (/4 1280) >[696106.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a54400] >[696106.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a54400] width 1280 pitch 5120 (/4 1280) >[696106.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0cf70] >[696106.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0cf70] width 1280 pitch 5120 (/4 1280) >[696106.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53ee0] >[696106.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53ee0] width 1280 pitch 5120 (/4 1280) >[696106.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b39a60] >[696106.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b39a60] width 1280 pitch 5120 (/4 1280) >[696106.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f20] >[696106.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f20] width 1280 pitch 5120 (/4 1280) >[696106.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f80] >[696106.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f80] width 1280 pitch 5120 (/4 1280) >[696106.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f20] >[696106.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f20] width 1280 pitch 5120 (/4 1280) >[696106.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f80] >[696106.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f80] width 1280 pitch 5120 (/4 1280) >[696106.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f20] >[696106.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f20] width 1280 pitch 5120 (/4 1280) >[696106.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f80] >[696106.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f80] width 1280 pitch 5120 (/4 1280) >[696106.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a53f20] >[696106.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a53f20] width 1280 pitch 5120 (/4 1280) >[696313.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c7990] >[696313.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c7990] width 1280 pitch 5120 (/4 1280) >[696313.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a94200] >[696313.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a94200] width 1280 pitch 5120 (/4 1280) >[696314.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5ed0] >[696314.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5ed0] width 1280 pitch 5120 (/4 1280) >[696314.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5ed0] >[696314.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5ed0] width 1280 pitch 5120 (/4 1280) >[696358.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba1d80] >[696358.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba1d80] width 1280 pitch 5120 (/4 1280) >[696358.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba1d80] >[696358.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba1d80] width 1280 pitch 5120 (/4 1280) >[696358.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba1d80] >[696358.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba1d80] width 1280 pitch 5120 (/4 1280) >[696358.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba1d80] >[696358.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba1d80] width 1280 pitch 5120 (/4 1280) >[696358.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3bef0] >[696358.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3bef0] width 1280 pitch 5120 (/4 1280) >[696358.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3bef0] >[696358.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3bef0] width 1280 pitch 5120 (/4 1280) >[696358.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba7590] >[696358.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba7590] width 1280 pitch 5120 (/4 1280) >[696358.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3bef0] >[696358.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3bef0] width 1280 pitch 5120 (/4 1280) >[696358.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c8240] >[696358.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c8240] width 1280 pitch 5120 (/4 1280) >[696359.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b032a0] >[696359.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b032a0] width 1280 pitch 5120 (/4 1280) >[696359.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696359.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696359.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696359.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe20] >[696359.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe20] width 1280 pitch 5120 (/4 1280) >[696368.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696368.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696368.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696368.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696368.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696368.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696368.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696368.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696368.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696368.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696368.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696368.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696368.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696369.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696369.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696369.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696369.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696369.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696369.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696369.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696369.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696369.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696369.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696369.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696369.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696369.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696369.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696369.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696369.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696370.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba75d0] >[696370.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba75d0] width 1280 pitch 5120 (/4 1280) >[696370.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5611ff0] >[696370.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5611ff0] width 1280 pitch 5120 (/4 1280) >[696371.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696372.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696372.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696372.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696372.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696373.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696373.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696373.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696373.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696373.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696373.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696373.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696373.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696373.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696373.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696373.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696373.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696373.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696373.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696373.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696374.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5874e10] >[696374.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5874e10] width 1280 pitch 5120 (/4 1280) >[696374.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696374.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696384.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b880] >[696384.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b880] width 1280 pitch 5120 (/4 1280) >[696391.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55efc80] >[696391.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55efc80] width 1280 pitch 5120 (/4 1280) >[696541.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5617840] >[696541.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5617840] width 1280 pitch 5120 (/4 1280) >[696548.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa2310] >[696548.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa2310] width 1280 pitch 5120 (/4 1280) >[696548.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5617840] >[696548.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5617840] width 1280 pitch 5120 (/4 1280) >[697083.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b07850] >[697083.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b07850] width 1280 pitch 5120 (/4 1280) >[697083.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b056f0] >[697083.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b056f0] width 1280 pitch 5120 (/4 1280) >[697083.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697083.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697083.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697083.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697083.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697084.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697084.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697084.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697084.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697085.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697085.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697085.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697085.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697086.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697086.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697086.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697086.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697086.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697086.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697086.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697086.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c010] >[697086.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c010] width 1280 pitch 5120 (/4 1280) >[697086.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697086.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697086.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697086.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697086.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697086.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697086.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697087.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697087.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697087.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697087.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697087.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697087.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697087.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697087.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697087.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697087.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697087.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697087.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697087.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697087.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697087.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697088.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697088.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697088.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697088.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697088.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697088.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697088.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697088.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697088.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697088.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697088.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697088.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697088.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697088.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697088.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697088.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697088.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697088.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697088.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697088.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697088.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697088.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697088.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697088.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697088.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697088.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697088.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697088.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697088.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697088.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697089.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697089.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697089.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697089.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[697089.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[697089.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697089.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697090.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697090.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697090.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697090.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697090.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697090.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697090.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697090.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697090.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697090.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697090.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697090.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697090.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697090.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697090.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697090.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697090.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c010] >[697090.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c010] width 1280 pitch 5120 (/4 1280) >[697090.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa35b0] >[697090.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa35b0] width 1280 pitch 5120 (/4 1280) >[697090.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[697090.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[697090.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5617ac0] >[697090.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5617ac0] width 1280 pitch 5120 (/4 1280) >[697090.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866e60] >[697090.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866e60] width 1280 pitch 5120 (/4 1280) >[697090.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697090.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697090.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697090.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697090.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[697090.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[697090.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[697090.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[697090.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697090.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697090.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a360] >[697090.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a360] width 1280 pitch 5120 (/4 1280) >[697090.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[697090.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[697090.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57614d0] >[697090.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57614d0] width 1280 pitch 5120 (/4 1280) >[697105.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697105.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697106.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697106.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697106.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697106.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697106.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697106.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697106.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697107.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697107.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697107.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697107.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697107.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697107.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697107.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697107.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697107.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697107.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697107.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697107.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697107.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697107.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697108.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697108.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697108.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697108.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697108.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697108.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697108.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697108.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697108.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697108.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697108.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697108.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697108.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697108.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697108.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697108.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5612e70] >[697108.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5612e70] width 1280 pitch 5120 (/4 1280) >[697108.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697108.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697108.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697108.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697108.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5612e70] >[697108.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5612e70] width 1280 pitch 5120 (/4 1280) >[697108.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697109.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697109.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697109.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab78a0] >[697109.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab78a0] width 1280 pitch 5120 (/4 1280) >[697110.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5612e70] >[697110.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5612e70] width 1280 pitch 5120 (/4 1280) >[697110.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b70690] >[697110.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b70690] width 1280 pitch 5120 (/4 1280) >[697110.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697110.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697110.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697110.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697110.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697110.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697110.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697110.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697110.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697110.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697110.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697110.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697110.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697110.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697110.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697110.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697111.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697111.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697111.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ab820] >[697111.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ab820] width 1280 pitch 5120 (/4 1280) >[697112.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bcac10] >[697112.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bcac10] width 1280 pitch 5120 (/4 1280) >[697112.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab76d0] >[697112.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab76d0] width 1280 pitch 5120 (/4 1280) >[697112.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b9fdc0] >[697112.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b9fdc0] width 1280 pitch 5120 (/4 1280) >[697112.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5801100] >[697112.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5801100] width 1280 pitch 5120 (/4 1280) >[697346.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c1c30] >[697346.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c1c30] width 1280 pitch 5120 (/4 1280) >[697346.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46c80] >[697346.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46c80] width 1280 pitch 5120 (/4 1280) >[697346.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae9090] >[697346.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae9090] width 1280 pitch 5120 (/4 1280) >[697346.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697346.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697346.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697346.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697346.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697346.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697346.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697346.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697346.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae9090] >[697346.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae9090] width 1280 pitch 5120 (/4 1280) >[697346.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46c80] >[697346.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46c80] width 1280 pitch 5120 (/4 1280) >[697346.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c1c30] >[697346.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c1c30] width 1280 pitch 5120 (/4 1280) >[697346.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a62db0] >[697346.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a62db0] width 1280 pitch 5120 (/4 1280) >[697346.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697346.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697346.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c1c30] >[697347.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c1c30] width 1280 pitch 5120 (/4 1280) >[697347.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46c80] >[697347.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46c80] width 1280 pitch 5120 (/4 1280) >[697347.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae9090] >[697347.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae9090] width 1280 pitch 5120 (/4 1280) >[697347.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c1c30] >[697347.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c1c30] width 1280 pitch 5120 (/4 1280) >[697347.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c3d90] >[697347.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c3d90] width 1280 pitch 5120 (/4 1280) >[697347.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697347.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697347.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c1c30] >[697347.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c1c30] width 1280 pitch 5120 (/4 1280) >[697347.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae9090] >[697347.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae9090] width 1280 pitch 5120 (/4 1280) >[697348.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46c80] >[697348.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46c80] width 1280 pitch 5120 (/4 1280) >[697348.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c3d90] >[697348.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c3d90] width 1280 pitch 5120 (/4 1280) >[697348.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4d7d0] >[697348.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4d7d0] width 1280 pitch 5120 (/4 1280) >[697348.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c3d90] >[697348.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c3d90] width 1280 pitch 5120 (/4 1280) >[697348.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5616890] >[697348.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5616890] width 1280 pitch 5120 (/4 1280) >[697349.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a4c0] >[697349.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a4c0] width 1280 pitch 5120 (/4 1280) >[697349.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5616890] >[697349.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5616890] width 1280 pitch 5120 (/4 1280) >[697349.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697349.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43a80] >[697349.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43a80] width 1280 pitch 5120 (/4 1280) >[697349.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697349.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697365.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46b50] >[697365.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46b50] width 1280 pitch 5120 (/4 1280) >[697368.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b43500] >[697368.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b43500] width 1280 pitch 5120 (/4 1280) >[697629.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aa34b0] >[697629.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aa34b0] width 1280 pitch 5120 (/4 1280) >[697629.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bff570] >[697629.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bff570] width 1280 pitch 5120 (/4 1280) >[697631.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bff0c0] >[697631.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bff0c0] width 1280 pitch 5120 (/4 1280) >[697852.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c01f20] >[697852.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c01f20] width 1280 pitch 5120 (/4 1280) >[697852.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c01f20] >[697852.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c01f20] width 1280 pitch 5120 (/4 1280) >[697856.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c08820] >[697856.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c08820] width 1280 pitch 5120 (/4 1280) >[697857.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c15240] >[697857.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c15240] width 1280 pitch 5120 (/4 1280) >[697875.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697875.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697875.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697875.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697875.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697875.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697875.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697876.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697876.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697876.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697876.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697876.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697876.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697876.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697876.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697876.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697876.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697876.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697876.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697876.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697876.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697876.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697876.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697877.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697877.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697877.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae560] >[697877.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae560] width 1280 pitch 5120 (/4 1280) >[697877.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b00] >[697877.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b00] width 1280 pitch 5120 (/4 1280) >[697877.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a403f0] >[697877.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a403f0] width 1280 pitch 5120 (/4 1280) >[697878.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04220] >[697878.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04220] width 1280 pitch 5120 (/4 1280) >[697878.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52260] >[697878.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52260] width 1280 pitch 5120 (/4 1280) >[697878.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f33e0] >[697878.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f33e0] width 1280 pitch 5120 (/4 1280) >[697878.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791610] >[697878.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791610] width 1280 pitch 5120 (/4 1280) >[697878.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697878.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697878.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791610] >[697878.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791610] width 1280 pitch 5120 (/4 1280) >[697878.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697878.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697878.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a40970] >[697878.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a40970] width 1280 pitch 5120 (/4 1280) >[697878.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f33e0] >[697878.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f33e0] width 1280 pitch 5120 (/4 1280) >[697878.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52260] >[697878.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52260] width 1280 pitch 5120 (/4 1280) >[697878.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b670] >[697878.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b670] width 1280 pitch 5120 (/4 1280) >[697878.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697878.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697878.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697878.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697879.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697879.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697879.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697879.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697879.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697879.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697879.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697879.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697879.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697879.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697879.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697879.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c84d0] >[697879.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c84d0] width 1280 pitch 5120 (/4 1280) >[697879.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bae660] >[697879.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bae660] width 1280 pitch 5120 (/4 1280) >[697879.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52260] >[697879.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52260] width 1280 pitch 5120 (/4 1280) >[697879.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f33e0] >[697879.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f33e0] width 1280 pitch 5120 (/4 1280) >[697879.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a40970] >[697879.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a40970] width 1280 pitch 5120 (/4 1280) >[697879.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5865f40] >[697879.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5865f40] width 1280 pitch 5120 (/4 1280) >[697879.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b670] >[697879.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b670] width 1280 pitch 5120 (/4 1280) >[697880.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5756cc0] >[697880.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5756cc0] width 1280 pitch 5120 (/4 1280) >[697880.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697880.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697880.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697880.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697880.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697880.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697880.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697880.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697880.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697882.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697882.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697882.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697882.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697882.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697882.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697882.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697882.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697882.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697882.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697882.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697883.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697883.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697883.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697883.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[697883.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[697883.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b020] >[697883.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b020] width 1280 pitch 5120 (/4 1280) >[697883.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x575f830] >[697883.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x575f830] width 1280 pitch 5120 (/4 1280) >[697883.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57a14e0] >[697883.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57a14e0] width 1280 pitch 5120 (/4 1280) >[697883.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697883.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697883.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697883.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697883.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697883.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697883.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697883.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697883.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697883.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697883.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697883.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697883.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697883.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697883.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8fc0] >[697883.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8fc0] width 1280 pitch 5120 (/4 1280) >[697883.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5753620] >[697883.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5753620] width 1280 pitch 5120 (/4 1280) >[697885.796] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[697885.797] (II) RADEON(0): Printing DDC gathered Modelines: >[697885.797] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[697885.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[697885.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[698623.279] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[698623.279] (II) RADEON(0): Printing DDC gathered Modelines: >[698623.279] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[698713.919] (II) RADEON(0): RADEONSaveScreen(2) >[698713.925] (II) RADEON(0): RADEONSaveScreen(0) >[708839.815] (II) RADEON(0): RADEONSaveScreen(1) >[708851.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f8f0] >[708851.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f8f0] width 1280 pitch 5120 (/4 1280) >[708854.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56169b0] >[708854.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56169b0] width 1280 pitch 5120 (/4 1280) >[708855.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5801680] >[708855.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5801680] width 1280 pitch 5120 (/4 1280) >[708855.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56169b0] >[708855.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56169b0] width 1280 pitch 5120 (/4 1280) >[708855.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5801680] >[708855.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5801680] width 1280 pitch 5120 (/4 1280) >[708856.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56169b0] >[708856.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56169b0] width 1280 pitch 5120 (/4 1280) >[708857.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5801680] >[708857.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5801680] width 1280 pitch 5120 (/4 1280) >[708857.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[708857.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[708857.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f8f0] >[708857.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f8f0] width 1280 pitch 5120 (/4 1280) >[708859.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[708859.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[708859.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947380] >[708859.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947380] width 1280 pitch 5120 (/4 1280) >[708859.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f8f0] >[708859.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f8f0] width 1280 pitch 5120 (/4 1280) >[708859.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[708860.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[708860.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f8f0] >[708860.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f8f0] width 1280 pitch 5120 (/4 1280) >[708861.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959970] >[708861.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959970] width 1280 pitch 5120 (/4 1280) >[708861.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f8f0] >[708861.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f8f0] width 1280 pitch 5120 (/4 1280) >[708861.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ee00] >[708862.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ee00] width 1280 pitch 5120 (/4 1280) >[708862.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56169b0] >[708862.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56169b0] width 1280 pitch 5120 (/4 1280) >[708862.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5801680] >[708862.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5801680] width 1280 pitch 5120 (/4 1280) >[708862.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56169b0] >[708862.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56169b0] width 1280 pitch 5120 (/4 1280) >[708862.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x567e3d0] >[708862.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x567e3d0] width 1280 pitch 5120 (/4 1280) >[708873.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5865f40] >[708873.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5865f40] width 1280 pitch 5120 (/4 1280) >[708940.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5797a00] >[708940.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5797a00] width 1280 pitch 5120 (/4 1280) >[708940.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708940.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708964.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708964.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708964.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708964.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708964.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708964.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708964.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708964.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708964.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708964.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708964.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708964.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708964.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708964.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708964.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708964.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708964.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708964.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708964.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[708964.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[708964.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b48ae0] >[708964.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b48ae0] width 1280 pitch 5120 (/4 1280) >[708964.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[708964.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[708964.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b48ae0] >[708964.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b48ae0] width 1280 pitch 5120 (/4 1280) >[708964.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708964.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708964.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708965.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708965.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708965.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708965.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708965.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708965.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708965.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708965.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[708965.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[708965.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708965.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708965.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[708966.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[708966.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708966.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708966.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[708966.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[708966.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708966.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708966.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[708966.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[708966.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708966.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708966.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[708966.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[708966.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5827830] >[708966.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5827830] width 1280 pitch 5120 (/4 1280) >[708989.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708989.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[708990.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708990.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708990.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[708990.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[708990.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708990.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708990.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[708990.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[708990.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55fd0] >[708990.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55fd0] width 1280 pitch 5120 (/4 1280) >[708990.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b48ae0] >[708990.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b48ae0] width 1280 pitch 5120 (/4 1280) >[708990.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b48ae0] >[708990.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b48ae0] width 1280 pitch 5120 (/4 1280) >[708990.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708990.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aabe90] >[708990.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aabe90] width 1280 pitch 5120 (/4 1280) >[708990.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[708990.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[708995.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[708995.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[709032.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57847b0] >[709032.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57847b0] width 1280 pitch 5120 (/4 1280) >[709144.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5784e10] >[709144.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5784e10] width 1280 pitch 5120 (/4 1280) >[709144.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591c5d0] >[709144.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591c5d0] width 1280 pitch 5120 (/4 1280) >[709144.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57afcc0] >[709144.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57afcc0] width 1280 pitch 5120 (/4 1280) >[709144.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5784e10] >[709144.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5784e10] width 1280 pitch 5120 (/4 1280) >[709210.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709210.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709210.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bafd0] >[709210.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bafd0] width 1280 pitch 5120 (/4 1280) >[709221.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709221.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709221.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709221.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709221.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709221.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709222.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709222.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709222.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709222.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709223.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709223.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709223.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709223.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709223.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709223.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709223.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709223.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709223.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709223.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709223.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709223.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709223.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709224.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709224.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709224.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709224.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709224.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709224.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709224.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709225.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709225.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709225.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709225.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709225.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709225.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709225.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709225.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709225.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709225.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709227.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709227.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709227.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709227.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709227.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709227.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709227.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709227.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709227.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709227.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709228.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709228.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709228.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709228.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709231.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709231.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709232.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7520] >[709232.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7520] width 1280 pitch 5120 (/4 1280) >[709232.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c02320] >[709232.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c02320] width 1280 pitch 5120 (/4 1280) >[709260.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5775e20] >[709260.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5775e20] width 1280 pitch 5120 (/4 1280) >[709260.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bb34a0] >[709260.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bb34a0] width 1280 pitch 5120 (/4 1280) >[709264.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c8a0] >[709264.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c8a0] width 1280 pitch 5120 (/4 1280) >[709264.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34360] >[709264.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34360] width 1280 pitch 5120 (/4 1280) >[709271.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709272.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709272.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709272.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709272.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709272.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709273.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709273.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709273.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709273.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709273.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709273.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709273.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709273.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709274.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709274.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709274.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709274.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709274.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709274.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709274.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709274.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709274.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709274.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709274.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709274.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709275.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709275.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709275.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709275.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709275.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709275.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709276.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709276.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709276.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709276.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709276.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709276.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709276.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[709276.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[709276.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709276.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709277.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709277.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709277.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c37c90] >[709277.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c37c90] width 1280 pitch 5120 (/4 1280) >[709277.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709277.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709277.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c37c90] >[709277.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c37c90] width 1280 pitch 5120 (/4 1280) >[709278.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709278.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709278.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709278.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709278.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4ddd0] >[709278.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4ddd0] width 1280 pitch 5120 (/4 1280) >[709278.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709278.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709278.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4ddd0] >[709278.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4ddd0] width 1280 pitch 5120 (/4 1280) >[709278.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709279.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709279.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aac190] >[709279.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aac190] width 1280 pitch 5120 (/4 1280) >[709279.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709279.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709279.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c52b00] >[709279.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c52b00] width 1280 pitch 5120 (/4 1280) >[709280.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c37c90] >[709280.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c37c90] width 1280 pitch 5120 (/4 1280) >[709280.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c52b00] >[709280.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c52b00] width 1280 pitch 5120 (/4 1280) >[709280.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709280.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709281.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709281.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709282.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709282.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709282.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c37c90] >[709282.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c37c90] width 1280 pitch 5120 (/4 1280) >[709282.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709282.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709282.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c37c90] >[709282.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c37c90] width 1280 pitch 5120 (/4 1280) >[709282.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c171a0] >[709282.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c171a0] width 1280 pitch 5120 (/4 1280) >[709319.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[709319.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[709319.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x574d3d0] >[709319.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x574d3d0] width 1280 pitch 5120 (/4 1280) >[709319.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[709319.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[709319.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709319.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709319.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709319.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709319.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709319.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709319.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709319.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709319.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709319.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709319.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709319.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709319.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709319.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709319.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709319.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709319.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709319.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709320.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586fa40] >[709320.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586fa40] width 1280 pitch 5120 (/4 1280) >[709320.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[709320.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[709320.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709320.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709320.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709320.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709320.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709320.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709320.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586fa40] >[709320.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586fa40] width 1280 pitch 5120 (/4 1280) >[709320.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586fa40] >[709320.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586fa40] width 1280 pitch 5120 (/4 1280) >[709320.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586fa40] >[709320.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586fa40] width 1280 pitch 5120 (/4 1280) >[709320.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ba40] >[709320.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ba40] width 1280 pitch 5120 (/4 1280) >[709320.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586fa40] >[709320.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586fa40] width 1280 pitch 5120 (/4 1280) >[709321.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709321.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709321.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577b610] >[709321.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577b610] width 1280 pitch 5120 (/4 1280) >[709321.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c7a0] >[709321.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c7a0] width 1280 pitch 5120 (/4 1280) >[709321.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709321.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709382.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c27440] >[709382.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c27440] width 1280 pitch 5120 (/4 1280) >[709383.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c271d0] >[709383.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c271d0] width 1280 pitch 5120 (/4 1280) >[709383.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c39a30] >[709383.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c39a30] width 1280 pitch 5120 (/4 1280) >[709383.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c271d0] >[709383.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c271d0] width 1280 pitch 5120 (/4 1280) >[709383.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c39a30] >[709383.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c39a30] width 1280 pitch 5120 (/4 1280) >[709384.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c39a30] >[709384.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c39a30] width 1280 pitch 5120 (/4 1280) >[709384.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c271d0] >[709384.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c271d0] width 1280 pitch 5120 (/4 1280) >[709384.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c270d0] >[709384.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c270d0] width 1280 pitch 5120 (/4 1280) >[709384.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c271d0] >[709384.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c271d0] width 1280 pitch 5120 (/4 1280) >[709384.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c39a30] >[709384.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c39a30] width 1280 pitch 5120 (/4 1280) >[709443.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c27440] >[709443.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c27440] width 1280 pitch 5120 (/4 1280) >[709443.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ba0400] >[709443.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ba0400] width 1280 pitch 5120 (/4 1280) >[709501.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac4730] >[709501.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac4730] width 1280 pitch 5120 (/4 1280) >[709501.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac4640] >[709501.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac4640] width 1280 pitch 5120 (/4 1280) >[709580.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709580.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709580.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709580.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709580.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709580.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709580.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709580.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709580.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709580.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709581.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709581.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709581.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709581.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709581.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709581.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709582.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709582.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709582.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc7760] >[709582.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc7760] width 1280 pitch 5120 (/4 1280) >[709582.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709582.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709582.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709582.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709583.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709583.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709583.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709583.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709584.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709584.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709585.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709585.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709585.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709585.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709585.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709586.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709588.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709588.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709588.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709588.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709589.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c07020] >[709589.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c07020] width 1280 pitch 5120 (/4 1280) >[709589.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709589.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709589.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c07020] >[709589.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c07020] width 1280 pitch 5120 (/4 1280) >[709589.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709589.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709589.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c07020] >[709589.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c07020] width 1280 pitch 5120 (/4 1280) >[709589.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709590.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709590.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709590.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709590.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709590.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709592.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc7760] >[709592.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc7760] width 1280 pitch 5120 (/4 1280) >[709593.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709593.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709593.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709593.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709593.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a9d030] >[709593.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a9d030] width 1280 pitch 5120 (/4 1280) >[709593.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5683200] >[709593.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5683200] width 1280 pitch 5120 (/4 1280) >[709709.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ca220] >[709709.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ca220] width 1280 pitch 5120 (/4 1280) >[709709.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bb3b90] >[709709.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bb3b90] width 1280 pitch 5120 (/4 1280) >[709720.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04db0] >[709720.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04db0] width 1280 pitch 5120 (/4 1280) >[709720.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709721.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709721.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04db0] >[709721.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04db0] width 1280 pitch 5120 (/4 1280) >[709721.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709721.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709721.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04db0] >[709721.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04db0] width 1280 pitch 5120 (/4 1280) >[709721.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709721.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709721.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04db0] >[709721.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04db0] width 1280 pitch 5120 (/4 1280) >[709722.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709722.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709722.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a521d0] >[709722.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a521d0] width 1280 pitch 5120 (/4 1280) >[709722.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52170] >[709722.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52170] width 1280 pitch 5120 (/4 1280) >[709722.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709722.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709722.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52170] >[709722.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52170] width 1280 pitch 5120 (/4 1280) >[709722.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709722.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709722.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52170] >[709722.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52170] width 1280 pitch 5120 (/4 1280) >[709722.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3250] >[709722.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3250] width 1280 pitch 5120 (/4 1280) >[709722.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b04e10] >[709722.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b04e10] width 1280 pitch 5120 (/4 1280) >[711181.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711181.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711206.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711206.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711206.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711206.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711206.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711207.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711207.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711207.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711207.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711207.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711207.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711207.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711207.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711207.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711243.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711243.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711243.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711243.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711243.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711243.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711243.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711244.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711244.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711244.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711244.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711244.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711244.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c00680] >[711244.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c00680] width 1280 pitch 5120 (/4 1280) >[711244.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711244.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711244.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711244.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711257.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711257.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711258.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711258.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711258.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711258.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711258.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711258.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711258.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711258.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711261.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711261.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711262.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d7fe0] >[711262.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d7fe0] width 1280 pitch 5120 (/4 1280) >[711262.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711262.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711263.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d7fe0] >[711263.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d7fe0] width 1280 pitch 5120 (/4 1280) >[711263.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711263.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711263.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d7fe0] >[711263.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d7fe0] width 1280 pitch 5120 (/4 1280) >[711263.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570c900] >[711263.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570c900] width 1280 pitch 5120 (/4 1280) >[711263.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711263.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711263.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5722bf0] >[711264.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5722bf0] width 1280 pitch 5120 (/4 1280) >[711264.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711264.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711264.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5722bf0] >[711264.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5722bf0] width 1280 pitch 5120 (/4 1280) >[711264.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2c430] >[711264.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2c430] width 1280 pitch 5120 (/4 1280) >[711296.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586f9c0] >[711296.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586f9c0] width 1280 pitch 5120 (/4 1280) >[711471.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571a8f0] >[711471.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571a8f0] width 1280 pitch 5120 (/4 1280) >[711471.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c9a240] >[711471.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c9a240] width 1280 pitch 5120 (/4 1280) >[711642.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d6b0] >[711642.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d6b0] width 1280 pitch 5120 (/4 1280) >[711643.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c46380] >[711643.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c46380] width 1280 pitch 5120 (/4 1280) >[711643.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d6b0] >[711643.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d6b0] width 1280 pitch 5120 (/4 1280) >[711643.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c46380] >[711643.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c46380] width 1280 pitch 5120 (/4 1280) >[711643.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d6b0] >[711643.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d6b0] width 1280 pitch 5120 (/4 1280) >[711644.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae8530] >[711644.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae8530] width 1280 pitch 5120 (/4 1280) >[711645.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c46380] >[711645.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c46380] width 1280 pitch 5120 (/4 1280) >[711645.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2f5c0] >[711645.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2f5c0] width 1280 pitch 5120 (/4 1280) >[711646.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d301d0] >[711646.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d301d0] width 1280 pitch 5120 (/4 1280) >[711646.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d3f9d0] >[711646.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d3f9d0] width 1280 pitch 5120 (/4 1280) >[711646.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2eda0] >[711646.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2eda0] width 1280 pitch 5120 (/4 1280) >[711646.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d3f720] >[711646.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d3f720] width 1280 pitch 5120 (/4 1280) >[711649.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711649.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711649.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711649.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711649.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711649.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711649.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711649.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711649.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711649.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711649.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711649.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711649.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711650.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711650.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711650.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711650.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711650.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711650.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711650.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711650.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d36850] >[711650.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d36850] width 1280 pitch 5120 (/4 1280) >[711650.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5daba30] >[711650.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5daba30] width 1280 pitch 5120 (/4 1280) >[711659.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f165d0] >[711659.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f165d0] width 1280 pitch 5120 (/4 1280) >[711659.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711659.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711659.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711659.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711659.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711659.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711659.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711659.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711659.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711660.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711660.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711660.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711660.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711660.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711660.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711660.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711660.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711660.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711660.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711660.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711660.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711660.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711660.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f172a0] >[711660.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f172a0] width 1280 pitch 5120 (/4 1280) >[711660.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0f180] >[711660.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0f180] width 1280 pitch 5120 (/4 1280) >[711663.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb8e80] >[711663.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb8e80] width 1280 pitch 5120 (/4 1280) >[711677.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5e270] >[711677.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5e270] width 1280 pitch 5120 (/4 1280) >[711677.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5e270] >[711677.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5e270] width 1280 pitch 5120 (/4 1280) >[711684.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f9fc0] >[711684.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f9fc0] width 1280 pitch 5120 (/4 1280) >[711684.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f9fc0] >[711684.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f9fc0] width 1280 pitch 5120 (/4 1280) >[711684.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3db90] >[711684.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3db90] width 1280 pitch 5120 (/4 1280) >[711688.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d790] >[711688.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d790] width 1280 pitch 5120 (/4 1280) >[711688.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711688.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711688.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d790] >[711688.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d790] width 1280 pitch 5120 (/4 1280) >[711688.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711688.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711688.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d790] >[711688.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d790] width 1280 pitch 5120 (/4 1280) >[711688.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711688.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711688.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c60520] >[711688.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c60520] width 1280 pitch 5120 (/4 1280) >[711688.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711688.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711688.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5d790] >[711688.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5d790] width 1280 pitch 5120 (/4 1280) >[711688.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c60520] >[711688.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c60520] width 1280 pitch 5120 (/4 1280) >[711688.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711688.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711688.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711688.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711688.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c60ab0] >[711688.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c60ab0] width 1280 pitch 5120 (/4 1280) >[711689.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c60ab0] >[711689.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c60ab0] width 1280 pitch 5120 (/4 1280) >[711689.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711689.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711689.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5dbc0] >[711689.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5dbc0] width 1280 pitch 5120 (/4 1280) >[711689.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711689.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711689.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711689.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711689.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711689.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711689.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5dbc0] >[711689.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5dbc0] width 1280 pitch 5120 (/4 1280) >[711689.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711689.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711689.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711689.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711689.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711689.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711689.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca4750] >[711689.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca4750] width 1280 pitch 5120 (/4 1280) >[711689.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5dbc0] >[711689.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5dbc0] width 1280 pitch 5120 (/4 1280) >[711689.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5a9c0] >[711689.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5a9c0] width 1280 pitch 5120 (/4 1280) >[711842.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5719840] >[711842.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5719840] width 1280 pitch 5120 (/4 1280) >[711843.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b4e620] >[711843.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b4e620] width 1280 pitch 5120 (/4 1280) >[711843.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb4070] >[711844.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb4070] width 1280 pitch 5120 (/4 1280) >[711844.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b62400] >[711844.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b62400] width 1280 pitch 5120 (/4 1280) >[711846.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a6f70] >[711846.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a6f70] width 1280 pitch 5120 (/4 1280) >[711846.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb4070] >[711846.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb4070] width 1280 pitch 5120 (/4 1280) >[711846.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x571ebc0] >[711846.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x571ebc0] width 1280 pitch 5120 (/4 1280) >[711846.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3db90] >[711846.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3db90] width 1280 pitch 5120 (/4 1280) >[711919.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570ee70] >[711919.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570ee70] width 1280 pitch 5120 (/4 1280) >[711919.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c46240] >[711919.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c46240] width 1280 pitch 5120 (/4 1280) >[711939.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711939.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca010] >[711940.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca010] width 1280 pitch 5120 (/4 1280) >[711940.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca010] >[711940.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca010] width 1280 pitch 5120 (/4 1280) >[711940.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711940.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711940.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711940.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711940.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711940.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711940.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711940.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711940.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711940.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711940.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711940.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711940.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711940.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711940.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711941.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711941.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711941.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711941.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711941.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711941.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711941.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711941.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711941.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711941.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711941.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711941.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711941.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711942.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711942.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711942.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711942.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711942.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711942.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711942.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711942.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711942.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711943.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711943.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711943.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711943.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18540] >[711943.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18540] width 1280 pitch 5120 (/4 1280) >[711943.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711943.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711943.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711943.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711943.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711943.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711945.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711945.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711945.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711945.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711945.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca1a0] >[711945.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca1a0] width 1280 pitch 5120 (/4 1280) >[711945.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca1a0] >[711945.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca1a0] width 1280 pitch 5120 (/4 1280) >[711945.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3ccd0] >[711945.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3ccd0] width 1280 pitch 5120 (/4 1280) >[711945.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca1a0] >[711945.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca1a0] width 1280 pitch 5120 (/4 1280) >[711945.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[711945.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[711945.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca1a0] >[711945.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca1a0] width 1280 pitch 5120 (/4 1280) >[711945.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711945.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aca1a0] >[711945.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aca1a0] width 1280 pitch 5120 (/4 1280) >[711945.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b31850] >[711945.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b31850] width 1280 pitch 5120 (/4 1280) >[711950.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfe40] >[711950.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfe40] width 1280 pitch 5120 (/4 1280) >[711956.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb73f0] >[711956.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb73f0] width 1280 pitch 5120 (/4 1280) >[711962.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb7d80] >[711962.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb7d80] width 1280 pitch 5120 (/4 1280) >[711962.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53d8480] >[711962.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53d8480] width 1280 pitch 5120 (/4 1280) >[712205.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bfb840] >[712205.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bfb840] width 1280 pitch 5120 (/4 1280) >[712211.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d52f40] >[712211.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d52f40] width 1280 pitch 5120 (/4 1280) >[712211.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b21d70] >[712211.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b21d70] width 1280 pitch 5120 (/4 1280) >[712313.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd9e60] >[712313.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd9e60] width 1280 pitch 5120 (/4 1280) >[712913.413] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[712913.413] (II) RADEON(0): Printing DDC gathered Modelines: >[712913.413] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[713003.925] (II) RADEON(0): RADEONSaveScreen(2) >[713003.986] (II) RADEON(0): RADEONSaveScreen(0) >[725855.946] (II) RADEON(0): RADEONSaveScreen(1) >[725867.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[725867.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[725867.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb59c0] >[725867.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb59c0] width 1280 pitch 5120 (/4 1280) >[725867.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[725867.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[725868.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e7430] >[725868.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e7430] width 1280 pitch 5120 (/4 1280) >[725868.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9ed0] >[725869.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9ed0] width 1280 pitch 5120 (/4 1280) >[725869.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725869.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725869.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab6540] >[725869.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab6540] width 1280 pitch 5120 (/4 1280) >[725869.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[725869.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[725869.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab6540] >[725869.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab6540] width 1280 pitch 5120 (/4 1280) >[725869.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725869.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725869.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725869.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725869.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725869.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725869.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725869.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725869.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725869.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725869.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725869.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725869.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725869.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725869.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725869.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725869.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725869.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725869.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725869.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725870.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[725870.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[725870.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a56480] >[725870.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a56480] width 1280 pitch 5120 (/4 1280) >[725870.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bdf130] >[725870.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bdf130] width 1280 pitch 5120 (/4 1280) >[725870.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a56480] >[725870.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a56480] width 1280 pitch 5120 (/4 1280) >[725870.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bdf130] >[725870.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bdf130] width 1280 pitch 5120 (/4 1280) >[725870.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[725870.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[725870.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[725870.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[725870.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[725870.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[725870.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[725870.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[725870.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725870.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725870.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be85a0] >[725870.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be85a0] width 1280 pitch 5120 (/4 1280) >[725871.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cafc0] >[725871.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cafc0] width 1280 pitch 5120 (/4 1280) >[725871.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725871.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725871.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725871.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725871.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725871.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725871.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725871.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725871.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725872.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725872.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725872.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725872.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725872.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725872.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725872.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725872.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725872.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725872.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725872.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725872.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725872.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725872.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725872.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725872.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[725872.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[725872.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4181540] >[725872.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4181540] width 1280 pitch 5120 (/4 1280) >[725874.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c790] >[725874.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c790] width 1280 pitch 5120 (/4 1280) >[725874.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9ed0] >[725874.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9ed0] width 1280 pitch 5120 (/4 1280) >[725874.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[725874.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[725875.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab6540] >[725875.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab6540] width 1280 pitch 5120 (/4 1280) >[725875.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[725875.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[725875.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab6540] >[725875.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab6540] width 1280 pitch 5120 (/4 1280) >[725875.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[725875.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[725876.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab6540] >[725876.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab6540] width 1280 pitch 5120 (/4 1280) >[725876.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9ed0] >[725876.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9ed0] width 1280 pitch 5120 (/4 1280) >[725876.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[725876.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[725876.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725876.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725877.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725877.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725877.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[725877.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[725877.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce0250] >[725877.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce0250] width 1280 pitch 5120 (/4 1280) >[725877.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725878.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725878.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f0b6c0] >[725878.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f0b6c0] width 1280 pitch 5120 (/4 1280) >[725878.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ae91e0] >[725878.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ae91e0] width 1280 pitch 5120 (/4 1280) >[725878.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x579fbf0] >[725878.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x579fbf0] width 1280 pitch 5120 (/4 1280) >[725946.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321a190] >[725946.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321a190] width 1280 pitch 5120 (/4 1280) >[725967.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d55c20] >[725967.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d55c20] width 1280 pitch 5120 (/4 1280) >[725967.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1a222e0] >[725967.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1a222e0] width 1280 pitch 5120 (/4 1280) >[726031.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d464e0] >[726031.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d464e0] width 1280 pitch 5120 (/4 1280) >[726031.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2fba0] >[726031.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2fba0] width 1280 pitch 5120 (/4 1280) >[726032.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d4a730] >[726032.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d4a730] width 1280 pitch 5120 (/4 1280) >[726032.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x570cda0] >[726032.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x570cda0] width 1280 pitch 5120 (/4 1280) >[726057.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584e710] >[726057.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584e710] width 1280 pitch 5120 (/4 1280) >[726057.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf5970] >[726057.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf5970] width 1280 pitch 5120 (/4 1280) >[726090.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d35490] >[726090.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d35490] width 1280 pitch 5120 (/4 1280) >[726091.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52b80] >[726091.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52b80] width 1280 pitch 5120 (/4 1280) >[726207.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5910] >[726207.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5910] width 1280 pitch 5120 (/4 1280) >[726207.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2770d80] >[726207.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2770d80] width 1280 pitch 5120 (/4 1280) >[726209.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2770d80] >[726209.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2770d80] width 1280 pitch 5120 (/4 1280) >[726222.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5830] >[726222.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5830] width 1280 pitch 5120 (/4 1280) >[726222.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726222.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726222.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5830] >[726222.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5830] width 1280 pitch 5120 (/4 1280) >[726222.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726222.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726222.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5830] >[726222.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5830] width 1280 pitch 5120 (/4 1280) >[726222.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726222.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726222.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5830] >[726222.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5830] width 1280 pitch 5120 (/4 1280) >[726222.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726222.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726222.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca5830] >[726222.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca5830] width 1280 pitch 5120 (/4 1280) >[726222.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726222.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726222.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726222.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726223.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726223.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726223.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726223.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726223.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726223.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726223.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdb170] >[726223.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdb170] width 1280 pitch 5120 (/4 1280) >[726223.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdfa50] >[726223.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdfa50] width 1280 pitch 5120 (/4 1280) >[726223.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59275d0] >[726223.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59275d0] width 1280 pitch 5120 (/4 1280) >[726223.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59275d0] >[726223.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59275d0] width 1280 pitch 5120 (/4 1280) >[726223.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[726223.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59275d0] >[726223.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59275d0] width 1280 pitch 5120 (/4 1280) >[726223.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d54dd0] >[726223.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d54dd0] width 1280 pitch 5120 (/4 1280) >[727176.130] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[727176.130] (II) RADEON(0): Printing DDC gathered Modelines: >[727176.130] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[727207.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bd4b10] >[727207.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bd4b10] width 1280 pitch 5120 (/4 1280) >[727493.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf0b10] >[727493.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf0b10] width 1280 pitch 5120 (/4 1280) >[727493.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cae1e0] >[727493.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cae1e0] width 1280 pitch 5120 (/4 1280) >[727499.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5de20] >[727499.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5de20] width 1280 pitch 5120 (/4 1280) >[727531.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cbd4f0] >[727531.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cbd4f0] width 1280 pitch 5120 (/4 1280) >[727531.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d591e0] >[727531.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d591e0] width 1280 pitch 5120 (/4 1280) >[727531.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d59220] >[727531.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d59220] width 1280 pitch 5120 (/4 1280) >[727531.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d591e0] >[727531.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d591e0] width 1280 pitch 5120 (/4 1280) >[727555.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e2e720] >[727555.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e2e720] width 1280 pitch 5120 (/4 1280) >[727589.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[727589.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[727770.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06960] >[727770.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06960] width 1280 pitch 5120 (/4 1280) >[727770.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[727770.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[727776.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[727776.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[727776.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[727776.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[727776.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[727776.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[727776.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[727776.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[727778.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[727778.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[727778.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e2e310] >[727778.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e2e310] width 1280 pitch 5120 (/4 1280) >[727778.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e6990] >[727778.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e6990] width 1280 pitch 5120 (/4 1280) >[727778.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97790] >[727778.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97790] width 1280 pitch 5120 (/4 1280) >[727778.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e6990] >[727778.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e6990] width 1280 pitch 5120 (/4 1280) >[727783.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5c3a0] >[727783.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5c3a0] width 1280 pitch 5120 (/4 1280) >[727783.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8c930] >[727783.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8c930] width 1280 pitch 5120 (/4 1280) >[727786.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b8c930] >[727786.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b8c930] width 1280 pitch 5120 (/4 1280) >[727971.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb9200] >[727971.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb9200] width 1280 pitch 5120 (/4 1280) >[727971.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb9200] >[727971.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb9200] width 1280 pitch 5120 (/4 1280) >[728032.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e257b0] >[728032.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e257b0] width 1280 pitch 5120 (/4 1280) >[728032.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb0890] >[728032.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb0890] width 1280 pitch 5120 (/4 1280) >[728101.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e02e60] >[728101.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e02e60] width 1280 pitch 5120 (/4 1280) >[728101.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f26810] >[728101.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f26810] width 1280 pitch 5120 (/4 1280) >[728169.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e044c0] >[728169.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e044c0] width 1280 pitch 5120 (/4 1280) >[728169.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f26bc0] >[728169.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f26bc0] width 1280 pitch 5120 (/4 1280) >[728174.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d410] >[728174.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d410] width 1280 pitch 5120 (/4 1280) >[728174.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04d00] >[728174.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04d00] width 1280 pitch 5120 (/4 1280) >[728239.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da8160] >[728239.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da8160] width 1280 pitch 5120 (/4 1280) >[728239.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e24730] >[728239.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e24730] width 1280 pitch 5120 (/4 1280) >[728844.648] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[728844.648] (II) RADEON(0): Printing DDC gathered Modelines: >[728844.648] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[728934.899] (II) RADEON(0): RADEONSaveScreen(2) >[728934.899] (II) RADEON(0): RADEONSaveScreen(0) >[731476.034] (II) RADEON(0): RADEONSaveScreen(1) >[731481.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731481.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731481.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da4160] >[731481.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da4160] width 1280 pitch 5120 (/4 1280) >[731481.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731481.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731481.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da4160] >[731481.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da4160] width 1280 pitch 5120 (/4 1280) >[731481.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731481.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731481.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da4160] >[731481.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da4160] width 1280 pitch 5120 (/4 1280) >[731481.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731481.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731481.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da4160] >[731481.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da4160] width 1280 pitch 5120 (/4 1280) >[731481.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731481.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d908a0] >[731483.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d908a0] width 1280 pitch 5120 (/4 1280) >[731483.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d908a0] >[731483.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d908a0] width 1280 pitch 5120 (/4 1280) >[731483.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d908a0] >[731483.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d908a0] width 1280 pitch 5120 (/4 1280) >[731483.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d908a0] >[731483.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d908a0] width 1280 pitch 5120 (/4 1280) >[731483.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731483.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d908a0] >[731483.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d908a0] width 1280 pitch 5120 (/4 1280) >[731483.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731483.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731491.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731491.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731491.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731491.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731491.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731491.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731491.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731491.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731491.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731491.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731491.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731491.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731491.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731491.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c510] >[731492.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c510] width 1280 pitch 5120 (/4 1280) >[731492.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c510] >[731492.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c510] width 1280 pitch 5120 (/4 1280) >[731492.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c510] >[731492.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c510] width 1280 pitch 5120 (/4 1280) >[731492.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da78e0] >[731492.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da78e0] width 1280 pitch 5120 (/4 1280) >[731492.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cddaa0] >[731492.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cddaa0] width 1280 pitch 5120 (/4 1280) >[731492.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdbba0] >[731492.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdbba0] width 1280 pitch 5120 (/4 1280) >[731492.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da4ba0] >[731492.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da4ba0] width 1280 pitch 5120 (/4 1280) >[731492.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d96080] >[731492.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d96080] width 1280 pitch 5120 (/4 1280) >[731496.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da3f20] >[731496.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da3f20] width 1280 pitch 5120 (/4 1280) >[731636.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e221d0] >[731636.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e221d0] width 1280 pitch 5120 (/4 1280) >[732312.923] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[732312.923] (II) RADEON(0): Printing DDC gathered Modelines: >[732312.923] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[732402.887] (II) RADEON(0): RADEONSaveScreen(2) >[732402.888] (II) RADEON(0): RADEONSaveScreen(0) >[736960.866] (II) RADEON(0): RADEONSaveScreen(1) >[736966.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04500] >[736966.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04500] width 1280 pitch 5120 (/4 1280) >[736974.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736974.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736974.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d91a20] >[736974.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d91a20] width 1280 pitch 5120 (/4 1280) >[736974.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdd500] >[736974.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdd500] width 1280 pitch 5120 (/4 1280) >[736974.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736974.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736974.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdd500] >[736974.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdd500] width 1280 pitch 5120 (/4 1280) >[736974.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736974.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736974.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdd500] >[736974.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdd500] width 1280 pitch 5120 (/4 1280) >[736974.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680] >[736974.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1280 pitch 5120 (/4 1280) >[736975.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d91a20] >[736975.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d91a20] width 1280 pitch 5120 (/4 1280) >[736975.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736975.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736975.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d91a20] >[736975.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d91a20] width 1280 pitch 5120 (/4 1280) >[736975.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d91a20] >[736975.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d91a20] width 1280 pitch 5120 (/4 1280) >[736975.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680] >[736975.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1280 pitch 5120 (/4 1280) >[736975.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d91a20] >[736975.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d91a20] width 1280 pitch 5120 (/4 1280) >[736975.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680] >[736975.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1280 pitch 5120 (/4 1280) >[736975.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736975.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736975.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736975.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736976.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736976.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736976.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736976.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736976.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736976.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736976.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736976.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736976.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736976.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736976.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736976.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0d390] >[736976.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0d390] width 1280 pitch 5120 (/4 1280) >[736976.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e13c60] >[736976.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e13c60] width 1280 pitch 5120 (/4 1280) >[736976.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680] >[736976.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1280 pitch 5120 (/4 1280) >[736977.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d8dd80] >[736977.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d8dd80] width 1280 pitch 5120 (/4 1280) >[737024.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdd9c0] >[737025.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdd9c0] width 1280 pitch 5120 (/4 1280) >[737025.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f20db0] >[737025.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f20db0] width 1280 pitch 5120 (/4 1280) >[737180.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e11130] >[737180.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e11130] width 1280 pitch 5120 (/4 1280) >[737180.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e01ab0] >[737180.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e01ab0] width 1280 pitch 5120 (/4 1280) >[737215.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5763910] >[737215.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5763910] width 1280 pitch 5120 (/4 1280) >[737215.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cce5f0] >[737215.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cce5f0] width 1280 pitch 5120 (/4 1280) >[737228.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d97460] >[737228.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d97460] width 1280 pitch 5120 (/4 1280) >[737228.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e15c90] >[737228.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e15c90] width 1280 pitch 5120 (/4 1280) >[737232.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d97460] >[737232.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d97460] width 1280 pitch 5120 (/4 1280) >[737313.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e15590] >[737313.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e15590] width 1280 pitch 5120 (/4 1280) >[737313.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e0f000] >[737313.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e0f000] width 1280 pitch 5120 (/4 1280) >[737429.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e01ab0] >[737429.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e01ab0] width 1280 pitch 5120 (/4 1280) >[737429.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e16c80] >[737429.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e16c80] width 1280 pitch 5120 (/4 1280) >[737532.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da1420] >[737532.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da1420] width 1280 pitch 5120 (/4 1280) >[737532.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d80970] >[737532.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d80970] width 1280 pitch 5120 (/4 1280) >[737684.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d81580] >[737684.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d81580] width 1280 pitch 5120 (/4 1280) >[737684.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e50e80] >[737684.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e50e80] width 1280 pitch 5120 (/4 1280) >[737830.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d81b40] >[737830.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d81b40] width 1280 pitch 5120 (/4 1280) >[737831.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d327c0] >[737831.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d327c0] width 1280 pitch 5120 (/4 1280) >[737864.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e1df10] >[737864.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e1df10] width 1280 pitch 5120 (/4 1280) >[737887.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cce970] >[737887.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cce970] width 1280 pitch 5120 (/4 1280) >[737894.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d8f290] >[737894.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d8f290] width 1280 pitch 5120 (/4 1280) >[737977.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c60360] >[737977.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c60360] width 1280 pitch 5120 (/4 1280) >[737977.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d9c020] >[737978.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d9c020] width 1280 pitch 5120 (/4 1280) >[737981.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d8d120] >[737981.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d8d120] width 1280 pitch 5120 (/4 1280) >[737981.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d8d120] >[737981.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d8d120] width 1280 pitch 5120 (/4 1280) >[738221.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b2aa0] >[738221.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b2aa0] width 1280 pitch 5120 (/4 1280) >[738262.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dfeeb0] >[738262.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dfeeb0] width 1280 pitch 5120 (/4 1280) >[738262.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff190] >[738262.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff190] width 1280 pitch 5120 (/4 1280) >[738268.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738268.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e97970] >[738268.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e97970] width 1280 pitch 5120 (/4 1280) >[738268.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01bc0] >[738268.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01bc0] width 1280 pitch 5120 (/4 1280) >[738278.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff0b0] >[738278.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff0b0] width 1280 pitch 5120 (/4 1280) >[738278.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738278.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01c90] >[738278.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01c90] width 1280 pitch 5120 (/4 1280) >[738282.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff110] >[738282.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff110] width 1280 pitch 5120 (/4 1280) >[738287.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d89990] >[738287.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d89990] width 1280 pitch 5120 (/4 1280) >[738287.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f03f80] >[738287.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f03f80] width 1280 pitch 5120 (/4 1280) >[738288.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da1290] >[738288.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da1290] width 1280 pitch 5120 (/4 1280) >[738288.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff300] >[738288.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff300] width 1280 pitch 5120 (/4 1280) >[738300.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eff300] >[738300.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eff300] width 1280 pitch 5120 (/4 1280) >[738300.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f01df0] >[738300.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f01df0] width 1280 pitch 5120 (/4 1280) >[738407.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f03f80] >[738407.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f03f80] width 1280 pitch 5120 (/4 1280) >[738407.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c62c60] >[738407.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c62c60] width 1280 pitch 5120 (/4 1280) >[738630.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da61d0] >[738630.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da61d0] width 1280 pitch 5120 (/4 1280) >[738630.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d83bb0] >[738630.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d83bb0] width 1280 pitch 5120 (/4 1280) >[738655.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd2a50] >[738655.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd2a50] width 1280 pitch 5120 (/4 1280) >[738655.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a9e00] >[738655.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a9e00] width 1280 pitch 5120 (/4 1280) >[738777.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f09150] >[738777.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f09150] width 1280 pitch 5120 (/4 1280) >[738803.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e96e50] >[738803.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e96e50] width 1280 pitch 5120 (/4 1280) >[738803.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e67740] >[738803.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e67740] width 1280 pitch 5120 (/4 1280) >[738847.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e69230] >[738847.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e69230] width 1280 pitch 5120 (/4 1280) >[738847.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9d3f0] >[738847.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9d3f0] width 1280 pitch 5120 (/4 1280) >[738853.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2a850] >[738853.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2a850] width 1280 pitch 5120 (/4 1280) >[739070.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc0bd0] >[739070.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc0bd0] width 1280 pitch 5120 (/4 1280) >[739070.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2910] >[739070.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2910] width 1280 pitch 5120 (/4 1280) >[739815.440] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[739815.440] (II) RADEON(0): Printing DDC gathered Modelines: >[739815.440] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[739904.913] (II) RADEON(0): RADEONSaveScreen(2) >[739904.917] (II) RADEON(0): RADEONSaveScreen(0) >[740081.085] (II) RADEON(0): RADEONSaveScreen(1) >[740105.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc5110] >[740105.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc5110] width 1280 pitch 5120 (/4 1280) >[740106.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0c470] >[740106.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0c470] width 1280 pitch 5120 (/4 1280) >[740106.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0c470] >[740106.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0c470] width 1280 pitch 5120 (/4 1280) >[740108.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0c470] >[740108.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0c470] width 1280 pitch 5120 (/4 1280) >[740108.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5997670] >[740108.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5997670] width 1280 pitch 5120 (/4 1280) >[740126.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595fa70] >[740127.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595fa70] width 1280 pitch 5120 (/4 1280) >[740161.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc5110] >[740162.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc5110] width 1280 pitch 5120 (/4 1280) >[740179.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f17cf0] >[740179.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f17cf0] width 1280 pitch 5120 (/4 1280) >[740179.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc58d0] >[740179.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc58d0] width 1280 pitch 5120 (/4 1280) >[740179.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740179.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740179.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc58d0] >[740179.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc58d0] width 1280 pitch 5120 (/4 1280) >[740179.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740179.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740179.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc58d0] >[740179.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc58d0] width 1280 pitch 5120 (/4 1280) >[740179.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740179.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740179.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2570] >[740179.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2570] width 1280 pitch 5120 (/4 1280) >[740179.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740180.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740180.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2570] >[740180.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2570] width 1280 pitch 5120 (/4 1280) >[740180.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740180.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740180.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2570] >[740180.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2570] width 1280 pitch 5120 (/4 1280) >[740180.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c49920] >[740180.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c49920] width 1280 pitch 5120 (/4 1280) >[740180.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2570] >[740180.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2570] width 1280 pitch 5120 (/4 1280) >[740180.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f09570] >[740180.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f09570] width 1280 pitch 5120 (/4 1280) >[740180.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cccc60] >[740180.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cccc60] width 1280 pitch 5120 (/4 1280) >[740180.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04c20] >[740180.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04c20] width 1280 pitch 5120 (/4 1280) >[740180.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cccc60] >[740180.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cccc60] width 1280 pitch 5120 (/4 1280) >[740180.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04c20] >[740180.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04c20] width 1280 pitch 5120 (/4 1280) >[740180.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cccc60] >[740180.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cccc60] width 1280 pitch 5120 (/4 1280) >[740180.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04c20] >[740180.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04c20] width 1280 pitch 5120 (/4 1280) >[740180.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cccc60] >[740180.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cccc60] width 1280 pitch 5120 (/4 1280) >[740180.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e04c20] >[740180.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e04c20] width 1280 pitch 5120 (/4 1280) >[740180.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cccc60] >[740180.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cccc60] width 1280 pitch 5120 (/4 1280) >[740180.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2f5c0] >[740180.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2f5c0] width 1280 pitch 5120 (/4 1280) >[740181.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb3150] >[740181.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb3150] width 1280 pitch 5120 (/4 1280) >[740181.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595fa70] >[740181.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595fa70] width 1280 pitch 5120 (/4 1280) >[740182.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb3150] >[740183.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb3150] width 1280 pitch 5120 (/4 1280) >[740184.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595fa70] >[740184.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595fa70] width 1280 pitch 5120 (/4 1280) >[740184.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb3150] >[740184.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb3150] width 1280 pitch 5120 (/4 1280) >[740185.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c5dbc0] >[740185.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c5dbc0] width 1280 pitch 5120 (/4 1280) >[740185.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5980] >[740185.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5980] width 1280 pitch 5120 (/4 1280) >[740186.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[740186.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[740188.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[740188.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[740188.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[740188.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[740188.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[740188.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[740188.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[740188.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[740188.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[740188.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[740189.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[740189.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[740189.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cdffc0] >[740189.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cdffc0] width 1280 pitch 5120 (/4 1280) >[740189.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b05430] >[740190.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b05430] width 1280 pitch 5120 (/4 1280) >[740191.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb59c0] >[740191.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb59c0] width 1280 pitch 5120 (/4 1280) >[740191.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d53b80] >[740191.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d53b80] width 1280 pitch 5120 (/4 1280) >[740191.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb21e0] >[740191.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb21e0] width 1280 pitch 5120 (/4 1280) >[740191.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280df90] >[740191.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280df90] width 1280 pitch 5120 (/4 1280) >[740195.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aef10] >[740195.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aef10] width 1280 pitch 5120 (/4 1280) >[740195.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[740195.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[740195.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24aef10] >[740195.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24aef10] width 1280 pitch 5120 (/4 1280) >[740195.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[740195.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[740195.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a578e0] >[740195.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a578e0] width 1280 pitch 5120 (/4 1280) >[740196.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[740196.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[740196.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a578e0] >[740196.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a578e0] width 1280 pitch 5120 (/4 1280) >[740196.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c85ab0] >[740196.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c85ab0] width 1280 pitch 5120 (/4 1280) >[740197.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a578e0] >[740197.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a578e0] width 1280 pitch 5120 (/4 1280) >[740197.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5364a20] >[740197.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5364a20] width 1280 pitch 5120 (/4 1280) >[740197.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bfaa00] >[740197.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bfaa00] width 1280 pitch 5120 (/4 1280) >[740197.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb59c0] >[740197.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb59c0] width 1280 pitch 5120 (/4 1280) >[740197.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bfaa00] >[740197.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bfaa00] width 1280 pitch 5120 (/4 1280) >[740197.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb59c0] >[740197.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb59c0] width 1280 pitch 5120 (/4 1280) >[740197.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bfaa00] >[740197.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bfaa00] width 1280 pitch 5120 (/4 1280) >[740206.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6b500] >[740206.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6b500] width 1280 pitch 5120 (/4 1280) >[740223.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e44510] >[740223.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e44510] width 1280 pitch 5120 (/4 1280) >[740225.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc58d0] >[740225.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc58d0] width 1280 pitch 5120 (/4 1280) >[740226.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4da70] >[740226.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4da70] width 1280 pitch 5120 (/4 1280) >[740278.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6dff0] >[740278.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6dff0] width 1280 pitch 5120 (/4 1280) >[740278.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f8c80] >[740278.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f8c80] width 1280 pitch 5120 (/4 1280) >[740310.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da5550] >[740310.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da5550] width 1280 pitch 5120 (/4 1280) >[740310.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6dff0] >[740310.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6dff0] width 1280 pitch 5120 (/4 1280) >[740400.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef6d90] >[740400.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef6d90] width 1280 pitch 5120 (/4 1280) >[740483.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6d850] >[740483.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6d850] width 1280 pitch 5120 (/4 1280) >[740483.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d751a0] >[740483.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d751a0] width 1280 pitch 5120 (/4 1280) >[740484.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6d850] >[740484.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6d850] width 1280 pitch 5120 (/4 1280) >[740484.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d751a0] >[740484.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d751a0] width 1280 pitch 5120 (/4 1280) >[740486.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6d850] >[740486.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6d850] width 1280 pitch 5120 (/4 1280) >[740486.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6d850] >[740486.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6d850] width 1280 pitch 5120 (/4 1280) >[740550.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efe320] >[740550.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efe320] width 1280 pitch 5120 (/4 1280) >[740551.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef73f0] >[740551.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef73f0] width 1280 pitch 5120 (/4 1280) >[740561.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6b820] >[740561.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6b820] width 1280 pitch 5120 (/4 1280) >[740585.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db2cc0] >[740585.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db2cc0] width 1280 pitch 5120 (/4 1280) >[740585.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[740585.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[740585.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e460f0] >[740585.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e460f0] width 1280 pitch 5120 (/4 1280) >[740586.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e460f0] >[740586.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e460f0] width 1280 pitch 5120 (/4 1280) >[740586.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db0830] >[740586.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db0830] width 1280 pitch 5120 (/4 1280) >[740640.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db2cc0] >[740640.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db2cc0] width 1280 pitch 5120 (/4 1280) >[740640.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6c7c0] >[740640.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6c7c0] width 1280 pitch 5120 (/4 1280) >[740640.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccc5e0] >[740640.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccc5e0] width 1280 pitch 5120 (/4 1280) >[740640.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db0830] >[740640.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db0830] width 1280 pitch 5120 (/4 1280) >[740641.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559d2b0] >[740641.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559d2b0] width 1280 pitch 5120 (/4 1280) >[740641.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c66440] >[740641.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c66440] width 1280 pitch 5120 (/4 1280) >[740642.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db2cc0] >[740642.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db2cc0] width 1280 pitch 5120 (/4 1280) >[740648.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740648.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740648.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef73f0] >[740648.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef73f0] width 1280 pitch 5120 (/4 1280) >[740649.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4c900] >[740649.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4c900] width 1280 pitch 5120 (/4 1280) >[740649.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4cca0] >[740649.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4cca0] width 1280 pitch 5120 (/4 1280) >[740649.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740649.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740649.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6660] >[740649.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6660] width 1280 pitch 5120 (/4 1280) >[740651.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740651.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740652.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740652.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740652.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dae880] >[740652.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dae880] width 1280 pitch 5120 (/4 1280) >[740652.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740652.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740652.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db0830] >[740652.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db0830] width 1280 pitch 5120 (/4 1280) >[740652.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db0830] >[740652.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db0830] width 1280 pitch 5120 (/4 1280) >[740700.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740700.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740701.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[740701.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[740701.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef6800] >[740701.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef6800] width 1280 pitch 5120 (/4 1280) >[740702.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef6800] >[740702.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef6800] width 1280 pitch 5120 (/4 1280) >[740702.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b18110] >[740702.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b18110] width 1280 pitch 5120 (/4 1280) >[740702.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4ca70] >[740702.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4ca70] width 1280 pitch 5120 (/4 1280) >[740714.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4beb0] >[740714.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4beb0] width 1280 pitch 5120 (/4 1280) >[740714.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6660] >[740714.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6660] width 1280 pitch 5120 (/4 1280) >[740715.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4c950] >[740715.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4c950] width 1280 pitch 5120 (/4 1280) >[740716.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740716.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740716.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740716.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740716.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4beb0] >[740716.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4beb0] width 1280 pitch 5120 (/4 1280) >[740719.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e53c80] >[740719.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e53c80] width 1280 pitch 5120 (/4 1280) >[740720.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55cb060] >[740720.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55cb060] width 1280 pitch 5120 (/4 1280) >[740720.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e2b90] >[740720.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e2b90] width 1280 pitch 5120 (/4 1280) >[740720.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740720.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740731.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4beb0] >[740731.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4beb0] width 1280 pitch 5120 (/4 1280) >[740731.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740731.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740732.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e446f0] >[740732.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e446f0] width 1280 pitch 5120 (/4 1280) >[740732.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6a8d0] >[740732.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6a8d0] width 1280 pitch 5120 (/4 1280) >[740773.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x447be20] >[740773.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x447be20] width 1280 pitch 5120 (/4 1280) >[740773.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e53c80] >[740773.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e53c80] width 1280 pitch 5120 (/4 1280) >[740802.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c4f810] >[740802.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c4f810] width 1280 pitch 5120 (/4 1280) >[740802.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4beb0] >[740802.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4beb0] width 1280 pitch 5120 (/4 1280) >[740895.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df4e00] >[740895.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df4e00] width 1280 pitch 5120 (/4 1280) >[740895.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6a8d0] >[740895.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6a8d0] width 1280 pitch 5120 (/4 1280) >[740900.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eadf10] >[740900.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eadf10] width 1280 pitch 5120 (/4 1280) >[740900.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c4f810] >[740900.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c4f810] width 1280 pitch 5120 (/4 1280) >[740904.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[740904.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[740904.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c4f810] >[740904.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c4f810] width 1280 pitch 5120 (/4 1280) >[741006.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741006.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741006.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6fe20] >[741006.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6fe20] width 1280 pitch 5120 (/4 1280) >[741034.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6fe20] >[741034.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6fe20] width 1280 pitch 5120 (/4 1280) >[741034.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[741034.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[741040.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741040.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741040.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d72130] >[741040.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d72130] width 1280 pitch 5120 (/4 1280) >[741040.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a000] >[741040.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a000] width 1280 pitch 5120 (/4 1280) >[741040.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741040.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741041.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d72130] >[741041.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d72130] width 1280 pitch 5120 (/4 1280) >[741041.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5557a60] >[741041.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5557a60] width 1280 pitch 5120 (/4 1280) >[741042.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a000] >[741042.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a000] width 1280 pitch 5120 (/4 1280) >[741042.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741042.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741042.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741042.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741042.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d70060] >[741042.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d70060] width 1280 pitch 5120 (/4 1280) >[741043.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741043.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741043.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741043.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741044.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d70060] >[741044.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d70060] width 1280 pitch 5120 (/4 1280) >[741044.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741044.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741062.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e617d0] >[741062.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e617d0] width 1280 pitch 5120 (/4 1280) >[741062.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a000] >[741062.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a000] width 1280 pitch 5120 (/4 1280) >[741070.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741070.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741070.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d70060] >[741070.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d70060] width 1280 pitch 5120 (/4 1280) >[741083.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6b930] >[741083.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6b930] width 1280 pitch 5120 (/4 1280) >[741083.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741083.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741085.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741085.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741085.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741085.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741100.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc5f0] >[741100.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc5f0] width 1280 pitch 5120 (/4 1280) >[741100.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741100.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741101.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741101.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741101.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e604d0] >[741101.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e604d0] width 1280 pitch 5120 (/4 1280) >[741182.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741182.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741182.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e58fa0] >[741182.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e58fa0] width 1280 pitch 5120 (/4 1280) >[741237.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e5efe0] >[741237.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e5efe0] width 1280 pitch 5120 (/4 1280) >[741238.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6e3c0] >[741238.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6e3c0] width 1280 pitch 5120 (/4 1280) >[741238.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[741238.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[741238.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e58fa0] >[741238.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e58fa0] width 1280 pitch 5120 (/4 1280) >[741239.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6b930] >[741239.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6b930] width 1280 pitch 5120 (/4 1280) >[741239.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef5520] >[741239.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef5520] width 1280 pitch 5120 (/4 1280) >[741239.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e604d0] >[741239.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e604d0] width 1280 pitch 5120 (/4 1280) >[741240.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6b930] >[741240.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6b930] width 1280 pitch 5120 (/4 1280) >[741240.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741240.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741240.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef5520] >[741240.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef5520] width 1280 pitch 5120 (/4 1280) >[741240.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ee60] >[741240.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ee60] width 1280 pitch 5120 (/4 1280) >[741253.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78290] >[741253.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78290] width 1280 pitch 5120 (/4 1280) >[741253.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741253.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741256.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef5520] >[741256.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef5520] width 1280 pitch 5120 (/4 1280) >[741256.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef5520] >[741256.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef5520] width 1280 pitch 5120 (/4 1280) >[741274.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6e060] >[741274.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6e060] width 1280 pitch 5120 (/4 1280) >[741274.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5441120] >[741274.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5441120] width 1280 pitch 5120 (/4 1280) >[741276.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3b790] >[741276.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3b790] width 1280 pitch 5120 (/4 1280) >[741276.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da1240] >[741276.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da1240] width 1280 pitch 5120 (/4 1280) >[741288.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f367e0] >[741288.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f367e0] width 1280 pitch 5120 (/4 1280) >[741288.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da1240] >[741288.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da1240] width 1280 pitch 5120 (/4 1280) >[741291.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5da1240] >[741291.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5da1240] width 1280 pitch 5120 (/4 1280) >[741291.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5441120] >[741291.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5441120] width 1280 pitch 5120 (/4 1280) >[741317.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee89a0] >[741317.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee89a0] width 1280 pitch 5120 (/4 1280) >[741317.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7adf0] >[741317.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7adf0] width 1280 pitch 5120 (/4 1280) >[741317.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7adf0] >[741318.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7adf0] width 1280 pitch 5120 (/4 1280) >[741318.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee89a0] >[741318.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee89a0] width 1280 pitch 5120 (/4 1280) >[741326.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[741326.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[741326.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7adf0] >[741326.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7adf0] width 1280 pitch 5120 (/4 1280) >[741327.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f36970] >[741327.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f36970] width 1280 pitch 5120 (/4 1280) >[741327.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6e060] >[741327.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6e060] width 1280 pitch 5120 (/4 1280) >[741356.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7adf0] >[741356.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7adf0] width 1280 pitch 5120 (/4 1280) >[741357.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3af10] >[741357.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3af10] width 1280 pitch 5120 (/4 1280) >[741358.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[741358.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[741358.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e5c140] >[741358.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e5c140] width 1280 pitch 5120 (/4 1280) >[741375.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741375.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741375.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e5fc10] >[741375.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e5fc10] width 1280 pitch 5120 (/4 1280) >[741380.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e5fc10] >[741380.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e5fc10] width 1280 pitch 5120 (/4 1280) >[741382.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c16f20] >[741382.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c16f20] width 1280 pitch 5120 (/4 1280) >[741382.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eefd70] >[741382.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eefd70] width 1280 pitch 5120 (/4 1280) >[741383.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[741383.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[741384.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741384.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741393.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f39f80] >[741393.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f39f80] width 1280 pitch 5120 (/4 1280) >[741394.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e819e0] >[741394.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e819e0] width 1280 pitch 5120 (/4 1280) >[741397.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eeedf0] >[741397.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eeedf0] width 1280 pitch 5120 (/4 1280) >[741397.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cb3530] >[741397.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cb3530] width 1280 pitch 5120 (/4 1280) >[741399.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[741399.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[741399.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7eff0] >[741399.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7eff0] width 1280 pitch 5120 (/4 1280) >[741400.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[741400.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[741400.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a000] >[741400.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a000] width 1280 pitch 5120 (/4 1280) >[741408.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a000] >[741408.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a000] width 1280 pitch 5120 (/4 1280) >[741408.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e62da0] >[741408.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e62da0] width 1280 pitch 5120 (/4 1280) >[741410.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[741410.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[741410.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7eff0] >[741410.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7eff0] width 1280 pitch 5120 (/4 1280) >[741467.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd82b0] >[741467.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd82b0] width 1280 pitch 5120 (/4 1280) >[741468.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3af10] >[741468.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3af10] width 1280 pitch 5120 (/4 1280) >[741667.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78330] >[741667.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78330] width 1280 pitch 5120 (/4 1280) >[741667.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5737790] >[741667.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5737790] width 1280 pitch 5120 (/4 1280) >[741667.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78330] >[741667.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78330] width 1280 pitch 5120 (/4 1280) >[741667.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78330] >[741667.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78330] width 1280 pitch 5120 (/4 1280) >[741774.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[741774.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[741774.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[741774.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[741774.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f40c80] >[741774.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f40c80] width 1280 pitch 5120 (/4 1280) >[741774.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[741774.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[742042.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[742042.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[742042.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78290] >[742042.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78290] width 1280 pitch 5120 (/4 1280) >[742042.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[742042.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[742042.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742042.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742042.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[742042.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[742042.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742042.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742042.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[742042.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[742042.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742042.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742042.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[742042.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[742042.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742042.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742042.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d863e0] >[742042.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d863e0] width 1280 pitch 5120 (/4 1280) >[742042.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742042.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742043.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[742043.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[742043.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742043.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742043.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[742043.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[742043.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742043.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742043.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[742043.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[742043.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742043.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742043.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[742043.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[742043.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78290] >[742043.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78290] width 1280 pitch 5120 (/4 1280) >[742043.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[742043.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[742044.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7cce0] >[742044.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7cce0] width 1280 pitch 5120 (/4 1280) >[742045.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eeb760] >[742045.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eeb760] width 1280 pitch 5120 (/4 1280) >[742046.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221cc00] >[742046.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221cc00] width 1280 pitch 5120 (/4 1280) >[742046.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[742046.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[742046.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2c230] >[742046.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2c230] width 1280 pitch 5120 (/4 1280) >[742047.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[742047.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[742047.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5816080] >[742047.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5816080] width 1280 pitch 5120 (/4 1280) >[742047.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742047.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742047.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742047.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742047.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2900] >[742047.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2900] width 1280 pitch 5120 (/4 1280) >[742047.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[742047.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[742047.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e5c140] >[742048.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e5c140] width 1280 pitch 5120 (/4 1280) >[742048.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[742048.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[742048.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765640] >[742048.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765640] width 1280 pitch 5120 (/4 1280) >[742048.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221cc00] >[742048.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221cc00] width 1280 pitch 5120 (/4 1280) >[742049.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[742049.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[742050.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938bb0] >[742050.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938bb0] width 1280 pitch 5120 (/4 1280) >[742050.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938bb0] >[742050.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938bb0] width 1280 pitch 5120 (/4 1280) >[742050.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5938bb0] >[742050.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5938bb0] width 1280 pitch 5120 (/4 1280) >[742050.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5959810] >[742050.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5959810] width 1280 pitch 5120 (/4 1280) >[742216.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742216.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742216.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78330] >[742216.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78330] width 1280 pitch 5120 (/4 1280) >[742242.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742242.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742242.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742242.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742242.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742242.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742242.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742242.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742242.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742242.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742242.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[742242.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[742242.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c16f20] >[742242.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c16f20] width 1280 pitch 5120 (/4 1280) >[742242.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[742242.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[742242.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742242.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742242.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742242.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742242.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742242.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742242.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742242.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742242.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[742242.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[742242.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742243.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742243.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[742243.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[742243.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742243.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742243.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5466f50] >[742243.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5466f50] width 1280 pitch 5120 (/4 1280) >[742243.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef10a0] >[742243.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef10a0] width 1280 pitch 5120 (/4 1280) >[742245.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742245.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742245.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742245.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742245.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742246.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742246.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742246.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742246.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742246.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742246.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742246.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742246.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742246.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742246.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742246.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742246.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742246.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742246.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baa30] >[742246.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baa30] width 1280 pitch 5120 (/4 1280) >[742246.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742246.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742246.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baa30] >[742246.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baa30] width 1280 pitch 5120 (/4 1280) >[742246.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742246.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742246.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baa30] >[742246.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baa30] width 1280 pitch 5120 (/4 1280) >[742246.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742246.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742246.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29baa30] >[742246.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29baa30] width 1280 pitch 5120 (/4 1280) >[742246.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742247.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742247.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742247.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742247.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5efdb40] >[742247.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5efdb40] width 1280 pitch 5120 (/4 1280) >[742247.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742247.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742247.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742247.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742247.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742247.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742247.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742247.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742247.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742247.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742247.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742247.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742247.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[742247.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[742247.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a4e30] >[742247.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a4e30] width 1280 pitch 5120 (/4 1280) >[742247.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742247.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742247.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[742247.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[742247.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742247.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742247.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[742247.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[742247.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742247.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742247.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[742247.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[742247.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742247.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742247.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[742247.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[742247.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594a450] >[742247.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594a450] width 1280 pitch 5120 (/4 1280) >[742252.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d1f70] >[742252.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d1f70] width 1280 pitch 5120 (/4 1280) >[742259.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e780e0] >[742259.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e780e0] width 1280 pitch 5120 (/4 1280) >[742635.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c16f20] >[742635.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c16f20] width 1280 pitch 5120 (/4 1280) >[742635.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ddec90] >[742635.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ddec90] width 1280 pitch 5120 (/4 1280) >[742635.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742635.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742635.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b80060] >[742635.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b80060] width 1280 pitch 5120 (/4 1280) >[742635.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742635.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742635.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742635.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742636.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742636.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742636.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742636.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742636.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742636.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742637.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742637.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742637.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742637.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742637.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742637.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742637.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742637.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742638.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742638.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742638.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742638.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742638.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742638.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742638.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742638.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742638.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ee50] >[742638.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ee50] width 1280 pitch 5120 (/4 1280) >[742639.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742639.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742639.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742639.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742639.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742639.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742639.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742639.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742639.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742639.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742639.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742639.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742639.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742639.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742639.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742639.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742639.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742639.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742639.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742639.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742640.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742640.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742640.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742640.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742640.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742640.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742640.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742640.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742640.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742640.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742640.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fad0] >[742640.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fad0] width 1280 pitch 5120 (/4 1280) >[742640.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742640.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742640.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fad0] >[742640.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fad0] width 1280 pitch 5120 (/4 1280) >[742640.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742640.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742640.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fad0] >[742640.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fad0] width 1280 pitch 5120 (/4 1280) >[742640.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742640.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742640.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fad0] >[742640.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fad0] width 1280 pitch 5120 (/4 1280) >[742640.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742640.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742640.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fad0] >[742640.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fad0] width 1280 pitch 5120 (/4 1280) >[742640.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742640.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742640.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742640.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742640.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[742640.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[742640.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742640.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742640.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5721960] >[742640.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5721960] width 1280 pitch 5120 (/4 1280) >[742640.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88ea0] >[742640.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88ea0] width 1280 pitch 5120 (/4 1280) >[742640.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[742640.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[742640.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742640.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742640.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742640.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742640.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742640.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742640.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742640.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742640.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742641.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742641.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b210] >[742641.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b210] width 1280 pitch 5120 (/4 1280) >[742641.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c95100] >[742641.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c95100] width 1280 pitch 5120 (/4 1280) >[742642.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e79de0] >[742642.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e79de0] width 1280 pitch 5120 (/4 1280) >[742646.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eef810] >[742646.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eef810] width 1280 pitch 5120 (/4 1280) >[742646.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de2220] >[742646.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de2220] width 1280 pitch 5120 (/4 1280) >[742646.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eef810] >[742646.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eef810] width 1280 pitch 5120 (/4 1280) >[742646.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de2220] >[742646.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de2220] width 1280 pitch 5120 (/4 1280) >[742646.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742646.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742646.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742646.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742646.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742646.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742646.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742646.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742647.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742647.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742647.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742647.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742647.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742647.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742647.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742647.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742647.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742647.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742647.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742647.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742647.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742647.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742647.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742647.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742647.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742647.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742648.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742648.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742648.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742648.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742648.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742648.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742648.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742648.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742648.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742648.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742648.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742648.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742648.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8d900] >[742648.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8d900] width 1280 pitch 5120 (/4 1280) >[742648.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f7d40] >[742648.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f7d40] width 1280 pitch 5120 (/4 1280) >[742649.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595ed70] >[742649.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595ed70] width 1280 pitch 5120 (/4 1280) >[742649.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f82c0] >[742649.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f82c0] width 1280 pitch 5120 (/4 1280) >[742649.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[742649.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[742650.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5828e30] >[742650.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5828e30] width 1280 pitch 5120 (/4 1280) >[742650.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2bb20] >[742650.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2bb20] width 1280 pitch 5120 (/4 1280) >[742650.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[742650.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[742650.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3ae00] >[742650.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3ae00] width 1280 pitch 5120 (/4 1280) >[742650.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5816080] >[742650.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5816080] width 1280 pitch 5120 (/4 1280) >[742650.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742650.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742650.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5816080] >[742650.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5816080] width 1280 pitch 5120 (/4 1280) >[742650.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f3c010] >[742650.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f3c010] width 1280 pitch 5120 (/4 1280) >[742650.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742650.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742650.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742650.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742650.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2900] >[742650.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2900] width 1280 pitch 5120 (/4 1280) >[742661.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7b530] >[742661.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7b530] width 1280 pitch 5120 (/4 1280) >[742662.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45f4c20] >[742662.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45f4c20] width 1280 pitch 5120 (/4 1280) >[742723.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5a90] >[742723.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5a90] width 1280 pitch 5120 (/4 1280) >[742723.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8e810] >[742723.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8e810] width 1280 pitch 5120 (/4 1280) >[742749.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742749.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742749.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742749.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742749.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e87f50] >[742749.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e87f50] width 1280 pitch 5120 (/4 1280) >[742749.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742749.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742749.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742749.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742749.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53805f0] >[742749.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53805f0] width 1280 pitch 5120 (/4 1280) >[742749.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e87f50] >[742749.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e87f50] width 1280 pitch 5120 (/4 1280) >[742749.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742749.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742749.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53805f0] >[742749.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53805f0] width 1280 pitch 5120 (/4 1280) >[742749.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742749.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742749.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742749.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742749.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53805f0] >[742749.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53805f0] width 1280 pitch 5120 (/4 1280) >[742749.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f3740] >[742749.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f3740] width 1280 pitch 5120 (/4 1280) >[742749.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53805f0] >[742749.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53805f0] width 1280 pitch 5120 (/4 1280) >[742750.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e87f50] >[742750.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e87f50] width 1280 pitch 5120 (/4 1280) >[742750.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f3740] >[742750.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f3740] width 1280 pitch 5120 (/4 1280) >[742750.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742750.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742750.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742750.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742750.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742750.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742750.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e87f50] >[742750.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e87f50] width 1280 pitch 5120 (/4 1280) >[742750.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44f3740] >[742750.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44f3740] width 1280 pitch 5120 (/4 1280) >[742750.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[742750.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[742750.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5acb0] >[742750.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5acb0] width 1280 pitch 5120 (/4 1280) >[742750.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742750.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742751.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b338c0] >[742751.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b338c0] width 1280 pitch 5120 (/4 1280) >[742751.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[742751.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[742751.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742751.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742751.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7adf0] >[742751.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7adf0] width 1280 pitch 5120 (/4 1280) >[742751.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742751.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742751.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[742751.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[742751.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[742751.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[742751.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765640] >[742751.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765640] width 1280 pitch 5120 (/4 1280) >[742751.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[742751.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[742751.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5739830] >[742751.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5739830] width 1280 pitch 5120 (/4 1280) >[742751.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577c900] >[742751.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577c900] width 1280 pitch 5120 (/4 1280) >[742751.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5bea0] >[742751.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5bea0] width 1280 pitch 5120 (/4 1280) >[742751.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[742751.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[742751.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58263f0] >[742751.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58263f0] width 1280 pitch 5120 (/4 1280) >[742751.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[742751.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[742751.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[742751.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[742751.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742751.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742751.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[742751.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[742751.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742751.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742751.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f670] >[742751.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f670] width 1280 pitch 5120 (/4 1280) >[742751.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c87630] >[742751.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c87630] width 1280 pitch 5120 (/4 1280) >[742751.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dddba0] >[742751.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dddba0] width 1280 pitch 5120 (/4 1280) >[742751.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x582bfb0] >[742751.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x582bfb0] width 1280 pitch 5120 (/4 1280) >[742751.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58e2900] >[742751.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58e2900] width 1280 pitch 5120 (/4 1280) >[742751.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[742751.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[742753.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5721960] >[742753.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5721960] width 1280 pitch 5120 (/4 1280) >[742764.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[742764.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[742764.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[742764.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[742818.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d0620] >[742818.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d0620] width 1280 pitch 5120 (/4 1280) >[742818.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d0620] >[742818.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d0620] width 1280 pitch 5120 (/4 1280) >[742953.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742953.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742953.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742953.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742953.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742953.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742953.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742953.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742953.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742953.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742953.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742953.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742953.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742954.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742954.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742954.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742954.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742954.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742954.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742954.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742954.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742954.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742954.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742954.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742955.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742955.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742955.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742955.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742955.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742955.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742955.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742955.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742956.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742956.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742956.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742956.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742956.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742956.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742956.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742956.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742956.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742956.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742956.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742956.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742956.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742956.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742957.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742957.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742957.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742957.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742957.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742957.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742957.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742957.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742957.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742957.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742957.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742957.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742957.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742957.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742957.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f56e10] >[742957.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f56e10] width 1280 pitch 5120 (/4 1280) >[742957.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f666e0] >[742957.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f666e0] width 1280 pitch 5120 (/4 1280) >[742958.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b1130] >[742958.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b1130] width 1280 pitch 5120 (/4 1280) >[742959.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742959.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742959.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742959.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f699e0] >[742959.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f699e0] width 1280 pitch 5120 (/4 1280) >[742959.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742959.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8e00] >[742965.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8e00] width 1280 pitch 5120 (/4 1280) >[742965.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8e810] >[742965.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8e810] width 1280 pitch 5120 (/4 1280) >[742965.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742965.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742965.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8e00] >[742965.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8e00] width 1280 pitch 5120 (/4 1280) >[742965.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742965.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742965.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742965.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742965.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742965.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742965.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742965.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742965.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742965.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742965.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613750] >[742965.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613750] width 1280 pitch 5120 (/4 1280) >[742965.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c8e810] >[742965.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c8e810] width 1280 pitch 5120 (/4 1280) >[742965.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742965.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742965.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742965.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742965.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742965.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742965.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742965.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742965.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742966.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742966.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742966.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742966.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742966.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742966.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742966.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742966.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742966.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742966.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742966.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742966.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742966.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[742966.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593b130] >[742966.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593b130] width 1280 pitch 5120 (/4 1280) >[742966.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c080] >[742966.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c080] width 1280 pitch 5120 (/4 1280) >[743076.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f58080] >[743076.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f58080] width 1280 pitch 5120 (/4 1280) >[743076.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f58080] >[743076.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f58080] width 1280 pitch 5120 (/4 1280) >[743081.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f511e0] >[743081.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f511e0] width 1280 pitch 5120 (/4 1280) >[743081.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743081.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743081.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f511e0] >[743081.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f511e0] width 1280 pitch 5120 (/4 1280) >[743081.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743081.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743081.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f511e0] >[743081.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f511e0] width 1280 pitch 5120 (/4 1280) >[743081.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743081.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743081.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f511e0] >[743081.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f511e0] width 1280 pitch 5120 (/4 1280) >[743081.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f52470] >[743081.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f52470] width 1280 pitch 5120 (/4 1280) >[743081.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743081.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743081.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f52470] >[743081.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f52470] width 1280 pitch 5120 (/4 1280) >[743081.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743081.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc0730] >[743082.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc0730] width 1280 pitch 5120 (/4 1280) >[743082.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743082.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743082.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd5ad0] >[743082.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd5ad0] width 1280 pitch 5120 (/4 1280) >[743082.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc0730] >[743082.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc0730] width 1280 pitch 5120 (/4 1280) >[743082.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b0d40] >[743083.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b0d40] width 1280 pitch 5120 (/4 1280) >[743083.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b0d40] >[743083.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b0d40] width 1280 pitch 5120 (/4 1280) >[743083.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b0d40] >[743083.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b0d40] width 1280 pitch 5120 (/4 1280) >[743083.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53b0d40] >[743083.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53b0d40] width 1280 pitch 5120 (/4 1280) >[743083.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc0730] >[743083.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc0730] width 1280 pitch 5120 (/4 1280) >[743083.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c0fc0] >[743083.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c0fc0] width 1280 pitch 5120 (/4 1280) >[743083.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c0fc0] >[743083.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c0fc0] width 1280 pitch 5120 (/4 1280) >[743083.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc0730] >[743083.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc0730] width 1280 pitch 5120 (/4 1280) >[743083.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d6a270] >[743083.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d6a270] width 1280 pitch 5120 (/4 1280) >[743083.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743083.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743083.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743083.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743083.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743083.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743083.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743083.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743083.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743083.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743083.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743084.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743084.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743084.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743084.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743087.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743087.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743087.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743087.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743097.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743097.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743097.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743097.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743097.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743097.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743097.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b2530] >[743097.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b2530] width 1280 pitch 5120 (/4 1280) >[743097.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e83e90] >[743097.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e83e90] width 1280 pitch 5120 (/4 1280) >[743097.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[743097.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[743097.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de5940] >[743097.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de5940] width 1280 pitch 5120 (/4 1280) >[743097.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f743b0] >[743097.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f743b0] width 1280 pitch 5120 (/4 1280) >[743097.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743097.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743097.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[743097.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[743117.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f405e0] >[743117.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f405e0] width 1280 pitch 5120 (/4 1280) >[743120.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743120.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743121.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743121.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743121.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743121.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743121.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743121.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f743b0] >[743121.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f743b0] width 1280 pitch 5120 (/4 1280) >[743121.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[743121.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[743121.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743121.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743121.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743121.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743121.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743121.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743121.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756b0] >[743121.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756b0] width 1280 pitch 5120 (/4 1280) >[743121.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf4860] >[743121.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf4860] width 1280 pitch 5120 (/4 1280) >[743150.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f62690] >[743150.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f62690] width 1280 pitch 5120 (/4 1280) >[743150.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb3dd0] >[743150.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb3dd0] width 1280 pitch 5120 (/4 1280) >[743150.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6cd60] >[743150.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6cd60] width 1280 pitch 5120 (/4 1280) >[743150.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743150.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743151.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb13e0] >[743151.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb13e0] width 1280 pitch 5120 (/4 1280) >[743151.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb13e0] >[743151.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb13e0] width 1280 pitch 5120 (/4 1280) >[743313.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5faa840] >[743313.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5faa840] width 1280 pitch 5120 (/4 1280) >[743313.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7ddb0] >[743313.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7ddb0] width 1280 pitch 5120 (/4 1280) >[743313.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743313.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743313.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d78330] >[743313.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d78330] width 1280 pitch 5120 (/4 1280) >[743314.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5faa840] >[743314.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5faa840] width 1280 pitch 5120 (/4 1280) >[743315.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb7550] >[743316.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb7550] width 1280 pitch 5120 (/4 1280) >[743316.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7ddb0] >[743316.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7ddb0] width 1280 pitch 5120 (/4 1280) >[743316.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb7550] >[743316.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb7550] width 1280 pitch 5120 (/4 1280) >[743316.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcedb0] >[743316.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcedb0] width 1280 pitch 5120 (/4 1280) >[743317.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743317.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743317.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f750e0] >[743317.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f750e0] width 1280 pitch 5120 (/4 1280) >[743317.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb1360] >[743317.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb1360] width 1280 pitch 5120 (/4 1280) >[743363.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743363.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743364.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f750e0] >[743364.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f750e0] width 1280 pitch 5120 (/4 1280) >[743364.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743364.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743364.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743364.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743364.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743364.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743364.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55038a0] >[743364.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55038a0] width 1280 pitch 5120 (/4 1280) >[743365.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58007d0] >[743365.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58007d0] width 1280 pitch 5120 (/4 1280) >[743366.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b0bb0] >[743366.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b0bb0] width 1280 pitch 5120 (/4 1280) >[743366.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6660] >[743366.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6660] width 1280 pitch 5120 (/4 1280) >[743366.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55038a0] >[743366.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55038a0] width 1280 pitch 5120 (/4 1280) >[743369.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6dff0] >[743369.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6dff0] width 1280 pitch 5120 (/4 1280) >[743370.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ef6800] >[743370.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ef6800] width 1280 pitch 5120 (/4 1280) >[743371.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d74d80] >[743371.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d74d80] width 1280 pitch 5120 (/4 1280) >[743371.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743371.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743371.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743371.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743371.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743371.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743372.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559ceb0] >[743372.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559ceb0] width 1280 pitch 5120 (/4 1280) >[743372.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743372.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743384.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f74f90] >[743384.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f74f90] width 1280 pitch 5120 (/4 1280) >[743384.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x577a1a0] >[743384.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x577a1a0] width 1280 pitch 5120 (/4 1280) >[743384.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[743384.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[743384.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576ca00] >[743384.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576ca00] width 1280 pitch 5120 (/4 1280) >[743384.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c6dff0] >[743384.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c6dff0] width 1280 pitch 5120 (/4 1280) >[743384.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d74d80] >[743384.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d74d80] width 1280 pitch 5120 (/4 1280) >[743391.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743391.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743391.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[743391.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[743391.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743391.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743391.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[743391.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[743392.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743392.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743393.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x411d6b0] >[743393.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x411d6b0] width 1280 pitch 5120 (/4 1280) >[743393.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c0f30] >[743393.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c0f30] width 1280 pitch 5120 (/4 1280) >[743393.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[743393.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[743393.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c0f30] >[743393.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c0f30] width 1280 pitch 5120 (/4 1280) >[743393.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[743393.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[743394.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e55cd0] >[743394.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e55cd0] width 1280 pitch 5120 (/4 1280) >[743394.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560cf00] >[743394.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560cf00] width 1280 pitch 5120 (/4 1280) >[743394.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560cff0] >[743394.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560cff0] width 1280 pitch 5120 (/4 1280) >[743394.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6c870] >[743394.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6c870] width 1280 pitch 5120 (/4 1280) >[743395.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560cf00] >[743395.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560cf00] width 1280 pitch 5120 (/4 1280) >[743395.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6c870] >[743395.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6c870] width 1280 pitch 5120 (/4 1280) >[743395.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f71840] >[743395.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f71840] width 1280 pitch 5120 (/4 1280) >[743395.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5765640] >[743395.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5765640] width 1280 pitch 5120 (/4 1280) >[743395.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f71840] >[743395.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f71840] width 1280 pitch 5120 (/4 1280) >[743395.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[743395.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[743398.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[743398.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[743398.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f670] >[743398.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f670] width 1280 pitch 5120 (/4 1280) >[743408.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f670] >[743408.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f670] width 1280 pitch 5120 (/4 1280) >[743408.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[743408.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[743409.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[743409.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[743409.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[743409.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[743421.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221cc00] >[743421.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221cc00] width 1280 pitch 5120 (/4 1280) >[743421.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5816660] >[743422.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5816660] width 1280 pitch 5120 (/4 1280) >[743422.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e81b80] >[743422.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e81b80] width 1280 pitch 5120 (/4 1280) >[743422.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[743422.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[743423.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f670] >[743423.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f670] width 1280 pitch 5120 (/4 1280) >[743424.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[743424.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[743424.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[743424.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[743424.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd2f00] >[743424.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd2f00] width 1280 pitch 5120 (/4 1280) >[743431.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743431.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743431.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aad9b0] >[743431.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aad9b0] width 1280 pitch 5120 (/4 1280) >[743432.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743432.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743432.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aad9b0] >[743432.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aad9b0] width 1280 pitch 5120 (/4 1280) >[743432.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743432.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743433.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743433.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743433.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743433.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743433.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743433.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743433.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743433.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743433.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743433.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743433.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743433.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743433.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743433.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743433.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcf730] >[743433.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcf730] width 1280 pitch 5120 (/4 1280) >[743434.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c34040] >[743434.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c34040] width 1280 pitch 5120 (/4 1280) >[743435.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4c950] >[743435.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4c950] width 1280 pitch 5120 (/4 1280) >[743435.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6660] >[743435.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6660] width 1280 pitch 5120 (/4 1280) >[743435.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4c950] >[743435.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4c950] width 1280 pitch 5120 (/4 1280) >[743436.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6660] >[743436.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6660] width 1280 pitch 5120 (/4 1280) >[743436.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e4c950] >[743436.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e4c950] width 1280 pitch 5120 (/4 1280) >[743436.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221cc00] >[743436.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221cc00] width 1280 pitch 5120 (/4 1280) >[743436.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f71840] >[743436.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f71840] width 1280 pitch 5120 (/4 1280) >[743436.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[743436.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[743485.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[743485.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[743485.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[743485.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[743516.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x559ceb0] >[743516.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x559ceb0] width 1280 pitch 5120 (/4 1280) >[743516.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[743516.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[743539.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f670] >[743539.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f670] width 1280 pitch 5120 (/4 1280) >[743539.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dafff0] >[743539.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dafff0] width 1280 pitch 5120 (/4 1280) >[743539.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40effb0] >[743540.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40effb0] width 1280 pitch 5120 (/4 1280) >[743540.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c907b0] >[743540.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c907b0] width 1280 pitch 5120 (/4 1280) >[743565.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb5fb0] >[743565.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb5fb0] width 1280 pitch 5120 (/4 1280) >[743565.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5816660] >[743565.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5816660] width 1280 pitch 5120 (/4 1280) >[743598.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2f440] >[743598.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2f440] width 1280 pitch 5120 (/4 1280) >[743598.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f71940] >[743598.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f71940] width 1280 pitch 5120 (/4 1280) >[743598.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6e5b0] >[743598.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6e5b0] width 1280 pitch 5120 (/4 1280) >[743599.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db6680] >[743599.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db6680] width 1280 pitch 5120 (/4 1280) >[743601.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[743601.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[743601.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f150] >[743601.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f150] width 1280 pitch 5120 (/4 1280) >[743601.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a92a00] >[743601.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a92a00] width 1280 pitch 5120 (/4 1280) >[743601.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5528230] >[743601.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5528230] width 1280 pitch 5120 (/4 1280) >[743626.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4413ea0] >[743626.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4413ea0] width 1280 pitch 5120 (/4 1280) >[743626.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5e020] >[743626.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5e020] width 1280 pitch 5120 (/4 1280) >[743628.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58161f0] >[743628.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58161f0] width 1280 pitch 5120 (/4 1280) >[743628.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d2f440] >[743628.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d2f440] width 1280 pitch 5120 (/4 1280) >[743641.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5eebef0] >[743641.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5eebef0] width 1280 pitch 5120 (/4 1280) >[743641.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5766e00] >[743641.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5766e00] width 1280 pitch 5120 (/4 1280) >[743729.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c91c00] >[743729.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c91c00] width 1280 pitch 5120 (/4 1280) >[743885.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x221cd50] >[743885.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x221cd50] width 1280 pitch 5120 (/4 1280) >[743888.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd310] >[743888.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd310] width 1280 pitch 5120 (/4 1280) >[744021.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f8fac0] >[744021.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f8fac0] width 1280 pitch 5120 (/4 1280) >[744022.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5faa840] >[744022.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5faa840] width 1280 pitch 5120 (/4 1280) >[744023.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5faa840] >[744023.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5faa840] width 1280 pitch 5120 (/4 1280) >[744024.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5faa840] >[744024.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5faa840] width 1280 pitch 5120 (/4 1280) >[744178.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f8dea0] >[744178.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f8dea0] width 1280 pitch 5120 (/4 1280) >[744185.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9e7b0] >[744185.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9e7b0] width 1280 pitch 5120 (/4 1280) >[744291.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c91c00] >[744291.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c91c00] width 1280 pitch 5120 (/4 1280) >[744337.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcf5c0] >[744337.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcf5c0] width 1280 pitch 5120 (/4 1280) >[744337.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcddf0] >[744337.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcddf0] width 1280 pitch 5120 (/4 1280) >[744388.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcf5c0] >[744388.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcf5c0] width 1280 pitch 5120 (/4 1280) >[744388.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60171e0] >[744388.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60171e0] width 1280 pitch 5120 (/4 1280) >[744589.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744589.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744609.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61421e0] >[744609.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61421e0] width 1280 pitch 5120 (/4 1280) >[744609.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744609.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744609.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61421e0] >[744609.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61421e0] width 1280 pitch 5120 (/4 1280) >[744609.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744609.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744609.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61421e0] >[744609.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61421e0] width 1280 pitch 5120 (/4 1280) >[744609.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f82380] >[744609.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f82380] width 1280 pitch 5120 (/4 1280) >[744609.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744609.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744609.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f82380] >[744609.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f82380] width 1280 pitch 5120 (/4 1280) >[744614.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fd08b0] >[744614.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fd08b0] width 1280 pitch 5120 (/4 1280) >[744614.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f82380] >[744614.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f82380] width 1280 pitch 5120 (/4 1280) >[744614.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744614.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744614.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f98980] >[744614.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f98980] width 1280 pitch 5120 (/4 1280) >[744614.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744614.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744614.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744614.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744614.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fd08b0] >[744614.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fd08b0] width 1280 pitch 5120 (/4 1280) >[744614.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f82380] >[744614.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f82380] width 1280 pitch 5120 (/4 1280) >[744614.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d210] >[744614.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d210] width 1280 pitch 5120 (/4 1280) >[744615.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f98980] >[744615.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f98980] width 1280 pitch 5120 (/4 1280) >[744615.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744615.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744615.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744615.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744615.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744615.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744616.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744616.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744616.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744616.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744616.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744616.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744616.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744616.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744616.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744616.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744616.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744616.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744616.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744616.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744616.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f990b0] >[744616.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f990b0] width 1280 pitch 5120 (/4 1280) >[744616.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9edd0] >[744616.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9edd0] width 1280 pitch 5120 (/4 1280) >[744949.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6145ca0] >[744949.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6145ca0] width 1280 pitch 5120 (/4 1280) >[744949.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614c5a0] >[744949.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614c5a0] width 1280 pitch 5120 (/4 1280) >[745222.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614c990] >[745222.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614c990] width 1280 pitch 5120 (/4 1280) >[745222.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614c990] >[745222.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614c990] width 1280 pitch 5120 (/4 1280) >[745222.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614c990] >[745222.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614c990] width 1280 pitch 5120 (/4 1280) >[745222.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9dba0] >[745222.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9dba0] width 1280 pitch 5120 (/4 1280) >[745222.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9dba0] >[745222.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9dba0] width 1280 pitch 5120 (/4 1280) >[745222.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745222.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745222.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f9dba0] >[745222.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f9dba0] width 1280 pitch 5120 (/4 1280) >[745301.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614c990] >[745301.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614c990] width 1280 pitch 5120 (/4 1280) >[745302.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fffd40] >[745302.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fffd40] width 1280 pitch 5120 (/4 1280) >[745302.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[745302.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6154c70] >[745302.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6154c70] width 1280 pitch 5120 (/4 1280) >[745302.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[745302.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[746505.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x613d730] >[746505.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x613d730] width 1280 pitch 5120 (/4 1280) >[746505.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fd08b0] >[746505.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fd08b0] width 1280 pitch 5120 (/4 1280) >[746561.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6145ca0] >[746561.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6145ca0] width 1280 pitch 5120 (/4 1280) >[746562.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6005a20] >[746562.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6005a20] width 1280 pitch 5120 (/4 1280) >[746563.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff9d90] >[746563.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff9d90] width 1280 pitch 5120 (/4 1280) >[746564.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff9d90] >[746564.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff9d90] width 1280 pitch 5120 (/4 1280) >[746564.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f883c0] >[746564.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f883c0] width 1280 pitch 5120 (/4 1280) >[746564.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fff150] >[746564.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fff150] width 1280 pitch 5120 (/4 1280) >[746621.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f948f0] >[746621.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f948f0] width 1280 pitch 5120 (/4 1280) >[746621.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6005a20] >[746621.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6005a20] width 1280 pitch 5120 (/4 1280) >[746621.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f948f0] >[746621.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f948f0] width 1280 pitch 5120 (/4 1280) >[746622.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff6da0] >[746622.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff6da0] width 1280 pitch 5120 (/4 1280) >[746622.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61550f0] >[746622.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61550f0] width 1280 pitch 5120 (/4 1280) >[746622.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff6da0] >[746622.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff6da0] width 1280 pitch 5120 (/4 1280) >[746622.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61550f0] >[746622.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61550f0] width 1280 pitch 5120 (/4 1280) >[746623.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x612c950] >[746623.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x612c950] width 1280 pitch 5120 (/4 1280) >[746623.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61550f0] >[746623.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61550f0] width 1280 pitch 5120 (/4 1280) >[746623.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6005a20] >[746623.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6005a20] width 1280 pitch 5120 (/4 1280) >[746623.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61550f0] >[746623.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61550f0] width 1280 pitch 5120 (/4 1280) >[746624.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6005a20] >[746624.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6005a20] width 1280 pitch 5120 (/4 1280) >[746956.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a6cc0] >[746956.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a6cc0] width 1280 pitch 5120 (/4 1280) >[746956.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6134200] >[746956.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6134200] width 1280 pitch 5120 (/4 1280) >[746956.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fe5110] >[746956.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fe5110] width 1280 pitch 5120 (/4 1280) >[746956.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fd7090] >[746956.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fd7090] width 1280 pitch 5120 (/4 1280) >[746960.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60b3ab0] >[746960.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60b3ab0] width 1280 pitch 5120 (/4 1280) >[746960.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[746961.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[746961.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff7980] >[746961.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff7980] width 1280 pitch 5120 (/4 1280) >[746961.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fcad40] >[746961.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fcad40] width 1280 pitch 5120 (/4 1280) >[746962.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff7980] >[746962.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff7980] width 1280 pitch 5120 (/4 1280) >[746962.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fe5110] >[746962.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fe5110] width 1280 pitch 5120 (/4 1280) >[746962.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a6cc0] >[746962.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a6cc0] width 1280 pitch 5120 (/4 1280) >[746962.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d9b0a0] >[746962.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d9b0a0] width 1280 pitch 5120 (/4 1280) >[747088.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6119200] >[747088.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6119200] width 1280 pitch 5120 (/4 1280) >[747088.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x611a8a0] >[747088.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x611a8a0] width 1280 pitch 5120 (/4 1280) >[747090.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5febf10] >[747090.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5febf10] width 1280 pitch 5120 (/4 1280) >[747090.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614dfc0] >[747090.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614dfc0] width 1280 pitch 5120 (/4 1280) >[747857.685] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[747857.686] (II) RADEON(0): Printing DDC gathered Modelines: >[747857.686] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[747947.925] (II) RADEON(0): RADEONSaveScreen(2) >[747947.930] (II) RADEON(0): RADEONSaveScreen(0) >[748452.858] (II) RADEON(0): RADEONSaveScreen(1) >[748463.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x613a200] >[748463.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x613a200] width 1280 pitch 5120 (/4 1280) >[748464.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6119200] >[748464.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6119200] width 1280 pitch 5120 (/4 1280) >[748464.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6118050] >[748464.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6118050] width 1280 pitch 5120 (/4 1280) >[748464.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f98980] >[748464.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f98980] width 1280 pitch 5120 (/4 1280) >[748464.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6119200] >[748464.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6119200] width 1280 pitch 5120 (/4 1280) >[748464.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f98980] >[748464.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f98980] width 1280 pitch 5120 (/4 1280) >[748465.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fe3a50] >[748465.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fe3a50] width 1280 pitch 5120 (/4 1280) >[748465.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6118050] >[748465.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6118050] width 1280 pitch 5120 (/4 1280) >[748465.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6107750] >[748465.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6107750] width 1280 pitch 5120 (/4 1280) >[748623.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6095050] >[748623.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6095050] width 1280 pitch 5120 (/4 1280) >[748623.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6095050] >[748623.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6095050] width 1280 pitch 5120 (/4 1280) >[748656.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a4ff0] >[748656.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a4ff0] width 1280 pitch 5120 (/4 1280) >[748656.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[748656.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[748656.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[748656.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[748656.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6121f60] >[748656.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6121f60] width 1280 pitch 5120 (/4 1280) >[748661.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60baf70] >[748661.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60baf70] width 1280 pitch 5120 (/4 1280) >[748661.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f50290] >[748661.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f50290] width 1280 pitch 5120 (/4 1280) >[748661.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6121f60] >[748661.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6121f60] width 1280 pitch 5120 (/4 1280) >[748661.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6121f60] >[748661.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6121f60] width 1280 pitch 5120 (/4 1280) >[748681.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x601ea70] >[748681.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x601ea70] width 1280 pitch 5120 (/4 1280) >[748681.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fbdaa0] >[748681.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fbdaa0] width 1280 pitch 5120 (/4 1280) >[748681.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x601ea70] >[748681.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x601ea70] width 1280 pitch 5120 (/4 1280) >[748681.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60b6590] >[748681.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60b6590] width 1280 pitch 5120 (/4 1280) >[748682.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff4470] >[748682.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff4470] width 1280 pitch 5120 (/4 1280) >[748682.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ff4470] >[748682.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ff4470] width 1280 pitch 5120 (/4 1280) >[748688.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60b6590] >[748688.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60b6590] width 1280 pitch 5120 (/4 1280) >[748688.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60b6590] >[748688.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60b6590] width 1280 pitch 5120 (/4 1280) >[748815.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60d69f0] >[748815.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60d69f0] width 1280 pitch 5120 (/4 1280) >[748816.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60d9950] >[748816.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60d9950] width 1280 pitch 5120 (/4 1280) >[748843.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748843.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748843.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748843.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748843.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748843.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748843.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748843.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748843.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748843.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748843.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748843.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748844.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748844.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748844.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748844.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748844.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748844.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748844.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748844.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748844.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609cc00] >[748844.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609cc00] width 1280 pitch 5120 (/4 1280) >[748844.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6079b70] >[748844.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6079b70] width 1280 pitch 5120 (/4 1280) >[748845.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[748845.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[748845.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd6a60] >[748845.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd6a60] width 1280 pitch 5120 (/4 1280) >[748845.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748845.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748845.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748845.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748845.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[748845.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[748845.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748845.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748845.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[748845.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[748845.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748845.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748845.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[748846.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[748846.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5963a90] >[748846.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5963a90] width 1280 pitch 5120 (/4 1280) >[748846.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748846.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5791140] >[748846.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5791140] width 1280 pitch 5120 (/4 1280) >[748846.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748846.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748851.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e80b40] >[748851.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e80b40] width 1280 pitch 5120 (/4 1280) >[748851.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5925000] >[748851.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5925000] width 1280 pitch 5120 (/4 1280) >[748852.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e7edb0] >[748852.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e7edb0] width 1280 pitch 5120 (/4 1280) >[748852.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f536d0] >[748852.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f536d0] width 1280 pitch 5120 (/4 1280) >[748852.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55004d0] >[748852.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55004d0] width 1280 pitch 5120 (/4 1280) >[749682.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x606fec0] >[749682.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x606fec0] width 1280 pitch 5120 (/4 1280) >[749682.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x606fec0] >[749682.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x606fec0] width 1280 pitch 5120 (/4 1280) >[749790.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be70b0] >[749790.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be70b0] width 1280 pitch 5120 (/4 1280) >[749790.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60b77d0] >[749790.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60b77d0] width 1280 pitch 5120 (/4 1280) >[750008.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750008.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750008.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750008.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750008.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750008.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750009.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750009.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750009.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750009.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750009.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750009.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750010.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750010.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750010.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750010.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750010.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750010.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750010.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750010.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750010.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750010.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750010.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750010.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750010.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750010.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750010.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750010.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750010.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750010.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750011.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750011.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750011.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750011.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750011.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750011.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750011.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750011.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750011.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750011.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750012.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750012.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750012.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750012.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750012.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750012.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750012.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750012.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750012.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750012.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750012.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750012.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750013.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750013.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750013.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750013.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750013.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750013.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750013.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750013.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750013.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750013.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750013.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750013.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750013.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750014.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b41100] >[750014.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b41100] width 1280 pitch 5120 (/4 1280) >[750014.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202a320] >[750014.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202a320] width 1280 pitch 5120 (/4 1280) >[750014.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ce3d0] >[750014.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ce3d0] width 1280 pitch 5120 (/4 1280) >[750014.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750014.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750015.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750015.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750015.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750015.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750015.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750015.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750015.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750015.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60c4bc0] >[750015.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60c4bc0] width 1280 pitch 5120 (/4 1280) >[750015.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750015.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f54e80] >[750015.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f54e80] width 1280 pitch 5120 (/4 1280) >[750015.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x609e190] >[750015.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x609e190] width 1280 pitch 5120 (/4 1280) >[750023.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x276d8a0] >[750023.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x276d8a0] width 1280 pitch 5120 (/4 1280) >[750598.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60855c0] >[750598.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60855c0] width 1280 pitch 5120 (/4 1280) >[750598.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c922d0] >[750598.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c922d0] width 1280 pitch 5120 (/4 1280) >[750599.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60855c0] >[750599.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60855c0] width 1280 pitch 5120 (/4 1280) >[750599.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c922d0] >[750599.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c922d0] width 1280 pitch 5120 (/4 1280) >[751704.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6056e70] >[751704.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6056e70] width 1280 pitch 5120 (/4 1280) >[751704.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x605bfa0] >[751704.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x605bfa0] width 1280 pitch 5120 (/4 1280) >[751992.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60698b0] >[751992.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60698b0] width 1280 pitch 5120 (/4 1280) >[751992.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616dfd0] >[751992.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616dfd0] width 1280 pitch 5120 (/4 1280) >[752002.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60db3d0] >[752002.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60db3d0] width 1280 pitch 5120 (/4 1280) >[752002.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6179ca0] >[752002.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6179ca0] width 1280 pitch 5120 (/4 1280) >[752060.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60d7400] >[752060.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60d7400] width 1280 pitch 5120 (/4 1280) >[752060.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6179ca0] >[752060.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6179ca0] width 1280 pitch 5120 (/4 1280) >[752125.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6178950] >[752125.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6178950] width 1280 pitch 5120 (/4 1280) >[752125.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f53310] >[752125.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f53310] width 1280 pitch 5120 (/4 1280) >[752146.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616dfd0] >[752146.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616dfd0] width 1280 pitch 5120 (/4 1280) >[752146.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x601e7d0] >[752146.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x601e7d0] width 1280 pitch 5120 (/4 1280) >[752178.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6181b70] >[752178.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6181b70] width 1280 pitch 5120 (/4 1280) >[752188.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604fa60] >[752188.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604fa60] width 1280 pitch 5120 (/4 1280) >[752188.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6181b70] >[752188.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6181b70] width 1280 pitch 5120 (/4 1280) >[752188.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61aba60] >[752188.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61aba60] width 1280 pitch 5120 (/4 1280) >[752188.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x619c7b0] >[752188.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x619c7b0] width 1280 pitch 5120 (/4 1280) >[752265.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604c490] >[752265.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604c490] width 1280 pitch 5120 (/4 1280) >[752265.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604bb50] >[752265.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604bb50] width 1280 pitch 5120 (/4 1280) >[752265.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604c490] >[752265.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604c490] width 1280 pitch 5120 (/4 1280) >[752265.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6056e70] >[752265.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6056e70] width 1280 pitch 5120 (/4 1280) >[752265.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x601e7d0] >[752265.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x601e7d0] width 1280 pitch 5120 (/4 1280) >[752265.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6056e70] >[752265.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6056e70] width 1280 pitch 5120 (/4 1280) >[752265.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604c490] >[752265.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604c490] width 1280 pitch 5120 (/4 1280) >[752265.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616dfd0] >[752265.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616dfd0] width 1280 pitch 5120 (/4 1280) >[752272.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x601e7d0] >[752272.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x601e7d0] width 1280 pitch 5120 (/4 1280) >[752272.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6056e70] >[752272.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6056e70] width 1280 pitch 5120 (/4 1280) >[752379.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752379.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752379.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d11e0] >[752379.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d11e0] width 1280 pitch 5120 (/4 1280) >[752379.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752379.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752379.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752379.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752379.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752379.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752380.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60fb400] >[752380.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60fb400] width 1280 pitch 5120 (/4 1280) >[752380.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7fd30] >[752380.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7fd30] width 1280 pitch 5120 (/4 1280) >[752382.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6183210] >[752382.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6183210] width 1280 pitch 5120 (/4 1280) >[752382.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d11e0] >[752382.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d11e0] width 1280 pitch 5120 (/4 1280) >[752384.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cd5e0] >[752384.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cd5e0] width 1280 pitch 5120 (/4 1280) >[752384.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0bc0] >[752384.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0bc0] width 1280 pitch 5120 (/4 1280) >[752384.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cd5e0] >[752384.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cd5e0] width 1280 pitch 5120 (/4 1280) >[752384.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0bc0] >[752384.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0bc0] width 1280 pitch 5120 (/4 1280) >[752384.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0bc0] >[752384.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0bc0] width 1280 pitch 5120 (/4 1280) >[752384.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61ff230] >[752384.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61ff230] width 1280 pitch 5120 (/4 1280) >[752384.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd650] >[752384.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd650] width 1280 pitch 5120 (/4 1280) >[752385.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61ff230] >[752385.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61ff230] width 1280 pitch 5120 (/4 1280) >[752386.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6202140] >[752386.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6202140] width 1280 pitch 5120 (/4 1280) >[752386.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62020f0] >[752386.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62020f0] width 1280 pitch 5120 (/4 1280) >[752386.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62020f0] >[752386.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62020f0] width 1280 pitch 5120 (/4 1280) >[752386.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cf090] >[752386.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cf090] width 1280 pitch 5120 (/4 1280) >[752386.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60ffeb0] >[752386.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60ffeb0] width 1280 pitch 5120 (/4 1280) >[752386.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752386.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752386.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60ffeb0] >[752386.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60ffeb0] width 1280 pitch 5120 (/4 1280) >[752386.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fef30] >[752386.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fef30] width 1280 pitch 5120 (/4 1280) >[752386.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60ffeb0] >[752386.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60ffeb0] width 1280 pitch 5120 (/4 1280) >[752386.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cf090] >[752386.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cf090] width 1280 pitch 5120 (/4 1280) >[752387.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cf090] >[752387.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cf090] width 1280 pitch 5120 (/4 1280) >[752387.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752387.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752387.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fd600] >[752387.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fd600] width 1280 pitch 5120 (/4 1280) >[752387.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fedc0] >[752387.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fedc0] width 1280 pitch 5120 (/4 1280) >[752387.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60ffeb0] >[752387.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60ffeb0] width 1280 pitch 5120 (/4 1280) >[752387.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61fedc0] >[752387.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61fedc0] width 1280 pitch 5120 (/4 1280) >[752387.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60ffeb0] >[752387.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60ffeb0] width 1280 pitch 5120 (/4 1280) >[752406.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61ff1d0] >[752406.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61ff1d0] width 1280 pitch 5120 (/4 1280) >[752407.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d1100] >[752407.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d1100] width 1280 pitch 5120 (/4 1280) >[752409.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60cb260] >[752409.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60cb260] width 1280 pitch 5120 (/4 1280) >[752409.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104270] >[752409.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104270] width 1280 pitch 5120 (/4 1280) >[752432.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752432.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752432.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752432.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752432.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752432.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752432.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752432.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752432.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752432.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752432.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752432.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752432.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752432.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752433.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752433.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752433.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752433.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752433.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752433.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752433.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752433.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752433.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752433.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752433.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752433.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61047f0] >[752433.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61047f0] width 1280 pitch 5120 (/4 1280) >[752433.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104850] >[752433.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104850] width 1280 pitch 5120 (/4 1280) >[752433.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752433.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752433.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104850] >[752433.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104850] width 1280 pitch 5120 (/4 1280) >[752434.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752434.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752434.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104450] >[752434.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104450] width 1280 pitch 5120 (/4 1280) >[752434.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104450] >[752434.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104450] width 1280 pitch 5120 (/4 1280) >[752434.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0e70] >[752434.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0e70] width 1280 pitch 5120 (/4 1280) >[752434.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0ed0] >[752434.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0ed0] width 1280 pitch 5120 (/4 1280) >[752434.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61043f0] >[752434.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61043f0] width 1280 pitch 5120 (/4 1280) >[752434.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104640] >[752434.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104640] width 1280 pitch 5120 (/4 1280) >[752434.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752434.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6104460] >[752434.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6104460] width 1280 pitch 5120 (/4 1280) >[752434.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61046f0] >[752434.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61046f0] width 1280 pitch 5120 (/4 1280) >[752440.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61dd360] >[752440.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61dd360] width 1280 pitch 5120 (/4 1280) >[752454.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61864c0] >[752454.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61864c0] width 1280 pitch 5120 (/4 1280) >[752458.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6185550] >[752458.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6185550] width 1280 pitch 5120 (/4 1280) >[752904.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61dffa0] >[752904.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61dffa0] width 1280 pitch 5120 (/4 1280) >[752904.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604dce0] >[752904.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604dce0] width 1280 pitch 5120 (/4 1280) >[752905.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61e0130] >[752905.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61e0130] width 1280 pitch 5120 (/4 1280) >[752905.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61dffa0] >[752905.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61dffa0] width 1280 pitch 5120 (/4 1280) >[753342.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61870b0] >[753342.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61870b0] width 1280 pitch 5120 (/4 1280) >[753342.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61894a0] >[753342.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61894a0] width 1280 pitch 5120 (/4 1280) >[753542.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bd390] >[753542.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bd390] width 1280 pitch 5120 (/4 1280) >[753542.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61c5460] >[753542.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61c5460] width 1280 pitch 5120 (/4 1280) >[753640.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61ba820] >[753640.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61ba820] width 1280 pitch 5120 (/4 1280) >[753640.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61ba820] >[753640.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61ba820] width 1280 pitch 5120 (/4 1280) >[754355.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62092b0] >[754355.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62092b0] width 1280 pitch 5120 (/4 1280) >[754356.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620eea0] >[754356.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620eea0] width 1280 pitch 5120 (/4 1280) >[754356.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62092b0] >[754356.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62092b0] width 1280 pitch 5120 (/4 1280) >[754356.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620eea0] >[754356.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620eea0] width 1280 pitch 5120 (/4 1280) >[754366.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6248350] >[754366.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6248350] width 1280 pitch 5120 (/4 1280) >[754366.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620eea0] >[754366.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620eea0] width 1280 pitch 5120 (/4 1280) >[754641.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754641.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754641.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754641.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754641.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754641.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754641.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754641.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754641.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754641.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754641.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754641.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754738.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754738.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754738.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754738.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754738.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754738.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754738.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754738.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754738.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754738.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754738.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754738.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754738.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754738.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754738.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754738.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754739.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754739.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754739.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754739.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754740.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754740.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754740.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754740.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754740.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754740.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754740.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754740.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754740.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754740.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754740.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754740.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253a80] >[754741.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253a80] width 1280 pitch 5120 (/4 1280) >[754741.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6253d10] >[754741.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6253d10] width 1280 pitch 5120 (/4 1280) >[754741.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754741.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754741.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754741.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754741.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754741.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754741.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754741.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754741.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61bf990] >[754741.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61bf990] width 1280 pitch 5120 (/4 1280) >[754741.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754741.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754839.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754839.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754839.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754839.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754839.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754840.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754840.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754840.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754840.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754840.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754840.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754840.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754840.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754840.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754840.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754840.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754840.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754840.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754840.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754840.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754840.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754841.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754841.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754841.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754841.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754841.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754841.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754841.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754841.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754841.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754841.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754841.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754841.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754841.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754841.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754842.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754842.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243510] >[754842.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243510] width 1280 pitch 5120 (/4 1280) >[754842.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754842.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754842.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754842.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754842.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754842.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754842.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754842.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754842.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754842.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754842.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6258430] >[754842.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6258430] width 1280 pitch 5120 (/4 1280) >[754842.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754842.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754844.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754844.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754844.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754844.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754844.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754844.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754844.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754844.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754844.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754844.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754844.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754844.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754844.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754844.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754844.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754844.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754844.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754844.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754844.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754845.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754845.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754845.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754845.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754845.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754845.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754845.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754845.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754845.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754845.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754847.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754847.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754847.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754847.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754848.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754848.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754848.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754848.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754848.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754848.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754853.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754853.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754853.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754853.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754853.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754853.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754853.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754853.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754853.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754853.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754853.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754853.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754853.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754853.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754853.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754853.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754853.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754853.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754853.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754853.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754853.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754853.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754853.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754853.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754854.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754854.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754854.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754854.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754854.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754854.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754854.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754854.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754854.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754854.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754854.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754854.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754854.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754854.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754854.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754854.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754854.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754854.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754854.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754854.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754854.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754854.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754854.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754854.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754854.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754854.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754854.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754854.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754854.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754854.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754854.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754854.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754854.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754855.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754855.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754855.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754855.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754855.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754855.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6212f00] >[754855.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6212f00] width 1280 pitch 5120 (/4 1280) >[754855.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754855.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754855.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754855.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754855.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754855.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754855.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754855.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754855.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754855.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754855.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62450a0] >[754855.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62450a0] width 1280 pitch 5120 (/4 1280) >[754856.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61df020] >[754856.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61df020] width 1280 pitch 5120 (/4 1280) >[754857.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754857.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754857.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754857.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754857.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754857.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754857.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754858.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754858.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754858.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754858.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754858.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754858.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6244e90] >[754858.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6244e90] width 1280 pitch 5120 (/4 1280) >[754858.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620e530] >[754858.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620e530] width 1280 pitch 5120 (/4 1280) >[754858.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754858.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754858.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754858.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754858.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754858.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754858.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754858.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[754858.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6243330] >[754858.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6243330] width 1280 pitch 5120 (/4 1280) >[754864.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e9f950] >[754864.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e9f950] width 1280 pitch 5120 (/4 1280) >[755016.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62694a0] >[755016.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62694a0] width 1280 pitch 5120 (/4 1280) >[755016.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6092800] >[755016.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6092800] width 1280 pitch 5120 (/4 1280) >[755069.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62519b0] >[755069.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62519b0] width 1280 pitch 5120 (/4 1280) >[755069.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608f7b0] >[755069.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608f7b0] width 1280 pitch 5120 (/4 1280) >[755355.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6260970] >[755355.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6260970] width 1280 pitch 5120 (/4 1280) >[755355.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x617ab30] >[755355.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x617ab30] width 1280 pitch 5120 (/4 1280) >[755355.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x625e340] >[755355.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x625e340] width 1280 pitch 5120 (/4 1280) >[755355.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x617ab30] >[755355.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x617ab30] width 1280 pitch 5120 (/4 1280) >[755398.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61cfa60] >[755398.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61cfa60] width 1280 pitch 5120 (/4 1280) >[755398.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6211bf0] >[755398.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6211bf0] width 1280 pitch 5120 (/4 1280) >[755401.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6263a20] >[755401.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6263a20] width 1280 pitch 5120 (/4 1280) >[755402.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x602c970] >[755402.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x602c970] width 1280 pitch 5120 (/4 1280) >[755409.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6263a20] >[755409.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6263a20] width 1280 pitch 5120 (/4 1280) >[755409.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6260970] >[755409.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6260970] width 1280 pitch 5120 (/4 1280) >[755409.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x625e340] >[755409.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x625e340] width 1280 pitch 5120 (/4 1280) >[755410.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6264070] >[755410.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6264070] width 1280 pitch 5120 (/4 1280) >[755691.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6032a50] >[755691.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6032a50] width 1280 pitch 5120 (/4 1280) >[755691.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6029ed0] >[755691.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6029ed0] width 1280 pitch 5120 (/4 1280) >[755919.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x625b520] >[755919.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x625b520] width 1280 pitch 5120 (/4 1280) >[755919.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x602e640] >[755919.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x602e640] width 1280 pitch 5120 (/4 1280) >[756502.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6281e00] >[756502.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6281e00] width 1280 pitch 5120 (/4 1280) >[756515.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6281e00] >[756515.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6281e00] width 1280 pitch 5120 (/4 1280) >[756959.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[756959.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757007.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757007.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757007.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757007.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757007.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757007.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x632be20] >[757007.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x632be20] width 1280 pitch 5120 (/4 1280) >[757007.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757007.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757007.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6205de0] >[757007.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6205de0] width 1280 pitch 5120 (/4 1280) >[757007.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757007.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757007.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6205de0] >[757007.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6205de0] width 1280 pitch 5120 (/4 1280) >[757007.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757007.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757007.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620d530] >[757007.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620d530] width 1280 pitch 5120 (/4 1280) >[757007.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757007.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757007.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757007.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757007.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757007.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757007.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757007.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757007.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757007.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757007.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757007.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757007.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757007.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757007.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757007.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757007.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757007.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757007.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757007.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757008.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757008.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757008.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757008.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757009.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757009.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757009.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757009.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757009.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757009.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757009.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757009.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757009.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757009.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757009.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604d2f0] >[757009.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604d2f0] width 1280 pitch 5120 (/4 1280) >[757009.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d5e770] >[757009.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d5e770] width 1280 pitch 5120 (/4 1280) >[757010.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620d530] >[757010.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620d530] width 1280 pitch 5120 (/4 1280) >[757010.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757010.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757011.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757011.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757011.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604d2f0] >[757011.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604d2f0] width 1280 pitch 5120 (/4 1280) >[757012.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604d2f0] >[757012.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604d2f0] width 1280 pitch 5120 (/4 1280) >[757012.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757012.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757012.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6205de0] >[757012.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6205de0] width 1280 pitch 5120 (/4 1280) >[757012.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757012.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757012.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757012.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757012.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757012.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757012.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6205de0] >[757012.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6205de0] width 1280 pitch 5120 (/4 1280) >[757019.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757019.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757019.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620d530] >[757019.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620d530] width 1280 pitch 5120 (/4 1280) >[757019.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x632be20] >[757019.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x632be20] width 1280 pitch 5120 (/4 1280) >[757019.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757019.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757019.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604d2f0] >[757019.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604d2f0] width 1280 pitch 5120 (/4 1280) >[757020.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6205de0] >[757020.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6205de0] width 1280 pitch 5120 (/4 1280) >[757020.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757020.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757020.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757020.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757057.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757057.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757057.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757057.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757057.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x632be20] >[757057.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x632be20] width 1280 pitch 5120 (/4 1280) >[757057.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5aba0] >[757057.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5aba0] width 1280 pitch 5120 (/4 1280) >[757060.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757060.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757060.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757060.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757060.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x638adb0] >[757060.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x638adb0] width 1280 pitch 5120 (/4 1280) >[757060.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60e5d60] >[757060.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60e5d60] width 1280 pitch 5120 (/4 1280) >[757060.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x604d2f0] >[757060.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x604d2f0] width 1280 pitch 5120 (/4 1280) >[757120.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x620d530] >[757120.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x620d530] width 1280 pitch 5120 (/4 1280) >[757120.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6329170] >[757120.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6329170] width 1280 pitch 5120 (/4 1280) >[757447.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757447.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757447.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e7b0] >[757447.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e7b0] width 1280 pitch 5120 (/4 1280) >[757447.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757447.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757447.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e7b0] >[757447.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e7b0] width 1280 pitch 5120 (/4 1280) >[757447.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757447.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757447.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e7b0] >[757447.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e7b0] width 1280 pitch 5120 (/4 1280) >[757447.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757447.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757447.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757447.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757447.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633af10] >[757447.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633af10] width 1280 pitch 5120 (/4 1280) >[757447.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757447.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e7b0] >[757448.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e7b0] width 1280 pitch 5120 (/4 1280) >[757448.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757448.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757448.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e520] >[757448.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e520] width 1280 pitch 5120 (/4 1280) >[757448.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757448.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757448.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e520] >[757448.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e520] width 1280 pitch 5120 (/4 1280) >[757448.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757448.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757448.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e520] >[757448.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e520] width 1280 pitch 5120 (/4 1280) >[757448.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757448.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757448.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633e520] >[757448.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633e520] width 1280 pitch 5120 (/4 1280) >[757448.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6339f80] >[757448.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6339f80] width 1280 pitch 5120 (/4 1280) >[757448.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757448.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633b750] >[757448.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633b750] width 1280 pitch 5120 (/4 1280) >[757448.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633a4a0] >[757448.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633a4a0] width 1280 pitch 5120 (/4 1280) >[757534.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6178fd0] >[757534.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6178fd0] width 1280 pitch 5120 (/4 1280) >[757534.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x633f010] >[757534.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x633f010] width 1280 pitch 5120 (/4 1280) >[757707.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6419b90] >[757707.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6419b90] width 1280 pitch 5120 (/4 1280) >[757707.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x622ba00] >[757707.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x622ba00] width 1280 pitch 5120 (/4 1280) >[757743.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6029200] >[757743.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6029200] width 1280 pitch 5120 (/4 1280) >[757743.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x622ce90] >[757743.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x622ce90] width 1280 pitch 5120 (/4 1280) >[757744.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x622ce90] >[757744.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x622ce90] width 1280 pitch 5120 (/4 1280) >[757744.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6417ae0] >[757744.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6417ae0] width 1280 pitch 5120 (/4 1280) >[757880.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x623d0c0] >[757880.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x623d0c0] width 1280 pitch 5120 (/4 1280) >[757880.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x634a9b0] >[757880.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x634a9b0] width 1280 pitch 5120 (/4 1280) >[757882.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6231110] >[757882.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6231110] width 1280 pitch 5120 (/4 1280) >[757883.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x616cd90] >[757883.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x616cd90] width 1280 pitch 5120 (/4 1280) >[757885.471] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[757885.479] (II) RADEON(0): Printing DDC gathered Modelines: >[757885.479] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[758484.092] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[758484.092] (II) RADEON(0): Printing DDC gathered Modelines: >[758484.092] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[758573.919] (II) RADEON(0): RADEONSaveScreen(2) >[758573.924] (II) RADEON(0): RADEONSaveScreen(0) >[760698.802] (II) RADEON(0): RADEONSaveScreen(1) >[760707.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64156d0] >[760707.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64156d0] width 1280 pitch 5120 (/4 1280) >[760708.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a2430] >[760708.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a2430] width 1280 pitch 5120 (/4 1280) >[760708.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bef190] >[760709.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bef190] width 1280 pitch 5120 (/4 1280) >[760709.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fdbc30] >[760709.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fdbc30] width 1280 pitch 5120 (/4 1280) >[760709.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dfdfc0] >[760709.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dfdfc0] width 1280 pitch 5120 (/4 1280) >[760709.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x619fe60] >[760709.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x619fe60] width 1280 pitch 5120 (/4 1280) >[760709.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a27b0] >[760709.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a27b0] width 1280 pitch 5120 (/4 1280) >[760710.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64156d0] >[760710.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64156d0] width 1280 pitch 5120 (/4 1280) >[760710.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dfa610] >[760710.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dfa610] width 1280 pitch 5120 (/4 1280) >[760710.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d7f800] >[760711.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d7f800] width 1280 pitch 5120 (/4 1280) >[760711.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x606f4b0] >[760711.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x606f4b0] width 1280 pitch 5120 (/4 1280) >[760711.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bef190] >[760711.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bef190] width 1280 pitch 5120 (/4 1280) >[760711.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a2510] >[760711.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a2510] width 1280 pitch 5120 (/4 1280) >[760711.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fdbc30] >[760711.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fdbc30] width 1280 pitch 5120 (/4 1280) >[760711.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bef190] >[760711.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bef190] width 1280 pitch 5120 (/4 1280) >[761261.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x640d6d0] >[761261.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x640d6d0] width 1280 pitch 5120 (/4 1280) >[761262.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x640d9e0] >[761262.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x640d9e0] width 1280 pitch 5120 (/4 1280) >[761474.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x640d9e0] >[761474.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x640d9e0] width 1280 pitch 5120 (/4 1280) >[761474.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x640d9e0] >[761474.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x640d9e0] width 1280 pitch 5120 (/4 1280) >[761895.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6413ef0] >[761895.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6413ef0] width 1280 pitch 5120 (/4 1280) >[761895.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d340] >[761895.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d340] width 1280 pitch 5120 (/4 1280) >[761968.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62862f0] >[761968.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62862f0] width 1280 pitch 5120 (/4 1280) >[761968.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d340] >[761968.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d340] width 1280 pitch 5120 (/4 1280) >[763530.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763530.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763531.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763531.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763531.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763531.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763531.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763531.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763531.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763531.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763531.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763531.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763531.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763531.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763531.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763531.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763531.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763531.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763532.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763532.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763532.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763532.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763532.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763532.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763532.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763532.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763532.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763532.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763532.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763532.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763532.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763532.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763532.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763532.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763532.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763533.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763533.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763534.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763534.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763534.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6454510] >[763534.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6454510] width 1280 pitch 5120 (/4 1280) >[763534.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763534.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763534.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763534.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763534.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763534.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763535.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763535.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763535.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763535.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763536.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763536.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763536.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763536.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763536.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763553.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763553.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e09370] >[763616.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e09370] width 1280 pitch 5120 (/4 1280) >[763616.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6249940] >[763616.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6249940] width 1280 pitch 5120 (/4 1280) >[763616.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e09370] >[763616.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e09370] width 1280 pitch 5120 (/4 1280) >[763616.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6249940] >[763616.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6249940] width 1280 pitch 5120 (/4 1280) >[763616.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e09370] >[763616.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e09370] width 1280 pitch 5120 (/4 1280) >[763616.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6249940] >[763616.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6249940] width 1280 pitch 5120 (/4 1280) >[763616.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e09370] >[763616.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e09370] width 1280 pitch 5120 (/4 1280) >[763616.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6249940] >[763616.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6249940] width 1280 pitch 5120 (/4 1280) >[763616.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e09370] >[763616.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e09370] width 1280 pitch 5120 (/4 1280) >[763616.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6249940] >[763616.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6249940] width 1280 pitch 5120 (/4 1280) >[763616.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763616.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763616.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763616.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763616.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763616.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763616.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763616.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763616.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763616.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6464fc0] >[763616.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6464fc0] width 1280 pitch 5120 (/4 1280) >[763616.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763616.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763617.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x645c300] >[763617.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x645c300] width 1280 pitch 5120 (/4 1280) >[763618.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763618.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763618.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763618.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763618.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763618.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763618.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763618.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763618.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763618.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763618.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ef210] >[763618.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ef210] width 1280 pitch 5120 (/4 1280) >[763618.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763618.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763618.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763618.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63fde70] >[763618.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63fde70] width 1280 pitch 5120 (/4 1280) >[763622.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763622.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763627.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64573e0] >[763627.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64573e0] width 1280 pitch 5120 (/4 1280) >[763627.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x632e500] >[763627.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x632e500] width 1280 pitch 5120 (/4 1280) >[763629.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6435f10] >[763629.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6435f10] width 1280 pitch 5120 (/4 1280) >[763630.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763630.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763671.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60472d0] >[763671.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60472d0] width 1280 pitch 5120 (/4 1280) >[763671.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6435f10] >[763671.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6435f10] width 1280 pitch 5120 (/4 1280) >[763716.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763716.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763717.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[763717.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[763717.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6435f10] >[763717.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6435f10] width 1280 pitch 5120 (/4 1280) >[763717.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6458d70] >[763717.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6458d70] width 1280 pitch 5120 (/4 1280) >[763717.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6435f10] >[763717.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6435f10] width 1280 pitch 5120 (/4 1280) >[763720.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[763720.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[763720.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60472d0] >[763720.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60472d0] width 1280 pitch 5120 (/4 1280) >[763720.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dff5d0] >[763720.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dff5d0] width 1280 pitch 5120 (/4 1280) >[763720.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64550e0] >[763720.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64550e0] width 1280 pitch 5120 (/4 1280) >[764327.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764327.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764327.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764327.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764327.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764327.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764327.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764327.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764327.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764327.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764327.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764327.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764327.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764327.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764327.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764327.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764327.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764328.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764328.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764328.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764328.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764328.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764328.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764328.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764328.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764328.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764328.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764328.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764328.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764328.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764328.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764328.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764328.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764328.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d4e40] >[764328.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d4e40] width 1280 pitch 5120 (/4 1280) >[764328.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764328.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764328.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764329.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764329.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764329.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764329.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764329.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764329.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764329.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764329.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764329.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764329.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764329.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764329.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764329.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764329.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764335.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764335.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764352.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764352.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764352.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64519c0] >[764352.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64519c0] width 1280 pitch 5120 (/4 1280) >[764366.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764366.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764366.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764366.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764366.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764366.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764366.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764366.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764366.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764366.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764366.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764366.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764366.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764367.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764367.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764367.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764367.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764367.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764367.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764367.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764367.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764367.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764367.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764367.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764368.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764368.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764368.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764368.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764368.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6493330] >[764368.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6493330] width 1280 pitch 5120 (/4 1280) >[764368.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764368.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764369.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d23e0] >[764369.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d23e0] width 1280 pitch 5120 (/4 1280) >[764369.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764369.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764369.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764369.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764369.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc580] >[764369.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc580] width 1280 pitch 5120 (/4 1280) >[764369.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764369.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x648af10] >[764370.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x648af10] width 1280 pitch 5120 (/4 1280) >[764370.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f5ab20] >[764370.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f5ab20] width 1280 pitch 5120 (/4 1280) >[764370.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764370.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764370.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764370.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764370.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764370.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764370.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764370.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764370.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63445a0] >[764371.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63445a0] width 1280 pitch 5120 (/4 1280) >[764371.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6488790] >[764371.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6488790] width 1280 pitch 5120 (/4 1280) >[764371.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63445a0] >[764371.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63445a0] width 1280 pitch 5120 (/4 1280) >[764371.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764371.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764371.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764371.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764371.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764371.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764371.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6465090] >[764372.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6465090] width 1280 pitch 5120 (/4 1280) >[764372.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764372.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764372.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764372.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764372.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764372.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764372.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764372.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764372.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764372.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764372.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764372.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64996b0] >[764372.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64996b0] width 1280 pitch 5120 (/4 1280) >[764373.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6488790] >[764373.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6488790] width 1280 pitch 5120 (/4 1280) >[764374.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6488790] >[764374.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6488790] width 1280 pitch 5120 (/4 1280) >[764374.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764374.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764375.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764375.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764375.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764375.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764376.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764376.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764376.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764376.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764376.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764376.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764377.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764377.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764377.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764377.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764378.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764378.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764378.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608c750] >[764378.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608c750] width 1280 pitch 5120 (/4 1280) >[764378.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de2c0] >[764378.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de2c0] width 1280 pitch 5120 (/4 1280) >[764635.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764635.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764635.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764635.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764635.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764635.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764635.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764635.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764636.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764636.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764636.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764636.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764637.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764637.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764637.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764637.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764641.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62dc360] >[764641.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62dc360] width 1280 pitch 5120 (/4 1280) >[764641.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764641.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764732.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764732.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764732.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d42e0] >[764732.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d42e0] width 1280 pitch 5120 (/4 1280) >[764732.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764732.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764732.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d42e0] >[764732.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d42e0] width 1280 pitch 5120 (/4 1280) >[764732.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764732.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764732.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764732.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764732.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646a520] >[764732.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646a520] width 1280 pitch 5120 (/4 1280) >[764732.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764732.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764732.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646a520] >[764732.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646a520] width 1280 pitch 5120 (/4 1280) >[764732.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764732.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764732.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764732.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764732.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764732.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764732.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764732.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764733.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x643ef00] >[764733.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x643ef00] width 1280 pitch 5120 (/4 1280) >[764733.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64599a0] >[764733.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64599a0] width 1280 pitch 5120 (/4 1280) >[764734.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x646d650] >[764734.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x646d650] width 1280 pitch 5120 (/4 1280) >[764735.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64093a0] >[764735.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64093a0] width 1280 pitch 5120 (/4 1280) >[765183.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c42a0] >[765183.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c42a0] width 1280 pitch 5120 (/4 1280) >[765587.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9dc0] >[765587.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9dc0] width 1280 pitch 5120 (/4 1280) >[765587.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765587.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765587.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765588.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765588.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765588.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765588.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765588.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765588.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9dc0] >[765588.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9dc0] width 1280 pitch 5120 (/4 1280) >[765588.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765588.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765588.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9dc0] >[765588.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9dc0] width 1280 pitch 5120 (/4 1280) >[765588.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765588.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765588.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9dc0] >[765588.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9dc0] width 1280 pitch 5120 (/4 1280) >[765588.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765588.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765589.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765589.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765589.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c78e0] >[765589.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c78e0] width 1280 pitch 5120 (/4 1280) >[765589.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765589.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765589.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c78e0] >[765589.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c78e0] width 1280 pitch 5120 (/4 1280) >[765589.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765589.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765589.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c78e0] >[765589.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c78e0] width 1280 pitch 5120 (/4 1280) >[765589.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765589.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765589.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c78e0] >[765589.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c78e0] width 1280 pitch 5120 (/4 1280) >[765589.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765589.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765589.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c78e0] >[765589.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c78e0] width 1280 pitch 5120 (/4 1280) >[765589.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765589.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765589.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6416490] >[765589.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6416490] width 1280 pitch 5120 (/4 1280) >[765589.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765589.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765589.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765589.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765589.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765589.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765589.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9dc0] >[765589.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9dc0] width 1280 pitch 5120 (/4 1280) >[765589.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765590.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765590.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b9840] >[765590.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b9840] width 1280 pitch 5120 (/4 1280) >[765590.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6416490] >[765590.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6416490] width 1280 pitch 5120 (/4 1280) >[765590.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765590.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63c61d0] >[765590.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63c61d0] width 1280 pitch 5120 (/4 1280) >[765590.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63b7d00] >[765590.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63b7d00] width 1280 pitch 5120 (/4 1280) >[765593.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6416490] >[765593.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6416490] width 1280 pitch 5120 (/4 1280) >[766112.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6425310] >[766112.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6425310] width 1280 pitch 5120 (/4 1280) >[766112.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6425230] >[766112.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6425230] width 1280 pitch 5120 (/4 1280) >[766140.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495df0] >[766140.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495df0] width 1280 pitch 5120 (/4 1280) >[766140.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x61d0bc0] >[766140.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x61d0bc0] width 1280 pitch 5120 (/4 1280) >[766141.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495df0] >[766141.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495df0] width 1280 pitch 5120 (/4 1280) >[766741.584] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[766741.584] (II) RADEON(0): Printing DDC gathered Modelines: >[766741.584] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[766831.904] (II) RADEON(0): RADEONSaveScreen(2) >[766831.908] (II) RADEON(0): RADEONSaveScreen(0) >[766888.447] (II) RADEON(0): RADEONSaveScreen(1) >[766901.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766901.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766902.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766902.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766902.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766902.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766902.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766902.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766903.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766903.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766903.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766903.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766903.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766903.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766903.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766903.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766903.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766903.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766903.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766903.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766904.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766904.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766904.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766904.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766904.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766904.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766904.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766904.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766904.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766904.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766904.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766905.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766905.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766905.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766905.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766905.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766905.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766905.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766905.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766905.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766905.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766905.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766906.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766906.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766906.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766906.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766906.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766906.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766906.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766907.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766907.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766907.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766926.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766926.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766926.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766926.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766926.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766926.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766926.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766926.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766926.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766926.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766926.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766926.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766926.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62cf6c0] >[766926.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62cf6c0] width 1280 pitch 5120 (/4 1280) >[766927.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62cf6c0] >[766927.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62cf6c0] width 1280 pitch 5120 (/4 1280) >[766927.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62cf6c0] >[766927.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62cf6c0] width 1280 pitch 5120 (/4 1280) >[766927.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62cf6c0] >[766927.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62cf6c0] width 1280 pitch 5120 (/4 1280) >[766927.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766927.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766927.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766927.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766927.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766927.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766927.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766927.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766927.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62cf6c0] >[766927.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62cf6c0] width 1280 pitch 5120 (/4 1280) >[766927.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766927.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766927.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495cd0] >[766927.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495cd0] width 1280 pitch 5120 (/4 1280) >[766927.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766927.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766927.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766927.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766927.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766927.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766927.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766928.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766928.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766929.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766930.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766930.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766930.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766930.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495bc0] >[766930.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495bc0] width 1280 pitch 5120 (/4 1280) >[766930.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766930.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766930.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766930.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766932.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766932.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766932.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ea430] >[766932.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ea430] width 1280 pitch 5120 (/4 1280) >[766932.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766932.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766943.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642a9b0] >[766943.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642a9b0] width 1280 pitch 5120 (/4 1280) >[766944.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766944.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766944.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766944.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766944.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6176810] >[766944.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6176810] width 1280 pitch 5120 (/4 1280) >[766944.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60bbb10] >[766944.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60bbb10] width 1280 pitch 5120 (/4 1280) >[766945.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ba860] >[766945.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ba860] width 1280 pitch 5120 (/4 1280) >[766949.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642a9b0] >[766949.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642a9b0] width 1280 pitch 5120 (/4 1280) >[766949.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62c5920] >[766950.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62c5920] width 1280 pitch 5120 (/4 1280) >[766950.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6495bc0] >[766950.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6495bc0] width 1280 pitch 5120 (/4 1280) >[767111.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767111.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767111.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767111.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767111.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767111.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767111.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767111.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767112.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767112.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767114.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767114.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767114.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767114.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767114.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767114.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767114.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767114.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767115.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767115.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767117.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767117.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767117.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767117.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767118.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767118.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767118.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767118.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767118.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767118.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767118.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767118.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767120.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767120.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767120.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767120.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767120.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767120.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767121.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767121.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767121.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd270] >[767121.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd270] width 1280 pitch 5120 (/4 1280) >[767121.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767121.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767121.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd270] >[767121.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd270] width 1280 pitch 5120 (/4 1280) >[767121.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767121.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767147.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767147.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767147.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629e8e0] >[767147.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629e8e0] width 1280 pitch 5120 (/4 1280) >[767149.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767149.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767164.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629dfb0] >[767164.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629dfb0] width 1280 pitch 5120 (/4 1280) >[767164.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cdb00] >[767164.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cdb00] width 1280 pitch 5120 (/4 1280) >[767165.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767165.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767165.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629dfb0] >[767165.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629dfb0] width 1280 pitch 5120 (/4 1280) >[767165.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767165.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767165.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767165.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767166.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767166.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767169.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a13c0] >[767169.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a13c0] width 1280 pitch 5120 (/4 1280) >[767169.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767169.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767170.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767170.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767170.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767170.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767171.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767171.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767171.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767171.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767171.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767171.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767171.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767171.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767171.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767171.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767171.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767171.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767171.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767171.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767171.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767171.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767172.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767172.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767172.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767172.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63cd4b0] >[767172.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63cd4b0] width 1280 pitch 5120 (/4 1280) >[767172.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767172.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767172.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767172.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767172.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767173.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767173.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767173.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767173.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767173.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767173.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767173.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767173.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767173.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767173.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767173.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767173.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767173.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767179.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d1210] >[767179.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d1210] width 1280 pitch 5120 (/4 1280) >[767184.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64856b0] >[767184.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64856b0] width 1280 pitch 5120 (/4 1280) >[767184.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64856b0] >[767184.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64856b0] width 1280 pitch 5120 (/4 1280) >[767184.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767184.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767184.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ca1b0] >[767184.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ca1b0] width 1280 pitch 5120 (/4 1280) >[767188.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64856b0] >[767188.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64856b0] width 1280 pitch 5120 (/4 1280) >[767188.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a0ac0] >[767188.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a0ac0] width 1280 pitch 5120 (/4 1280) >[767243.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6298140] >[767243.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6298140] width 1280 pitch 5120 (/4 1280) >[767243.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65110f0] >[767243.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65110f0] width 1280 pitch 5120 (/4 1280) >[767243.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6513620] >[767243.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6513620] width 1280 pitch 5120 (/4 1280) >[767243.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6298140] >[767243.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6298140] width 1280 pitch 5120 (/4 1280) >[767246.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6298140] >[767246.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6298140] width 1280 pitch 5120 (/4 1280) >[767246.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65110f0] >[767246.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65110f0] width 1280 pitch 5120 (/4 1280) >[767246.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6513620] >[767246.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6513620] width 1280 pitch 5120 (/4 1280) >[767246.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65110f0] >[767246.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65110f0] width 1280 pitch 5120 (/4 1280) >[767254.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767254.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6511270] >[767254.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6511270] width 1280 pitch 5120 (/4 1280) >[767254.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767254.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767255.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6511270] >[767255.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6511270] width 1280 pitch 5120 (/4 1280) >[767255.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0750] >[767255.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0750] width 1280 pitch 5120 (/4 1280) >[767255.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0b80] >[767255.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0b80] width 1280 pitch 5120 (/4 1280) >[767255.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767255.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767255.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0b80] >[767255.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0b80] width 1280 pitch 5120 (/4 1280) >[767255.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767255.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767255.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0b80] >[767255.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0b80] width 1280 pitch 5120 (/4 1280) >[767255.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767255.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767255.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d0b80] >[767255.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d0b80] width 1280 pitch 5120 (/4 1280) >[767255.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767255.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767255.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767255.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767256.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767256.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767256.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63debb0] >[767256.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63debb0] width 1280 pitch 5120 (/4 1280) >[767259.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6298140] >[767259.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6298140] width 1280 pitch 5120 (/4 1280) >[767446.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63d3210] >[767446.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63d3210] width 1280 pitch 5120 (/4 1280) >[767446.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64257a0] >[767446.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64257a0] width 1280 pitch 5120 (/4 1280) >[767452.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6298140] >[767452.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6298140] width 1280 pitch 5120 (/4 1280) >[767452.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x576b7f0] >[767452.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x576b7f0] width 1280 pitch 5120 (/4 1280) >[767845.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[767845.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[767847.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aabe0] >[767847.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aabe0] width 1280 pitch 5120 (/4 1280) >[767847.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62d99e0] >[767847.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62d99e0] width 1280 pitch 5120 (/4 1280) >[767847.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[767847.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[767847.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6321200] >[767847.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6321200] width 1280 pitch 5120 (/4 1280) >[767847.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[767847.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[767848.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63508c0] >[767848.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63508c0] width 1280 pitch 5120 (/4 1280) >[767848.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64b5000] >[767848.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64b5000] width 1280 pitch 5120 (/4 1280) >[767848.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63508c0] >[767848.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63508c0] width 1280 pitch 5120 (/4 1280) >[767851.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af7290] >[767851.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af7290] width 1280 pitch 5120 (/4 1280) >[767854.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767854.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767854.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767854.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767854.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64b5000] >[767854.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64b5000] width 1280 pitch 5120 (/4 1280) >[767854.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767854.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767859.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6511db0] >[767859.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6511db0] width 1280 pitch 5120 (/4 1280) >[767863.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6511db0] >[767863.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6511db0] width 1280 pitch 5120 (/4 1280) >[767863.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767863.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767863.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767863.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767863.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767863.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767863.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767863.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767863.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767863.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767863.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767863.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767863.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767863.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767863.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767863.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767863.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767864.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767864.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767864.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767864.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767864.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767864.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767864.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767864.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aa730] >[767864.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aa730] width 1280 pitch 5120 (/4 1280) >[767864.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9d80] >[767864.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9d80] width 1280 pitch 5120 (/4 1280) >[767865.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x650f530] >[767865.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x650f530] width 1280 pitch 5120 (/4 1280) >[767865.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x650f530] >[767865.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x650f530] width 1280 pitch 5120 (/4 1280) >[767865.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a9b10] >[767865.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a9b10] width 1280 pitch 5120 (/4 1280) >[767872.128] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[767872.128] (II) RADEON(0): Printing DDC gathered Modelines: >[767872.128] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[768471.975] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[768471.975] (II) RADEON(0): Printing DDC gathered Modelines: >[768471.975] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[768561.902] (II) RADEON(0): RADEONSaveScreen(2) >[768561.902] (II) RADEON(0): RADEONSaveScreen(0) >[800850.734] (II) RADEON(0): RADEONSaveScreen(1) >[800860.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b390] >[800860.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b390] width 1280 pitch 5120 (/4 1280) >[800861.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800861.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800861.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62ac610] >[800861.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62ac610] width 1280 pitch 5120 (/4 1280) >[800861.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x650ca50] >[800861.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x650ca50] width 1280 pitch 5120 (/4 1280) >[800861.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afb150] >[800861.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afb150] width 1280 pitch 5120 (/4 1280) >[800861.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c842b0] >[800861.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c842b0] width 1280 pitch 5120 (/4 1280) >[800861.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b390] >[800861.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b390] width 1280 pitch 5120 (/4 1280) >[800861.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x653db50] >[800861.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x653db50] width 1280 pitch 5120 (/4 1280) >[800861.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800861.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800861.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62e39e0] >[800861.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62e39e0] width 1280 pitch 5120 (/4 1280) >[800861.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64d9e80] >[800861.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64d9e80] width 1280 pitch 5120 (/4 1280) >[800861.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b390] >[800861.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b390] width 1280 pitch 5120 (/4 1280) >[800861.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c842b0] >[800861.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c842b0] width 1280 pitch 5120 (/4 1280) >[800861.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62e39e0] >[800861.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62e39e0] width 1280 pitch 5120 (/4 1280) >[800861.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800862.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800862.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x653db50] >[800862.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x653db50] width 1280 pitch 5120 (/4 1280) >[800862.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62ac610] >[800862.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62ac610] width 1280 pitch 5120 (/4 1280) >[800862.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c842b0] >[800862.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c842b0] width 1280 pitch 5120 (/4 1280) >[800862.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64d9e80] >[800862.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64d9e80] width 1280 pitch 5120 (/4 1280) >[800862.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800862.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800862.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62ac610] >[800862.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62ac610] width 1280 pitch 5120 (/4 1280) >[800862.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800862.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800862.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800862.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800862.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c842b0] >[800862.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c842b0] width 1280 pitch 5120 (/4 1280) >[800862.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64d9e80] >[800862.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64d9e80] width 1280 pitch 5120 (/4 1280) >[800862.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b390] >[800862.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b390] width 1280 pitch 5120 (/4 1280) >[800862.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62e39e0] >[800862.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62e39e0] width 1280 pitch 5120 (/4 1280) >[800862.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64d9e80] >[800862.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64d9e80] width 1280 pitch 5120 (/4 1280) >[800862.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b390] >[800862.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b390] width 1280 pitch 5120 (/4 1280) >[800862.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a6720] >[800862.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a6720] width 1280 pitch 5120 (/4 1280) >[800862.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800862.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800862.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x650ca50] >[800862.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x650ca50] width 1280 pitch 5120 (/4 1280) >[800862.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afb150] >[800862.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afb150] width 1280 pitch 5120 (/4 1280) >[800862.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800862.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800862.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62e39e0] >[800862.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62e39e0] width 1280 pitch 5120 (/4 1280) >[800862.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x653db50] >[800862.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x653db50] width 1280 pitch 5120 (/4 1280) >[800868.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64d99b0] >[800868.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64d99b0] width 1280 pitch 5120 (/4 1280) >[800868.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6396cb0] >[800868.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6396cb0] width 1280 pitch 5120 (/4 1280) >[800868.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800868.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800869.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a6720] >[800869.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a6720] width 1280 pitch 5120 (/4 1280) >[800869.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800869.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800870.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800870.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800870.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62e39e0] >[800870.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62e39e0] width 1280 pitch 5120 (/4 1280) >[800870.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c84760] >[800870.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c84760] width 1280 pitch 5120 (/4 1280) >[800874.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62a4590] >[800874.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62a4590] width 1280 pitch 5120 (/4 1280) >[800875.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c05d0] >[800875.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c05d0] width 1280 pitch 5120 (/4 1280) >[800887.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb04f0] >[800887.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb04f0] width 1280 pitch 5120 (/4 1280) >[800887.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64abda0] >[800887.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64abda0] width 1280 pitch 5120 (/4 1280) >[801229.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b7030] >[801229.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b7030] width 1280 pitch 5120 (/4 1280) >[801229.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[801229.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[801419.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x652e8b0] >[801419.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x652e8b0] width 1280 pitch 5120 (/4 1280) >[801419.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x652e8b0] >[801419.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x652e8b0] width 1280 pitch 5120 (/4 1280) >[801706.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[801706.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[801706.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x658f8c0] >[801706.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x658f8c0] width 1280 pitch 5120 (/4 1280) >[801706.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[801706.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[801706.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65719f0] >[801706.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65719f0] width 1280 pitch 5120 (/4 1280) >[801706.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[801706.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[801706.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65719f0] >[801706.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65719f0] width 1280 pitch 5120 (/4 1280) >[801706.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a83a0] >[801706.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a83a0] width 1280 pitch 5120 (/4 1280) >[801706.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6520a50] >[801706.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6520a50] width 1280 pitch 5120 (/4 1280) >[801706.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a83a0] >[801706.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a83a0] width 1280 pitch 5120 (/4 1280) >[801706.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6520a50] >[801706.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6520a50] width 1280 pitch 5120 (/4 1280) >[801878.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65edd70] >[801878.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65edd70] width 1280 pitch 5120 (/4 1280) >[801878.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x651d3a0] >[801878.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x651d3a0] width 1280 pitch 5120 (/4 1280) >[802242.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f7ac0] >[802242.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f7ac0] width 1280 pitch 5120 (/4 1280) >[802242.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[802242.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[802349.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c6730] >[802349.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c6730] width 1280 pitch 5120 (/4 1280) >[802350.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5a30] >[802350.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5a30] width 1280 pitch 5120 (/4 1280) >[802464.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c6b10] >[802464.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c6b10] width 1280 pitch 5120 (/4 1280) >[802464.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5a30] >[802464.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5a30] width 1280 pitch 5120 (/4 1280) >[802555.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f2b50] >[802555.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f2b50] width 1280 pitch 5120 (/4 1280) >[802555.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5a30] >[802555.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5a30] width 1280 pitch 5120 (/4 1280) >[802621.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x651d3a0] >[802622.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x651d3a0] width 1280 pitch 5120 (/4 1280) >[802622.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65863c0] >[802622.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65863c0] width 1280 pitch 5120 (/4 1280) >[802626.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65863c0] >[802626.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65863c0] width 1280 pitch 5120 (/4 1280) >[802626.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6595fc0] >[802626.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6595fc0] width 1280 pitch 5120 (/4 1280) >[802892.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6625850] >[802892.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6625850] width 1280 pitch 5120 (/4 1280) >[802892.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6625850] >[802892.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6625850] width 1280 pitch 5120 (/4 1280) >[802892.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624fe0] >[802892.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624fe0] width 1280 pitch 5120 (/4 1280) >[802892.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[802892.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624fe0] >[802892.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624fe0] width 1280 pitch 5120 (/4 1280) >[802892.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[802892.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624fe0] >[802892.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624fe0] width 1280 pitch 5120 (/4 1280) >[802892.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[802892.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624fe0] >[802892.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624fe0] width 1280 pitch 5120 (/4 1280) >[802892.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[802892.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624fe0] >[802892.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624fe0] width 1280 pitch 5120 (/4 1280) >[802892.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[802892.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661df30] >[802892.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661df30] width 1280 pitch 5120 (/4 1280) >[803338.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[803338.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[803339.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[803339.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[803343.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803343.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803343.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803343.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803343.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803343.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803343.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803343.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803343.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803343.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803343.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803343.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803343.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624cc0] >[803343.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624cc0] width 1280 pitch 5120 (/4 1280) >[803343.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803343.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803343.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803343.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6624cc0] >[803344.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6624cc0] width 1280 pitch 5120 (/4 1280) >[803344.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803344.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803344.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[803344.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[803344.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803344.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803344.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803344.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803344.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x628e400] >[803344.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x628e400] width 1280 pitch 5120 (/4 1280) >[803344.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803344.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803344.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6561530] >[803344.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6561530] width 1280 pitch 5120 (/4 1280) >[803344.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803344.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655dc20] >[803344.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655dc20] width 1280 pitch 5120 (/4 1280) >[803344.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65d1e50] >[803344.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65d1e50] width 1280 pitch 5120 (/4 1280) >[803527.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803527.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803527.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655b690] >[803527.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655b690] width 1280 pitch 5120 (/4 1280) >[803527.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6628e60] >[803527.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6628e60] width 1280 pitch 5120 (/4 1280) >[803528.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803528.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655a150] >[803528.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655a150] width 1280 pitch 5120 (/4 1280) >[803528.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662b620] >[803528.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662b620] width 1280 pitch 5120 (/4 1280) >[803882.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66814e0] >[803882.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66814e0] width 1280 pitch 5120 (/4 1280) >[803882.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6602240] >[803882.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6602240] width 1280 pitch 5120 (/4 1280) >[803886.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6607250] >[803886.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6607250] width 1280 pitch 5120 (/4 1280) >[803887.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x660e0d0] >[803887.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x660e0d0] width 1280 pitch 5120 (/4 1280) >[803892.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6607250] >[803892.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6607250] width 1280 pitch 5120 (/4 1280) >[803929.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64fd970] >[803929.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64fd970] width 1280 pitch 5120 (/4 1280) >[803929.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x660c380] >[803929.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x660c380] width 1280 pitch 5120 (/4 1280) >[803946.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66814e0] >[803946.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66814e0] width 1280 pitch 5120 (/4 1280) >[803947.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x660e0d0] >[803947.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x660e0d0] width 1280 pitch 5120 (/4 1280) >[803948.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6610170] >[803948.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6610170] width 1280 pitch 5120 (/4 1280) >[803948.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6607250] >[803948.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6607250] width 1280 pitch 5120 (/4 1280) >[804433.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804433.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804433.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804433.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804433.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804433.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6612940] >[804433.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6612940] width 1280 pitch 5120 (/4 1280) >[804433.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804433.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804434.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a2700] >[804434.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a2700] width 1280 pitch 5120 (/4 1280) >[804434.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6602240] >[804434.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6602240] width 1280 pitch 5120 (/4 1280) >[804434.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64af0e0] >[804434.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64af0e0] width 1280 pitch 5120 (/4 1280) >[804434.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6602240] >[804434.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6602240] width 1280 pitch 5120 (/4 1280) >[804434.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64af0e0] >[804434.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64af0e0] width 1280 pitch 5120 (/4 1280) >[804434.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6602240] >[804434.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6602240] width 1280 pitch 5120 (/4 1280) >[804434.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64af0e0] >[804434.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64af0e0] width 1280 pitch 5120 (/4 1280) >[804434.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x660c380] >[804434.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x660c380] width 1280 pitch 5120 (/4 1280) >[804434.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608b5a0] >[804434.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608b5a0] width 1280 pitch 5120 (/4 1280) >[804435.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x660c380] >[804435.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x660c380] width 1280 pitch 5120 (/4 1280) >[804437.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x608d540] >[804437.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x608d540] width 1280 pitch 5120 (/4 1280) >[804437.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x60a2700] >[804437.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x60a2700] width 1280 pitch 5120 (/4 1280) >[804439.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6610170] >[804439.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6610170] width 1280 pitch 5120 (/4 1280) >[804439.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6610170] >[804440.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6610170] width 1280 pitch 5120 (/4 1280) >[804440.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x650f000] >[804440.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x650f000] width 1280 pitch 5120 (/4 1280) >[805857.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a24c0] >[805857.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a24c0] width 1280 pitch 5120 (/4 1280) >[805857.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64e1160] >[805857.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64e1160] width 1280 pitch 5120 (/4 1280) >[805916.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x667b170] >[805916.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x667b170] width 1280 pitch 5120 (/4 1280) >[805917.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x667b170] >[805917.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x667b170] width 1280 pitch 5120 (/4 1280) >[806098.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e6dc0] >[806098.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e6dc0] width 1280 pitch 5120 (/4 1280) >[806098.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66558b0] >[806098.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66558b0] width 1280 pitch 5120 (/4 1280) >[806246.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6697440] >[806246.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6697440] width 1280 pitch 5120 (/4 1280) >[806246.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66dfaf0] >[806246.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66dfaf0] width 1280 pitch 5120 (/4 1280) >[806267.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66dfaf0] >[806267.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66dfaf0] width 1280 pitch 5120 (/4 1280) >[806279.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806279.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806279.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806279.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806279.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806279.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806279.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806279.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806279.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806279.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806279.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806279.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806279.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806279.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806279.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806279.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e9620] >[806280.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e9620] width 1280 pitch 5120 (/4 1280) >[806280.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806280.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6658b80] >[806280.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6658b80] width 1280 pitch 5120 (/4 1280) >[806280.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f4950] >[806280.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f4950] width 1280 pitch 5120 (/4 1280) >[806317.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee770] >[806317.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee770] width 1280 pitch 5120 (/4 1280) >[806317.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f8b50] >[806317.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f8b50] width 1280 pitch 5120 (/4 1280) >[806317.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec480] >[806317.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec480] width 1280 pitch 5120 (/4 1280) >[806317.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f8b50] >[806317.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f8b50] width 1280 pitch 5120 (/4 1280) >[806317.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec480] >[806317.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec480] width 1280 pitch 5120 (/4 1280) >[806317.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f8b50] >[806317.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f8b50] width 1280 pitch 5120 (/4 1280) >[806317.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec480] >[806317.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec480] width 1280 pitch 5120 (/4 1280) >[806317.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f8b50] >[806317.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f8b50] width 1280 pitch 5120 (/4 1280) >[806317.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec480] >[806317.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec480] width 1280 pitch 5120 (/4 1280) >[806317.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c1320] >[806317.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c1320] width 1280 pitch 5120 (/4 1280) >[806317.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c10c0] >[806317.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c10c0] width 1280 pitch 5120 (/4 1280) >[806317.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c1320] >[806317.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c1320] width 1280 pitch 5120 (/4 1280) >[806317.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c10c0] >[806317.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c10c0] width 1280 pitch 5120 (/4 1280) >[806318.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c10c0] >[806318.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c10c0] width 1280 pitch 5120 (/4 1280) >[806318.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec830] >[806318.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec830] width 1280 pitch 5120 (/4 1280) >[806318.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c10c0] >[806318.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c10c0] width 1280 pitch 5120 (/4 1280) >[806318.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec830] >[806318.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec830] width 1280 pitch 5120 (/4 1280) >[806318.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c10c0] >[806318.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c10c0] width 1280 pitch 5120 (/4 1280) >[806318.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec830] >[806318.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec830] width 1280 pitch 5120 (/4 1280) >[806318.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee770] >[806318.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee770] width 1280 pitch 5120 (/4 1280) >[806318.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ec830] >[806318.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ec830] width 1280 pitch 5120 (/4 1280) >[806318.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806318.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806318.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f63a0] >[806318.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f63a0] width 1280 pitch 5120 (/4 1280) >[806318.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806318.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806318.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f63a0] >[806318.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f63a0] width 1280 pitch 5120 (/4 1280) >[806318.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806318.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806318.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f63a0] >[806318.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f63a0] width 1280 pitch 5120 (/4 1280) >[806318.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806319.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806319.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c1320] >[806319.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c1320] width 1280 pitch 5120 (/4 1280) >[806319.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806319.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806319.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c1320] >[806319.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c1320] width 1280 pitch 5120 (/4 1280) >[806319.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ee6c0] >[806319.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ee6c0] width 1280 pitch 5120 (/4 1280) >[806319.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64c1320] >[806319.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64c1320] width 1280 pitch 5120 (/4 1280) >[806385.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e6230] >[806385.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e6230] width 1280 pitch 5120 (/4 1280) >[806386.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f5800] >[806386.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f5800] width 1280 pitch 5120 (/4 1280) >[807196.253] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[807196.257] (II) RADEON(0): Printing DDC gathered Modelines: >[807196.257] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[807285.918] (II) RADEON(0): RADEONSaveScreen(2) >[807285.923] (II) RADEON(0): RADEONSaveScreen(0) >[807328.051] (II) RADEON(0): RADEONSaveScreen(1) >[807341.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6543e60] >[807341.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6543e60] width 1280 pitch 5120 (/4 1280) >[808110.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x683ae90] >[808110.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x683ae90] width 1280 pitch 5120 (/4 1280) >[808111.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68351a0] >[808111.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68351a0] width 1280 pitch 5120 (/4 1280) >[808214.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6679ae0] >[808214.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6679ae0] width 1280 pitch 5120 (/4 1280) >[808214.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e3570] >[808214.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e3570] width 1280 pitch 5120 (/4 1280) >[808584.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64fa730] >[808584.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64fa730] width 1280 pitch 5120 (/4 1280) >[808584.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64fa730] >[808584.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64fa730] width 1280 pitch 5120 (/4 1280) >[809066.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6815360] >[809066.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6815360] width 1280 pitch 5120 (/4 1280) >[809066.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662ad10] >[809066.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662ad10] width 1280 pitch 5120 (/4 1280) >[809068.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662ad10] >[809068.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662ad10] width 1280 pitch 5120 (/4 1280) >[809070.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6818b70] >[809070.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6818b70] width 1280 pitch 5120 (/4 1280) >[809093.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6818b70] >[809093.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6818b70] width 1280 pitch 5120 (/4 1280) >[809144.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809144.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809144.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662ad10] >[809144.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662ad10] width 1280 pitch 5120 (/4 1280) >[809144.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6815360] >[809144.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6815360] width 1280 pitch 5120 (/4 1280) >[809145.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6815360] >[809145.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6815360] width 1280 pitch 5120 (/4 1280) >[809145.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809145.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809145.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662ad10] >[809145.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662ad10] width 1280 pitch 5120 (/4 1280) >[809146.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729260] >[809146.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729260] width 1280 pitch 5120 (/4 1280) >[809146.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6815360] >[809146.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6815360] width 1280 pitch 5120 (/4 1280) >[809146.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x662ad10] >[809147.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x662ad10] width 1280 pitch 5120 (/4 1280) >[809147.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6815360] >[809147.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6815360] width 1280 pitch 5120 (/4 1280) >[809147.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809147.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809151.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809151.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809223.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44194d0] >[809223.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44194d0] width 1280 pitch 5120 (/4 1280) >[809232.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a730] >[809232.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a730] width 1280 pitch 5120 (/4 1280) >[809233.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fe30] >[809233.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fe30] width 1280 pitch 5120 (/4 1280) >[809233.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a730] >[809233.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a730] width 1280 pitch 5120 (/4 1280) >[809233.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809233.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809233.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67eb340] >[809233.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67eb340] width 1280 pitch 5120 (/4 1280) >[809233.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67eb340] >[809233.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67eb340] width 1280 pitch 5120 (/4 1280) >[809233.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729620] >[809233.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729620] width 1280 pitch 5120 (/4 1280) >[809237.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a730] >[809237.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a730] width 1280 pitch 5120 (/4 1280) >[809238.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fd10] >[809238.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fd10] width 1280 pitch 5120 (/4 1280) >[809239.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672ced0] >[809239.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672ced0] width 1280 pitch 5120 (/4 1280) >[809239.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1e9d0] >[809239.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1e9d0] width 1280 pitch 5120 (/4 1280) >[809254.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6767370] >[809254.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6767370] width 1280 pitch 5120 (/4 1280) >[809254.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3070] >[809254.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3070] width 1280 pitch 5120 (/4 1280) >[809256.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676bb10] >[809256.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676bb10] width 1280 pitch 5120 (/4 1280) >[809307.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d0c00] >[809307.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d0c00] width 1280 pitch 5120 (/4 1280) >[809334.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fe30] >[809334.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fe30] width 1280 pitch 5120 (/4 1280) >[809334.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d0410] >[809334.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d0410] width 1280 pitch 5120 (/4 1280) >[809350.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2210] >[809350.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2210] width 1280 pitch 5120 (/4 1280) >[809350.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cfaf0] >[809350.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cfaf0] width 1280 pitch 5120 (/4 1280) >[809354.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fa50] >[809354.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fa50] width 1280 pitch 5120 (/4 1280) >[809354.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cfaf0] >[809354.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cfaf0] width 1280 pitch 5120 (/4 1280) >[809958.064] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[809958.064] (II) RADEON(0): Printing DDC gathered Modelines: >[809958.064] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[810047.891] (II) RADEON(0): RADEONSaveScreen(2) >[810047.891] (II) RADEON(0): RADEONSaveScreen(0) >[813369.844] (II) RADEON(0): RADEONSaveScreen(1) >[813378.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cabd0] >[813378.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cabd0] width 1280 pitch 5120 (/4 1280) >[813396.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da6a0] >[813396.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da6a0] width 1280 pitch 5120 (/4 1280) >[813399.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c9110] >[813399.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c9110] width 1280 pitch 5120 (/4 1280) >[813416.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800980] >[813416.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800980] width 1280 pitch 5120 (/4 1280) >[813427.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800980] >[813427.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800980] width 1280 pitch 5120 (/4 1280) >[813439.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65466c0] >[813439.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65466c0] width 1280 pitch 5120 (/4 1280) >[813578.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6546ca0] >[813578.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6546ca0] width 1280 pitch 5120 (/4 1280) >[813578.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c8a10] >[813578.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c8a10] width 1280 pitch 5120 (/4 1280) >[813581.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e2ae0] >[813581.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e2ae0] width 1280 pitch 5120 (/4 1280) >[813592.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c4370] >[813592.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c4370] width 1280 pitch 5120 (/4 1280) >[813736.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738c30] >[813736.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738c30] width 1280 pitch 5120 (/4 1280) >[813736.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e3640] >[813736.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e3640] width 1280 pitch 5120 (/4 1280) >[813762.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813762.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813765.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813765.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813765.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813765.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813765.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813765.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813765.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bbc00] >[813765.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bbc00] width 1280 pitch 5120 (/4 1280) >[813765.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813765.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813765.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813765.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813765.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813765.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813765.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bbc00] >[813765.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bbc00] width 1280 pitch 5120 (/4 1280) >[813765.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813765.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813765.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813765.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813765.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813765.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813765.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813765.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813765.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bbc00] >[813766.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bbc00] width 1280 pitch 5120 (/4 1280) >[813766.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bbc00] >[813766.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bbc00] width 1280 pitch 5120 (/4 1280) >[813766.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813766.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813766.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813766.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813766.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813766.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813766.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813766.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813766.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813766.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813766.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813766.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813766.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813766.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813766.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813766.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813766.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813766.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813766.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813766.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813766.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813766.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813766.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813766.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813766.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813766.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813766.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813766.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813766.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff2c0] >[813766.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff2c0] width 1280 pitch 5120 (/4 1280) >[813913.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813913.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813913.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67639b0] >[813913.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67639b0] width 1280 pitch 5120 (/4 1280) >[813913.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813913.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813914.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813914.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813914.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[813914.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[813914.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813914.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813915.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813915.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813915.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67639b0] >[813915.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67639b0] width 1280 pitch 5120 (/4 1280) >[813915.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afe4a0] >[813915.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afe4a0] width 1280 pitch 5120 (/4 1280) >[813915.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66d81c0] >[813916.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66d81c0] width 1280 pitch 5120 (/4 1280) >[813916.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d9a40] >[813916.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d9a40] width 1280 pitch 5120 (/4 1280) >[813931.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afdd40] >[813931.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afdd40] width 1280 pitch 5120 (/4 1280) >[814558.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5183a80] >[814559.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5183a80] width 1280 pitch 5120 (/4 1280) >[814564.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5183a80] >[814564.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5183a80] width 1280 pitch 5120 (/4 1280) >[814570.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51959c0] >[814570.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51959c0] width 1280 pitch 5120 (/4 1280) >[814571.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51959c0] >[814571.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51959c0] width 1280 pitch 5120 (/4 1280) >[814623.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51850d0] >[814623.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51850d0] width 1280 pitch 5120 (/4 1280) >[814631.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772ea0] >[814631.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772ea0] width 1280 pitch 5120 (/4 1280) >[814631.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5183a80] >[814631.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5183a80] width 1280 pitch 5120 (/4 1280) >[814647.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51959c0] >[814647.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51959c0] width 1280 pitch 5120 (/4 1280) >[814657.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5183a80] >[814657.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5183a80] width 1280 pitch 5120 (/4 1280) >[814657.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x517de00] >[814657.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x517de00] width 1280 pitch 5120 (/4 1280) >[814729.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6759400] >[814729.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6759400] width 1280 pitch 5120 (/4 1280) >[814729.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5180a90] >[814729.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5180a90] width 1280 pitch 5120 (/4 1280) >[814815.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814815.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814815.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814815.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814815.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb1b0] >[814815.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb1b0] width 1280 pitch 5120 (/4 1280) >[814815.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814815.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814815.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814815.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814815.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd880] >[814815.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd880] width 1280 pitch 5120 (/4 1280) >[814815.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814815.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814816.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd830] >[814816.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd830] width 1280 pitch 5120 (/4 1280) >[814816.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd400] >[814816.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd400] width 1280 pitch 5120 (/4 1280) >[814816.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb1b0] >[814816.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb1b0] width 1280 pitch 5120 (/4 1280) >[814816.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd400] >[814816.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd400] width 1280 pitch 5120 (/4 1280) >[814816.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd400] >[814816.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd400] width 1280 pitch 5120 (/4 1280) >[814816.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814816.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814816.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814816.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814816.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814816.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814816.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814816.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814817.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677b1d0] >[814817.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677b1d0] width 1280 pitch 5120 (/4 1280) >[814817.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814817.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814817.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd400] >[814817.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd400] width 1280 pitch 5120 (/4 1280) >[814817.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814817.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814817.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814817.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814817.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814817.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814817.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814817.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814817.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814817.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814818.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814818.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814818.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814818.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814818.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814818.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814818.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814818.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814818.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814818.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814818.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814818.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814818.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814818.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814818.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814818.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814818.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814818.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ff4c0] >[814818.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ff4c0] width 1280 pitch 5120 (/4 1280) >[814818.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67193c0] >[814818.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67193c0] width 1280 pitch 5120 (/4 1280) >[814839.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffba0] >[814839.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffba0] width 1280 pitch 5120 (/4 1280) >[814839.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd400] >[814839.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd400] width 1280 pitch 5120 (/4 1280) >[814996.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6708fc0] >[814996.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6708fc0] width 1280 pitch 5120 (/4 1280) >[814997.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6708fc0] >[814997.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6708fc0] width 1280 pitch 5120 (/4 1280) >[815213.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5310] >[815213.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5310] width 1280 pitch 5120 (/4 1280) >[815690.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815690.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815690.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815690.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815690.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815690.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815690.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815690.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815690.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815690.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815690.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815690.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815690.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815690.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815691.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815691.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815691.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815691.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815691.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815691.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815691.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815691.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815691.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815691.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815691.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815691.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815691.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815691.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815691.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815691.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815691.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815691.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815691.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815691.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815691.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815691.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815692.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815692.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815692.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815692.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815692.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815692.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815692.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815692.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815692.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815692.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815692.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815692.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815692.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815692.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815692.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5219c50] >[815692.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5219c50] width 1280 pitch 5120 (/4 1280) >[815692.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815692.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815693.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815693.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815693.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815693.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815694.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815694.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815694.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521b540] >[815694.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521b540] width 1280 pitch 5120 (/4 1280) >[815694.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521bf70] >[815694.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521bf70] width 1280 pitch 5120 (/4 1280) >[815694.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af6620] >[815694.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af6620] width 1280 pitch 5120 (/4 1280) >[815694.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63f2cc0] >[815694.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63f2cc0] width 1280 pitch 5120 (/4 1280) >[815694.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815694.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815694.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af6620] >[815695.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af6620] width 1280 pitch 5120 (/4 1280) >[815695.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x523a700] >[815695.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x523a700] width 1280 pitch 5120 (/4 1280) >[815695.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675f760] >[815695.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675f760] width 1280 pitch 5120 (/4 1280) >[815695.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815695.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815695.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675f760] >[815695.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675f760] width 1280 pitch 5120 (/4 1280) >[815695.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815695.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815695.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675f760] >[815695.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675f760] width 1280 pitch 5120 (/4 1280) >[815695.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5223cb0] >[815695.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5223cb0] width 1280 pitch 5120 (/4 1280) >[815701.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5198a30] >[815701.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5198a30] width 1280 pitch 5120 (/4 1280) >[815712.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a1c0] >[815712.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a1c0] width 1280 pitch 5120 (/4 1280) >[816039.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816039.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816039.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x518c660] >[816039.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x518c660] width 1280 pitch 5120 (/4 1280) >[816039.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816039.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816039.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816039.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816039.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6047ef0] >[816039.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6047ef0] width 1280 pitch 5120 (/4 1280) >[816039.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816039.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816039.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6047ef0] >[816039.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6047ef0] width 1280 pitch 5120 (/4 1280) >[816039.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70d63a0] >[816039.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70d63a0] width 1280 pitch 5120 (/4 1280) >[816039.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816039.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816039.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70d63a0] >[816039.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70d63a0] width 1280 pitch 5120 (/4 1280) >[816039.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816039.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816039.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70d63a0] >[816039.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70d63a0] width 1280 pitch 5120 (/4 1280) >[816039.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816039.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816039.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x518c660] >[816039.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x518c660] width 1280 pitch 5120 (/4 1280) >[816039.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816039.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70d43e0] >[816040.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70d43e0] width 1280 pitch 5120 (/4 1280) >[816040.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816040.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791990] >[816040.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791990] width 1280 pitch 5120 (/4 1280) >[816040.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816040.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816087.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816087.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816175.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816175.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816175.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816175.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816175.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816175.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816175.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816175.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816175.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816175.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816175.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816175.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816175.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816175.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816176.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816176.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816176.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816176.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816176.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816176.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816176.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816176.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816176.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816176.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b0430] >[816177.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b0430] width 1280 pitch 5120 (/4 1280) >[816177.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816177.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816177.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb2c70] >[816177.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb2c70] width 1280 pitch 5120 (/4 1280) >[816177.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb2c70] >[816177.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb2c70] width 1280 pitch 5120 (/4 1280) >[816177.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816177.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb2c70] >[816177.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb2c70] width 1280 pitch 5120 (/4 1280) >[816177.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816177.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816178.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fb2c70] >[816178.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fb2c70] width 1280 pitch 5120 (/4 1280) >[816202.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816202.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b0430] >[816207.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b0430] width 1280 pitch 5120 (/4 1280) >[816207.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816207.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816207.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816207.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816207.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816207.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816207.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816207.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816207.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816208.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5220c20] >[816208.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5220c20] width 1280 pitch 5120 (/4 1280) >[816208.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816208.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816208.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816208.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816208.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816208.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816208.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c150] >[816208.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c150] width 1280 pitch 5120 (/4 1280) >[816208.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b0430] >[816208.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b0430] width 1280 pitch 5120 (/4 1280) >[816208.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5220c20] >[816208.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5220c20] width 1280 pitch 5120 (/4 1280) >[816208.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b0430] >[816208.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b0430] width 1280 pitch 5120 (/4 1280) >[816208.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816208.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816208.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x62de0c0] >[816208.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x62de0c0] width 1280 pitch 5120 (/4 1280) >[816208.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70dc8c0] >[816208.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70dc8c0] width 1280 pitch 5120 (/4 1280) >[816879.812] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[816879.812] (II) RADEON(0): Printing DDC gathered Modelines: >[816879.812] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[816969.905] (II) RADEON(0): RADEONSaveScreen(2) >[816969.905] (II) RADEON(0): RADEONSaveScreen(0) >[817612.306] (II) RADEON(0): RADEONSaveScreen(1) >[817624.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7108410] >[817624.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7108410] width 1280 pitch 5120 (/4 1280) >[817684.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70f4880] >[817684.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70f4880] width 1280 pitch 5120 (/4 1280) >[817684.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67937f0] >[817684.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67937f0] width 1280 pitch 5120 (/4 1280) >[817689.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f764e0] >[817689.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f764e0] width 1280 pitch 5120 (/4 1280) >[817689.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792ef0] >[817689.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792ef0] width 1280 pitch 5120 (/4 1280) >[817888.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ee980] >[817889.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ee980] width 1280 pitch 5120 (/4 1280) >[817889.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70f4880] >[817889.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70f4880] width 1280 pitch 5120 (/4 1280) >[817902.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ee980] >[817902.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ee980] width 1280 pitch 5120 (/4 1280) >[818035.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fb460] >[818035.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fb460] width 1280 pitch 5120 (/4 1280) >[818150.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818150.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818159.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ffe90] >[818159.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ffe90] width 1280 pitch 5120 (/4 1280) >[818159.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818159.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818159.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818159.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818160.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818160.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818160.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818160.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818160.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ffe90] >[818160.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ffe90] width 1280 pitch 5120 (/4 1280) >[818289.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818289.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818290.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818290.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818290.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e9ec0] >[818290.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e9ec0] width 1280 pitch 5120 (/4 1280) >[818291.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818291.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818291.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818291.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818316.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818316.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818318.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818318.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818318.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818318.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818318.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818318.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818318.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818318.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818318.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ffe90] >[818318.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ffe90] width 1280 pitch 5120 (/4 1280) >[818318.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70ffe90] >[818318.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70ffe90] width 1280 pitch 5120 (/4 1280) >[818318.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818318.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818318.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818318.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818319.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818319.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818319.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818319.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818319.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818319.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818319.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818320.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818320.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818320.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818320.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818320.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818320.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818320.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818320.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818320.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818320.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818321.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818321.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818321.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818321.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818321.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818321.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818322.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fafd40] >[818322.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fafd40] width 1280 pitch 5120 (/4 1280) >[818322.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818322.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818323.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71040f0] >[818323.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71040f0] width 1280 pitch 5120 (/4 1280) >[818324.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd3c80] >[818324.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd3c80] width 1280 pitch 5120 (/4 1280) >[818327.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d5e0] >[818327.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d5e0] width 1280 pitch 5120 (/4 1280) >[818334.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bf840] >[818334.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bf840] width 1280 pitch 5120 (/4 1280) >[818336.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71602f0] >[818336.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71602f0] width 1280 pitch 5120 (/4 1280) >[818338.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0320] >[818338.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0320] width 1280 pitch 5120 (/4 1280) >[818338.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0180] >[818338.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0180] width 1280 pitch 5120 (/4 1280) >[818338.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0180] >[818338.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0180] width 1280 pitch 5120 (/4 1280) >[818338.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0090] >[818338.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0090] width 1280 pitch 5120 (/4 1280) >[818338.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0090] >[818338.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0090] width 1280 pitch 5120 (/4 1280) >[818338.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0090] >[818338.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0090] width 1280 pitch 5120 (/4 1280) >[818338.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0090] >[818338.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0090] width 1280 pitch 5120 (/4 1280) >[818338.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f0120] >[818338.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f0120] width 1280 pitch 5120 (/4 1280) >[818338.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[818338.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[818339.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177a00] >[818339.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177a00] width 1280 pitch 5120 (/4 1280) >[818339.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cdb70] >[818340.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cdb70] width 1280 pitch 5120 (/4 1280) >[818340.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177a00] >[818340.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177a00] width 1280 pitch 5120 (/4 1280) >[818340.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cdb70] >[818340.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cdb70] width 1280 pitch 5120 (/4 1280) >[818340.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177a00] >[818340.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177a00] width 1280 pitch 5120 (/4 1280) >[818340.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cdb70] >[818340.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cdb70] width 1280 pitch 5120 (/4 1280) >[818340.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675c750] >[818340.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675c750] width 1280 pitch 5120 (/4 1280) >[818340.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675c6f0] >[818340.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675c6f0] width 1280 pitch 5120 (/4 1280) >[818340.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675c750] >[818340.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675c750] width 1280 pitch 5120 (/4 1280) >[818340.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675c630] >[818340.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675c630] width 1280 pitch 5120 (/4 1280) >[818340.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715d5d0] >[818340.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715d5d0] width 1280 pitch 5120 (/4 1280) >[818340.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675c630] >[818340.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675c630] width 1280 pitch 5120 (/4 1280) >[818350.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a8240] >[818350.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a8240] width 1280 pitch 5120 (/4 1280) >[818369.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585f750] >[818370.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585f750] width 1280 pitch 5120 (/4 1280) >[818397.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818397.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818536.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818536.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818536.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818536.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818536.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818536.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818536.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818536.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818536.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818536.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818536.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818536.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818536.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818536.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818536.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818537.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a3880] >[818537.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a3880] width 1280 pitch 5120 (/4 1280) >[818537.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f73a0] >[818537.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f73a0] width 1280 pitch 5120 (/4 1280) >[818861.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818861.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818861.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818861.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818861.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818861.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818861.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818861.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818861.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818861.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818861.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818861.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818861.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[818861.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[818861.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818861.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818861.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[818862.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31f0] >[818862.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31f0] width 1280 pitch 5120 (/4 1280) >[818862.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b3c30] >[818862.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b3c30] width 1280 pitch 5120 (/4 1280) >[819037.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a1260] >[819037.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a1260] width 1280 pitch 5120 (/4 1280) >[819039.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7164840] >[819039.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7164840] width 1280 pitch 5120 (/4 1280) >[819040.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31d0] >[819040.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31d0] width 1280 pitch 5120 (/4 1280) >[819040.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71adb20] >[819040.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71adb20] width 1280 pitch 5120 (/4 1280) >[819040.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b31d0] >[819040.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b31d0] width 1280 pitch 5120 (/4 1280) >[819041.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ab660] >[819041.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ab660] width 1280 pitch 5120 (/4 1280) >[819041.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ab660] >[819041.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ab660] width 1280 pitch 5120 (/4 1280) >[819041.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71adb20] >[819041.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71adb20] width 1280 pitch 5120 (/4 1280) >[819042.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71adb20] >[819042.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71adb20] width 1280 pitch 5120 (/4 1280) >[819056.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a98a0] >[819056.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a98a0] width 1280 pitch 5120 (/4 1280) >[819057.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae0c0] >[819057.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae0c0] width 1280 pitch 5120 (/4 1280) >[820069.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6429cc0] >[820069.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6429cc0] width 1280 pitch 5120 (/4 1280) >[820072.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820072.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820072.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820072.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820072.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820072.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820072.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820072.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820072.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820072.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820072.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820072.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820072.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820072.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820072.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820072.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820072.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820072.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820072.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820072.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820073.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7ee10] >[820073.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7ee10] width 1280 pitch 5120 (/4 1280) >[820073.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7105250] >[820073.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7105250] width 1280 pitch 5120 (/4 1280) >[820073.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820073.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820073.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820073.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820073.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820073.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820073.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820074.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4bb0] >[820074.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4bb0] width 1280 pitch 5120 (/4 1280) >[820074.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177080] >[820074.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177080] width 1280 pitch 5120 (/4 1280) >[820079.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6429cc0] >[820079.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6429cc0] width 1280 pitch 5120 (/4 1280) >[820110.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a87c0] >[820110.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a87c0] width 1280 pitch 5120 (/4 1280) >[820110.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d590] >[820110.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d590] width 1280 pitch 5120 (/4 1280) >[821274.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f8410] >[821274.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f8410] width 1280 pitch 5120 (/4 1280) >[821276.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821276.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821277.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c2a90] >[821277.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c2a90] width 1280 pitch 5120 (/4 1280) >[821277.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821277.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a2540] >[821277.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a2540] width 1280 pitch 5120 (/4 1280) >[821277.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71c22a0] >[821277.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71c22a0] width 1280 pitch 5120 (/4 1280) >[821278.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821278.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821278.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a2540] >[821278.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a2540] width 1280 pitch 5120 (/4 1280) >[821278.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821278.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821278.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a2540] >[821278.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a2540] width 1280 pitch 5120 (/4 1280) >[821279.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821279.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821279.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821280.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821280.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821280.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821280.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a770] >[821280.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a770] width 1280 pitch 5120 (/4 1280) >[821280.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153b90] >[821280.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153b90] width 1280 pitch 5120 (/4 1280) >[821303.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ec540] >[821303.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ec540] width 1280 pitch 5120 (/4 1280) >[821303.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ec540] >[821303.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ec540] width 1280 pitch 5120 (/4 1280) >[821342.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[821342.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[821343.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210bb0] >[821343.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210bb0] width 1280 pitch 5120 (/4 1280) >[822244.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[822244.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[822244.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822244.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822244.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822244.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822244.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822244.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822244.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822244.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822244.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[822244.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[822244.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822244.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822244.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[822244.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[822244.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822244.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822244.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[822244.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[822244.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822244.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822244.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[822244.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[822244.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822244.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822244.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822244.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822245.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4e20] >[822245.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4e20] width 1280 pitch 5120 (/4 1280) >[822245.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7210cf0] >[822245.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7210cf0] width 1280 pitch 5120 (/4 1280) >[822789.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822789.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822789.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720fb80] >[822789.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720fb80] width 1280 pitch 5120 (/4 1280) >[822789.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822789.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822789.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720fb80] >[822789.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720fb80] width 1280 pitch 5120 (/4 1280) >[822789.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822789.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822789.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720fb80] >[822789.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720fb80] width 1280 pitch 5120 (/4 1280) >[822789.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822789.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822789.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720fb80] >[822789.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720fb80] width 1280 pitch 5120 (/4 1280) >[822789.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822789.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822789.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720fb80] >[822789.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720fb80] width 1280 pitch 5120 (/4 1280) >[822883.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[822883.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72401e0] >[822883.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72401e0] width 1280 pitch 5120 (/4 1280) >[822883.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[822883.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825084.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a4da0] >[825084.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a4da0] width 1280 pitch 5120 (/4 1280) >[825084.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218880] >[825084.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218880] width 1280 pitch 5120 (/4 1280) >[825352.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[825352.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[825352.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[825352.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[825352.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825352.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825352.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825352.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825352.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[825352.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[825352.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825352.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[825352.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[825352.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825352.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825401.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7115b80] >[825401.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7115b80] width 1280 pitch 5120 (/4 1280) >[825401.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825401.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825401.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b110] >[825401.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b110] width 1280 pitch 5120 (/4 1280) >[825401.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b110] >[825401.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b110] width 1280 pitch 5120 (/4 1280) >[825401.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b110] >[825401.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b110] width 1280 pitch 5120 (/4 1280) >[825401.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825401.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825401.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825401.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825401.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[825401.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[825401.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[825401.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[825401.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825401.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825402.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[825402.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[825996.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7218ee0] >[825996.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7218ee0] width 1280 pitch 5120 (/4 1280) >[825997.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825997.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825997.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[825997.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[825997.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825997.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825997.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[825997.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[825997.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825997.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825997.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[825997.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[825997.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825997.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[825997.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[825997.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[825997.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71779a0] >[825997.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71779a0] width 1280 pitch 5120 (/4 1280) >[826000.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x712ea80] >[826000.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x712ea80] width 1280 pitch 5120 (/4 1280) >[826000.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826000.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826000.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826000.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826000.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826001.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826001.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b9b0] >[826001.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b9b0] width 1280 pitch 5120 (/4 1280) >[826001.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826001.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826001.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826001.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826001.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826001.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826001.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826001.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826001.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826001.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826001.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826001.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826001.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826001.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[826001.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[826002.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826002.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826002.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724cdf0] >[826002.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724cdf0] width 1280 pitch 5120 (/4 1280) >[826002.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826002.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826002.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724cdf0] >[826002.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724cdf0] width 1280 pitch 5120 (/4 1280) >[826002.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826002.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826002.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724cdf0] >[826002.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724cdf0] width 1280 pitch 5120 (/4 1280) >[826002.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826002.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826002.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724cdf0] >[826002.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724cdf0] width 1280 pitch 5120 (/4 1280) >[826002.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826002.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826002.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724cdf0] >[826002.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724cdf0] width 1280 pitch 5120 (/4 1280) >[826003.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72460e0] >[826003.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72460e0] width 1280 pitch 5120 (/4 1280) >[826004.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[826004.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[826004.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826004.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826004.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724aa90] >[826004.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724aa90] width 1280 pitch 5120 (/4 1280) >[826004.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7177490] >[826004.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7177490] width 1280 pitch 5120 (/4 1280) >[826004.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[826004.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[826012.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72092a0] >[826012.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72092a0] width 1280 pitch 5120 (/4 1280) >[826013.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7114f00] >[826013.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7114f00] width 1280 pitch 5120 (/4 1280) >[826023.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7196910] >[826023.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7196910] width 1280 pitch 5120 (/4 1280) >[826023.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x712ea80] >[826023.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x712ea80] width 1280 pitch 5120 (/4 1280) >[826033.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72178c0] >[826033.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72178c0] width 1280 pitch 5120 (/4 1280) >[826033.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b110] >[826033.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b110] width 1280 pitch 5120 (/4 1280) >[826033.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x720f590] >[826033.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x720f590] width 1280 pitch 5120 (/4 1280) >[826034.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x712ea80] >[826034.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x712ea80] width 1280 pitch 5120 (/4 1280) >[826099.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71972c0] >[826099.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71972c0] width 1280 pitch 5120 (/4 1280) >[826100.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721bef0] >[826100.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721bef0] width 1280 pitch 5120 (/4 1280) >[826100.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x517b7c0] >[826100.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x517b7c0] width 1280 pitch 5120 (/4 1280) >[826100.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x712ea80] >[826100.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x712ea80] width 1280 pitch 5120 (/4 1280) >[826330.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a02a0] >[826330.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a02a0] width 1280 pitch 5120 (/4 1280) >[826330.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a02a0] >[826330.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a02a0] width 1280 pitch 5120 (/4 1280) >[826506.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72448b0] >[826506.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72448b0] width 1280 pitch 5120 (/4 1280) >[826506.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72448b0] >[826506.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72448b0] width 1280 pitch 5120 (/4 1280) >[826516.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7247cc0] >[826516.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7247cc0] width 1280 pitch 5120 (/4 1280) >[826518.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67706e0] >[826518.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67706e0] width 1280 pitch 5120 (/4 1280) >[826533.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7206100] >[826533.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7206100] width 1280 pitch 5120 (/4 1280) >[826533.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7206100] >[826533.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7206100] width 1280 pitch 5120 (/4 1280) >[826535.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a67e0] >[826535.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a67e0] width 1280 pitch 5120 (/4 1280) >[826544.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51ece50] >[826544.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51ece50] width 1280 pitch 5120 (/4 1280) >[826575.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718e4c0] >[826575.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718e4c0] width 1280 pitch 5120 (/4 1280) >[826585.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826585.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826586.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826586.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826586.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826586.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826586.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826586.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826586.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826586.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826594.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718e4c0] >[826594.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718e4c0] width 1280 pitch 5120 (/4 1280) >[826594.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826594.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826594.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826594.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826594.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826594.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826594.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826594.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826594.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826594.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826595.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826595.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7123690] >[826595.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7123690] width 1280 pitch 5120 (/4 1280) >[826595.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7123690] >[826595.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7123690] width 1280 pitch 5120 (/4 1280) >[826595.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150c40] >[826595.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150c40] width 1280 pitch 5120 (/4 1280) >[826595.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7123690] >[826595.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7123690] width 1280 pitch 5120 (/4 1280) >[826595.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7123690] >[826595.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7123690] width 1280 pitch 5120 (/4 1280) >[826595.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150c40] >[826595.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150c40] width 1280 pitch 5120 (/4 1280) >[826595.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150c40] >[826595.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150c40] width 1280 pitch 5120 (/4 1280) >[826595.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718e4c0] >[826595.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718e4c0] width 1280 pitch 5120 (/4 1280) >[826595.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150c40] >[826595.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150c40] width 1280 pitch 5120 (/4 1280) >[826595.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150c40] >[826595.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150c40] width 1280 pitch 5120 (/4 1280) >[826595.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718e4c0] >[826595.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718e4c0] width 1280 pitch 5120 (/4 1280) >[826595.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7150000] >[826595.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7150000] width 1280 pitch 5120 (/4 1280) >[826595.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x714fdc0] >[826595.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x714fdc0] width 1280 pitch 5120 (/4 1280) >[826595.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x718f580] >[826595.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x718f580] width 1280 pitch 5120 (/4 1280) >[826649.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ba990] >[826650.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ba990] width 1280 pitch 5120 (/4 1280) >[826650.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ba990] >[826650.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ba990] width 1280 pitch 5120 (/4 1280) >[826665.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71931d0] >[826665.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71931d0] width 1280 pitch 5120 (/4 1280) >[826666.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63ce4a0] >[826666.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63ce4a0] width 1280 pitch 5120 (/4 1280) >[826850.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7147ef0] >[826850.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7147ef0] width 1280 pitch 5120 (/4 1280) >[827912.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a0930] >[827912.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a0930] width 1280 pitch 5120 (/4 1280) >[827912.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[827912.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828004.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x731a410] >[828004.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x731a410] width 1280 pitch 5120 (/4 1280) >[828008.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72ae310] >[828008.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72ae310] width 1280 pitch 5120 (/4 1280) >[828008.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72b81f0] >[828008.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72b81f0] width 1280 pitch 5120 (/4 1280) >[828008.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72861d0] >[828008.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72861d0] width 1280 pitch 5120 (/4 1280) >[828008.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72b81f0] >[828008.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72b81f0] width 1280 pitch 5120 (/4 1280) >[828297.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d0220] >[828297.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d0220] width 1280 pitch 5120 (/4 1280) >[828297.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d1590] >[828297.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d1590] width 1280 pitch 5120 (/4 1280) >[828300.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7308640] >[828300.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7308640] width 1280 pitch 5120 (/4 1280) >[828313.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7247d60] >[828313.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7247d60] width 1280 pitch 5120 (/4 1280) >[828313.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828313.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828425.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828425.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828425.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828425.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828425.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828425.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828425.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828425.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828426.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828426.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828426.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828426.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828426.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828427.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828427.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828427.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828427.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828427.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828427.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828427.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828427.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730e590] >[828427.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730e590] width 1280 pitch 5120 (/4 1280) >[828428.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717c240] >[828428.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717c240] width 1280 pitch 5120 (/4 1280) >[828428.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828428.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828428.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828428.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828428.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828428.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828428.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828428.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828428.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828428.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828428.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828428.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828428.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828428.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828428.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828428.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828428.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828428.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828428.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828428.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828428.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828428.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828428.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828429.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828429.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828429.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828429.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828429.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828429.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828429.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828429.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828429.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828429.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675ca80] >[828429.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675ca80] width 1280 pitch 5120 (/4 1280) >[828429.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828429.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828429.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828429.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828429.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828429.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828429.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828429.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828429.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828429.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828429.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828429.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828429.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828429.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828429.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828429.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828429.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828429.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828429.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828429.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828429.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828430.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828430.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828430.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828430.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828430.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828430.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828430.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828430.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828430.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828430.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7306f30] >[828430.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7306f30] width 1280 pitch 5120 (/4 1280) >[828430.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828430.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828430.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828430.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828430.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828431.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828431.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828431.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828431.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828432.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828432.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828432.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828432.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828432.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d64a0] >[828432.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d64a0] width 1280 pitch 5120 (/4 1280) >[828432.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d3cf0] >[828432.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d3cf0] width 1280 pitch 5120 (/4 1280) >[828432.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828432.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828432.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d3cf0] >[828432.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d3cf0] width 1280 pitch 5120 (/4 1280) >[828432.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828432.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828432.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d3cf0] >[828432.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d3cf0] width 1280 pitch 5120 (/4 1280) >[828432.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726b830] >[828432.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726b830] width 1280 pitch 5120 (/4 1280) >[828432.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d3cf0] >[828432.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d3cf0] width 1280 pitch 5120 (/4 1280) >[828432.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828432.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828432.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828432.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828432.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d3cf0] >[828432.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d3cf0] width 1280 pitch 5120 (/4 1280) >[828433.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828433.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828434.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828434.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828439.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72a2b70] >[828440.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72a2b70] width 1280 pitch 5120 (/4 1280) >[828440.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7324880] >[828440.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7324880] width 1280 pitch 5120 (/4 1280) >[828479.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f3d00] >[828479.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f3d00] width 1280 pitch 5120 (/4 1280) >[828850.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159400] >[828850.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159400] width 1280 pitch 5120 (/4 1280) >[828850.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72ac690] >[828850.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72ac690] width 1280 pitch 5120 (/4 1280) >[828850.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159400] >[828850.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159400] width 1280 pitch 5120 (/4 1280) >[828850.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d8650] >[828851.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d8650] width 1280 pitch 5120 (/4 1280) >[828853.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72d8650] >[828854.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72d8650] width 1280 pitch 5120 (/4 1280) >[828854.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159400] >[828854.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159400] width 1280 pitch 5120 (/4 1280) >[828854.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72506d0] >[828854.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72506d0] width 1280 pitch 5120 (/4 1280) >[829394.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x735a910] >[829394.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x735a910] width 1280 pitch 5120 (/4 1280) >[829394.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7291450] >[829394.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7291450] width 1280 pitch 5120 (/4 1280) >[829668.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829668.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829669.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73029a0] >[829669.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73029a0] width 1280 pitch 5120 (/4 1280) >[829670.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829670.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829670.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73029a0] >[829670.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73029a0] width 1280 pitch 5120 (/4 1280) >[829680.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829680.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829680.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829680.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829680.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829680.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829697.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829697.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829701.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7211d10] >[829701.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7211d10] width 1280 pitch 5120 (/4 1280) >[829709.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72caf30] >[829709.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72caf30] width 1280 pitch 5120 (/4 1280) >[829711.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73029a0] >[829711.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73029a0] width 1280 pitch 5120 (/4 1280) >[829728.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829728.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829729.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829729.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829736.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829736.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829736.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829736.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829736.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829736.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829736.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829736.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829736.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829736.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829736.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829736.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829736.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829736.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829736.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829736.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829736.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829736.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829736.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829737.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829737.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829737.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7157150] >[829737.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7157150] width 1280 pitch 5120 (/4 1280) >[829737.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73029a0] >[829737.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73029a0] width 1280 pitch 5120 (/4 1280) >[829737.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72faf30] >[829737.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72faf30] width 1280 pitch 5120 (/4 1280) >[829737.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829737.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829737.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829737.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829737.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72f7280] >[829737.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72f7280] width 1280 pitch 5120 (/4 1280) >[829737.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x725bd10] >[829738.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x725bd10] width 1280 pitch 5120 (/4 1280) >[829738.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829738.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7222b60] >[829738.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7222b60] width 1280 pitch 5120 (/4 1280) >[829738.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7153bd0] >[829738.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7153bd0] width 1280 pitch 5120 (/4 1280) >[829835.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72605d0] >[829835.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72605d0] width 1280 pitch 5120 (/4 1280) >[829835.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72e8840] >[829835.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72e8840] width 1280 pitch 5120 (/4 1280) >[829885.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7211d10] >[829885.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7211d10] width 1280 pitch 5120 (/4 1280) >[830426.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72bf440] >[830426.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72bf440] width 1280 pitch 5120 (/4 1280) >[830431.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7364a90] >[830431.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7364a90] width 1280 pitch 5120 (/4 1280) >[830431.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7385010] >[830431.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7385010] width 1280 pitch 5120 (/4 1280) >[830431.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72e3c60] >[830431.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72e3c60] width 1280 pitch 5120 (/4 1280) >[830431.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7385010] >[830431.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7385010] width 1280 pitch 5120 (/4 1280) >[830591.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830591.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830591.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830591.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e4120] >[830591.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e4120] width 1280 pitch 5120 (/4 1280) >[830594.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726db50] >[830594.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726db50] width 1280 pitch 5120 (/4 1280) >[830594.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726f660] >[830594.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726f660] width 1280 pitch 5120 (/4 1280) >[830594.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830594.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830594.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726f660] >[830594.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726f660] width 1280 pitch 5120 (/4 1280) >[830594.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830594.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830594.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x726f660] >[830594.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x726f660] width 1280 pitch 5120 (/4 1280) >[830594.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830594.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830594.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e59c0] >[830594.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e59c0] width 1280 pitch 5120 (/4 1280) >[830594.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x630a440] >[830594.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x630a440] width 1280 pitch 5120 (/4 1280) >[830594.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7385010] >[830595.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7385010] width 1280 pitch 5120 (/4 1280) >[830595.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f6ba0] >[830595.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f6ba0] width 1280 pitch 5120 (/4 1280) >[830595.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7301c00] >[830595.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7301c00] width 1280 pitch 5120 (/4 1280) >[830595.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830595.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c2e20] >[830595.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c2e20] width 1280 pitch 5120 (/4 1280) >[830595.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x730f8d0] >[830595.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x730f8d0] width 1280 pitch 5120 (/4 1280) >[830687.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7372280] >[830687.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7372280] width 1280 pitch 5120 (/4 1280) >[830687.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7372280] >[830687.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7372280] width 1280 pitch 5120 (/4 1280) >[830838.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ec020] >[830838.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ec020] width 1280 pitch 5120 (/4 1280) >[830838.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72e58f0] >[830838.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72e58f0] width 1280 pitch 5120 (/4 1280) >[830839.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x735b3b0] >[830839.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x735b3b0] width 1280 pitch 5120 (/4 1280) >[830840.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525e800] >[830840.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525e800] width 1280 pitch 5120 (/4 1280) >[830842.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6594ad0] >[830842.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6594ad0] width 1280 pitch 5120 (/4 1280) >[830842.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73779c0] >[830842.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73779c0] width 1280 pitch 5120 (/4 1280) >[831261.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73959b0] >[831261.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73959b0] width 1280 pitch 5120 (/4 1280) >[831261.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a10a0] >[831261.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a10a0] width 1280 pitch 5120 (/4 1280) >[831278.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f390] >[831278.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f390] width 1280 pitch 5120 (/4 1280) >[831822.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739a5e0] >[831822.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739a5e0] width 1280 pitch 5120 (/4 1280) >[831822.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739a840] >[831822.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739a840] width 1280 pitch 5120 (/4 1280) >[831824.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e5870] >[831824.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e5870] width 1280 pitch 5120 (/4 1280) >[831824.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831824.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831860.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831860.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831860.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a6520] >[831861.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a6520] width 1280 pitch 5120 (/4 1280) >[831861.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a6520] >[831861.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a6520] width 1280 pitch 5120 (/4 1280) >[831861.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a6520] >[831861.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a6520] width 1280 pitch 5120 (/4 1280) >[831861.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739f190] >[831861.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739f190] width 1280 pitch 5120 (/4 1280) >[831861.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73e4de0] >[831861.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73e4de0] width 1280 pitch 5120 (/4 1280) >[831861.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831861.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[831861.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a6520] >[831862.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a6520] width 1280 pitch 5120 (/4 1280) >[831862.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x739b0a0] >[831862.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x739b0a0] width 1280 pitch 5120 (/4 1280) >[832186.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7331950] >[832186.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7331950] width 1280 pitch 5120 (/4 1280) >[832188.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7339d30] >[832188.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7339d30] width 1280 pitch 5120 (/4 1280) >[834532.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73d06b0] >[834533.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73d06b0] width 1280 pitch 5120 (/4 1280) >[834579.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ac530] >[834579.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ac530] width 1280 pitch 5120 (/4 1280) >[834587.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ac530] >[834587.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ac530] width 1280 pitch 5120 (/4 1280) >[834588.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73d06b0] >[834588.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73d06b0] width 1280 pitch 5120 (/4 1280) >[834591.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73d06b0] >[834591.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73d06b0] width 1280 pitch 5120 (/4 1280) >[834640.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ac530] >[834640.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ac530] width 1280 pitch 5120 (/4 1280) >[834640.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ac530] >[834640.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ac530] width 1280 pitch 5120 (/4 1280) >[837756.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7335fc0] >[837756.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7335fc0] width 1280 pitch 5120 (/4 1280) >[837756.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73d3c70] >[837756.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73d3c70] width 1280 pitch 5120 (/4 1280) >[837835.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837835.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837835.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ca560] >[837835.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ca560] width 1280 pitch 5120 (/4 1280) >[837835.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837835.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837835.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ca560] >[837835.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ca560] width 1280 pitch 5120 (/4 1280) >[837835.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837835.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837835.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ca560] >[837835.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ca560] width 1280 pitch 5120 (/4 1280) >[837835.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd990] >[837835.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd990] width 1280 pitch 5120 (/4 1280) >[837836.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837836.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837836.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd990] >[837836.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd990] width 1280 pitch 5120 (/4 1280) >[837836.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837836.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837836.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd990] >[837836.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd990] width 1280 pitch 5120 (/4 1280) >[837836.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837836.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837836.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd990] >[837836.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd990] width 1280 pitch 5120 (/4 1280) >[837836.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd9f0] >[837836.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd9f0] width 1280 pitch 5120 (/4 1280) >[837836.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837836.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837836.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837836.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72dd990] >[837837.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72dd990] width 1280 pitch 5120 (/4 1280) >[837837.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837837.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[837837.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837837.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[837837.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837837.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[837837.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741eee0] >[837837.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741eee0] width 1280 pitch 5120 (/4 1280) >[837837.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837837.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[837837.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837837.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[837837.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73da260] >[837837.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73da260] width 1280 pitch 5120 (/4 1280) >[837837.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e2dc0] >[837837.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e2dc0] width 1280 pitch 5120 (/4 1280) >[837854.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741c290] >[837854.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741c290] width 1280 pitch 5120 (/4 1280) >[837854.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741bd80] >[837854.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741bd80] width 1280 pitch 5120 (/4 1280) >[837854.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73a8850] >[837854.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73a8850] width 1280 pitch 5120 (/4 1280) >[837854.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741c290] >[837854.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741c290] width 1280 pitch 5120 (/4 1280) >[837955.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x734b680] >[837955.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x734b680] width 1280 pitch 5120 (/4 1280) >[837956.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x738ec50] >[837956.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x738ec50] width 1280 pitch 5120 (/4 1280) >[837958.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c4000] >[837958.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c4000] width 1280 pitch 5120 (/4 1280) >[837958.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c7680] >[837958.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c7680] width 1280 pitch 5120 (/4 1280) >[845601.283] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[845601.283] (II) RADEON(0): Printing DDC gathered Modelines: >[845601.283] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[846382.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c5210] >[846382.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c5210] width 1280 pitch 5120 (/4 1280) >[846382.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x744c180] >[846382.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x744c180] width 1280 pitch 5120 (/4 1280) >[846382.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c5210] >[846382.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c5210] width 1280 pitch 5120 (/4 1280) >[846383.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7423d50] >[846383.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7423d50] width 1280 pitch 5120 (/4 1280) >[872753.325] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[872753.352] (II) RADEON(0): Printing DDC gathered Modelines: >[872753.353] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[872757.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x744c120] >[872757.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x744c120] width 1280 pitch 5120 (/4 1280) >[872757.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56fd0d0] >[872757.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56fd0d0] width 1280 pitch 5120 (/4 1280) >[872757.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af22e0] >[872757.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af22e0] width 1280 pitch 5120 (/4 1280) >[872757.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af22e0] >[872757.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af22e0] width 1280 pitch 5120 (/4 1280) >[872757.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af22e0] >[872757.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af22e0] width 1280 pitch 5120 (/4 1280) >[872757.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af22e0] >[872757.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af22e0] width 1280 pitch 5120 (/4 1280) >[872757.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872757.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af22e0] >[872757.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af22e0] width 1280 pitch 5120 (/4 1280) >[872757.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74df710] >[872757.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74df710] width 1280 pitch 5120 (/4 1280) >[872821.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872821.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872821.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872821.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872821.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872821.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872821.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872822.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872822.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872822.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872822.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872822.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872822.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872822.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872822.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872822.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872832.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872832.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872832.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872832.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872832.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872832.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872832.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872832.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872833.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872833.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872834.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872834.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872834.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7135b40] >[872834.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7135b40] width 1280 pitch 5120 (/4 1280) >[872834.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872834.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872834.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7135b40] >[872834.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7135b40] width 1280 pitch 5120 (/4 1280) >[872834.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872834.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872834.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7135b40] >[872834.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7135b40] width 1280 pitch 5120 (/4 1280) >[872834.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872834.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872834.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7135b40] >[872834.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7135b40] width 1280 pitch 5120 (/4 1280) >[872834.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872834.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872835.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872835.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872835.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872835.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872835.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872835.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872835.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872835.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872835.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872835.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872835.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872835.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872835.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872835.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872835.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872835.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872835.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872835.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872835.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724f260] >[872835.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724f260] width 1280 pitch 5120 (/4 1280) >[872835.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872835.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872836.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71368d0] >[872836.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71368d0] width 1280 pitch 5120 (/4 1280) >[872836.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872836.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872839.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872839.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7587420] >[872840.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7587420] width 1280 pitch 5120 (/4 1280) >[872840.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872840.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7424040] >[872840.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7424040] width 1280 pitch 5120 (/4 1280) >[872840.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7294380] >[872840.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7294380] width 1280 pitch 5120 (/4 1280) >[872852.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673af50] >[872852.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673af50] width 1280 pitch 5120 (/4 1280) >[872865.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[872865.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[872878.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7373280] >[872878.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7373280] width 1280 pitch 5120 (/4 1280) >[872894.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74475b0] >[872894.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74475b0] width 1280 pitch 5120 (/4 1280) >[872897.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741e200] >[872897.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741e200] width 1280 pitch 5120 (/4 1280) >[872905.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f4d80] >[872905.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f4d80] width 1280 pitch 5120 (/4 1280) >[872914.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7448f10] >[872914.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7448f10] width 1280 pitch 5120 (/4 1280) >[873123.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873123.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873123.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873123.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873123.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873123.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873123.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873123.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873123.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873123.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873123.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873123.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873123.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873123.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873123.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873123.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873123.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873123.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873123.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873123.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873123.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873124.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873124.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873124.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873124.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873124.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873124.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873124.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873124.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873124.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873124.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873124.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873124.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873124.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873124.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873124.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873124.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873124.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873124.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873125.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873125.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873125.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873125.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873125.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873125.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873125.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873125.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873125.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873125.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873125.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873125.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873125.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873125.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873127.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873127.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873127.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873127.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873127.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873128.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873128.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873128.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873128.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873128.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873128.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873128.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873128.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873128.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873128.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873128.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873128.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873128.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873128.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873128.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873128.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873150.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873150.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873150.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873150.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873150.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873150.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873150.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873150.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873150.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873150.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873150.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873150.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873150.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873150.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873150.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873150.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873150.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873150.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873150.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873150.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873150.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873150.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873150.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873150.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873151.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873151.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873151.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873151.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873151.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873152.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873152.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873152.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873152.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873152.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873152.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873152.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873152.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873152.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873152.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873152.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873152.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873152.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873152.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873152.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873152.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873153.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873153.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873153.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873153.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873153.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873153.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873153.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873153.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873153.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873153.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873153.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873153.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873153.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873153.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873153.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873153.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873154.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873154.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873154.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873154.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873154.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873154.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873154.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873154.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873154.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873154.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873154.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873154.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873154.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873154.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873154.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873154.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873154.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873154.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873154.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873154.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873154.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873154.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873154.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873154.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873154.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873154.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873154.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873154.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873154.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873154.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873155.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873155.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873155.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873155.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873156.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873156.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873156.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873156.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873156.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873156.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873156.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873156.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873156.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873156.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873157.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873157.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873157.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c6510] >[873157.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c6510] width 1280 pitch 5120 (/4 1280) >[873164.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873164.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873164.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873164.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873164.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873164.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873164.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873164.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873164.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873164.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873164.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873164.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873164.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873165.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873165.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873165.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873165.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873165.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873165.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873165.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873165.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873165.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873165.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873166.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873166.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873166.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873166.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873166.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873166.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873166.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873166.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873166.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873166.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873166.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873166.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873166.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873166.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873166.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x721ab50] >[873166.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x721ab50] width 1280 pitch 5120 (/4 1280) >[873166.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873166.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873166.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873166.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873167.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873167.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873167.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7412d80] >[873167.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7412d80] width 1280 pitch 5120 (/4 1280) >[873167.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x607b750] >[873167.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x607b750] width 1280 pitch 5120 (/4 1280) >[873257.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27620a0] >[873257.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27620a0] width 1280 pitch 5120 (/4 1280) >[873257.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873257.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873257.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27620a0] >[873257.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27620a0] width 1280 pitch 5120 (/4 1280) >[873258.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873258.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873258.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27620a0] >[873258.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27620a0] width 1280 pitch 5120 (/4 1280) >[873258.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873258.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873258.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74074c0] >[873259.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74074c0] width 1280 pitch 5120 (/4 1280) >[873259.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873259.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873259.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[873259.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[873284.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873284.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873284.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873284.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873284.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873284.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873284.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873284.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873284.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873284.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873284.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873284.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873285.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873285.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873285.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f029f0] >[873285.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f029f0] width 1280 pitch 5120 (/4 1280) >[873285.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873285.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873285.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f029f0] >[873285.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f029f0] width 1280 pitch 5120 (/4 1280) >[873285.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873285.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873285.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f029f0] >[873285.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f029f0] width 1280 pitch 5120 (/4 1280) >[873285.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873285.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873285.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f029f0] >[873285.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f029f0] width 1280 pitch 5120 (/4 1280) >[873285.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873285.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873285.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f029f0] >[873286.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f029f0] width 1280 pitch 5120 (/4 1280) >[873286.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873286.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873302.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873302.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873302.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873302.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873302.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873302.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873302.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873303.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873303.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873303.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873303.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873303.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873303.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873303.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873303.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873303.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873303.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873303.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873303.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873303.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873303.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873303.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873303.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873303.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873303.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873303.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873303.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873303.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873303.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873303.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873303.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873303.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873303.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873303.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873303.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873303.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873303.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873303.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873303.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873303.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873303.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873303.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873303.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873303.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873303.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873304.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873304.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873304.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873304.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873304.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873304.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873304.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873304.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873304.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873304.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873304.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873304.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873304.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873304.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873304.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873304.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873304.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873305.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873305.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873305.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873305.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873305.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873305.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873305.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873305.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873305.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7488f90] >[873305.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7488f90] width 1280 pitch 5120 (/4 1280) >[873305.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873305.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873305.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7488f90] >[873305.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7488f90] width 1280 pitch 5120 (/4 1280) >[873305.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873305.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873305.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873305.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873305.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873305.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873306.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873306.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873306.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873306.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873306.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873306.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873306.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873306.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873306.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873306.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873306.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873306.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873306.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873306.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873306.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873306.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873306.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873306.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873306.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873306.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873307.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873307.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873307.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873307.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873307.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873307.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873307.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873307.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873307.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873307.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873307.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873307.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873308.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873308.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873313.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873313.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873315.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873315.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873315.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873315.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873318.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7487da0] >[873318.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7487da0] width 1280 pitch 5120 (/4 1280) >[873318.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a0a10] >[873318.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a0a10] width 1280 pitch 5120 (/4 1280) >[873318.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a0a10] >[873318.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a0a10] width 1280 pitch 5120 (/4 1280) >[873318.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873318.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a850] >[873318.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a850] width 1280 pitch 5120 (/4 1280) >[873319.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873319.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873319.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749b470] >[873319.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749b470] width 1280 pitch 5120 (/4 1280) >[873319.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873320.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873320.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873320.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873320.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873320.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873320.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873320.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873320.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873320.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873320.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873320.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873320.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873320.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873320.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873320.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873320.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873320.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873320.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873320.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873320.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873320.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873320.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873320.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873320.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873320.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873320.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873320.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873320.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873320.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873320.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873320.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873320.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873320.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873320.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873320.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873320.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873320.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873320.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749b470] >[873320.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749b470] width 1280 pitch 5120 (/4 1280) >[873320.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873320.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873320.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873320.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873320.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873320.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873320.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873320.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873320.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873321.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873321.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873321.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873321.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873321.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873321.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873321.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873321.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873321.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873321.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873321.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873321.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873321.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873321.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873321.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873321.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873321.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873321.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873321.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873321.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873321.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873321.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873321.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873321.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873321.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873321.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873321.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873321.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749b470] >[873321.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749b470] width 1280 pitch 5120 (/4 1280) >[873321.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873321.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873322.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873322.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873322.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7586d00] >[873322.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7586d00] width 1280 pitch 5120 (/4 1280) >[873322.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873322.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873322.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873322.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873322.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873322.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873322.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873323.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873323.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873323.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873323.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873323.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873323.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873326.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873326.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873343.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b1790] >[873343.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b1790] width 1280 pitch 5120 (/4 1280) >[873343.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873343.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873343.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873344.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873344.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873344.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873344.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873344.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873344.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873344.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873344.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873346.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873346.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873347.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873347.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873347.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873347.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873347.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873347.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873347.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873347.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873347.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873347.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873347.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873347.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873347.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873347.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873347.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873347.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873347.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873347.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873347.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873348.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873348.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741a220] >[873348.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741a220] width 1280 pitch 5120 (/4 1280) >[873348.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873348.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873348.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7730d70] >[873348.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7730d70] width 1280 pitch 5120 (/4 1280) >[873348.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873348.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873349.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873349.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873349.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873349.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873349.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873349.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873350.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873350.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873350.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873351.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873351.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[873351.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[873351.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873351.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873351.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[873351.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[873352.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873352.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873352.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873352.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873352.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873352.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873352.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873352.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873352.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873352.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873352.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x614d420] >[873352.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x614d420] width 1280 pitch 5120 (/4 1280) >[873352.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x741dcb0] >[873352.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x741dcb0] width 1280 pitch 5120 (/4 1280) >[873352.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873352.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873352.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[873352.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[873352.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873352.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873352.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873352.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873352.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74490e0] >[873352.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74490e0] width 1280 pitch 5120 (/4 1280) >[873353.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873353.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873353.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873353.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873353.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873353.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873353.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[873353.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[873353.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873353.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873353.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7447470] >[873353.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7447470] width 1280 pitch 5120 (/4 1280) >[873353.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873353.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7755110] >[873353.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7755110] width 1280 pitch 5120 (/4 1280) >[873353.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873353.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873354.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159b50] >[873354.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159b50] width 1280 pitch 5120 (/4 1280) >[873354.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159b50] >[873354.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159b50] width 1280 pitch 5120 (/4 1280) >[873354.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6a10] >[873354.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6a10] width 1280 pitch 5120 (/4 1280) >[873354.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7754220] >[873354.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7754220] width 1280 pitch 5120 (/4 1280) >[873354.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5ec0] >[873354.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5ec0] width 1280 pitch 5120 (/4 1280) >[873354.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873354.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873354.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5ec0] >[873354.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5ec0] width 1280 pitch 5120 (/4 1280) >[873354.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873354.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873354.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5ec0] >[873354.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5ec0] width 1280 pitch 5120 (/4 1280) >[873354.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873354.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873354.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6780] >[873354.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6780] width 1280 pitch 5120 (/4 1280) >[873354.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873354.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873354.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6780] >[873354.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6780] width 1280 pitch 5120 (/4 1280) >[873354.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873354.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873354.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6780] >[873355.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6780] width 1280 pitch 5120 (/4 1280) >[873355.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873355.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873355.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873355.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873355.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873355.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873355.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873355.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873355.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873355.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873355.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873355.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873355.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873355.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873355.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873355.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873355.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7159af0] >[873355.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7159af0] width 1280 pitch 5120 (/4 1280) >[873355.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7405cb0] >[873355.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7405cb0] width 1280 pitch 5120 (/4 1280) >[873356.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873356.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873432.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873432.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873432.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[873432.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[873467.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873467.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873467.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[873467.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[873519.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5750] >[873519.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5750] width 1280 pitch 5120 (/4 1280) >[873519.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7494b10] >[873519.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7494b10] width 1280 pitch 5120 (/4 1280) >[873520.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[873520.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[873520.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745fbb0] >[873520.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745fbb0] width 1280 pitch 5120 (/4 1280) >[873520.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5990] >[873521.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5990] width 1280 pitch 5120 (/4 1280) >[873521.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742e120] >[873521.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742e120] width 1280 pitch 5120 (/4 1280) >[874223.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745bbe0] >[874223.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745bbe0] width 1280 pitch 5120 (/4 1280) >[874224.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454410] >[874224.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454410] width 1280 pitch 5120 (/4 1280) >[874224.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745bbe0] >[874224.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745bbe0] width 1280 pitch 5120 (/4 1280) >[874224.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454410] >[874224.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454410] width 1280 pitch 5120 (/4 1280) >[874224.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745bbe0] >[874224.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745bbe0] width 1280 pitch 5120 (/4 1280) >[874225.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874225.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874225.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874225.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874225.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745bbe0] >[874225.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745bbe0] width 1280 pitch 5120 (/4 1280) >[874225.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874225.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874225.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874226.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874226.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874226.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874227.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874227.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874227.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874227.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874228.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7459970] >[874228.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7459970] width 1280 pitch 5120 (/4 1280) >[874232.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874232.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874233.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874233.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874233.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7459970] >[874233.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7459970] width 1280 pitch 5120 (/4 1280) >[874233.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874233.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874234.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7459970] >[874234.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7459970] width 1280 pitch 5120 (/4 1280) >[874234.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e3f0] >[874235.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e3f0] width 1280 pitch 5120 (/4 1280) >[874235.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874235.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874235.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874235.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874235.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874235.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874235.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874235.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874235.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874235.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874237.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746ef80] >[874237.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746ef80] width 1280 pitch 5120 (/4 1280) >[874237.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874237.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874237.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874237.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874237.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874237.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874237.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874238.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874238.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874238.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874238.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874238.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874238.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874238.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874238.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874238.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874238.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874238.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874238.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874238.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874238.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874238.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874238.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874238.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874238.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874238.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874238.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874238.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874238.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874238.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874239.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874239.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874239.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874239.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874239.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874239.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874240.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874240.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874240.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874240.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874240.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874241.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874241.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874241.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874241.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874241.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874241.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874241.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874241.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874241.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874242.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874242.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874242.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874242.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874243.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874243.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874243.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874243.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874243.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874243.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874244.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874244.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874245.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874245.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874245.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874245.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874245.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874245.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874245.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874245.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874245.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874245.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874245.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874245.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874246.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746ef80] >[874246.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746ef80] width 1280 pitch 5120 (/4 1280) >[874246.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e3f0] >[874246.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e3f0] width 1280 pitch 5120 (/4 1280) >[874246.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874246.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874246.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874246.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874246.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874246.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874246.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874246.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874246.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874246.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874246.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874246.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874246.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874246.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874246.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874246.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874247.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874247.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874247.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874247.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874247.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874247.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874247.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874247.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874247.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874247.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874248.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874248.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874248.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874248.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874248.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874248.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874248.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874248.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874250.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475bd0] >[874250.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475bd0] width 1280 pitch 5120 (/4 1280) >[874251.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749e4f0] >[874251.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749e4f0] width 1280 pitch 5120 (/4 1280) >[874252.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874252.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874253.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874254.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874255.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7454210] >[874255.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7454210] width 1280 pitch 5120 (/4 1280) >[874256.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874256.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874257.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874257.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874257.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874257.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874257.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b35fe0] >[874257.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b35fe0] width 1280 pitch 5120 (/4 1280) >[874257.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2f530] >[874258.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2f530] width 1280 pitch 5120 (/4 1280) >[874258.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73ff960] >[874258.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73ff960] width 1280 pitch 5120 (/4 1280) >[874259.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b327d0] >[874259.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b327d0] width 1280 pitch 5120 (/4 1280) >[874259.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7475ff0] >[874259.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7475ff0] width 1280 pitch 5120 (/4 1280) >[874360.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521d570] >[874360.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521d570] width 1280 pitch 5120 (/4 1280) >[874367.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745e530] >[874367.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745e530] width 1280 pitch 5120 (/4 1280) >[874474.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5341e30] >[874474.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5341e30] width 1280 pitch 5120 (/4 1280) >[874474.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5341e30] >[874474.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5341e30] width 1280 pitch 5120 (/4 1280) >[874484.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7467e10] >[874484.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7467e10] width 1280 pitch 5120 (/4 1280) >[874484.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7467e10] >[874484.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7467e10] width 1280 pitch 5120 (/4 1280) >[874572.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74d3480] >[874572.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74d3480] width 1280 pitch 5120 (/4 1280) >[874572.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce7e0] >[874572.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce7e0] width 1280 pitch 5120 (/4 1280) >[874595.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74d7370] >[874595.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74d7370] width 1280 pitch 5120 (/4 1280) >[874595.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874595.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874731.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874731.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874731.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874731.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874731.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874731.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874731.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874731.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874731.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874731.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874731.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874731.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874731.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874731.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874731.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874731.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874731.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874731.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874731.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874731.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874731.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874731.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874731.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874731.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874732.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749fd50] >[874732.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749fd50] width 1280 pitch 5120 (/4 1280) >[874732.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749fd50] >[874732.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749fd50] width 1280 pitch 5120 (/4 1280) >[874732.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749fd50] >[874732.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749fd50] width 1280 pitch 5120 (/4 1280) >[874732.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874732.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874732.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874732.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874732.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874732.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874732.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874732.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874732.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874732.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874732.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874732.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874732.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874732.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874732.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874733.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874733.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874733.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874733.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874733.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874733.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874733.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874733.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874733.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874733.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874733.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874733.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874733.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874733.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874733.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874733.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874733.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874733.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874733.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874733.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874733.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874733.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874733.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874733.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874733.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874733.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874733.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874735.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874735.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874736.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747f2a0] >[874736.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747f2a0] width 1280 pitch 5120 (/4 1280) >[874736.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874736.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874737.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749d690] >[874737.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749d690] width 1280 pitch 5120 (/4 1280) >[874737.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874738.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874738.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749d690] >[874738.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749d690] width 1280 pitch 5120 (/4 1280) >[874738.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874738.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874739.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874739.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874741.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874741.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874741.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874742.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874742.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874742.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874742.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874742.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874742.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72039a0] >[874742.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72039a0] width 1280 pitch 5120 (/4 1280) >[874742.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874742.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874742.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874743.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874743.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b72e0] >[874743.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b72e0] width 1280 pitch 5120 (/4 1280) >[874743.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874743.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874743.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484ab0] >[874743.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484ab0] width 1280 pitch 5120 (/4 1280) >[874743.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874743.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874746.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x747ebf0] >[874746.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x747ebf0] width 1280 pitch 5120 (/4 1280) >[874747.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874747.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874747.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874747.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874747.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874747.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874747.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874747.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874748.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98380] >[874748.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98380] width 1280 pitch 5120 (/4 1280) >[874749.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874749.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874749.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ce9b0] >[874749.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ce9b0] width 1280 pitch 5120 (/4 1280) >[874749.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874749.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874753.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74870e0] >[874753.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74870e0] width 1280 pitch 5120 (/4 1280) >[874754.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772c8a0] >[874754.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772c8a0] width 1280 pitch 5120 (/4 1280) >[874755.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x753ce60] >[874755.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x753ce60] width 1280 pitch 5120 (/4 1280) >[874873.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d1160] >[874873.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d1160] width 1280 pitch 5120 (/4 1280) >[874874.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d1160] >[874874.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d1160] width 1280 pitch 5120 (/4 1280) >[874960.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7494aa0] >[874960.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7494aa0] width 1280 pitch 5120 (/4 1280) >[874960.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773aef0] >[874960.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773aef0] width 1280 pitch 5120 (/4 1280) >[874984.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a7560] >[874984.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a7560] width 1280 pitch 5120 (/4 1280) >[874984.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b3f00] >[874985.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b3f00] width 1280 pitch 5120 (/4 1280) >[875003.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73fa3b0] >[875003.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73fa3b0] width 1280 pitch 5120 (/4 1280) >[875003.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875003.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875003.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a7560] >[875003.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a7560] width 1280 pitch 5120 (/4 1280) >[875003.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74947a0] >[875003.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74947a0] width 1280 pitch 5120 (/4 1280) >[875054.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875054.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875054.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875054.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875072.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875072.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875072.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875072.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875072.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875075.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875075.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875075.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875075.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875075.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875075.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875075.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875075.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875075.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875075.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875075.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875075.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875075.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875075.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875075.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875075.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875075.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875075.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875075.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875075.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875075.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875076.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875076.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875076.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875076.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875096.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875096.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875096.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875096.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875096.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875096.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875096.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875096.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875096.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875096.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875096.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875096.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875096.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875096.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875096.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875096.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875096.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875096.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875096.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875097.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875097.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875097.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875097.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875097.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875098.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875098.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875098.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875098.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875098.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875098.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875099.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875099.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875099.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875099.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875099.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875099.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875099.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875099.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875101.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875101.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875101.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875101.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875101.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875101.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875101.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875101.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875101.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875101.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875101.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875101.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875101.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875101.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875101.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875101.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875101.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875101.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875101.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875101.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875101.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875101.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875101.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875101.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875102.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875102.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875102.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875102.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875102.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875102.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875102.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875102.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875102.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875102.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875102.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875102.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875102.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875102.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875102.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875102.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875102.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875102.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875102.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875102.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875102.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875102.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875102.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875102.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875102.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875102.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875102.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875102.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875103.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875103.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875103.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a6a10] >[875103.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a6a10] width 1280 pitch 5120 (/4 1280) >[875103.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875103.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875103.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875104.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875104.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875104.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875104.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875104.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875104.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875104.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875110.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875110.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875122.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875122.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875122.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875122.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875123.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ccdf0] >[875123.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ccdf0] width 1280 pitch 5120 (/4 1280) >[875124.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875124.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875124.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875124.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875124.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875124.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875136.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875136.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875136.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875136.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875137.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5229da0] >[875137.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5229da0] width 1280 pitch 5120 (/4 1280) >[875137.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875137.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875137.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875137.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875137.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875137.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875157.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875157.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875157.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875157.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875157.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875157.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875158.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875158.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875158.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875158.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875158.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875158.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875165.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875165.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875165.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875165.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875165.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875165.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875165.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875165.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875168.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875168.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875168.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875168.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875168.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875168.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875168.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875168.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875172.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875172.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875173.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875173.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875173.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875173.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875173.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875173.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875173.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875174.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875176.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875176.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875176.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875176.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875176.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875176.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875176.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875176.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875176.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875176.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875176.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875176.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875176.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875176.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875176.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875176.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875176.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875176.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875176.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875176.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875176.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875176.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875176.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875176.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875177.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875177.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875177.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875177.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875179.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875179.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875179.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875179.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875179.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875179.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875179.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875179.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875179.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875179.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875179.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875179.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875179.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875179.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875179.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875179.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875179.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875179.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875179.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629d890] >[875179.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629d890] width 1280 pitch 5120 (/4 1280) >[875179.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875179.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875179.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875179.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875179.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875179.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875180.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875180.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875180.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875180.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875180.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875180.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875180.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ad6c0] >[875180.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ad6c0] width 1280 pitch 5120 (/4 1280) >[875180.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875180.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875180.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875180.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875180.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875180.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875180.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773fdf0] >[875180.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773fdf0] width 1280 pitch 5120 (/4 1280) >[875180.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7460040] >[875180.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7460040] width 1280 pitch 5120 (/4 1280) >[875181.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875181.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875181.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[875181.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[875181.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875181.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875181.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[875181.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[875181.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875181.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875181.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7732540] >[875181.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7732540] width 1280 pitch 5120 (/4 1280) >[875181.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[875181.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[875181.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875181.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875181.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7494b10] >[875181.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7494b10] width 1280 pitch 5120 (/4 1280) >[875181.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75cf6e0] >[875181.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75cf6e0] width 1280 pitch 5120 (/4 1280) >[875181.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7494b10] >[875181.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7494b10] width 1280 pitch 5120 (/4 1280) >[875183.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875183.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875183.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875183.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875183.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875183.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875183.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875183.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875184.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875184.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875184.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77406f0] >[875184.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77406f0] width 1280 pitch 5120 (/4 1280) >[875184.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772f920] >[875185.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772f920] width 1280 pitch 5120 (/4 1280) >[875185.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875185.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875185.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875185.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875311.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875311.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875311.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742b8b0] >[875311.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742b8b0] width 1280 pitch 5120 (/4 1280) >[875341.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875341.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875342.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73fb040] >[875342.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73fb040] width 1280 pitch 5120 (/4 1280) >[875359.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875359.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875359.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7a10] >[875359.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7a10] width 1280 pitch 5120 (/4 1280) >[875392.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875392.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875392.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498ed0] >[875392.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498ed0] width 1280 pitch 5120 (/4 1280) >[875392.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875392.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875392.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7748d10] >[875392.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7748d10] width 1280 pitch 5120 (/4 1280) >[875392.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875392.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875392.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2b20] >[875392.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2b20] width 1280 pitch 5120 (/4 1280) >[875392.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875392.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875392.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875392.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875392.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5225640] >[875392.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5225640] width 1280 pitch 5120 (/4 1280) >[875392.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875392.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875392.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875392.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875392.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746cd50] >[875392.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746cd50] width 1280 pitch 5120 (/4 1280) >[875393.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x772f920] >[875393.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x772f920] width 1280 pitch 5120 (/4 1280) >[875393.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875393.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875393.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2b20] >[875393.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2b20] width 1280 pitch 5120 (/4 1280) >[875393.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875393.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875393.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[875393.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[875393.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5225640] >[875393.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5225640] width 1280 pitch 5120 (/4 1280) >[875393.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746cb90] >[875393.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746cb90] width 1280 pitch 5120 (/4 1280) >[875393.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7400] >[875393.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7400] width 1280 pitch 5120 (/4 1280) >[875393.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875393.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875393.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875393.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875393.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875393.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875393.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75be9e0] >[875393.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75be9e0] width 1280 pitch 5120 (/4 1280) >[875393.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73c68d0] >[875393.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73c68d0] width 1280 pitch 5120 (/4 1280) >[875393.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a12a0] >[875393.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a12a0] width 1280 pitch 5120 (/4 1280) >[875393.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75da0f0] >[875393.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75da0f0] width 1280 pitch 5120 (/4 1280) >[875393.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5227450] >[875393.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5227450] width 1280 pitch 5120 (/4 1280) >[875393.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71359d0] >[875393.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71359d0] width 1280 pitch 5120 (/4 1280) >[875393.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875393.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875393.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73fb040] >[875393.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73fb040] width 1280 pitch 5120 (/4 1280) >[875393.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f9480] >[875393.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f9480] width 1280 pitch 5120 (/4 1280) >[875393.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a6e0] >[875393.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a6e0] width 1280 pitch 5120 (/4 1280) >[875393.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875393.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875394.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875394.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875394.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875394.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875394.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2b20] >[875394.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2b20] width 1280 pitch 5120 (/4 1280) >[875394.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5225640] >[875394.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5225640] width 1280 pitch 5120 (/4 1280) >[875394.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875394.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875394.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875394.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875394.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746cd50] >[875394.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746cd50] width 1280 pitch 5120 (/4 1280) >[875394.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875394.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875394.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875394.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875394.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f9480] >[875394.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f9480] width 1280 pitch 5120 (/4 1280) >[875395.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73fb040] >[875395.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73fb040] width 1280 pitch 5120 (/4 1280) >[875395.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f9480] >[875395.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f9480] width 1280 pitch 5120 (/4 1280) >[875395.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7748d10] >[875395.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7748d10] width 1280 pitch 5120 (/4 1280) >[875395.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b7fc0] >[875395.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b7fc0] width 1280 pitch 5120 (/4 1280) >[875395.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875395.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875395.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2b20] >[875395.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2b20] width 1280 pitch 5120 (/4 1280) >[875395.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875395.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875395.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875395.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875395.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875395.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875395.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715a2b0] >[875395.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715a2b0] width 1280 pitch 5120 (/4 1280) >[875395.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5225640] >[875395.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5225640] width 1280 pitch 5120 (/4 1280) >[875395.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875395.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875395.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d8390] >[875395.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d8390] width 1280 pitch 5120 (/4 1280) >[875395.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74e2d20] >[875395.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74e2d20] width 1280 pitch 5120 (/4 1280) >[875395.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7400] >[875395.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7400] width 1280 pitch 5120 (/4 1280) >[875395.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875395.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875395.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875395.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875395.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875395.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875395.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52258d0] >[875396.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52258d0] width 1280 pitch 5120 (/4 1280) >[875396.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875396.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875396.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[875396.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[875396.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a2830] >[875396.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a2830] width 1280 pitch 5120 (/4 1280) >[875425.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746cb90] >[875425.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746cb90] width 1280 pitch 5120 (/4 1280) >[875425.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875425.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875486.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74944e0] >[875487.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74944e0] width 1280 pitch 5120 (/4 1280) >[875487.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875487.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875487.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875487.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875488.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875488.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875488.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875488.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875488.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75da0f0] >[875488.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75da0f0] width 1280 pitch 5120 (/4 1280) >[875495.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875495.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875495.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875495.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875495.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875495.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875495.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875495.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875495.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875495.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875495.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875495.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875495.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875495.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875495.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875495.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875495.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875495.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875495.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875495.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875496.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875496.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875496.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875496.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875496.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875496.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875496.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875496.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875496.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875496.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875496.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875496.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875496.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875496.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875496.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875496.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875496.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875496.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875497.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875497.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875497.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7747560] >[875497.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7747560] width 1280 pitch 5120 (/4 1280) >[875497.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[875497.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[875497.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875497.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875497.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875497.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875497.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875497.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875497.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875497.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875497.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875497.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875497.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875497.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875497.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875497.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875497.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875497.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875497.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875497.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875497.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875497.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875497.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74069a0] >[875497.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74069a0] width 1280 pitch 5120 (/4 1280) >[875497.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875497.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875497.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875497.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875497.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875497.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875497.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74cd600] >[875497.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74cd600] width 1280 pitch 5120 (/4 1280) >[875498.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74944e0] >[875498.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74944e0] width 1280 pitch 5120 (/4 1280) >[875498.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875498.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875498.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74944e0] >[875498.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74944e0] width 1280 pitch 5120 (/4 1280) >[875498.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7748d10] >[875499.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7748d10] width 1280 pitch 5120 (/4 1280) >[875499.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7748d10] >[875499.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7748d10] width 1280 pitch 5120 (/4 1280) >[875499.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875499.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875499.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875499.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875499.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875499.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875499.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875499.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875499.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875499.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875499.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f9480] >[875499.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f9480] width 1280 pitch 5120 (/4 1280) >[875500.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[875500.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[875500.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75c1350] >[875500.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75c1350] width 1280 pitch 5120 (/4 1280) >[875500.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[875500.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[875500.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875500.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875500.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875500.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875500.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875500.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746a290] >[875500.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746a290] width 1280 pitch 5120 (/4 1280) >[875500.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875500.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875501.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73f9130] >[875501.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73f9130] width 1280 pitch 5120 (/4 1280) >[875502.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749a6e0] >[875502.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749a6e0] width 1280 pitch 5120 (/4 1280) >[875502.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7747560] >[875502.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7747560] width 1280 pitch 5120 (/4 1280) >[875502.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875502.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875508.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875508.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875508.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7164f60] >[875508.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7164f60] width 1280 pitch 5120 (/4 1280) >[875509.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71647c0] >[875509.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71647c0] width 1280 pitch 5120 (/4 1280) >[875509.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875509.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875509.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b5a40] >[875509.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b5a40] width 1280 pitch 5120 (/4 1280) >[875509.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875509.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875521.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875521.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875523.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[875523.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[875523.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52258d0] >[875523.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52258d0] width 1280 pitch 5120 (/4 1280) >[875523.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ca810] >[875523.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ca810] width 1280 pitch 5120 (/4 1280) >[875578.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74623a0] >[875578.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74623a0] width 1280 pitch 5120 (/4 1280) >[875578.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71b03e0] >[875578.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71b03e0] width 1280 pitch 5120 (/4 1280) >[875578.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875578.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875578.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fc350] >[875578.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fc350] width 1280 pitch 5120 (/4 1280) >[875724.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875724.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875724.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7400] >[875724.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7400] width 1280 pitch 5120 (/4 1280) >[875724.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875724.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875724.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7400] >[875724.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7400] width 1280 pitch 5120 (/4 1280) >[875724.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875725.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875735.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875735.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875735.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746d890] >[875735.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746d890] width 1280 pitch 5120 (/4 1280) >[875735.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7106860] >[875735.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7106860] width 1280 pitch 5120 (/4 1280) >[875735.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875735.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875735.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72177c0] >[875735.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72177c0] width 1280 pitch 5120 (/4 1280) >[875735.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7164f60] >[875735.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7164f60] width 1280 pitch 5120 (/4 1280) >[875735.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7164f60] >[875735.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7164f60] width 1280 pitch 5120 (/4 1280) >[875752.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7164f60] >[875752.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7164f60] width 1280 pitch 5120 (/4 1280) >[875752.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71af7b0] >[875752.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71af7b0] width 1280 pitch 5120 (/4 1280) >[875753.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875753.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875753.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5227450] >[875753.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5227450] width 1280 pitch 5120 (/4 1280) >[875754.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x717a530] >[875754.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x717a530] width 1280 pitch 5120 (/4 1280) >[875787.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875787.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875787.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875787.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875787.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875787.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875787.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875787.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875787.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875787.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875787.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875787.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875787.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875788.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875788.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875788.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875788.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875788.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875788.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875788.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875788.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875788.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875788.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875788.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875788.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875788.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875788.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875788.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875788.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72177c0] >[875788.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72177c0] width 1280 pitch 5120 (/4 1280) >[875788.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[875788.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[875788.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72177c0] >[875788.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72177c0] width 1280 pitch 5120 (/4 1280) >[875788.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7106860] >[875788.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7106860] width 1280 pitch 5120 (/4 1280) >[875788.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875788.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875788.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7106860] >[875788.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7106860] width 1280 pitch 5120 (/4 1280) >[875789.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875789.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875790.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875790.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875790.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875790.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875790.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875790.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875790.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875790.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875790.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875790.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875790.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875790.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875790.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875790.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875790.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875790.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875790.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7749120] >[875790.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7749120] width 1280 pitch 5120 (/4 1280) >[875791.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875791.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875791.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875791.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875792.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875792.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875792.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875792.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875793.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875793.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875793.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[875793.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[875793.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[875793.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[875793.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7746d20] >[875793.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7746d20] width 1280 pitch 5120 (/4 1280) >[875804.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a7400] >[875804.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a7400] width 1280 pitch 5120 (/4 1280) >[875805.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875805.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875805.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aaa70] >[875805.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aaa70] width 1280 pitch 5120 (/4 1280) >[875805.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875805.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875805.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aaa70] >[875805.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aaa70] width 1280 pitch 5120 (/4 1280) >[875805.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875805.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875805.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aaa70] >[875805.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aaa70] width 1280 pitch 5120 (/4 1280) >[875805.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875805.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875805.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aaa70] >[875805.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aaa70] width 1280 pitch 5120 (/4 1280) >[875805.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875805.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875805.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aaa70] >[875805.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aaa70] width 1280 pitch 5120 (/4 1280) >[875805.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875805.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875805.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875805.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875805.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7106860] >[875805.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7106860] width 1280 pitch 5120 (/4 1280) >[875805.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875805.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875805.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875805.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875805.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875805.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875805.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7444b60] >[875805.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7444b60] width 1280 pitch 5120 (/4 1280) >[875805.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9bb0] >[875806.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9bb0] width 1280 pitch 5120 (/4 1280) >[875806.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875806.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875806.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[875806.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[875806.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875806.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875806.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[875806.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[875806.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[875806.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[875806.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75be9e0] >[875806.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75be9e0] width 1280 pitch 5120 (/4 1280) >[875806.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aee30] >[875806.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aee30] width 1280 pitch 5120 (/4 1280) >[875806.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75be9e0] >[875806.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75be9e0] width 1280 pitch 5120 (/4 1280) >[875807.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x749ffb0] >[875807.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x749ffb0] width 1280 pitch 5120 (/4 1280) >[875807.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71af7b0] >[875807.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71af7b0] width 1280 pitch 5120 (/4 1280) >[875807.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b9d50] >[875807.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b9d50] width 1280 pitch 5120 (/4 1280) >[875807.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875807.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875807.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746d890] >[875807.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746d890] width 1280 pitch 5120 (/4 1280) >[875807.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[875807.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[875807.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x746d890] >[875807.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x746d890] width 1280 pitch 5120 (/4 1280) >[875807.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x724b670] >[875807.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x724b670] width 1280 pitch 5120 (/4 1280) >[875807.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[875807.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[875807.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5227450] >[875807.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5227450] width 1280 pitch 5120 (/4 1280) >[875807.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875807.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875807.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875807.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875808.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875808.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875808.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875808.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875808.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875808.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875808.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875808.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875808.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875808.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875808.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875808.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875808.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aca30] >[875808.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aca30] width 1280 pitch 5120 (/4 1280) >[875808.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875808.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b7f660] >[875808.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b7f660] width 1280 pitch 5120 (/4 1280) >[875808.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x73cb3b0] >[875808.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x73cb3b0] width 1280 pitch 5120 (/4 1280) >[875820.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ad760] >[875820.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ad760] width 1280 pitch 5120 (/4 1280) >[875823.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75da0f0] >[875823.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75da0f0] width 1280 pitch 5120 (/4 1280) >[875823.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875823.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875823.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875823.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875823.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875823.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875823.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875823.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875823.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875823.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875823.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74effe0] >[875823.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74effe0] width 1280 pitch 5120 (/4 1280) >[875823.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[875823.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[875823.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[875823.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[875823.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875823.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875823.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[875824.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[875824.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875824.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875824.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[875824.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[875824.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745b1e0] >[875824.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745b1e0] width 1280 pitch 5120 (/4 1280) >[875824.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[875824.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[875824.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875824.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875824.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875824.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875825.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[875825.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[875825.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875825.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875825.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[875825.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[875826.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7496900] >[875826.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7496900] width 1280 pitch 5120 (/4 1280) >[875827.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7493b50] >[875827.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7493b50] width 1280 pitch 5120 (/4 1280) >[875828.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875828.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875828.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[875828.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[875828.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875828.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[875828.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75be9e0] >[875828.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75be9e0] width 1280 pitch 5120 (/4 1280) >[875828.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7445ec0] >[875828.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7445ec0] width 1280 pitch 5120 (/4 1280) >[877021.554] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[877021.554] (II) RADEON(0): Printing DDC gathered Modelines: >[877021.554] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[877111.920] (II) RADEON(0): RADEONSaveScreen(2) >[877111.925] (II) RADEON(0): RADEONSaveScreen(0) >[904102.014] (II) RADEON(0): RADEONSaveScreen(1) >[904115.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7170610] >[904115.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7170610] width 1280 pitch 5120 (/4 1280) >[904116.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b9d50] >[904116.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b9d50] width 1280 pitch 5120 (/4 1280) >[904117.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904117.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904117.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b9d50] >[904117.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b9d50] width 1280 pitch 5120 (/4 1280) >[904117.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904117.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904118.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b9d50] >[904118.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b9d50] width 1280 pitch 5120 (/4 1280) >[904118.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b9d50] >[904118.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b9d50] width 1280 pitch 5120 (/4 1280) >[904118.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[904118.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[904118.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[904118.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[904118.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[904118.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[904118.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7497c20] >[904118.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7497c20] width 1280 pitch 5120 (/4 1280) >[904118.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74a04b0] >[904118.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74a04b0] width 1280 pitch 5120 (/4 1280) >[904121.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7731370] >[904121.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7731370] width 1280 pitch 5120 (/4 1280) >[904135.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7464280] >[904135.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7464280] width 1280 pitch 5120 (/4 1280) >[904274.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7450320] >[904274.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7450320] width 1280 pitch 5120 (/4 1280) >[904296.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c31f0] >[904296.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c31f0] width 1280 pitch 5120 (/4 1280) >[904296.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904296.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904715.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fbd80] >[904715.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fbd80] width 1280 pitch 5120 (/4 1280) >[904715.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c31f0] >[904715.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c31f0] width 1280 pitch 5120 (/4 1280) >[904715.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fbd80] >[904715.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fbd80] width 1280 pitch 5120 (/4 1280) >[904715.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c31f0] >[904715.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c31f0] width 1280 pitch 5120 (/4 1280) >[904715.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fbd80] >[904715.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fbd80] width 1280 pitch 5120 (/4 1280) >[904715.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c31f0] >[904715.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c31f0] width 1280 pitch 5120 (/4 1280) >[904715.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fbd80] >[904715.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fbd80] width 1280 pitch 5120 (/4 1280) >[904715.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904715.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904715.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[904715.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[904715.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904716.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904716.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[904716.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[904716.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904716.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904716.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[904716.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[904716.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904716.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904716.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b12a0] >[904716.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b12a0] width 1280 pitch 5120 (/4 1280) >[904716.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904716.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904716.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904716.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904716.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904716.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75dc400] >[904716.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75dc400] width 1280 pitch 5120 (/4 1280) >[904716.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75d45d0] >[904716.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75d45d0] width 1280 pitch 5120 (/4 1280) >[904718.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70c3ee0] >[904718.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70c3ee0] width 1280 pitch 5120 (/4 1280) >[904718.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x715b680] >[904718.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x715b680] width 1280 pitch 5120 (/4 1280) >[904718.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70c3ee0] >[904718.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70c3ee0] width 1280 pitch 5120 (/4 1280) >[904718.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75fbd80] >[904718.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75fbd80] width 1280 pitch 5120 (/4 1280) >[904719.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904719.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904719.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[904719.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[904719.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904719.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904719.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748a150] >[904719.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748a150] width 1280 pitch 5120 (/4 1280) >[904719.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75b6990] >[904719.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75b6990] width 1280 pitch 5120 (/4 1280) >[904719.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904719.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74b94e0] >[904719.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74b94e0] width 1280 pitch 5120 (/4 1280) >[904719.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748f350] >[904719.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748f350] width 1280 pitch 5120 (/4 1280) >[904721.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b12a0] >[904721.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b12a0] width 1280 pitch 5120 (/4 1280) >[904723.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52053a0] >[904723.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52053a0] width 1280 pitch 5120 (/4 1280) >[904724.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b12a0] >[904724.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b12a0] width 1280 pitch 5120 (/4 1280) >[904748.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x600fb50] >[904748.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x600fb50] width 1280 pitch 5120 (/4 1280) >[904783.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7216380] >[904783.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7216380] width 1280 pitch 5120 (/4 1280) >[904785.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76caf60] >[904785.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76caf60] width 1280 pitch 5120 (/4 1280) >[904896.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7752aa0] >[904896.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7752aa0] width 1280 pitch 5120 (/4 1280) >[904901.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x745cb40] >[904901.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x745cb40] width 1280 pitch 5120 (/4 1280) >[904988.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52047c0] >[904988.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52047c0] width 1280 pitch 5120 (/4 1280) >[904988.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748d6a0] >[904988.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748d6a0] width 1280 pitch 5120 (/4 1280) >[905003.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74f14c0] >[905003.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74f14c0] width 1280 pitch 5120 (/4 1280) >[905063.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7166b60] >[905063.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7166b60] width 1280 pitch 5120 (/4 1280) >[905067.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74bcd30] >[905067.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74bcd30] width 1280 pitch 5120 (/4 1280) >[905067.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75bd090] >[905067.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75bd090] width 1280 pitch 5120 (/4 1280) >[905072.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7166b60] >[905072.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7166b60] width 1280 pitch 5120 (/4 1280) >[905227.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c7410] >[905227.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c7410] width 1280 pitch 5120 (/4 1280) >[905227.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c7410] >[905227.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c7410] width 1280 pitch 5120 (/4 1280) >[905335.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75bd090] >[905335.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75bd090] width 1280 pitch 5120 (/4 1280) >[905335.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7166b60] >[905335.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7166b60] width 1280 pitch 5120 (/4 1280) >[905943.042] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[905943.042] (II) RADEON(0): Printing DDC gathered Modelines: >[905943.042] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[906032.902] (II) RADEON(0): RADEONSaveScreen(2) >[906032.902] (II) RADEON(0): RADEONSaveScreen(0) >[910831.987] (II) RADEON(0): RADEONSaveScreen(1) >[910838.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c5cb0] >[910838.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c5cb0] width 1280 pitch 5120 (/4 1280) >[910850.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[910850.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[910871.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ea270] >[910871.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ea270] width 1280 pitch 5120 (/4 1280) >[910871.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ea270] >[910871.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ea270] width 1280 pitch 5120 (/4 1280) >[910871.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70b76b0] >[910871.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70b76b0] width 1280 pitch 5120 (/4 1280) >[910871.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c58e0] >[910871.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c58e0] width 1280 pitch 5120 (/4 1280) >[911471.835] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[911471.835] (II) RADEON(0): Printing DDC gathered Modelines: >[911471.835] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[911653.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911653.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911653.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911653.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911653.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b820] >[911653.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b820] width 1280 pitch 5120 (/4 1280) >[911653.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911653.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911653.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911653.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911653.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911653.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911653.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911653.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911653.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef7a0] >[911653.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef7a0] width 1280 pitch 5120 (/4 1280) >[911653.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70b76b0] >[911653.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70b76b0] width 1280 pitch 5120 (/4 1280) >[911653.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911653.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911654.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911654.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911654.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911654.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911654.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b820] >[911654.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b820] width 1280 pitch 5120 (/4 1280) >[911654.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911654.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911654.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b820] >[911654.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b820] width 1280 pitch 5120 (/4 1280) >[911654.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911654.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911654.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911654.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911654.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911654.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911654.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911654.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911654.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911654.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911655.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911655.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911655.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef7a0] >[911655.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef7a0] width 1280 pitch 5120 (/4 1280) >[911655.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911655.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911655.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b820] >[911655.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b820] width 1280 pitch 5120 (/4 1280) >[911655.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911655.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911655.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef7a0] >[911655.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef7a0] width 1280 pitch 5120 (/4 1280) >[911655.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911655.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911655.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911655.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911655.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911655.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[911655.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70b76b0] >[911655.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70b76b0] width 1280 pitch 5120 (/4 1280) >[911655.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911655.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911655.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911655.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911655.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911655.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911655.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911655.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911655.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911655.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911655.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911655.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911655.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911655.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911655.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef7a0] >[911655.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef7a0] width 1280 pitch 5120 (/4 1280) >[911655.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70b76b0] >[911655.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70b76b0] width 1280 pitch 5120 (/4 1280) >[911655.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911655.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911656.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911656.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911656.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b820] >[911656.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b820] width 1280 pitch 5120 (/4 1280) >[911656.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911656.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911656.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70b76b0] >[911656.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70b76b0] width 1280 pitch 5120 (/4 1280) >[911656.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64aba30] >[911656.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64aba30] width 1280 pitch 5120 (/4 1280) >[911657.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[911657.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[911657.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef7a0] >[911657.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef7a0] width 1280 pitch 5120 (/4 1280) >[911657.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[911657.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[911668.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[911668.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[911668.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[911668.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[911672.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[911672.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[912035.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770d5d0] >[912035.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770d5d0] width 1280 pitch 5120 (/4 1280) >[913276.533] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[913276.533] (II) RADEON(0): Printing DDC gathered Modelines: >[913276.533] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[913282.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913282.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913282.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913282.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913282.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913282.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913282.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913282.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913282.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913282.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913282.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913282.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913282.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913282.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913282.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913282.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913282.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913282.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913282.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913282.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913282.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913282.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913283.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913283.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913283.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913283.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913283.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913283.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913283.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913283.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913283.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913283.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913283.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913283.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913283.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913283.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913284.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913284.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913284.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913284.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913284.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913284.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913284.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913284.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913284.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913284.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913284.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913284.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913284.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913284.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913284.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913284.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913284.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913284.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913284.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913284.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913284.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913284.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913284.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913284.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913284.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913284.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913284.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913284.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913285.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913285.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913285.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913285.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913285.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913285.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913285.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913285.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913285.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913285.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913285.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913285.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913285.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913285.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913285.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913285.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913285.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913285.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913285.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913285.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913285.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913285.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913285.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913285.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913285.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913285.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913285.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913285.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913285.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913285.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913285.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913285.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913285.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913285.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913285.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913285.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913285.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913286.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913286.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913286.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913286.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913286.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913286.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913286.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913286.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913286.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913286.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913286.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913286.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913286.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913286.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913286.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913286.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913286.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913286.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913286.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913286.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913286.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913286.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913286.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913286.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913288.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913288.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913288.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913288.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913288.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913288.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913288.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913288.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913427.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913427.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913427.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913427.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913427.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913427.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913427.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913427.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913427.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913427.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913427.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913427.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913427.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913427.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913427.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913427.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913427.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913427.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913427.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913427.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913427.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913427.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913427.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913427.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913427.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913427.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913428.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913428.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913428.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913428.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913428.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913428.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913428.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913428.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913428.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913428.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913428.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913428.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913428.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913428.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913429.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913429.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913429.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913429.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913429.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913429.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913429.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913429.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913429.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913429.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913429.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x642b8a0] >[913429.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x642b8a0] width 1280 pitch 5120 (/4 1280) >[913429.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913429.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913429.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913429.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913430.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913430.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913430.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913430.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913431.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913431.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913431.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x63829f0] >[913431.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x63829f0] width 1280 pitch 5120 (/4 1280) >[913431.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74c4590] >[913431.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74c4590] width 1280 pitch 5120 (/4 1280) >[913432.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913432.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6311c20] >[913432.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6311c20] width 1280 pitch 5120 (/4 1280) >[913432.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eb820] >[913432.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eb820] width 1280 pitch 5120 (/4 1280) >[913433.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6070] >[913433.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6070] width 1280 pitch 5120 (/4 1280) >[913433.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b9d60] >[913433.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b9d60] width 1280 pitch 5120 (/4 1280) >[913433.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x770eb50] >[913433.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x770eb50] width 1280 pitch 5120 (/4 1280) >[913433.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6070] >[913433.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6070] width 1280 pitch 5120 (/4 1280) >[913433.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913433.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913433.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58b9d60] >[913433.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58b9d60] width 1280 pitch 5120 (/4 1280) >[913433.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913433.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913433.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d0e0] >[913433.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d0e0] width 1280 pitch 5120 (/4 1280) >[913433.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cbf340] >[913433.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cbf340] width 1280 pitch 5120 (/4 1280) >[913433.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484160] >[913433.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484160] width 1280 pitch 5120 (/4 1280) >[913433.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913433.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913433.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913433.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913433.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cbf340] >[913433.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cbf340] width 1280 pitch 5120 (/4 1280) >[913433.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d0e0] >[913433.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d0e0] width 1280 pitch 5120 (/4 1280) >[913433.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6070] >[913433.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6070] width 1280 pitch 5120 (/4 1280) >[913433.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d0e0] >[913433.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d0e0] width 1280 pitch 5120 (/4 1280) >[913434.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913434.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913434.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484160] >[913434.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484160] width 1280 pitch 5120 (/4 1280) >[913434.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484160] >[913434.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484160] width 1280 pitch 5120 (/4 1280) >[913435.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6070] >[913435.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6070] width 1280 pitch 5120 (/4 1280) >[913435.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x711a090] >[913435.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x711a090] width 1280 pitch 5120 (/4 1280) >[913435.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7484160] >[913435.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7484160] width 1280 pitch 5120 (/4 1280) >[913435.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6070] >[913435.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6070] width 1280 pitch 5120 (/4 1280) >[913441.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7753b20] >[913441.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7753b20] width 1280 pitch 5120 (/4 1280) >[913441.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7753b20] >[913441.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7753b20] width 1280 pitch 5120 (/4 1280) >[913470.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913470.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913470.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7707060] >[913470.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7707060] width 1280 pitch 5120 (/4 1280) >[913471.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913471.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913471.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913471.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913655.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913655.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913655.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913655.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913655.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913655.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913655.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913656.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913656.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913656.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913656.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913656.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913656.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913656.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913656.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913656.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913656.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913656.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913656.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913656.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913656.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913656.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913656.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913656.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913656.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913656.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913656.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913656.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913656.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913656.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913656.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913656.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913656.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913656.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913656.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913656.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913656.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913656.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913656.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913656.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913656.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913656.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913656.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913656.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913656.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913656.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913656.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913656.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913656.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913656.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913656.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913656.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913656.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913656.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913656.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913657.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913657.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913657.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913657.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913657.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913657.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913657.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913657.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913657.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913657.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913657.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913657.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913657.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913657.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913657.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913657.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913657.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913657.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913657.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913657.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913657.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913657.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913657.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913657.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913657.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913657.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913658.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913658.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913658.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913658.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913658.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913658.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913658.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913658.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913658.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913658.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913658.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913658.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913658.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913658.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913658.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913658.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913658.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913658.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913658.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913658.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913658.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913658.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913658.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913658.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913658.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913658.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913658.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913658.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913658.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913658.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913658.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913658.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913658.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913658.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x742ee00] >[913658.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x742ee00] width 1280 pitch 5120 (/4 1280) >[913658.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913658.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913680.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913680.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913680.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913680.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913701.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7624530] >[913701.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7624530] width 1280 pitch 5120 (/4 1280) >[913701.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913701.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913829.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913829.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913829.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913829.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913829.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913829.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913829.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913829.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913829.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913829.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913829.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913829.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913829.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913829.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913829.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913829.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913829.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913829.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913829.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913829.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913829.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913829.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913829.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913829.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913829.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913829.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913829.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913829.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913829.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913829.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913829.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913829.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913829.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913829.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913829.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913829.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913829.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913830.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913830.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913830.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913830.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913830.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913830.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913830.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913830.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913830.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913830.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913830.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913830.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913830.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913830.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913830.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913830.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913830.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913830.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[913830.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[913830.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[913830.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[913830.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913830.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913830.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913830.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913830.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913830.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913830.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913830.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913830.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913830.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913843.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913843.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913843.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[913843.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[913843.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76ce7a0] >[913843.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76ce7a0] width 1280 pitch 5120 (/4 1280) >[913843.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913843.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[913926.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[913926.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[913926.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[913926.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[913977.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[913977.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[913977.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[913977.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914008.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914008.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914008.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914008.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914008.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914008.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914008.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914008.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914008.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914008.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914008.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914008.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914008.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914008.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914008.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[914008.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[914008.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[914008.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[914008.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914008.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914008.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914008.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914008.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914008.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914008.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914008.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914008.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914008.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914008.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914008.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914008.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914008.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914008.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914008.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914008.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914008.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914008.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914008.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914008.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914008.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914008.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914009.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e280] >[914009.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e280] width 1280 pitch 5120 (/4 1280) >[914009.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914009.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914010.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914010.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914010.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914010.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[914011.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[914011.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914011.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914011.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914011.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914011.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914011.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914011.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914011.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914011.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x70cc990] >[914011.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x70cc990] width 1280 pitch 5120 (/4 1280) >[914011.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914011.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[914011.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[914011.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914011.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74989d0] >[914011.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74989d0] width 1280 pitch 5120 (/4 1280) >[914011.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914011.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914011.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914011.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914011.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7498510] >[914011.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7498510] width 1280 pitch 5120 (/4 1280) >[914011.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914011.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914011.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914011.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914011.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75eee20] >[914011.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75eee20] width 1280 pitch 5120 (/4 1280) >[914011.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773e1a0] >[914011.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773e1a0] width 1280 pitch 5120 (/4 1280) >[914119.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914119.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914121.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914121.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914121.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914121.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914121.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914121.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914121.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914121.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914121.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914121.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914121.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914121.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914121.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914121.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914121.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914121.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914121.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914121.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914121.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914121.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914121.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914121.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914121.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914121.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914121.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914121.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914122.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914122.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914122.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914122.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914122.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914122.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914122.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914122.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914122.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914122.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914122.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914122.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914122.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914122.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914122.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914122.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914122.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914122.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914122.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914122.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914122.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914122.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914122.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914122.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914122.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914122.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914122.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914122.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914123.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914123.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914123.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914123.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914123.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914123.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914123.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914123.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914123.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914123.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914123.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914123.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914123.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914123.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914123.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914123.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914123.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914123.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914123.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a7e0] >[914123.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a7e0] width 1280 pitch 5120 (/4 1280) >[914123.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee910] >[914123.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee910] width 1280 pitch 5120 (/4 1280) >[914123.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64818c0] >[914123.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64818c0] width 1280 pitch 5120 (/4 1280) >[914123.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914123.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914124.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d1b0] >[914124.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d1b0] width 1280 pitch 5120 (/4 1280) >[914124.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914124.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914132.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914132.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914135.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d340] >[914135.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d340] width 1280 pitch 5120 (/4 1280) >[914135.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914135.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d340] >[914135.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d340] width 1280 pitch 5120 (/4 1280) >[914135.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914135.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee2f0] >[914135.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee2f0] width 1280 pitch 5120 (/4 1280) >[914135.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914135.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee2f0] >[914135.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee2f0] width 1280 pitch 5120 (/4 1280) >[914135.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f30] >[914135.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f30] width 1280 pitch 5120 (/4 1280) >[914135.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914135.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914135.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914135.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914135.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914135.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914135.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914135.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914135.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ee2f0] >[914135.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ee2f0] width 1280 pitch 5120 (/4 1280) >[914136.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fed0] >[914136.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fed0] width 1280 pitch 5120 (/4 1280) >[914136.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914136.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fe70] >[914136.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fe70] width 1280 pitch 5120 (/4 1280) >[914136.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914136.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fe70] >[914136.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fe70] width 1280 pitch 5120 (/4 1280) >[914136.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914136.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fe70] >[914136.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fe70] width 1280 pitch 5120 (/4 1280) >[914136.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914136.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fee0] >[914136.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fee0] width 1280 pitch 5120 (/4 1280) >[914136.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914136.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763fee0] >[914136.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763fee0] width 1280 pitch 5120 (/4 1280) >[914136.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763bde0] >[914136.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763bde0] width 1280 pitch 5120 (/4 1280) >[914148.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6481870] >[914148.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6481870] width 1280 pitch 5120 (/4 1280) >[914153.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x773d2d0] >[914153.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x773d2d0] width 1280 pitch 5120 (/4 1280) >[914182.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6542070] >[914182.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6542070] width 1280 pitch 5120 (/4 1280) >[914182.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914182.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914182.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6542070] >[914182.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6542070] width 1280 pitch 5120 (/4 1280) >[914182.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914182.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914191.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6542070] >[914191.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6542070] width 1280 pitch 5120 (/4 1280) >[914191.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6481870] >[914191.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6481870] width 1280 pitch 5120 (/4 1280) >[914191.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763b9f0] >[914191.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763b9f0] width 1280 pitch 5120 (/4 1280) >[914191.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914192.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914192.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763b9f0] >[914192.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763b9f0] width 1280 pitch 5120 (/4 1280) >[914193.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914193.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914193.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914193.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914194.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914194.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914194.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763b9f0] >[914194.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763b9f0] width 1280 pitch 5120 (/4 1280) >[914195.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914195.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914195.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914195.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914195.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7657490] >[914195.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7657490] width 1280 pitch 5120 (/4 1280) >[914196.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7657490] >[914196.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7657490] width 1280 pitch 5120 (/4 1280) >[914196.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763b9f0] >[914196.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763b9f0] width 1280 pitch 5120 (/4 1280) >[914196.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c500] >[914196.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c500] width 1280 pitch 5120 (/4 1280) >[914196.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7657490] >[914196.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7657490] width 1280 pitch 5120 (/4 1280) >[914197.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76aa3b0] >[914197.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76aa3b0] width 1280 pitch 5120 (/4 1280) >[914197.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x769c6b0] >[914197.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x769c6b0] width 1280 pitch 5120 (/4 1280) >[914197.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76e9ab0] >[914197.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76e9ab0] width 1280 pitch 5120 (/4 1280) >[914197.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76727c0] >[914197.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76727c0] width 1280 pitch 5120 (/4 1280) >[914197.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x769c320] >[914197.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x769c320] width 1280 pitch 5120 (/4 1280) >[914199.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a87a0] >[914199.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a87a0] width 1280 pitch 5120 (/4 1280) >[914199.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a87a0] >[914199.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a87a0] width 1280 pitch 5120 (/4 1280) >[914199.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a4da0] >[914199.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a4da0] width 1280 pitch 5120 (/4 1280) >[914200.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76eacc0] >[914200.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76eacc0] width 1280 pitch 5120 (/4 1280) >[914200.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a68e0] >[914200.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a68e0] width 1280 pitch 5120 (/4 1280) >[914200.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a68e0] >[914200.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a68e0] width 1280 pitch 5120 (/4 1280) >[914200.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x769c320] >[914200.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x769c320] width 1280 pitch 5120 (/4 1280) >[914200.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a68e0] >[914200.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a68e0] width 1280 pitch 5120 (/4 1280) >[914205.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914205.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914205.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914205.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914205.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914205.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914205.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914205.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914206.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914206.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914206.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914206.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914206.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914206.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914206.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914206.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914206.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914206.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914206.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914206.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914208.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914208.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914209.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914209.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914209.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914209.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914211.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914211.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914211.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914211.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914211.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914211.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914211.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914211.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914212.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914212.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914212.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914212.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914212.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914212.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914213.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914213.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914213.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914213.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914213.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914213.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914214.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914214.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914214.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914214.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914214.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914214.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914216.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914216.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914216.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914216.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914216.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914216.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914216.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914216.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914216.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914216.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914216.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914216.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914217.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914217.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914217.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914217.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914217.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914217.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914218.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914218.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914218.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914218.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914219.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914219.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914219.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914219.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914219.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914219.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914219.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914219.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914219.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914219.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914293.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914293.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914293.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7644be0] >[914293.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7644be0] width 1280 pitch 5120 (/4 1280) >[914293.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914293.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914294.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914294.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914294.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914294.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914295.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7644be0] >[914295.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7644be0] width 1280 pitch 5120 (/4 1280) >[914295.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7644be0] >[914295.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7644be0] width 1280 pitch 5120 (/4 1280) >[914295.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914295.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914295.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914295.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914304.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914304.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914336.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914336.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914336.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914336.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914336.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914336.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914336.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914336.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914336.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914336.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914336.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914336.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914336.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914336.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914337.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914337.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914337.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914337.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914337.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914337.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914338.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914338.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914338.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914338.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914338.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914338.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914338.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7644be0] >[914338.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7644be0] width 1280 pitch 5120 (/4 1280) >[914338.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914338.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914338.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914339.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914339.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914339.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914339.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914339.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914339.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914339.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914339.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914339.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914339.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763c5a0] >[914339.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763c5a0] width 1280 pitch 5120 (/4 1280) >[914339.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914339.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914339.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914339.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914339.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2c080] >[914339.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2c080] width 1280 pitch 5120 (/4 1280) >[914339.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914339.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914339.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2c080] >[914339.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2c080] width 1280 pitch 5120 (/4 1280) >[914339.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914339.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914339.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914339.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914339.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914339.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914339.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914339.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914339.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914339.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914339.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914339.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914339.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7186cb0] >[914339.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7186cb0] width 1280 pitch 5120 (/4 1280) >[914339.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914339.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914381.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914381.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914381.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914381.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914381.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914381.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914381.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7644be0] >[914381.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7644be0] width 1280 pitch 5120 (/4 1280) >[914382.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914382.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914383.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914383.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914383.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71593a0] >[914383.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71593a0] width 1280 pitch 5120 (/4 1280) >[914384.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914384.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914384.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914384.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914384.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914384.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914384.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914384.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914384.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914384.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914384.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x766eba0] >[914384.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x766eba0] width 1280 pitch 5120 (/4 1280) >[914384.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914384.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914384.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x766eba0] >[914384.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x766eba0] width 1280 pitch 5120 (/4 1280) >[914384.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914384.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914384.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71593a0] >[914384.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71593a0] width 1280 pitch 5120 (/4 1280) >[914384.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914384.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914384.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2c080] >[914384.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2c080] width 1280 pitch 5120 (/4 1280) >[914384.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914384.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914385.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76076d0] >[914385.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76076d0] width 1280 pitch 5120 (/4 1280) >[914385.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71593a0] >[914385.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71593a0] width 1280 pitch 5120 (/4 1280) >[914385.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2c080] >[914385.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2c080] width 1280 pitch 5120 (/4 1280) >[914385.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914385.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914385.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914385.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914385.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914385.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914385.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760d9a0] >[914385.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760d9a0] width 1280 pitch 5120 (/4 1280) >[914385.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914385.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914385.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914385.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914385.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914385.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914385.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914385.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914385.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914385.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914385.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x766eba0] >[914385.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x766eba0] width 1280 pitch 5120 (/4 1280) >[914386.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914386.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914386.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914386.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914386.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914386.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914386.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914386.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914386.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71593a0] >[914386.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71593a0] width 1280 pitch 5120 (/4 1280) >[914386.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914386.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914386.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914386.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914386.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71593a0] >[914386.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71593a0] width 1280 pitch 5120 (/4 1280) >[914387.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914387.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914388.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914388.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914388.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be2d80] >[914388.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be2d80] width 1280 pitch 5120 (/4 1280) >[914388.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914388.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914448.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914448.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914448.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914448.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914449.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914449.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914450.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914450.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914451.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760a6a0] >[914451.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760a6a0] width 1280 pitch 5120 (/4 1280) >[914454.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x766eba0] >[914454.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x766eba0] width 1280 pitch 5120 (/4 1280) >[914454.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x766eba0] >[914454.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x766eba0] width 1280 pitch 5120 (/4 1280) >[914454.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76a2c50] >[914454.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76a2c50] width 1280 pitch 5120 (/4 1280) >[914466.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x765cfd0] >[914466.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x765cfd0] width 1280 pitch 5120 (/4 1280) >[914472.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7777380] >[914472.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7777380] width 1280 pitch 5120 (/4 1280) >[914472.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914472.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914472.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7777380] >[914472.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7777380] width 1280 pitch 5120 (/4 1280) >[914472.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64ab5b0] >[914472.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64ab5b0] width 1280 pitch 5120 (/4 1280) >[914472.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914472.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914472.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64ab5b0] >[914472.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64ab5b0] width 1280 pitch 5120 (/4 1280) >[914472.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760e120] >[914472.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760e120] width 1280 pitch 5120 (/4 1280) >[914472.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64ab5b0] >[914472.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64ab5b0] width 1280 pitch 5120 (/4 1280) >[914472.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74eab50] >[914472.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74eab50] width 1280 pitch 5120 (/4 1280) >[914472.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914472.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914472.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74eab50] >[914472.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74eab50] width 1280 pitch 5120 (/4 1280) >[914472.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914472.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914472.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74eab50] >[914472.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74eab50] width 1280 pitch 5120 (/4 1280) >[914472.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74eab50] >[914472.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74eab50] width 1280 pitch 5120 (/4 1280) >[914472.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x760e120] >[914472.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x760e120] width 1280 pitch 5120 (/4 1280) >[914473.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914473.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914473.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914473.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x64dbbb0] >[914473.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x64dbbb0] width 1280 pitch 5120 (/4 1280) >[914475.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ed090] >[914475.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ed090] width 1280 pitch 5120 (/4 1280) >[914522.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914522.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914522.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914522.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914522.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914522.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914522.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914522.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914523.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914523.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914523.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914523.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914524.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914524.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914524.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914524.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914524.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914524.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914524.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914524.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914524.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914524.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914524.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914524.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914524.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914524.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914524.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914524.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914524.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914524.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914524.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914524.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aebc0] >[914526.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aebc0] width 1280 pitch 5120 (/4 1280) >[914526.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914526.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914526.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914526.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914526.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914527.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914527.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914527.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914527.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914527.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914527.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914527.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914527.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914527.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914527.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914527.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914534.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914534.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914534.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914535.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914535.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914535.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914535.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b97d0] >[914535.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b97d0] width 1280 pitch 5120 (/4 1280) >[914535.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914535.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914535.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914535.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914564.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914564.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914564.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914564.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914564.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914564.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914564.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914564.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914564.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914564.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914564.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914564.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914564.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914564.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914564.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914564.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914564.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914564.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914564.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914564.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914564.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914564.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914565.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914565.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914565.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914565.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914565.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914565.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914565.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914565.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914565.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914565.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914565.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914565.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914565.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914565.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914565.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914565.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914565.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914565.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914565.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914565.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914565.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914566.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914566.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914566.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914566.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914567.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914567.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914567.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914567.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914596.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914596.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914596.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914596.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914596.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914596.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914596.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914596.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914596.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914596.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914596.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914596.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914596.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914596.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914596.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914596.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914596.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914596.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914596.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914596.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914596.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914596.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914596.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914596.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914596.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914596.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914596.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914596.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914596.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914597.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914597.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914597.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914597.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914597.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914597.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914597.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914597.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914597.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914597.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914597.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914597.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914597.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914597.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914597.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914597.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914597.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914597.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914597.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914597.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914597.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914597.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bb1f0] >[914597.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bb1f0] width 1280 pitch 5120 (/4 1280) >[914597.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914597.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914598.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914598.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914598.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914598.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914598.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914598.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914598.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914598.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914598.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914598.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914598.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914598.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914598.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914598.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914598.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914598.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914598.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914598.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914599.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914599.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914600.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914600.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914600.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914600.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914600.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914600.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914600.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7658490] >[914601.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7658490] width 1280 pitch 5120 (/4 1280) >[914601.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914601.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914609.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914609.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914609.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914609.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914609.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914609.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914609.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914609.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914609.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914609.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914609.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914609.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914609.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914609.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914609.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b2010] >[914609.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b2010] width 1280 pitch 5120 (/4 1280) >[914609.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914609.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914609.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914609.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914609.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914609.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914609.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914609.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914609.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914609.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914609.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914609.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914609.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b2010] >[914609.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b2010] width 1280 pitch 5120 (/4 1280) >[914609.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914609.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914609.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914609.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914609.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914609.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914609.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914609.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914609.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914609.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914609.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914609.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914609.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914609.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914609.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914609.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914609.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914609.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914609.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914609.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914609.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914609.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914609.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914609.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914609.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914609.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914609.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914609.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914609.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914609.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914610.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914610.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914610.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914610.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914610.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914610.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914610.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b2010] >[914610.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b2010] width 1280 pitch 5120 (/4 1280) >[914610.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914610.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914610.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914610.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914610.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914610.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914610.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914610.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914610.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914610.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914611.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914611.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914611.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914611.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914611.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4626f40] >[914611.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4626f40] width 1280 pitch 5120 (/4 1280) >[914611.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7734de0] >[914611.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7734de0] width 1280 pitch 5120 (/4 1280) >[914612.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914612.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914612.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914612.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914612.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914612.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914612.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d310] >[914612.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d310] width 1280 pitch 5120 (/4 1280) >[914646.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914646.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914646.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914646.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914647.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914647.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914648.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914648.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914648.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7695210] >[914648.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7695210] width 1280 pitch 5120 (/4 1280) >[914649.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914649.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914649.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914649.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914649.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914649.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914649.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71ae620] >[914649.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71ae620] width 1280 pitch 5120 (/4 1280) >[914649.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914649.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914649.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914649.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914649.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914649.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914666.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914666.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914698.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914698.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914699.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914699.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914699.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914699.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914700.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914700.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914702.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914702.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914702.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aeaf0] >[914702.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aeaf0] width 1280 pitch 5120 (/4 1280) >[914702.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914702.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914702.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914702.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914702.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914702.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914703.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914703.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914703.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914703.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914704.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914704.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914704.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914704.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914704.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914704.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914704.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775b380] >[914704.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775b380] width 1280 pitch 5120 (/4 1280) >[914704.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914704.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914708.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914708.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914709.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914709.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914711.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914711.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914711.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914711.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914711.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76e6830] >[914711.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76e6830] width 1280 pitch 5120 (/4 1280) >[914711.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d9d20] >[914711.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d9d20] width 1280 pitch 5120 (/4 1280) >[914722.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b360] >[914722.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b360] width 1280 pitch 5120 (/4 1280) >[914722.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76e6830] >[914723.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76e6830] width 1280 pitch 5120 (/4 1280) >[914723.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914723.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914723.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914723.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914723.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76e6830] >[914723.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76e6830] width 1280 pitch 5120 (/4 1280) >[914723.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914723.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914723.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914723.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914723.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914723.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914723.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914723.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914723.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914723.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914723.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914723.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914723.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914723.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914723.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76e6830] >[914723.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76e6830] width 1280 pitch 5120 (/4 1280) >[914723.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914723.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914724.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914724.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914724.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77934d0] >[914724.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77934d0] width 1280 pitch 5120 (/4 1280) >[914724.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77970a0] >[914724.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77970a0] width 1280 pitch 5120 (/4 1280) >[914724.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914724.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914724.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914724.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914724.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914724.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914724.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914724.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914724.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914724.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914724.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914724.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914724.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914724.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914724.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914724.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914724.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914738.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7795c70] >[914738.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7795c70] width 1280 pitch 5120 (/4 1280) >[914742.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x74ef200] >[914742.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x74ef200] width 1280 pitch 5120 (/4 1280) >[914745.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77753c0] >[914745.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77753c0] width 1280 pitch 5120 (/4 1280) >[914756.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7775420] >[914756.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7775420] width 1280 pitch 5120 (/4 1280) >[914756.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775ad40] >[914756.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775ad40] width 1280 pitch 5120 (/4 1280) >[914756.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914756.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914757.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914757.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914758.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b9e40] >[914758.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b9e40] width 1280 pitch 5120 (/4 1280) >[914763.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x779e5d0] >[914763.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x779e5d0] width 1280 pitch 5120 (/4 1280) >[914784.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77c7a30] >[914784.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77c7a30] width 1280 pitch 5120 (/4 1280) >[914796.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bae40] >[914796.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bae40] width 1280 pitch 5120 (/4 1280) >[914797.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914797.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914801.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914801.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914801.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914801.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914801.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914801.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914801.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914801.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914801.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914801.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b4510] >[914801.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b4510] width 1280 pitch 5120 (/4 1280) >[914801.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914801.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b4510] >[914801.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b4510] width 1280 pitch 5120 (/4 1280) >[914801.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bbf10] >[914801.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bbf10] width 1280 pitch 5120 (/4 1280) >[914803.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914803.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914803.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bae40] >[914803.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bae40] width 1280 pitch 5120 (/4 1280) >[914803.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bae40] >[914803.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bae40] width 1280 pitch 5120 (/4 1280) >[914803.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914803.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914803.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bae40] >[914803.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bae40] width 1280 pitch 5120 (/4 1280) >[914803.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76bae40] >[914803.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76bae40] width 1280 pitch 5120 (/4 1280) >[914803.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914803.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914803.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914803.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914803.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76263c0] >[914803.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76263c0] width 1280 pitch 5120 (/4 1280) >[914803.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x629ae40] >[914803.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x629ae40] width 1280 pitch 5120 (/4 1280) >[914847.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77920f0] >[914847.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77920f0] width 1280 pitch 5120 (/4 1280) >[914847.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914847.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914847.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914848.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914851.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7781790] >[914851.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7781790] width 1280 pitch 5120 (/4 1280) >[914856.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7530ae0] >[914856.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7530ae0] width 1280 pitch 5120 (/4 1280) >[914861.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75375f0] >[914861.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75375f0] width 1280 pitch 5120 (/4 1280) >[914861.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x750fdd0] >[914861.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x750fdd0] width 1280 pitch 5120 (/4 1280) >[914862.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75639f0] >[914862.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75639f0] width 1280 pitch 5120 (/4 1280) >[914862.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75375f0] >[914862.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75375f0] width 1280 pitch 5120 (/4 1280) >[914862.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75639f0] >[914862.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75639f0] width 1280 pitch 5120 (/4 1280) >[914862.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x750fdd0] >[914862.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x750fdd0] width 1280 pitch 5120 (/4 1280) >[914862.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75375f0] >[914862.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75375f0] width 1280 pitch 5120 (/4 1280) >[914863.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b6300] >[914863.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b6300] width 1280 pitch 5120 (/4 1280) >[914863.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7818c30] >[914863.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7818c30] width 1280 pitch 5120 (/4 1280) >[914863.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b6300] >[914863.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b6300] width 1280 pitch 5120 (/4 1280) >[914863.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7818c30] >[914863.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7818c30] width 1280 pitch 5120 (/4 1280) >[914863.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b6300] >[914863.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b6300] width 1280 pitch 5120 (/4 1280) >[914863.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7818c30] >[914863.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7818c30] width 1280 pitch 5120 (/4 1280) >[914863.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b6300] >[914863.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b6300] width 1280 pitch 5120 (/4 1280) >[914863.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7818c30] >[914863.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7818c30] width 1280 pitch 5120 (/4 1280) >[914863.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77b6300] >[914863.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77b6300] width 1280 pitch 5120 (/4 1280) >[914863.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7512c60] >[914863.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7512c60] width 1280 pitch 5120 (/4 1280) >[914876.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914876.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914876.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914876.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914876.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7541e50] >[914876.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7541e50] width 1280 pitch 5120 (/4 1280) >[914876.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914876.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914876.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537280] >[914876.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537280] width 1280 pitch 5120 (/4 1280) >[914876.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914876.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914876.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537280] >[914876.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537280] width 1280 pitch 5120 (/4 1280) >[914876.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914876.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914876.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537280] >[914876.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537280] width 1280 pitch 5120 (/4 1280) >[914876.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914877.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914877.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537280] >[914877.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537280] width 1280 pitch 5120 (/4 1280) >[914877.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78eb8f0] >[914877.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78eb8f0] width 1280 pitch 5120 (/4 1280) >[914880.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7886600] >[914880.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7886600] width 1280 pitch 5120 (/4 1280) >[914880.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7886600] >[914880.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7886600] width 1280 pitch 5120 (/4 1280) >[914881.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7887950] >[914882.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7887950] width 1280 pitch 5120 (/4 1280) >[914882.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7536dc0] >[914882.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7536dc0] width 1280 pitch 5120 (/4 1280) >[914882.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7887950] >[914882.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7887950] width 1280 pitch 5120 (/4 1280) >[914882.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537990] >[914882.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537990] width 1280 pitch 5120 (/4 1280) >[914882.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7887950] >[914882.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7887950] width 1280 pitch 5120 (/4 1280) >[914882.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775ad40] >[914882.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775ad40] width 1280 pitch 5120 (/4 1280) >[914882.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914882.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914882.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775ad40] >[914882.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775ad40] width 1280 pitch 5120 (/4 1280) >[914882.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914882.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914882.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914882.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914882.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775ad40] >[914882.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775ad40] width 1280 pitch 5120 (/4 1280) >[914882.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914882.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914882.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914882.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914882.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914882.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914882.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914882.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914882.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914882.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914882.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914882.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914882.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914882.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914882.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914882.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914882.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76744d0] >[914882.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76744d0] width 1280 pitch 5120 (/4 1280) >[914883.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914883.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914883.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914883.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914884.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914884.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914885.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76622b0] >[914885.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76622b0] width 1280 pitch 5120 (/4 1280) >[914885.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x775ad40] >[914885.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x775ad40] width 1280 pitch 5120 (/4 1280) >[914885.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b28c0] >[914885.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b28c0] width 1280 pitch 5120 (/4 1280) >[914885.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914885.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914886.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537a30] >[914886.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537a30] width 1280 pitch 5120 (/4 1280) >[914886.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537990] >[914886.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537990] width 1280 pitch 5120 (/4 1280) >[914889.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7542910] >[914889.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7542910] width 1280 pitch 5120 (/4 1280) >[914889.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7625f90] >[914889.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7625f90] width 1280 pitch 5120 (/4 1280) >[914889.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7542910] >[914889.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7542910] width 1280 pitch 5120 (/4 1280) >[914889.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914889.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914889.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537bb0] >[914889.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537bb0] width 1280 pitch 5120 (/4 1280) >[914889.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914889.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914889.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77d38f0] >[914889.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77d38f0] width 1280 pitch 5120 (/4 1280) >[914889.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537bb0] >[914889.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537bb0] width 1280 pitch 5120 (/4 1280) >[914889.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a0790] >[914889.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a0790] width 1280 pitch 5120 (/4 1280) >[914891.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef56d0] >[914891.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef56d0] width 1280 pitch 5120 (/4 1280) >[914891.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x792dc70] >[914891.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x792dc70] width 1280 pitch 5120 (/4 1280) >[914901.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b7f0] >[914901.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b7f0] width 1280 pitch 5120 (/4 1280) >[914901.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x765c5d0] >[914901.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x765c5d0] width 1280 pitch 5120 (/4 1280) >[914901.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914901.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914901.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7542910] >[914902.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7542910] width 1280 pitch 5120 (/4 1280) >[914902.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914902.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914902.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7542910] >[914902.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7542910] width 1280 pitch 5120 (/4 1280) >[914902.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914902.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914902.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914902.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914902.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914902.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914902.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914902.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914902.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7690c30] >[914902.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7690c30] width 1280 pitch 5120 (/4 1280) >[914902.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914902.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914902.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x748aa90] >[914902.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x748aa90] width 1280 pitch 5120 (/4 1280) >[914902.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71aefc0] >[914902.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71aefc0] width 1280 pitch 5120 (/4 1280) >[914902.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7539bd0] >[914902.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7539bd0] width 1280 pitch 5120 (/4 1280) >[914947.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537400] >[914947.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537400] width 1280 pitch 5120 (/4 1280) >[914947.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7799ae0] >[914948.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7799ae0] width 1280 pitch 5120 (/4 1280) >[914953.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537590] >[914953.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537590] width 1280 pitch 5120 (/4 1280) >[914953.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537920] >[914953.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537920] width 1280 pitch 5120 (/4 1280) >[914954.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7761ec0] >[914954.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7761ec0] width 1280 pitch 5120 (/4 1280) >[914955.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7537590] >[914955.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7537590] width 1280 pitch 5120 (/4 1280) >[914955.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7761ec0] >[914955.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7761ec0] width 1280 pitch 5120 (/4 1280) >[914957.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77940a0] >[914957.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77940a0] width 1280 pitch 5120 (/4 1280) >[914958.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914958.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914958.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914958.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914958.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914958.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914959.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7674580] >[914959.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7674580] width 1280 pitch 5120 (/4 1280) >[914959.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53779b0] >[914959.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53779b0] width 1280 pitch 5120 (/4 1280) >[914959.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a5f40] >[914959.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a5f40] width 1280 pitch 5120 (/4 1280) >[914959.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a5f40] >[914959.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a5f40] width 1280 pitch 5120 (/4 1280) >[914959.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7794680] >[914959.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7794680] width 1280 pitch 5120 (/4 1280) >[914959.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a5f40] >[914959.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a5f40] width 1280 pitch 5120 (/4 1280) >[914959.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7794680] >[914959.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7794680] width 1280 pitch 5120 (/4 1280) >[914959.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7794680] >[914959.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7794680] width 1280 pitch 5120 (/4 1280) >[914959.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914959.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914959.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7794680] >[914959.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7794680] width 1280 pitch 5120 (/4 1280) >[914960.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7794680] >[914960.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7794680] width 1280 pitch 5120 (/4 1280) >[914960.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b0710] >[914960.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b0710] width 1280 pitch 5120 (/4 1280) >[914960.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7674580] >[914960.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7674580] width 1280 pitch 5120 (/4 1280) >[914960.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7674580] >[914960.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7674580] width 1280 pitch 5120 (/4 1280) >[914960.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53779b0] >[914960.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53779b0] width 1280 pitch 5120 (/4 1280) >[914960.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76b0710] >[914960.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76b0710] width 1280 pitch 5120 (/4 1280) >[914960.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53779b0] >[914960.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53779b0] width 1280 pitch 5120 (/4 1280) >[914960.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53779b0] >[914960.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53779b0] width 1280 pitch 5120 (/4 1280) >[914960.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914960.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914960.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914960.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914960.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914960.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914960.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914960.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914960.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914960.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914962.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77d1f30] >[914962.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77d1f30] width 1280 pitch 5120 (/4 1280) >[914962.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914962.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914962.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784b10] >[914962.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784b10] width 1280 pitch 5120 (/4 1280) >[914962.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914962.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914962.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784b10] >[914962.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784b10] width 1280 pitch 5120 (/4 1280) >[914962.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x78839e0] >[914962.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x78839e0] width 1280 pitch 5120 (/4 1280) >[914962.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784b10] >[914962.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784b10] width 1280 pitch 5120 (/4 1280) >[914962.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784f60] >[914962.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784f60] width 1280 pitch 5120 (/4 1280) >[914962.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784bc0] >[914962.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784bc0] width 1280 pitch 5120 (/4 1280) >[914962.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784f60] >[914962.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784f60] width 1280 pitch 5120 (/4 1280) >[914962.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784bc0] >[914962.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784bc0] width 1280 pitch 5120 (/4 1280) >[914962.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784f60] >[914962.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784f60] width 1280 pitch 5120 (/4 1280) >[914962.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x763d9e0] >[914962.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x763d9e0] width 1280 pitch 5120 (/4 1280) >[914962.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7784b10] >[914962.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7784b10] width 1280 pitch 5120 (/4 1280) >[914962.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9960] >[914962.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9960] width 1280 pitch 5120 (/4 1280) >[914962.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914962.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914962.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914962.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914962.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914962.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914962.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9960] >[914962.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9960] width 1280 pitch 5120 (/4 1280) >[914962.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914962.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9960] >[914962.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9960] width 1280 pitch 5120 (/4 1280) >[914962.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914962.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914962.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914962.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914962.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a10] >[914962.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a10] width 1280 pitch 5120 (/4 1280) >[914963.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76378d0] >[914963.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76378d0] width 1280 pitch 5120 (/4 1280) >[914963.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914963.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914963.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a99f0] >[914963.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a99f0] width 1280 pitch 5120 (/4 1280) >[914963.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9990] >[914963.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9990] width 1280 pitch 5120 (/4 1280) >[914963.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9960] >[914963.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9960] width 1280 pitch 5120 (/4 1280) >[914963.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9aa0] >[914963.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9aa0] width 1280 pitch 5120 (/4 1280) >[914963.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76375f0] >[914963.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76375f0] width 1280 pitch 5120 (/4 1280) >[914963.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a99d0] >[914963.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a99d0] width 1280 pitch 5120 (/4 1280) >[914963.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76375f0] >[914963.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76375f0] width 1280 pitch 5120 (/4 1280) >[914963.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9f20] >[914963.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9f20] width 1280 pitch 5120 (/4 1280) >[914963.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a99d0] >[914963.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a99d0] width 1280 pitch 5120 (/4 1280) >[914963.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914963.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914963.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a99d0] >[914963.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a99d0] width 1280 pitch 5120 (/4 1280) >[914963.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914963.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914963.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76375f0] >[914963.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76375f0] width 1280 pitch 5120 (/4 1280) >[914963.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914963.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914963.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77d1500] >[914963.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77d1500] width 1280 pitch 5120 (/4 1280) >[914963.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914963.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914963.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77d1500] >[914963.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77d1500] width 1280 pitch 5120 (/4 1280) >[914963.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914963.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914963.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77d1500] >[914963.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77d1500] width 1280 pitch 5120 (/4 1280) >[914963.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914963.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914974.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6c30] >[914974.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6c30] width 1280 pitch 5120 (/4 1280) >[914980.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x777e750] >[914980.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x777e750] width 1280 pitch 5120 (/4 1280) >[914981.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x777e750] >[914981.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x777e750] width 1280 pitch 5120 (/4 1280) >[914981.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914981.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914981.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914981.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914981.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76378a0] >[914981.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76378a0] width 1280 pitch 5120 (/4 1280) >[914981.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x76378a0] >[914981.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x76378a0] width 1280 pitch 5120 (/4 1280) >[914982.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c2b830] >[914982.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c2b830] width 1280 pitch 5120 (/4 1280) >[914982.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7637510] >[914982.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7637510] width 1280 pitch 5120 (/4 1280) >[914982.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x75ef240] >[914982.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x75ef240] width 1280 pitch 5120 (/4 1280) >[914989.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x768e410] >[914989.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x768e410] width 1280 pitch 5120 (/4 1280) >[914991.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a50] >[914991.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a50] width 1280 pitch 5120 (/4 1280) >[914991.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7785dc0] >[914991.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7785dc0] width 1280 pitch 5120 (/4 1280) >[914991.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a50] >[914991.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a50] width 1280 pitch 5120 (/4 1280) >[914991.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x77a9a50] >[914991.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x77a9a50] width 1280 pitch 5120 (/4 1280) >[914992.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x762b990] >[914992.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x762b990] width 1280 pitch 5120 (/4 1280) >[914992.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x762b950] >[914992.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x762b950] width 1280 pitch 5120 (/4 1280) >[914992.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7785dc0] >[914992.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7785dc0] width 1280 pitch 5120 (/4 1280) >[914992.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x762b9b0] >[914992.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x762b9b0] width 1280 pitch 5120 (/4 1280) >[914993.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7785dc0] >[914993.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7785dc0] width 1280 pitch 5120 (/4 1280) >[915006.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7894460] >[915006.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7894460] width 1280 pitch 5120 (/4 1280) >[915006.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7767d50] >[915006.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7767d50] width 1280 pitch 5120 (/4 1280) >[915009.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x776cb70] >[915009.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x776cb70] width 1280 pitch 5120 (/4 1280) >[915173.536] (II) AIGLX: Suspending AIGLX clients for VT switch >[915173.852] (II) RADEON(0): RADEONLeaveVT_KMS >[915174.016] (II) RADEON(0): Ok, leaving now... >[915191.140] (II) AIGLX: Resuming AIGLX clients after VT switch >[915191.140] (II) RADEON(0): RADEONEnterVT_KMS >[915194.687] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[915194.687] (II) RADEON(0): Printing DDC gathered Modelines: >[915194.687] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[915195.941] (II) RADEON(0): RADEONSaveScreen(2) >[915204.015] (**) Option "Device" "/dev/input/event4" >[915209.778] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found >[915249.436] (II) AIGLX: Suspending AIGLX clients for VT switch >[915251.353] (II) RADEON(0): RADEONLeaveVT_KMS >[915251.354] (II) RADEON(0): Ok, leaving now... >[915405.954] (II) AIGLX: Resuming AIGLX clients after VT switch >[915406.070] (II) RADEON(0): RADEONEnterVT_KMS >[915406.163] (II) RADEON(0): EDID vendor "AUO", prod id 33140 >[915406.163] (II) RADEON(0): Printing DDC gathered Modelines: >[915406.163] (II) RADEON(0): Modeline "1280x800"x0.0 71.11 1280 1328 1360 1440 800 803 809 823 -hsync -vsync (49.4 kHz eP) >[915406.311] (II) RADEON(0): RADEONSaveScreen(2) >[915407.322] (**) Option "Device" "/dev/input/event4" >[915407.322] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found >[915411.154] [mi] EQ overflowing. Additional events will be discarded until existing events are processed. >[915411.154] >[915411.154] Backtrace: >[915412.908] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652a6] >[915412.908] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x5514ab] >[915412.908] 2: /usr/bin/Xorg (0x400000+0x47f02) [0x447f02] >[915412.948] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f691ff7a000+0x60e4) [0x7f691ff800e4] >[915412.948] 4: /usr/bin/Xorg (0x400000+0x80787) [0x480787] >[915412.948] 5: /usr/bin/Xorg (0x400000+0xa4a80) [0x4a4a80] >[915412.948] 6: /lib64/libpthread.so.0 (0x3dbcc00000+0xefe0) [0x3dbcc0efe0] >[915412.948] 7: /usr/bin/Xorg (FreeResource+0x6a) [0x455b8a] >[915412.948] 8: /usr/bin/Xorg (0x400000+0x3f503) [0x43f503] >[915412.948] 9: /usr/bin/Xorg (0x400000+0x5be67) [0x45be67] >[915412.948] 10: /usr/bin/Xorg (DeleteWindow+0x21f) [0x45ee6f] >[915412.948] 11: /usr/bin/Xorg (0x400000+0x55442) [0x455442] >[915412.948] 12: /usr/bin/Xorg (FreeClientResources+0x95) [0x456245] >[915412.949] 13: /usr/bin/Xorg (CloseDownClient+0x5a) [0x43388a] >[915412.949] 14: /usr/bin/Xorg (CheckConnections+0xef) [0x466b1f] >[915412.949] 15: /usr/bin/Xorg (WaitForSomething+0x92d) [0x462fbd] >[915412.949] 16: /usr/bin/Xorg (0x400000+0x34111) [0x434111] >[915412.949] 17: /usr/bin/Xorg (0x400000+0x23485) [0x423485] >[915412.949] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3dbc821735] >[915412.949] 19: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d] >[915412.949] >[915412.949] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack. >[915412.949] [mi] mieq is *NOT* the cause. It is a victim. >[915414.286] [mi] EQ overflow continuing. 100 events have been dropped. >[915414.286] >[915414.286] Backtrace: >[915414.286] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652a6] >[915414.286] 1: /usr/bin/Xorg (0x400000+0x47f02) [0x447f02] >[915414.286] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f691ff7a000+0x60e4) [0x7f691ff800e4] >[915414.286] 3: /usr/bin/Xorg (0x400000+0x80787) [0x480787] >[915414.286] 4: /usr/bin/Xorg (0x400000+0xa4a80) [0x4a4a80] >[915414.286] 5: /lib64/libpthread.so.0 (0x3dbcc00000+0xefe0) [0x3dbcc0efe0] >[915414.286] 6: /usr/bin/Xorg (FreeResource+0x6a) [0x455b8a] >[915414.286] 7: /usr/bin/Xorg (0x400000+0x3f503) [0x43f503] >[915414.286] 8: /usr/bin/Xorg (0x400000+0x5be67) [0x45be67] >[915414.286] 9: /usr/bin/Xorg (DeleteWindow+0x21f) [0x45ee6f] >[915414.286] 10: /usr/bin/Xorg (0x400000+0x55442) [0x455442] >[915414.286] 11: /usr/bin/Xorg (FreeClientResources+0x95) [0x456245] >[915414.286] 12: /usr/bin/Xorg (CloseDownClient+0x5a) [0x43388a] >[915414.286] 13: /usr/bin/Xorg (CheckConnections+0xef) [0x466b1f] >[915414.286] 14: /usr/bin/Xorg (WaitForSomething+0x92d) [0x462fbd] >[915414.286] 15: /usr/bin/Xorg (0x400000+0x34111) [0x434111] >[915414.286] 16: /usr/bin/Xorg (0x400000+0x23485) [0x423485] >[915414.286] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3dbc821735] >[915414.286] 18: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d] >[915414.286] >[915426.054] [mi] Increasing EQ size to 1024 to prevent dropped events. >[915426.055] [mi] EQ processing has resumed after 145 dropped events. >[915426.055] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.
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