Attachment 668571 Details for Bug 890056 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 889.42 KB, created by Rob on 2012-12-24 19:16:24 UTC

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Creator: Rob

Created: 2012-12-24 19:16:24 UTC

Size: 889.42 KB

patch

obsolete

>[    51.625] 
>X.Org X Server 1.12.4
>Release Date: 2012-08-27
>[    51.625] X Protocol Version 11, Revision 0
>[    51.625] Build Operating System:  2.6.32-279.9.1.el6.x86_64 
>[    51.625] Current Operating System: Linux hipster.localdomain 3.4.6-2.fc17.i686.PAE #1 SMP Thu Jul 19 21:49:03 UTC 2012 i686
>[    51.626] Kernel command line: BOOT_IMAGE=/vmlinuz-3.4.6-2.fc17.i686.PAE root=/dev/mapper/vg_hipster-lv_root ro rd.md=0 rd.lvm.lv=vg_hipster/lv_swap rd.dm=0 SYSFONT=True KEYTABLE=us rd.lvm.lv=vg_hipster/lv_root rd.luks=0 LANG=en_US.UTF-8 rhgb
>[    51.626] Build Date: 28 November 2012  05:13:08PM
>[    51.626] Build ID: xorg-x11-server 1.12.4-1.fc17 
>[    51.626] Current version of pixman: 0.24.4
>[    51.626] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    51.626] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    51.626] (==) Log file: "/var/log/Xorg.0.log", Time: Fri Dec 21 11:33:50 2012
>[    51.659] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    51.659] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    51.659] (==) No Layout section.  Using the first Screen section.
>[    51.659] (==) No screen section available. Using defaults.
>[    51.659] (**) |-->Screen "Default Screen Section" (0)
>[    51.659] (**) |   |-->Monitor "<default monitor>"
>[    51.659] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    51.659] (==) Automatically adding devices
>[    51.659] (==) Automatically enabling devices
>[    51.659] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    51.659] (==) ModulePath set to "/usr/lib/xorg/modules"
>[    51.659] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    51.659] (II) Loader magic: 0x8224580
>[    51.659] (II) Module ABI versions:
>[    51.659] 	X.Org ANSI C Emulation: 0.4
>[    51.659] 	X.Org Video Driver: 12.1
>[    51.659] 	X.Org XInput driver : 16.0
>[    51.659] 	X.Org Server Extension : 6.0
>[    51.661] (--) PCI:*(0:1:0:0) 1002:714a:103c:30ac rev 0, Mem @ 0xd8000000/67108864, 0xe0600000/65536, I/O @ 0x00004000/256, BIOS @ 0x????????/131072
>[    51.661] (II) LoadModule: "extmod"
>[    51.693] (II) Loading /usr/lib/xorg/modules/extensions/libextmod.so
>[    51.693] (II) Module extmod: vendor="X.Org Foundation"
>[    51.693] 	compiled for 1.12.4, module version = 1.0.0
>[    51.693] 	Module class: X.Org Server Extension
>[    51.693] 	ABI class: X.Org Server Extension, version 6.0
>[    51.693] (II) Loading extension SELinux
>[    51.693] (II) Loading extension MIT-SCREEN-SAVER
>[    51.693] (II) Loading extension XFree86-VidModeExtension
>[    51.693] (II) Loading extension XFree86-DGA
>[    51.693] (II) Loading extension DPMS
>[    51.693] (II) Loading extension XVideo
>[    51.693] (II) Loading extension XVideo-MotionCompensation
>[    51.693] (II) Loading extension X-Resource
>[    51.693] (II) LoadModule: "dbe"
>[    51.694] (II) Loading /usr/lib/xorg/modules/extensions/libdbe.so
>[    51.694] (II) Module dbe: vendor="X.Org Foundation"
>[    51.694] 	compiled for 1.12.4, module version = 1.0.0
>[    51.694] 	Module class: X.Org Server Extension
>[    51.694] 	ABI class: X.Org Server Extension, version 6.0
>[    51.694] (II) Loading extension DOUBLE-BUFFER
>[    51.694] (II) LoadModule: "glx"
>[    51.694] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
>[    51.695] (II) Module glx: vendor="X.Org Foundation"
>[    51.695] 	compiled for 1.12.4, module version = 1.0.0
>[    51.695] 	ABI class: X.Org Server Extension, version 6.0
>[    51.695] (==) AIGLX enabled
>[    51.695] (II) Loading extension GLX
>[    51.695] (II) LoadModule: "record"
>[    51.695] (II) Loading /usr/lib/xorg/modules/extensions/librecord.so
>[    51.695] (II) Module record: vendor="X.Org Foundation"
>[    51.695] 	compiled for 1.12.4, module version = 1.13.0
>[    51.695] 	Module class: X.Org Server Extension
>[    51.695] 	ABI class: X.Org Server Extension, version 6.0
>[    51.695] (II) Loading extension RECORD
>[    51.695] (II) LoadModule: "dri"
>[    51.696] (II) Loading /usr/lib/xorg/modules/extensions/libdri.so
>[    51.696] (II) Module dri: vendor="X.Org Foundation"
>[    51.696] 	compiled for 1.12.4, module version = 1.0.0
>[    51.696] 	ABI class: X.Org Server Extension, version 6.0
>[    51.696] (II) Loading extension XFree86-DRI
>[    51.696] (II) LoadModule: "dri2"
>[    51.697] (II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
>[    51.697] (II) Module dri2: vendor="X.Org Foundation"
>[    51.697] 	compiled for 1.12.4, module version = 1.2.0
>[    51.697] 	ABI class: X.Org Server Extension, version 6.0
>[    51.697] (II) Loading extension DRI2
>[    51.697] (==) Matched ati as autoconfigured driver 0
>[    51.697] (==) Matched vesa as autoconfigured driver 1
>[    51.697] (==) Matched modesetting as autoconfigured driver 2
>[    51.697] (==) Matched fbdev as autoconfigured driver 3
>[    51.697] (==) Assigned the driver to the xf86ConfigLayout
>[    51.697] (II) LoadModule: "ati"
>[    51.697] (II) Loading /usr/lib/xorg/modules/drivers/ati_drv.so
>[    51.697] (II) Module ati: vendor="X.Org Foundation"
>[    51.697] 	compiled for 1.12.0, module version = 6.14.99
>[    51.697] 	Module class: X.Org Video Driver
>[    51.697] 	ABI class: X.Org Video Driver, version 12.0
>[    51.697] (II) LoadModule: "radeon"
>[    51.698] (II) Loading /usr/lib/xorg/modules/drivers/radeon_drv.so
>[    51.698] (II) Module radeon: vendor="X.Org Foundation"
>[    51.698] 	compiled for 1.12.0, module version = 6.14.99
>[    51.698] 	Module class: X.Org Video Driver
>[    51.698] 	ABI class: X.Org Video Driver, version 12.0
>[    51.698] (II) LoadModule: "vesa"
>[    51.698] (II) Loading /usr/lib/xorg/modules/drivers/vesa_drv.so
>[    51.698] (II) Module vesa: vendor="X.Org Foundation"
>[    51.698] 	compiled for 1.12.0, module version = 2.3.1
>[    51.698] 	Module class: X.Org Video Driver
>[    51.698] 	ABI class: X.Org Video Driver, version 12.0
>[    51.698] (II) LoadModule: "modesetting"
>[    51.699] (II) Loading /usr/lib/xorg/modules/drivers/modesetting_drv.so
>[    51.699] (II) Module modesetting: vendor="X.Org Foundation"
>[    51.699] 	compiled for 1.12.2, module version = 0.4.0
>[    51.699] 	Module class: X.Org Video Driver
>[    51.699] 	ABI class: X.Org Video Driver, version 12.0
>[    51.699] (II) LoadModule: "fbdev"
>[    51.699] (II) Loading /usr/lib/xorg/modules/drivers/fbdev_drv.so
>[    51.699] (II) Module fbdev: vendor="X.Org Foundation"
>[    51.699] 	compiled for 1.11.99.901, module version = 0.4.2
>[    51.699] 	ABI class: X.Org Video Driver, version 12.0
>[    51.699] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    51.705] (II) VESA: driver for VESA chipsets: vesa
>[    51.705] (II) modesetting: Driver for Modesetting Kernel Drivers: kms
>[    51.705] (II) FBDEV: driver for framebuffer: fbdev
>[    51.705] (++) using VT number 1
>
>[    51.707] (II) [KMS] Kernel modesetting enabled.
>[    51.707] (WW) Falling back to old probe method for vesa
>[    51.707] (WW) Falling back to old probe method for modesetting
>[    51.707] (WW) Falling back to old probe method for fbdev
>[    51.707] (II) Loading sub module "fbdevhw"
>[    51.707] (II) LoadModule: "fbdevhw"
>[    51.707] (II) Loading /usr/lib/xorg/modules/libfbdevhw.so
>[    51.708] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    51.708] 	compiled for 1.12.4, module version = 0.0.2
>[    51.708] 	ABI class: X.Org Video Driver, version 12.1
>[    51.708] (II) RADEON(0): RADEONPreInit_KMS
>[    51.708] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    51.708] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    51.708] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    51.708] (==) RADEON(0): Default visual is TrueColor
>[    51.708] (==) RADEON(0): RGB weight 888
>[    51.708] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    51.708] (--) RADEON(0): Chipset: "ATI Mobility Radeon X1300" (ChipID = 0x714a)
>[    51.708] (II) RADEON(0): PCIE card detected
>[    51.708] drmOpenDevice: node name is /dev/dri/card0
>[    51.708] drmOpenDevice: open result is 8, (OK)
>[    51.708] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    51.708] drmOpenDevice: node name is /dev/dri/card0
>[    51.708] drmOpenDevice: open result is 8, (OK)
>[    51.708] drmOpenByBusid: drmOpenMinor returns 8
>[    51.708] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    51.708] (II) Loading sub module "exa"
>[    51.708] (II) LoadModule: "exa"
>[    51.708] (II) Loading /usr/lib/xorg/modules/libexa.so
>[    51.709] (II) Module exa: vendor="X.Org Foundation"
>[    51.709] 	compiled for 1.12.4, module version = 2.5.0
>[    51.709] 	ABI class: X.Org Video Driver, version 12.1
>[    51.709] (II) RADEON(0): KMS Color Tiling: enabled
>[    51.709] (II) RADEON(0): KMS Pageflipping: enabled
>[    51.709] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    51.735] (II) RADEON(0): Output VGA-0 has no monitor section
>[    51.735] (II) RADEON(0): Output LVDS has no monitor section
>[    51.759] (II) RADEON(0): Output S-video has no monitor section
>[    51.761] (II) RADEON(0): Output DVI-0 has no monitor section
>[    51.787] (II) RADEON(0): EDID for output VGA-0
>[    51.787] (II) RADEON(0): EDID for output LVDS
>[    51.787] (II) RADEON(0): Manufacturer: SEC  Model: 4142  Serial#: 0
>[    51.787] (II) RADEON(0): Year: 2005  Week: 0
>[    51.787] (II) RADEON(0): EDID Version: 1.3
>[    51.787] (II) RADEON(0): Digital Display Input
>[    51.787] (II) RADEON(0): Max Image Size [cm]: horiz.: 30  vert.: 19
>[    51.787] (II) RADEON(0): Gamma: 2.20
>[    51.787] (II) RADEON(0): No DPMS capabilities specified
>[    51.787] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>[    51.787] (II) RADEON(0): First detailed timing is preferred mode
>[    51.787] (II) RADEON(0): redX: 0.580 redY: 0.340   greenX: 0.310 greenY: 0.550
>[    51.787] (II) RADEON(0): blueX: 0.155 blueY: 0.155   whiteX: 0.313 whiteY: 0.329
>[    51.787] (II) RADEON(0): Manufacturer's mask: 0
>[    51.787] (II) RADEON(0): Supported detailed timing:
>[    51.787] (II) RADEON(0): clock: 68.9 MHz   Image Size:  303 x 190 mm
>[    51.787] (II) RADEON(0): h_active: 1280  h_sync: 1292  h_sync_end 1356 h_blank_end 1408 h_border: 0
>[    51.787] (II) RADEON(0): v_active: 800  v_sync: 803  v_sync_end 806 v_blanking: 816 v_border: 0
>[    51.787] (II) RADEON(0): Unknown vendor-specific block f
>[    51.787] (II) RADEON(0):  SAMSUNG
>[    51.787] (II) RADEON(0):  LTN141W1-L04
>[    51.787] (II) RADEON(0): EDID (in hex):
>[    51.788] (II) RADEON(0): 	00ffffffffffff004ca3424100000000
>[    51.788] (II) RADEON(0): 	000f0103801e13780a87f594574f8c27
>[    51.788] (II) RADEON(0): 	27505400000001010101010101010101
>[    51.788] (II) RADEON(0): 	010101010101ee1a0080502010300c40
>[    51.788] (II) RADEON(0): 	33002fbe100000190000000f00000000
>[    51.788] (II) RADEON(0): 	00000000002387026400000000fe0053
>[    51.788] (II) RADEON(0): 	414d53554e470a2020202020000000fe
>[    51.788] (II) RADEON(0): 	004c544e31343157312d4c30340a0067
>[    51.788] (II) RADEON(0): Printing probed modes for output LVDS
>[    51.788] (II) RADEON(0): Modeline "1280x800"x60.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[    51.788] (II) RADEON(0): Modeline "1280x720"x59.9   74.50  1280 1344 1472 1664  720 723 728 748 -hsync +vsync (44.8 kHz)
>[    51.788] (II) RADEON(0): Modeline "1152x768"x59.8   71.75  1152 1216 1328 1504  768 771 781 798 -hsync +vsync (47.7 kHz)
>[    51.788] (II) RADEON(0): Modeline "1024x768"x120.1  133.47  1024 1100 1212 1400  768 768 770 794 doublescan -hsync +vsync (95.3 kHz d)
>[    51.788] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz d)
>[    51.788] (II) RADEON(0): Modeline "1024x768"x59.9   63.50  1024 1072 1176 1328  768 771 775 798 -hsync +vsync (47.8 kHz)
>[    51.788] (II) RADEON(0): Modeline "960x720"x120.0  117.00  960 1024 1128 1300  720 720 722 750 doublescan -hsync +vsync (90.0 kHz d)
>[    51.788] (II) RADEON(0): Modeline "928x696"x120.1  109.15  928 976 1088 1264  696 696 698 719 doublescan -hsync +vsync (86.4 kHz d)
>[    51.788] (II) RADEON(0): Modeline "896x672"x120.0  102.40  896 960 1060 1224  672 672 674 697 doublescan -hsync +vsync (83.7 kHz d)
>[    51.788] (II) RADEON(0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
>[    51.788] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
>[    51.788] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    51.788] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
>[    51.788] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    51.788] (II) RADEON(0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
>[    51.788] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    51.788] (II) RADEON(0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
>[    51.788] (II) RADEON(0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
>[    51.789] (II) RADEON(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
>[    51.789] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    51.789] (II) RADEON(0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
>[    51.789] (II) RADEON(0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
>[    51.789] (II) RADEON(0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
>[    51.789] (II) RADEON(0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
>[    51.813] (II) RADEON(0): EDID for output S-video
>[    51.815] (II) RADEON(0): EDID for output DVI-0
>[    51.815] (II) RADEON(0): Output VGA-0 disconnected
>[    51.815] (II) RADEON(0): Output LVDS connected
>[    51.815] (II) RADEON(0): Output S-video disconnected
>[    51.815] (II) RADEON(0): Output DVI-0 disconnected
>[    51.815] (II) RADEON(0): Using exact sizes for initial modes
>[    51.815] (II) RADEON(0): Output LVDS using initial mode 1280x800 +0+0
>[    51.815] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    51.815] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:4000000 visible:3bd8000
>[    51.815] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    51.815] (==) RADEON(0): DPI set to (96, 96)
>[    51.815] (II) Loading sub module "fb"
>[    51.815] (II) LoadModule: "fb"
>[    51.816] (II) Loading /usr/lib/xorg/modules/libfb.so
>[    51.816] (II) Module fb: vendor="X.Org Foundation"
>[    51.817] 	compiled for 1.12.4, module version = 1.0.0
>[    51.817] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    51.817] (II) Loading sub module "ramdac"
>[    51.817] (II) LoadModule: "ramdac"
>[    51.817] (II) Module "ramdac" already built-in
>[    51.817] (II) UnloadModule: "vesa"
>[    51.817] (II) Unloading vesa
>[    51.817] (II) UnloadModule: "modesetting"
>[    51.817] (II) Unloading modesetting
>[    51.817] (II) UnloadModule: "fbdev"
>[    51.817] (II) Unloading fbdev
>[    51.817] (II) UnloadSubModule: "fbdevhw"
>[    51.817] (II) Unloading fbdevhw
>[    51.817] (--) Depth 24 pixmap format is 32 bpp
>[    51.817] (II) RADEON(0): [DRI2] Setup complete
>[    51.817] (II) RADEON(0): [DRI2]   DRI driver: r300
>[    51.817] (II) RADEON(0): [DRI2]   VDPAU driver: r300
>[    51.817] (II) RADEON(0): Front buffer size: 4000K
>[    51.817] (II) RADEON(0): VRAM usage limit set to 51552K
>[    51.818] (II) RADEON(0): Initializing backing store
>[    51.818] (==) RADEON(0): Backing store disabled
>[    51.818] (II) RADEON(0): Direct rendering enabled
>[    51.818] (II) RADEON(0): Initializing Acceleration
>[    51.818] (II) RADEON(0): Render acceleration enabled for R300/R400/R500 type cards.
>[    51.818] (II) RADEON(0): Setting EXA maxPitchBytes
>[    51.818] (II) RADEON(0): EngineInit (32/32)
>[    51.818] (II) EXA(0): Driver allocated offscreen pixmaps
>[    51.818] (II) EXA(0): Driver registered support for the following operations:
>[    51.818] (II)         Solid
>[    51.818] (II)         Copy
>[    51.818] (II)         Composite (RENDER acceleration)
>[    51.818] (II)         UploadToScreen
>[    51.818] (II)         DownloadFromScreen
>[    51.818] (II) RADEON(0): Acceleration enabled
>[    51.818] (II) RADEON(0): Initializing DPMS
>[    51.818] (==) RADEON(0): DPMS enabled
>[    51.818] (II) RADEON(0): Initializing Cursor
>[    51.818] (==) RADEON(0): Silken mouse enabled
>[    51.818] (II) RADEON(0): Initializing Xv
>[    51.818] (II) RADEON(0): Set up textured video
>[    51.818] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    51.818] (II) RADEON(0): [XvMC] Extension initialized.
>[    51.818] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    51.819] (II) RADEON(0): Initializing kms color map
>[    51.819] (II) RADEON(0): RADEONScreenInit finished
>[    51.819] (--) RandR disabled
>[    51.819] (II) Initializing built-in extension Generic Event Extension
>[    51.819] (II) Initializing built-in extension SHAPE
>[    51.819] (II) Initializing built-in extension MIT-SHM
>[    51.819] (II) Initializing built-in extension XInputExtension
>[    51.819] (II) Initializing built-in extension XTEST
>[    51.819] (II) Initializing built-in extension BIG-REQUESTS
>[    51.819] (II) Initializing built-in extension SYNC
>[    51.819] (II) Initializing built-in extension XKEYBOARD
>[    51.819] (II) Initializing built-in extension XC-MISC
>[    51.819] (II) Initializing built-in extension XINERAMA
>[    51.819] (II) Initializing built-in extension XFIXES
>[    51.819] (II) Initializing built-in extension RENDER
>[    51.819] (II) Initializing built-in extension RANDR
>[    51.819] (II) Initializing built-in extension COMPOSITE
>[    51.819] (II) Initializing built-in extension DAMAGE
>[    51.822] (II) SELinux: Disabled by boolean
>[    52.616] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    52.616] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    52.616] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    52.616] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    52.617] (II) AIGLX: Loaded and initialized r300
>[    52.617] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    52.619] (II) RADEON(0): Setting screen physical size to 338 x 211
>[    52.716] (II) XKB: Reusing cached keymap
>[    52.719] (II) config/udev: Adding input device Power Button (/dev/input/event2)
>[    52.720] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    52.720] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    52.720] (II) LoadModule: "evdev"
>[    52.720] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    52.720] (II) Module evdev: vendor="X.Org Foundation"
>[    52.720] 	compiled for 1.12.0, module version = 2.7.0
>[    52.720] 	Module class: X.Org XInput Driver
>[    52.720] 	ABI class: X.Org XInput driver, version 16.0
>[    52.720] (II) Using input driver 'evdev' for 'Power Button'
>[    52.720] 	Option "XkbRules" "evdev"
>[    52.720] 	Option "XkbModel" "pc105+inet"
>[    52.720] 	Option "XkbLayout" "us"
>[    52.720] 	Option "_source" "server/udev"
>[    52.720] 	Option "name" "Power Button"
>[    52.720] 	Option "path" "/dev/input/event2"
>[    52.720] 	Option "device" "/dev/input/event2"
>[    52.720] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    52.720] 	Option "driver" "evdev"
>[    52.720] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    52.720] (**) Power Button: always reports core events
>[    52.720] (**) evdev: Power Button: Device: "/dev/input/event2"
>[    52.720] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    52.720] (--) evdev: Power Button: Found keys
>[    52.720] (II) evdev: Power Button: Configuring as keyboard
>[    52.721] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    52.721] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    52.721] (**) Option "xkb_rules" "evdev"
>[    52.721] (**) Option "xkb_model" "pc105+inet"
>[    52.721] (**) Option "xkb_layout" "us"
>[    52.721] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    52.757] (II) config/udev: Adding input device Video Bus (/dev/input/event7)
>[    52.757] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    52.757] (**) Video Bus: Applying InputClass "system-setup-keyboard"
>[    52.757] (II) Using input driver 'evdev' for 'Video Bus'
>[    52.757] 	Option "XkbRules" "evdev"
>[    52.757] 	Option "XkbModel" "pc105+inet"
>[    52.757] 	Option "XkbLayout" "us"
>[    52.757] 	Option "_source" "server/udev"
>[    52.757] 	Option "name" "Video Bus"
>[    52.757] 	Option "path" "/dev/input/event7"
>[    52.757] 	Option "device" "/dev/input/event7"
>[    52.757] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input7/event7"
>[    52.757] 	Option "driver" "evdev"
>[    52.757] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    52.757] (**) Video Bus: always reports core events
>[    52.757] (**) evdev: Video Bus: Device: "/dev/input/event7"
>[    52.757] (--) evdev: Video Bus: Vendor 0 Product 0x6
>[    52.757] (--) evdev: Video Bus: Found keys
>[    52.757] (II) evdev: Video Bus: Configuring as keyboard
>[    52.757] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input7/event7"
>[    52.757] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7)
>[    52.757] (**) Option "xkb_rules" "evdev"
>[    52.757] (**) Option "xkb_model" "pc105+inet"
>[    52.757] (**) Option "xkb_layout" "us"
>[    52.757] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    52.757] (II) XKB: Reusing cached keymap
>[    52.758] (II) config/udev: Adding input device Lid Switch (/dev/input/event1)
>[    52.758] (II) No input driver specified, ignoring this device.
>[    52.758] (II) This device may have been added with another device file.
>[    52.758] (II) config/udev: Adding input device Sleep Button (/dev/input/event0)
>[    52.758] (**) Sleep Button: Applying InputClass "evdev keyboard catchall"
>[    52.758] (**) Sleep Button: Applying InputClass "system-setup-keyboard"
>[    52.758] (II) Using input driver 'evdev' for 'Sleep Button'
>[    52.758] 	Option "XkbRules" "evdev"
>[    52.758] 	Option "XkbModel" "pc105+inet"
>[    52.758] 	Option "XkbLayout" "us"
>[    52.758] 	Option "_source" "server/udev"
>[    52.758] 	Option "name" "Sleep Button"
>[    52.758] 	Option "path" "/dev/input/event0"
>[    52.758] 	Option "device" "/dev/input/event0"
>[    52.758] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    52.758] 	Option "driver" "evdev"
>[    52.758] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    52.758] (**) Sleep Button: always reports core events
>[    52.758] (**) evdev: Sleep Button: Device: "/dev/input/event0"
>[    52.759] (--) evdev: Sleep Button: Vendor 0 Product 0x3
>[    52.759] (--) evdev: Sleep Button: Found keys
>[    52.759] (II) evdev: Sleep Button: Configuring as keyboard
>[    52.759] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    52.759] (II) XINPUT: Adding extended input device "Sleep Button" (type: KEYBOARD, id 8)
>[    52.759] (**) Option "xkb_rules" "evdev"
>[    52.759] (**) Option "xkb_model" "pc105+inet"
>[    52.759] (**) Option "xkb_layout" "us"
>[    52.759] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    52.759] (II) XKB: Reusing cached keymap
>[    52.760] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event5)
>[    52.760] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[    52.760] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[    52.760] 	Option "XkbRules" "evdev"
>[    52.760] 	Option "XkbModel" "evdev"
>[    52.760] 	Option "XkbLayout" "us"
>[    52.760] 	Option "_source" "server/udev"
>[    52.760] 	Option "name" "Logitech USB Optical Mouse"
>[    52.760] 	Option "path" "/dev/input/event5"
>[    52.760] 	Option "device" "/dev/input/event5"
>[    52.760] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.4/1-7.4:1.0/input/input5/event5"
>[    52.760] 	Option "driver" "evdev"
>[    52.760] (**) Logitech USB Optical Mouse: always reports core events
>[    52.760] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event5"
>[    52.760] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc018
>[    52.760] (--) evdev: Logitech USB Optical Mouse: Found 3 mouse buttons
>[    52.760] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[    52.760] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[    52.760] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[    52.760] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[    52.760] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[    52.760] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[    52.760] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    52.760] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.4/1-7.4:1.0/input/input5/event5"
>[    52.760] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 9)
>[    52.760] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[    52.760] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[    52.760] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[    52.760] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[    52.760] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[    52.761] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse1)
>[    52.761] (II) No input driver specified, ignoring this device.
>[    52.761] (II) This device may have been added with another device file.
>[    52.761] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event3)
>[    52.761] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    52.761] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard"
>[    52.761] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    52.761] 	Option "XkbRules" "evdev"
>[    52.761] 	Option "XkbModel" "pc105+inet"
>[    52.761] 	Option "XkbLayout" "us"
>[    52.761] 	Option "_source" "server/udev"
>[    52.761] 	Option "name" "AT Translated Set 2 keyboard"
>[    52.761] 	Option "path" "/dev/input/event3"
>[    52.761] 	Option "device" "/dev/input/event3"
>[    52.761] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    52.761] 	Option "driver" "evdev"
>[    52.761] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    52.761] (**) AT Translated Set 2 keyboard: always reports core events
>[    52.761] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event3"
>[    52.762] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    52.762] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    52.762] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    52.762] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    52.762] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 10)
>[    52.762] (**) Option "xkb_rules" "evdev"
>[    52.762] (**) Option "xkb_model" "pc105+inet"
>[    52.762] (**) Option "xkb_layout" "us"
>[    52.762] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    52.762] (II) XKB: Reusing cached keymap
>[    52.762] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event4)
>[    52.762] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    52.763] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    52.763] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons"
>[    52.763] (II) LoadModule: "synaptics"
>[    52.763] (II) Loading /usr/lib/xorg/modules/input/synaptics_drv.so
>[    52.763] (II) Module synaptics: vendor="X.Org Foundation"
>[    52.763] 	compiled for 1.12.3, module version = 1.6.2
>[    52.763] 	Module class: X.Org XInput Driver
>[    52.763] 	ABI class: X.Org XInput driver, version 16.0
>[    52.763] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    52.763] 	Option "_source" "server/udev"
>[    52.763] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    52.763] 	Option "path" "/dev/input/event4"
>[    52.763] 	Option "device" "/dev/input/event4"
>[    52.763] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4"
>[    52.763] 	Option "driver" "synaptics"
>[    52.763] 	Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0"
>[    52.763] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    52.763] (**) Option "Device" "/dev/input/event4"
>[    52.786] (**) Option "Device" "/dev/input/event4"
>[    52.786] port opened successfully
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5472
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4448
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right double triple
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7
>[    52.786] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    52.786] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    52.796] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4"
>[    52.796] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 11)
>[    52.796] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    52.796] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    52.796] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.040
>[    52.796] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    52.796] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    52.796] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    52.796] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    52.796] (**) Option "Device" "/dev/input/event4"
>[    52.796] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    52.797] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0)
>[    52.797] (II) No input driver specified, ignoring this device.
>[    52.797] (II) This device may have been added with another device file.
>[    52.798] (II) config/udev: Adding input device PS/2 Generic Mouse (/dev/input/event6)
>[    52.798] (**) PS/2 Generic Mouse: Applying InputClass "evdev pointer catchall"
>[    52.798] (II) Using input driver 'evdev' for 'PS/2 Generic Mouse'
>[    52.798] 	Option "XkbRules" "evdev"
>[    52.798] 	Option "XkbModel" "evdev"
>[    52.798] 	Option "XkbLayout" "us"
>[    52.798] 	Option "_source" "server/udev"
>[    52.798] 	Option "name" "PS/2 Generic Mouse"
>[    52.798] 	Option "path" "/dev/input/event6"
>[    52.798] 	Option "device" "/dev/input/event6"
>[    52.798] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio4/serio5/input/input6/event6"
>[    52.798] 	Option "driver" "evdev"
>[    52.798] (**) PS/2 Generic Mouse: always reports core events
>[    52.798] (**) evdev: PS/2 Generic Mouse: Device: "/dev/input/event6"
>[    52.798] (--) evdev: PS/2 Generic Mouse: Vendor 0x2 Product 0x1
>[    52.798] (--) evdev: PS/2 Generic Mouse: Found 3 mouse buttons
>[    52.798] (--) evdev: PS/2 Generic Mouse: Found relative axes
>[    52.798] (--) evdev: PS/2 Generic Mouse: Found x and y relative axes
>[    52.798] (II) evdev: PS/2 Generic Mouse: Configuring as mouse
>[    52.798] (**) evdev: PS/2 Generic Mouse: YAxisMapping: buttons 4 and 5
>[    52.798] (**) evdev: PS/2 Generic Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    52.798] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio4/serio5/input/input6/event6"
>[    52.798] (II) XINPUT: Adding extended input device "PS/2 Generic Mouse" (type: MOUSE, id 12)
>[    52.798] (II) evdev: PS/2 Generic Mouse: initialized for relative axes.
>[    52.799] (**) PS/2 Generic Mouse: (accel) keeping acceleration scheme 1
>[    52.799] (**) PS/2 Generic Mouse: (accel) acceleration profile 0
>[    52.799] (**) PS/2 Generic Mouse: (accel) acceleration factor: 2.000
>[    52.799] (**) PS/2 Generic Mouse: (accel) acceleration threshold: 4
>[    52.799] (II) config/udev: Adding input device PS/2 Generic Mouse (/dev/input/mouse2)
>[    52.799] (II) No input driver specified, ignoring this device.
>[    52.800] (II) This device may have been added with another device file.
>[    52.800] (II) config/udev: Adding input device ST LIS3LV02DL Accelerometer (/dev/input/event8)
>[    52.800] (II) No input driver specified, ignoring this device.
>[    52.800] (II) This device may have been added with another device file.
>[    52.801] (II) config/udev: Adding input device HP WMI hotkeys (/dev/input/event9)
>[    52.801] (**) HP WMI hotkeys: Applying InputClass "evdev keyboard catchall"
>[    52.801] (**) HP WMI hotkeys: Applying InputClass "system-setup-keyboard"
>[    52.802] (II) Using input driver 'evdev' for 'HP WMI hotkeys'
>[    52.802] 	Option "XkbRules" "evdev"
>[    52.802] 	Option "XkbModel" "pc105+inet"
>[    52.802] 	Option "XkbLayout" "us"
>[    52.802] 	Option "_source" "server/udev"
>[    52.802] 	Option "name" "HP WMI hotkeys"
>[    52.802] 	Option "path" "/dev/input/event9"
>[    52.802] 	Option "device" "/dev/input/event9"
>[    52.802] 	Option "config_info" "udev:/sys/devices/virtual/input/input9/event9"
>[    52.802] 	Option "driver" "evdev"
>[    52.802] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    52.802] (**) HP WMI hotkeys: always reports core events
>[    52.802] (**) evdev: HP WMI hotkeys: Device: "/dev/input/event9"
>[    52.802] (--) evdev: HP WMI hotkeys: Vendor 0 Product 0
>[    52.802] (--) evdev: HP WMI hotkeys: Found keys
>[    52.802] (II) evdev: HP WMI hotkeys: Configuring as keyboard
>[    52.802] (**) Option "config_info" "udev:/sys/devices/virtual/input/input9/event9"
>[    52.802] (II) XINPUT: Adding extended input device "HP WMI hotkeys" (type: KEYBOARD, id 13)
>[    52.802] (**) Option "xkb_rules" "evdev"
>[    52.802] (**) Option "xkb_model" "pc105+inet"
>[    52.802] (**) Option "xkb_layout" "us"
>[    52.802] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    52.802] (II) XKB: Reusing cached keymap
>[    52.813] (II) RADEON(0): RADEONSaveScreen(2)
>[    52.843] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[    52.843] (II) RADEON(0): Printing DDC gathered Modelines:
>[    52.843] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[    54.914] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[    54.914] (II) RADEON(0): Printing DDC gathered Modelines:
>[    54.914] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[    58.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    58.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    58.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    58.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    58.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    58.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    58.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    58.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    58.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    58.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    58.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    58.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    58.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    58.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    58.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    58.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    59.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    59.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba48]
>[    59.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba48] width 1280 pitch 5120 (/4 1280)
>[    59.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    59.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    59.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[    59.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[    59.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[    61.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[    61.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   121.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[   121.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[   181.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   181.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   241.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[   241.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[   301.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   301.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   361.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c998]
>[   361.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c998] width 1280 pitch 5120 (/4 1280)
>[   384.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c980]
>[   384.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c980] width 1280 pitch 5120 (/4 1280)
>[   384.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c980]
>[   384.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c980] width 1280 pitch 5120 (/4 1280)
>[   384.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   384.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   384.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   384.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   384.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   385.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   385.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   385.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   385.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   385.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   385.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   385.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   385.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   385.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   385.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   385.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   385.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   385.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   385.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   385.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   385.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   386.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   386.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   386.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   386.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   386.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   386.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   386.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   386.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   386.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0c9f8]
>[   386.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0c9f8] width 1280 pitch 5120 (/4 1280)
>[   386.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   386.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   398.535] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event11)
>[   398.535] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[   398.535] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[   398.535] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[   398.535] 	Option "XkbRules" "evdev"
>[   398.535] 	Option "XkbModel" "pc105+inet"
>[   398.535] 	Option "XkbLayout" "us"
>[   398.535] 	Option "_source" "server/udev"
>[   398.535] 	Option "name" "HID 1267:0103"
>[   398.535] 	Option "path" "/dev/input/event11"
>[   398.535] 	Option "device" "/dev/input/event11"
>[   398.535] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input11/event11"
>[   398.535] 	Option "driver" "evdev"
>[   398.535] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[   398.535] (**) HID 1267:0103: always reports core events
>[   398.535] (**) evdev: HID 1267:0103: Device: "/dev/input/event11"
>[   398.536] (--) evdev: HID 1267:0103: absolute axis 0x20 [572..0]
>[   398.536] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[   398.536] (--) evdev: HID 1267:0103: Found 1 mouse buttons
>[   398.536] (--) evdev: HID 1267:0103: Found scroll wheel(s)
>[   398.536] (--) evdev: HID 1267:0103: Found relative axes
>[   398.536] (II) evdev: HID 1267:0103: Forcing relative x/y axes to exist.
>[   398.536] (--) evdev: HID 1267:0103: Found absolute axes
>[   398.536] (II) evdev: HID 1267:0103: Forcing absolute x/y axes to exist.
>[   398.536] (--) evdev: HID 1267:0103: Found keys
>[   398.536] (II) evdev: HID 1267:0103: Configuring as mouse
>[   398.536] (II) evdev: HID 1267:0103: Configuring as keyboard
>[   398.536] (II) evdev: HID 1267:0103: Adding scrollwheel support
>[   398.536] (**) evdev: HID 1267:0103: YAxisMapping: buttons 4 and 5
>[   398.536] (**) evdev: HID 1267:0103: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[   398.536] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input11/event11"
>[   398.536] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 14)
>[   398.536] (**) Option "xkb_rules" "evdev"
>[   398.536] (**) Option "xkb_model" "pc105+inet"
>[   398.536] (**) Option "xkb_layout" "us"
>[   398.536] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[   398.536] (II) XKB: Reusing cached keymap
>[   398.536] (II) evdev: HID 1267:0103: initialized for relative axes.
>[   398.536] (WW) evdev: HID 1267:0103: ignoring absolute axes.
>[   398.537] (**) HID 1267:0103: (accel) keeping acceleration scheme 1
>[   398.537] (**) HID 1267:0103: (accel) acceleration profile 0
>[   398.537] (**) HID 1267:0103: (accel) acceleration factor: 2.000
>[   398.537] (**) HID 1267:0103: (accel) acceleration threshold: 4
>[   398.539] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event10)
>[   398.539] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[   398.539] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[   398.539] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[   398.539] 	Option "XkbRules" "evdev"
>[   398.539] 	Option "XkbModel" "pc105+inet"
>[   398.539] 	Option "XkbLayout" "us"
>[   398.539] 	Option "_source" "server/udev"
>[   398.539] 	Option "name" "HID 1267:0103"
>[   398.539] 	Option "path" "/dev/input/event10"
>[   398.539] 	Option "device" "/dev/input/event10"
>[   398.539] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input10/event10"
>[   398.539] 	Option "driver" "evdev"
>[   398.539] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[   398.539] (**) HID 1267:0103: always reports core events
>[   398.539] (**) evdev: HID 1267:0103: Device: "/dev/input/event10"
>[   398.539] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[   398.539] (--) evdev: HID 1267:0103: Found keys
>[   398.539] (II) evdev: HID 1267:0103: Configuring as keyboard
>[   398.539] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input10/event10"
>[   398.539] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 15)
>[   398.539] (**) Option "xkb_rules" "evdev"
>[   398.539] (**) Option "xkb_model" "pc105+inet"
>[   398.539] (**) Option "xkb_layout" "us"
>[   398.539] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[   398.539] (II) XKB: Reusing cached keymap
>[   398.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   398.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   400.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   400.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   401.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   401.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   402.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   402.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   403.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   403.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   403.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   403.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   403.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   403.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   403.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   403.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   403.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   403.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   404.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   404.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   404.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   404.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   404.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0e720]
>[   404.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0e720] width 1280 pitch 5120 (/4 1280)
>[   405.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b0ba18]
>[   405.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b0ba18] width 1280 pitch 5120 (/4 1280)
>[   405.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x989b620]
>[   405.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x989b620] width 1280 pitch 5120 (/4 1280)
>[   405.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a7b7b0]
>[   407.797] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[   407.797] (II) RADEON(0): Printing DDC gathered Modelines:
>[   407.797] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[   411.074] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[   411.074] (II) RADEON(0): Printing DDC gathered Modelines:
>[   411.074] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[   412.611] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[   412.611] (II) RADEON(0): Printing DDC gathered Modelines:
>[   412.611] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[   417.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   417.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   417.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b74aa0]
>[   417.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b74aa0] width 1280 pitch 5120 (/4 1280)
>[   417.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b75958]
>[   417.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b75958] width 1280 pitch 5120 (/4 1280)
>[   418.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76850]
>[   418.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76850] width 1280 pitch 5120 (/4 1280)
>[   418.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b75958]
>[   418.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b75958] width 1280 pitch 5120 (/4 1280)
>[   437.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76850]
>[   437.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76850] width 1280 pitch 5120 (/4 1280)
>[   485.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76840]
>[   485.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76840] width 1280 pitch 5120 (/4 1280)
>[   485.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   485.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   485.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   485.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76938]
>[   485.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76938] width 1280 pitch 5120 (/4 1280)
>[   485.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b768c0]
>[   485.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b768c0] width 1280 pitch 5120 (/4 1280)
>[   485.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   485.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b768c0]
>[   485.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b768c0] width 1280 pitch 5120 (/4 1280)
>[   485.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   485.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b768c0]
>[   485.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b768c0] width 1280 pitch 5120 (/4 1280)
>[   485.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   485.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b768c0]
>[   485.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b768c0] width 1280 pitch 5120 (/4 1280)
>[   485.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   485.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b768c0]
>[   485.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b768c0] width 1280 pitch 5120 (/4 1280)
>[   485.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3a220]
>[   485.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3a220] width 1280 pitch 5120 (/4 1280)
>[   487.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b75950]
>[   487.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b75950] width 1280 pitch 5120 (/4 1280)
>[   487.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76940]
>[   487.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76940] width 1280 pitch 5120 (/4 1280)
>[   487.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   487.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   487.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76940]
>[   487.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76940] width 1280 pitch 5120 (/4 1280)
>[   487.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   487.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   487.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76940]
>[   487.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76940] width 1280 pitch 5120 (/4 1280)
>[   487.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   487.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   487.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76940]
>[   487.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76940] width 1280 pitch 5120 (/4 1280)
>[   487.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b758c8]
>[   487.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b758c8] width 1280 pitch 5120 (/4 1280)
>[   498.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1b30]
>[   498.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1b30] width 1280 pitch 5120 (/4 1280)
>[   498.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9fbe0]
>[   498.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9fbe0] width 1280 pitch 5120 (/4 1280)
>[   585.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b79600]
>[   585.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b79600] width 1280 pitch 5120 (/4 1280)
>[   585.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b5e578]
>[   585.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b5e578] width 1280 pitch 5120 (/4 1280)
>[   892.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9acae38]
>[   892.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9acae38] width 1280 pitch 5120 (/4 1280)
>[   893.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd9008]
>[   893.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd9008] width 1280 pitch 5120 (/4 1280)
>[  1034.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdbcf0]
>[  1034.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdbcf0] width 1280 pitch 5120 (/4 1280)
>[  1034.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdbcf0]
>[  1034.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdbcf0] width 1280 pitch 5120 (/4 1280)
>[  1192.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bf5480]
>[  1192.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bf5480] width 1280 pitch 5120 (/4 1280)
>[  1192.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bf8a78]
>[  1192.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bf8a78] width 1280 pitch 5120 (/4 1280)
>[  1252.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac98b8]
>[  1252.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac98b8] width 1280 pitch 5120 (/4 1280)
>[  1252.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0a830]
>[  1252.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0a830] width 1280 pitch 5120 (/4 1280)
>[  2202.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c13730]
>[  2202.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c13730] width 1280 pitch 5120 (/4 1280)
>[  2202.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0a0d0]
>[  2202.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0a0d0] width 1280 pitch 5120 (/4 1280)
>[  2311.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1fce8]
>[  2311.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1fce8] width 1280 pitch 5120 (/4 1280)
>[  2312.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2312.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2312.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2312.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2312.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2312.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2312.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2312.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2312.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2312.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2312.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2312.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2312.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2312.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2312.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2312.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2313.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2313.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2313.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2313.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2313.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2313.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2313.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  2313.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  2313.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1fce8]
>[  2313.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1fce8] width 1280 pitch 5120 (/4 1280)
>[  2313.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2a930]
>[  2313.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2a930] width 1280 pitch 5120 (/4 1280)
>[  2313.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2314.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2314.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2a930]
>[  2314.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2a930] width 1280 pitch 5120 (/4 1280)
>[  2314.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2314.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2314.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  2314.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  2314.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c235a8]
>[  2314.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c235a8] width 1280 pitch 5120 (/4 1280)
>[  2314.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2314.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2314.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2314.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2314.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2314.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2314.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28c38]
>[  2314.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28c38] width 1280 pitch 5120 (/4 1280)
>[  2314.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28a78]
>[  2314.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28a78] width 1280 pitch 5120 (/4 1280)
>[  2604.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1b110]
>[  2605.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1b110] width 1280 pitch 5120 (/4 1280)
>[  2605.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2605.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2605.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2605.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2605.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2606.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2606.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2606.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2606.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2606.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2606.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2606.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2606.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2606.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2606.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2606.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2606.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2606.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2606.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2606.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2606.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2607.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2607.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2607.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2607.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2607.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2607.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2607.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2607.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2607.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2607.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2607.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2607.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2607.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2607.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2607.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2607.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2608.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2608.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2608.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2608.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2609.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2609.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2609.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2609.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2609.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2609.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2609.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2609.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2609.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2609.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2609.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2609.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2609.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2609.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2609.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2609.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2610.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2610.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2610.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2610.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2610.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2610.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2610.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2610.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2610.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2610.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2610.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2610.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2610.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2610.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2610.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2610.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2611.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2611.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2611.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2611.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c234a0]
>[  2612.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c234a0] width 1280 pitch 5120 (/4 1280)
>[  2612.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2612.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2612.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2612.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2612.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2613.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2613.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2613.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2613.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2614.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2614.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2614.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2614.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2615.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2615.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2615.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2615.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2615.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2615.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2615.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2615.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2615.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2615.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2615.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2615.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2615.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2615.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2615.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2615.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2616.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2616.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2616.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2616.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2616.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2616.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2616.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2616.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2616.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2616.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2616.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2616.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2616.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2616.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2616.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2616.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2617.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2617.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2617.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2617.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2617.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2617.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2617.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2617.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2617.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2617.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2617.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2617.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2617.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2617.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2617.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2617.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2618.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2618.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2618.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2618.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2618.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2618.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2618.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2618.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2618.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2618.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2618.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2618.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2618.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2618.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2618.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2618.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2619.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2619.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2619.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2619.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2620.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2620.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2620.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2620.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2620.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2620.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2620.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2620.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2620.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2620.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2620.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2620.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2620.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2620.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2620.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2620.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2621.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2621.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2621.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2621.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2622.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2622.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2622.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2622.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2623.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2623.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2623.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2623.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2623.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2623.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2623.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2623.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2623.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2623.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2623.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2623.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2623.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2623.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2623.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2623.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2624.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2624.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2624.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2624.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2625.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2625.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2625.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2625.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2626.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2626.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2626.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2626.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2626.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2626.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2626.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2626.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2626.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2626.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2626.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2626.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2626.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2626.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2626.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2626.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2627.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2627.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2627.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2627.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2627.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2627.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2627.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2627.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2627.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2627.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2627.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2627.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2627.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2627.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2627.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2627.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2628.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2628.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2628.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2628.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2628.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2628.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2628.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2628.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2628.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2628.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2628.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2628.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2628.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2628.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2628.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2628.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2629.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2629.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2629.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2629.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2629.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2629.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2629.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2629.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2629.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2629.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2629.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2629.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2629.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2629.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2629.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2629.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2630.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2630.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2630.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2630.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  2631.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  2631.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c234a0]
>[  2631.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c234a0] width 1280 pitch 5120 (/4 1280)
>[  2631.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2631.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2631.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2631.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2631.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2632.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2632.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2632.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2632.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2633.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2633.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2633.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2633.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2633.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2633.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2633.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2633.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2633.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2633.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2633.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2633.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2633.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2633.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2633.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2633.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2634.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2634.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2634.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2634.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2634.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2634.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2634.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2634.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2634.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2634.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2634.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2634.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2634.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2634.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2634.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2634.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2635.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2635.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2635.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2635.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2635.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2635.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2635.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2635.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2635.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2635.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2635.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2635.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2636.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2636.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2636.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2636.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2637.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2637.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2637.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2637.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2637.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2637.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2637.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2637.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2637.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2637.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2637.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2637.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2637.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2637.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2637.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2637.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2638.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2638.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2638.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2638.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2638.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2638.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2638.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2638.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2638.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2638.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2638.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2638.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2638.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2638.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2638.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2638.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2639.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2639.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2639.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2639.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2639.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2639.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2639.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2639.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2639.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2639.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2639.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2639.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2639.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2639.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2639.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2639.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2640.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2640.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2640.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2640.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2640.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2640.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2640.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2640.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2640.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2640.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2640.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2640.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2640.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2640.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2640.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2640.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  2641.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  2641.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  2641.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  2641.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3014.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  3014.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3014.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  3014.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  3014.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  3014.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3014.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  3014.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  3014.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba1468]
>[  3014.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba1468] width 1280 pitch 5120 (/4 1280)
>[  3014.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c234a0]
>[  3014.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c234a0] width 1280 pitch 5120 (/4 1280)
>[  3014.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  3014.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  3014.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3014.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3014.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c234a0]
>[  3014.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c234a0] width 1280 pitch 5120 (/4 1280)
>[  3014.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3014.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3014.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  3014.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  3015.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  3015.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  3016.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3016.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3016.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc22c0]
>[  3016.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc22c0] width 1280 pitch 5120 (/4 1280)
>[  3016.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28d58]
>[  3016.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28d58] width 1280 pitch 5120 (/4 1280)
>[  3016.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  3016.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3016.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28d58]
>[  3016.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28d58] width 1280 pitch 5120 (/4 1280)
>[  3016.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  3016.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3016.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28d58]
>[  3016.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28d58] width 1280 pitch 5120 (/4 1280)
>[  3016.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bdfbc8]
>[  3016.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bdfbc8] width 1280 pitch 5120 (/4 1280)
>[  3034.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2a438]
>[  3034.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2a438] width 1280 pitch 5120 (/4 1280)
>[  3034.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2a438]
>[  3034.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2a438] width 1280 pitch 5120 (/4 1280)
>[  3034.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2a438]
>[  3034.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2a438] width 1280 pitch 5120 (/4 1280)
>[  3034.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2bfd0]
>[  3034.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2bfd0] width 1280 pitch 5120 (/4 1280)
>[  3034.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3034.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3034.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3034.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3034.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3034.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3034.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c135f0]
>[  3034.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c135f0] width 1280 pitch 5120 (/4 1280)
>[  3034.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1d000]
>[  3034.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1d000] width 1280 pitch 5120 (/4 1280)
>[  3035.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc1f70]
>[  3035.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc1f70] width 1280 pitch 5120 (/4 1280)
>[  3035.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c28750]
>[  3035.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c28750] width 1280 pitch 5120 (/4 1280)
>[  3035.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1e488]
>[  3035.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1e488] width 1280 pitch 5120 (/4 1280)
>[  3035.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1e5b0]
>[  3035.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1e5b0] width 1280 pitch 5120 (/4 1280)
>[  3035.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c18238]
>[  3035.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c18238] width 1280 pitch 5120 (/4 1280)
>[  3036.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c18238]
>[  3036.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c18238] width 1280 pitch 5120 (/4 1280)
>[  3036.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c1e488]
>[  3036.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c1e488] width 1280 pitch 5120 (/4 1280)
>[  3037.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2bfd0]
>[  3037.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2bfd0] width 1280 pitch 5120 (/4 1280)
>[  3037.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2bec0]
>[  3037.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2bec0] width 1280 pitch 5120 (/4 1280)
>[  3037.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33b30]
>[  3037.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33b30] width 1280 pitch 5120 (/4 1280)
>[  3037.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c376d8]
>[  3037.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c376d8] width 1280 pitch 5120 (/4 1280)
>[  3040.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c32728]
>[  3040.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c32728] width 1280 pitch 5120 (/4 1280)
>[  3041.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2b698]
>[  3041.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2b698] width 1280 pitch 5120 (/4 1280)
>[  3041.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c2bef0]
>[  3041.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c2bef0] width 1280 pitch 5120 (/4 1280)
>[  3047.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c63860]
>[  3047.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c63860] width 1280 pitch 5120 (/4 1280)
>[  3051.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37148]
>[  3051.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37148] width 1280 pitch 5120 (/4 1280)
>[  3051.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c30ea8]
>[  3051.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c30ea8] width 1280 pitch 5120 (/4 1280)
>[  3051.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c32930]
>[  3051.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c32930] width 1280 pitch 5120 (/4 1280)
>[  3051.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c30ea8]
>[  3052.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c30ea8] width 1280 pitch 5120 (/4 1280)
>[  3052.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c32930]
>[  3052.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c32930] width 1280 pitch 5120 (/4 1280)
>[  3764.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd4168]
>[  3764.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd4168] width 1280 pitch 5120 (/4 1280)
>[  3766.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c65608]
>[  3766.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c65608] width 1280 pitch 5120 (/4 1280)
>[  3766.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c65608]
>[  3766.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c65608] width 1280 pitch 5120 (/4 1280)
>[  3766.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c65608]
>[  3766.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c65608] width 1280 pitch 5120 (/4 1280)
>[  3766.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3766.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3766.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3766.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3766.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3766.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3766.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3766.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3766.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3766.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3766.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3766.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3789.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3789.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3789.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3789.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3789.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3789.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3789.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf25d8]
>[  3789.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf25d8] width 1280 pitch 5120 (/4 1280)
>[  3789.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3789.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3789.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf25d8]
>[  3789.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf25d8] width 1280 pitch 5120 (/4 1280)
>[  3789.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3789.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3789.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf25d8]
>[  3789.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf25d8] width 1280 pitch 5120 (/4 1280)
>[  3790.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd42f0]
>[  3790.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd42f0] width 1280 pitch 5120 (/4 1280)
>[  3791.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c65608]
>[  3791.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c65608] width 1280 pitch 5120 (/4 1280)
>[  3791.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd43b0]
>[  3791.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd43b0] width 1280 pitch 5120 (/4 1280)
>[  3791.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3791.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3791.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd43b0]
>[  3792.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd43b0] width 1280 pitch 5120 (/4 1280)
>[  3792.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c183c8]
>[  3792.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c183c8] width 1280 pitch 5120 (/4 1280)
>[  3792.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd43b0]
>[  3792.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd43b0] width 1280 pitch 5120 (/4 1280)
>[  4067.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  4067.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  4067.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  4067.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  4070.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  4070.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  4070.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  4070.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  4095.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  4095.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  4095.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  4095.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  4095.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  4095.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  4095.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  4095.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  4095.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  4095.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  4095.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  4095.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  4095.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  4095.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  4095.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  4095.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  4095.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  4095.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  4095.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  4095.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  4699.908] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[  4699.908] (II) RADEON(0): Printing DDC gathered Modelines:
>[  4699.908] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[  4790.296] (II) RADEON(0): RADEONSaveScreen(2)
>[  4790.306] (II) RADEON(0): RADEONSaveScreen(0)
>[  8146.226] (II) RADEON(0): RADEONSaveScreen(1)
>[  8155.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8155.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8158.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8158.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8158.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8159.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8159.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8159.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8159.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8159.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8159.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8159.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8159.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8159.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8159.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8159.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8159.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8159.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8159.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8159.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8159.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8159.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8159.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8159.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8160.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8160.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8160.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8160.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8160.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8160.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8161.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8161.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8161.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8161.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8161.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8161.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8161.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8161.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8161.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8161.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8162.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8162.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8162.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8162.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8164.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8164.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8166.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8166.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8166.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37e70]
>[  8166.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37e70] width 1280 pitch 5120 (/4 1280)
>[  8166.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8166.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8166.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8166.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8166.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b4e8]
>[  8166.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b4e8] width 1280 pitch 5120 (/4 1280)
>[  8166.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8166.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8166.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd06e0]
>[  8166.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd06e0] width 1280 pitch 5120 (/4 1280)
>[  8166.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8166.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8166.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd06e0]
>[  8166.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd06e0] width 1280 pitch 5120 (/4 1280)
>[  8174.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca60a0]
>[  8174.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca60a0] width 1280 pitch 5120 (/4 1280)
>[  8177.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8177.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8177.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8177.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8177.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8177.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8177.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04640]
>[  8177.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04640] width 1280 pitch 5120 (/4 1280)
>[  8177.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8177.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b4e8]
>[  8177.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b4e8] width 1280 pitch 5120 (/4 1280)
>[  8177.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8177.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8186.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8186.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8186.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8186.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8186.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8186.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8186.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8186.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8186.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8186.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8186.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8186.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8186.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8186.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8186.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8186.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8187.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8187.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8188.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8188.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c33e10]
>[  8188.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c33e10] width 1280 pitch 5120 (/4 1280)
>[  8188.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b4e8]
>[  8188.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b4e8] width 1280 pitch 5120 (/4 1280)
>[  8188.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8188.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8188.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8188.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8188.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8188.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8188.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8188.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8188.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8188.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8188.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be32c0]
>[  8188.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be32c0] width 1280 pitch 5120 (/4 1280)
>[  8188.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8188.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8188.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  8188.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  8188.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8188.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8190.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8190.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8218.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8218.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8218.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95828]
>[  8218.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95828] width 1280 pitch 5120 (/4 1280)
>[  8218.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95828]
>[  8218.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95828] width 1280 pitch 5120 (/4 1280)
>[  8218.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95828]
>[  8218.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95828] width 1280 pitch 5120 (/4 1280)
>[  8218.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95828]
>[  8218.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95828] width 1280 pitch 5120 (/4 1280)
>[  8218.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8218.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95828]
>[  8218.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95828] width 1280 pitch 5120 (/4 1280)
>[  8218.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c957b0]
>[  8218.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c957b0] width 1280 pitch 5120 (/4 1280)
>[  8220.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8bc28]
>[  8220.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8bc28] width 1280 pitch 5120 (/4 1280)
>[  8220.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39f60]
>[  8220.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39f60] width 1280 pitch 5120 (/4 1280)
>[  8220.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8220.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8220.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8220.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8220.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8220.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8c2e8]
>[  8220.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8c2e8] width 1280 pitch 5120 (/4 1280)
>[  8220.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cac588]
>[  8220.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cac588] width 1280 pitch 5120 (/4 1280)
>[  8221.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8221.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8221.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  8221.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  8221.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8221.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8221.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  8221.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  8221.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8221.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8221.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8221.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8221.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8222.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8222.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8222.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8222.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8222.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8222.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8222.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8222.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8222.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8222.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8222.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8222.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa940]
>[  8222.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa940] width 1280 pitch 5120 (/4 1280)
>[  8222.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c908c8]
>[  8222.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c908c8] width 1280 pitch 5120 (/4 1280)
>[  8241.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccadf8]
>[  8241.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccadf8] width 1280 pitch 5120 (/4 1280)
>[  8241.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccadc8]
>[  8241.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccadc8] width 1280 pitch 5120 (/4 1280)
>[  8241.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccadf8]
>[  8241.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccadf8] width 1280 pitch 5120 (/4 1280)
>[  8241.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccadc8]
>[  8241.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccadc8] width 1280 pitch 5120 (/4 1280)
>[  8241.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccb968]
>[  8241.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccb968] width 1280 pitch 5120 (/4 1280)
>[  8241.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccadc8]
>[  8241.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccadc8] width 1280 pitch 5120 (/4 1280)
>[  8241.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccb968]
>[  8242.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccb968] width 1280 pitch 5120 (/4 1280)
>[  8242.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca0a8]
>[  8242.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca0a8] width 1280 pitch 5120 (/4 1280)
>[  8242.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccb968]
>[  8242.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccb968] width 1280 pitch 5120 (/4 1280)
>[  8242.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37e70]
>[  8242.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37e70] width 1280 pitch 5120 (/4 1280)
>[  8242.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8242.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8242.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37e70]
>[  8242.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37e70] width 1280 pitch 5120 (/4 1280)
>[  8242.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8242.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8242.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37e70]
>[  8242.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37e70] width 1280 pitch 5120 (/4 1280)
>[  8242.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c75d48]
>[  8242.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c75d48] width 1280 pitch 5120 (/4 1280)
>[  8242.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c35818]
>[  8242.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c35818] width 1280 pitch 5120 (/4 1280)
>[  8252.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbbfe0]
>[  8252.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbbfe0] width 1280 pitch 5120 (/4 1280)
>[  8273.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0abf8]
>[  8273.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0abf8] width 1280 pitch 5120 (/4 1280)
>[  8273.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c37e70]
>[  8273.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c37e70] width 1280 pitch 5120 (/4 1280)
>[  8288.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca1fe8]
>[  8288.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca1fe8] width 1280 pitch 5120 (/4 1280)
>[  8291.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25ad0]
>[  8291.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25ad0] width 1280 pitch 5120 (/4 1280)
>[  8291.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25aa0]
>[  8291.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25aa0] width 1280 pitch 5120 (/4 1280)
>[  8291.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25ad0]
>[  8291.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25ad0] width 1280 pitch 5120 (/4 1280)
>[  8291.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25aa0]
>[  8291.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25aa0] width 1280 pitch 5120 (/4 1280)
>[  8291.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25ad0]
>[  8291.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25ad0] width 1280 pitch 5120 (/4 1280)
>[  8301.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d24e40]
>[  8301.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d24e40] width 1280 pitch 5120 (/4 1280)
>[  8301.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d249d0]
>[  8301.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d249d0] width 1280 pitch 5120 (/4 1280)
>[  8301.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca1ea8]
>[  8301.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca1ea8] width 1280 pitch 5120 (/4 1280)
>[  8301.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d24e40]
>[  8301.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d24e40] width 1280 pitch 5120 (/4 1280)
>[  8301.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b48]
>[  8301.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b48] width 1280 pitch 5120 (/4 1280)
>[  8301.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d24e40]
>[  8301.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d24e40] width 1280 pitch 5120 (/4 1280)
>[  8301.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b48]
>[  8301.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b48] width 1280 pitch 5120 (/4 1280)
>[  8301.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d24e40]
>[  8301.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d24e40] width 1280 pitch 5120 (/4 1280)
>[  8302.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0adb0]
>[  8302.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0adb0] width 1280 pitch 5120 (/4 1280)
>[  8303.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca2818]
>[  8303.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca2818] width 1280 pitch 5120 (/4 1280)
>[  8303.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d249d0]
>[  8303.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d249d0] width 1280 pitch 5120 (/4 1280)
>[  8303.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8303.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8303.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0abf8]
>[  8303.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0abf8] width 1280 pitch 5120 (/4 1280)
>[  8303.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07eb8]
>[  8303.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07eb8] width 1280 pitch 5120 (/4 1280)
>[  8303.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8303.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8303.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca20c8]
>[  8303.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca20c8] width 1280 pitch 5120 (/4 1280)
>[  8303.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07ff8]
>[  8303.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07ff8] width 1280 pitch 5120 (/4 1280)
>[  8303.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca20c8]
>[  8303.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca20c8] width 1280 pitch 5120 (/4 1280)
>[  8303.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07ff8]
>[  8303.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07ff8] width 1280 pitch 5120 (/4 1280)
>[  8303.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca20c8]
>[  8303.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca20c8] width 1280 pitch 5120 (/4 1280)
>[  8303.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07ff8]
>[  8303.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07ff8] width 1280 pitch 5120 (/4 1280)
>[  8303.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca20c8]
>[  8303.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca20c8] width 1280 pitch 5120 (/4 1280)
>[  8303.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89c00]
>[  8303.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89c00] width 1280 pitch 5120 (/4 1280)
>[  8303.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8303.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8303.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89c00]
>[  8303.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89c00] width 1280 pitch 5120 (/4 1280)
>[  8303.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8303.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8303.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8de78]
>[  8303.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8de78] width 1280 pitch 5120 (/4 1280)
>[  8304.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8304.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8304.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8304.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52b90]
>[  8304.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52b90] width 1280 pitch 5120 (/4 1280)
>[  8308.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8308.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39460]
>[  8308.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39460] width 1280 pitch 5120 (/4 1280)
>[  8308.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39490]
>[  8308.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39490] width 1280 pitch 5120 (/4 1280)
>[  8316.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8316.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8316.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8316.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8316.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8316.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8316.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3a640]
>[  8316.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3a640] width 1280 pitch 5120 (/4 1280)
>[  8316.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8316.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8316.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3a640]
>[  8316.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3a640] width 1280 pitch 5120 (/4 1280)
>[  8316.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb748]
>[  8316.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb748] width 1280 pitch 5120 (/4 1280)
>[  8316.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3a640]
>[  8316.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3a640] width 1280 pitch 5120 (/4 1280)
>[  8316.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb748]
>[  8316.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb748] width 1280 pitch 5120 (/4 1280)
>[  8317.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8317.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8317.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8317.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8317.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8317.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8318.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8318.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8318.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[  8318.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[  8318.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8318.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8318.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8318.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8319.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8319.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8319.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbac70]
>[  8319.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbac70] width 1280 pitch 5120 (/4 1280)
>[  8319.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c92a48]
>[  8320.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c92a48] width 1280 pitch 5120 (/4 1280)
>[  8322.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c58]
>[  8322.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c58] width 1280 pitch 5120 (/4 1280)
>[  8322.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c58]
>[  8322.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c58] width 1280 pitch 5120 (/4 1280)
>[  8322.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c58]
>[  8322.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c58] width 1280 pitch 5120 (/4 1280)
>[  8322.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c58]
>[  8322.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c58] width 1280 pitch 5120 (/4 1280)
>[  8322.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9b420]
>[  8322.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9b420] width 1280 pitch 5120 (/4 1280)
>[  8322.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8322.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8322.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c880f8]
>[  8322.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c880f8] width 1280 pitch 5120 (/4 1280)
>[  8322.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccaa20]
>[  8322.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccaa20] width 1280 pitch 5120 (/4 1280)
>[  8322.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b4e8]
>[  8322.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b4e8] width 1280 pitch 5120 (/4 1280)
>[  8323.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8323.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8323.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8323.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8323.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8323.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8324.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8324.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8325.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cacdf0]
>[  8325.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cacdf0] width 1280 pitch 5120 (/4 1280)
>[  8325.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c5a218]
>[  8325.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c5a218] width 1280 pitch 5120 (/4 1280)
>[  8325.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cacdf0]
>[  8325.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cacdf0] width 1280 pitch 5120 (/4 1280)
>[  8325.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8325.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8325.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cacdf0]
>[  8325.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cacdf0] width 1280 pitch 5120 (/4 1280)
>[  8325.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  8325.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  8325.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c58]
>[  8325.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c58] width 1280 pitch 5120 (/4 1280)
>[  8327.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c5a218]
>[  8327.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c5a218] width 1280 pitch 5120 (/4 1280)
>[  8328.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89b18]
>[  8328.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89b18] width 1280 pitch 5120 (/4 1280)
>[  8328.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c61738]
>[  8328.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c61738] width 1280 pitch 5120 (/4 1280)
>[  8328.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd0258]
>[  8328.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd0258] width 1280 pitch 5120 (/4 1280)
>[  8332.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b4e8]
>[  8332.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b4e8] width 1280 pitch 5120 (/4 1280)
>[  8333.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8333.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8335.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3fe60]
>[  8335.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3fe60] width 1280 pitch 5120 (/4 1280)
>[  8335.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cace80]
>[  8335.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cace80] width 1280 pitch 5120 (/4 1280)
>[  8340.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e738]
>[  8340.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e738] width 1280 pitch 5120 (/4 1280)
>[  8340.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8340.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8340.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd0258]
>[  8340.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd0258] width 1280 pitch 5120 (/4 1280)
>[  8340.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cace80]
>[  8340.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cace80] width 1280 pitch 5120 (/4 1280)
>[  8340.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd0258]
>[  8340.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd0258] width 1280 pitch 5120 (/4 1280)
>[  8340.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cace80]
>[  8340.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cace80] width 1280 pitch 5120 (/4 1280)
>[  8340.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd0258]
>[  8340.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd0258] width 1280 pitch 5120 (/4 1280)
>[  8340.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cace80]
>[  8340.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cace80] width 1280 pitch 5120 (/4 1280)
>[  8340.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cd0258]
>[  8340.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cd0258] width 1280 pitch 5120 (/4 1280)
>[  8342.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d08130]
>[  8342.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d08130] width 1280 pitch 5120 (/4 1280)
>[  8343.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6f3f8]
>[  8343.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6f3f8] width 1280 pitch 5120 (/4 1280)
>[  8343.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8b3f8]
>[  8343.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8b3f8] width 1280 pitch 5120 (/4 1280)
>[  8343.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c26408]
>[  8344.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c26408] width 1280 pitch 5120 (/4 1280)
>[  8344.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c76738]
>[  8344.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c76738] width 1280 pitch 5120 (/4 1280)
>[  8344.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca20d8]
>[  8344.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca20d8] width 1280 pitch 5120 (/4 1280)
>[  8349.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52c60]
>[  8350.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52c60] width 1280 pitch 5120 (/4 1280)
>[  8350.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2d328]
>[  8350.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2d328] width 1280 pitch 5120 (/4 1280)
>[  8350.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2d2b0]
>[  8350.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2d2b0] width 1280 pitch 5120 (/4 1280)
>[  8451.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac56b8]
>[  8451.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac56b8] width 1280 pitch 5120 (/4 1280)
>[  8457.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c936e8]
>[  8457.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c936e8] width 1280 pitch 5120 (/4 1280)
>[  8498.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9f570]
>[  8498.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9f570] width 1280 pitch 5120 (/4 1280)
>[  8498.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c968]
>[  8498.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c968] width 1280 pitch 5120 (/4 1280)
>[  8499.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c968]
>[  8499.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c968] width 1280 pitch 5120 (/4 1280)
>[  8499.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c936e8]
>[  8499.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c936e8] width 1280 pitch 5120 (/4 1280)
>[  8500.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52d30]
>[  8500.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52d30] width 1280 pitch 5120 (/4 1280)
>[  8501.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52d30]
>[  8501.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52d30] width 1280 pitch 5120 (/4 1280)
>[  8501.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca06f0]
>[  8501.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca06f0] width 1280 pitch 5120 (/4 1280)
>[  8501.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d12208]
>[  8501.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d12208] width 1280 pitch 5120 (/4 1280)
>[  8527.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52d30]
>[  8527.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52d30] width 1280 pitch 5120 (/4 1280)
>[  8530.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3cbd8]
>[  8530.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3cbd8] width 1280 pitch 5120 (/4 1280)
>[  8530.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfaf10]
>[  8530.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfaf10] width 1280 pitch 5120 (/4 1280)
>[  8530.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7768]
>[  8530.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7768] width 1280 pitch 5120 (/4 1280)
>[  8533.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19e60]
>[  8533.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19e60] width 1280 pitch 5120 (/4 1280)
>[  8558.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0438]
>[  8558.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0438] width 1280 pitch 5120 (/4 1280)
>[  8565.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d49ff8]
>[  8565.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d49ff8] width 1280 pitch 5120 (/4 1280)
>[  8572.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c928]
>[  8572.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c928] width 1280 pitch 5120 (/4 1280)
>[  8573.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a818]
>[  8573.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a818] width 1280 pitch 5120 (/4 1280)
>[  8574.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a818]
>[  8574.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a818] width 1280 pitch 5120 (/4 1280)
>[  8574.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d13d70]
>[  8574.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d13d70] width 1280 pitch 5120 (/4 1280)
>[  8575.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d352d0]
>[  8575.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d352d0] width 1280 pitch 5120 (/4 1280)
>[  8575.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d35208]
>[  8575.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d35208] width 1280 pitch 5120 (/4 1280)
>[  8578.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c98fe8]
>[  8578.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c98fe8] width 1280 pitch 5120 (/4 1280)
>[  8578.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c98fe8]
>[  8578.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c98fe8] width 1280 pitch 5120 (/4 1280)
>[  8581.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0240]
>[  8581.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0240] width 1280 pitch 5120 (/4 1280)
>[  8581.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0240]
>[  8581.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0240] width 1280 pitch 5120 (/4 1280)
>[  8587.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8dce0]
>[  8587.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8dce0] width 1280 pitch 5120 (/4 1280)
>[  8587.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c98fe8]
>[  8587.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c98fe8] width 1280 pitch 5120 (/4 1280)
>[  8587.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d35168]
>[  8587.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d35168] width 1280 pitch 5120 (/4 1280)
>[  8587.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c98fe8]
>[  8587.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c98fe8] width 1280 pitch 5120 (/4 1280)
>[  8604.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d50098]
>[  8604.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d50098] width 1280 pitch 5120 (/4 1280)
>[  8604.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47140]
>[  8604.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47140] width 1280 pitch 5120 (/4 1280)
>[  8604.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d50098]
>[  8604.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d50098] width 1280 pitch 5120 (/4 1280)
>[  8604.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47140]
>[  8604.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47140] width 1280 pitch 5120 (/4 1280)
>[  8702.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6cd70]
>[  8702.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6cd70] width 1280 pitch 5120 (/4 1280)
>[  8702.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6c9e8]
>[  8702.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6c9e8] width 1280 pitch 5120 (/4 1280)
>[  8702.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d338]
>[  8702.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d338] width 1280 pitch 5120 (/4 1280)
>[  8702.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6c9e8]
>[  8702.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6c9e8] width 1280 pitch 5120 (/4 1280)
>[  8702.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd0eb8]
>[  8702.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd0eb8] width 1280 pitch 5120 (/4 1280)
>[  8702.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6c9e8]
>[  8702.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6c9e8] width 1280 pitch 5120 (/4 1280)
>[  8702.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3efe0]
>[  8702.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3efe0] width 1280 pitch 5120 (/4 1280)
>[  8753.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d210f8]
>[  8753.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d210f8] width 1280 pitch 5120 (/4 1280)
>[  8753.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4da50]
>[  8753.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4da50] width 1280 pitch 5120 (/4 1280)
>[  8753.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d210f8]
>[  8753.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d210f8] width 1280 pitch 5120 (/4 1280)
>[  8753.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4da50]
>[  8753.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4da50] width 1280 pitch 5120 (/4 1280)
>[  8753.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d210f8]
>[  8753.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d210f8] width 1280 pitch 5120 (/4 1280)
>[  8753.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8753.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8753.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62480]
>[  8753.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62480] width 1280 pitch 5120 (/4 1280)
>[  8753.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d210f8]
>[  8753.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d210f8] width 1280 pitch 5120 (/4 1280)
>[  8753.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d205b0]
>[  8753.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d205b0] width 1280 pitch 5120 (/4 1280)
>[  8798.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8798.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8798.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c080]
>[  8798.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c080] width 1280 pitch 5120 (/4 1280)
>[  8798.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8798.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8798.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8798.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c080]
>[  8798.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c080] width 1280 pitch 5120 (/4 1280)
>[  8798.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d37328]
>[  8798.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d37328] width 1280 pitch 5120 (/4 1280)
>[  8801.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c280]
>[  8801.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c280] width 1280 pitch 5120 (/4 1280)
>[  8801.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62480]
>[  8801.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62480] width 1280 pitch 5120 (/4 1280)
>[  8801.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c280]
>[  8801.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c280] width 1280 pitch 5120 (/4 1280)
>[  8801.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62480]
>[  8801.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62480] width 1280 pitch 5120 (/4 1280)
>[  8801.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c280]
>[  8801.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c280] width 1280 pitch 5120 (/4 1280)
>[  8801.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d205b0]
>[  8802.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d205b0] width 1280 pitch 5120 (/4 1280)
>[  8802.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c080]
>[  8802.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c080] width 1280 pitch 5120 (/4 1280)
>[  8802.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3be18]
>[  8802.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3be18] width 1280 pitch 5120 (/4 1280)
>[  8802.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c080]
>[  8802.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c080] width 1280 pitch 5120 (/4 1280)
>[  9001.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d63ca0]
>[  9001.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d63ca0] width 1280 pitch 5120 (/4 1280)
>[  9001.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d210f8]
>[  9001.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d210f8] width 1280 pitch 5120 (/4 1280)
>[  9001.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d63ca0]
>[  9001.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d63ca0] width 1280 pitch 5120 (/4 1280)
>[  9006.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9006.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9022.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62480]
>[  9022.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62480] width 1280 pitch 5120 (/4 1280)
>[  9022.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d49550]
>[  9022.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d49550] width 1280 pitch 5120 (/4 1280)
>[  9022.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62500]
>[  9022.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62500] width 1280 pitch 5120 (/4 1280)
>[  9022.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4ab58]
>[  9022.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4ab58] width 1280 pitch 5120 (/4 1280)
>[  9023.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47728]
>[  9023.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47728] width 1280 pitch 5120 (/4 1280)
>[  9029.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47728]
>[  9029.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47728] width 1280 pitch 5120 (/4 1280)
>[  9029.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d62500]
>[  9029.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d62500] width 1280 pitch 5120 (/4 1280)
>[  9045.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9045.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9045.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d40818]
>[  9045.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d40818] width 1280 pitch 5120 (/4 1280)
>[  9045.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d49550]
>[  9045.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d49550] width 1280 pitch 5120 (/4 1280)
>[  9045.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d40818]
>[  9045.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d40818] width 1280 pitch 5120 (/4 1280)
>[  9050.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d70188]
>[  9050.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d70188] width 1280 pitch 5120 (/4 1280)
>[  9050.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4aca8]
>[  9050.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4aca8] width 1280 pitch 5120 (/4 1280)
>[  9070.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d51200]
>[  9070.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d51200] width 1280 pitch 5120 (/4 1280)
>[  9090.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4dab8]
>[  9090.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4dab8] width 1280 pitch 5120 (/4 1280)
>[  9094.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4dab8]
>[  9094.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4dab8] width 1280 pitch 5120 (/4 1280)
>[  9094.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9094.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9094.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9db9da8]
>[  9094.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9db9da8] width 1280 pitch 5120 (/4 1280)
>[  9094.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbc660]
>[  9094.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbc660] width 1280 pitch 5120 (/4 1280)
>[  9150.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d49550]
>[  9150.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d49550] width 1280 pitch 5120 (/4 1280)
>[  9150.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a200]
>[  9150.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a200] width 1280 pitch 5120 (/4 1280)
>[  9150.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3d2e0]
>[  9150.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3d2e0] width 1280 pitch 5120 (/4 1280)
>[  9150.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a200]
>[  9150.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a200] width 1280 pitch 5120 (/4 1280)
>[  9150.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d44d88]
>[  9150.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d44d88] width 1280 pitch 5120 (/4 1280)
>[  9155.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0ee28]
>[  9155.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0ee28] width 1280 pitch 5120 (/4 1280)
>[  9155.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d5b4a0]
>[  9155.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d5b4a0] width 1280 pitch 5120 (/4 1280)
>[  9155.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0ee10]
>[  9155.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0ee10] width 1280 pitch 5120 (/4 1280)
>[  9155.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9155.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9221.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcf270]
>[  9221.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcf270] width 1280 pitch 5120 (/4 1280)
>[  9221.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9221.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9221.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcf270]
>[  9221.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcf270] width 1280 pitch 5120 (/4 1280)
>[  9221.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9222.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9222.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9222.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9222.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9222.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9222.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9222.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9224.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcf270]
>[  9224.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcf270] width 1280 pitch 5120 (/4 1280)
>[  9224.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0ee10]
>[  9224.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0ee10] width 1280 pitch 5120 (/4 1280)
>[  9224.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcf270]
>[  9224.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcf270] width 1280 pitch 5120 (/4 1280)
>[  9224.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0ee10]
>[  9224.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0ee10] width 1280 pitch 5120 (/4 1280)
>[  9224.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcf270]
>[  9224.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcf270] width 1280 pitch 5120 (/4 1280)
>[  9224.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25a70]
>[  9224.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25a70] width 1280 pitch 5120 (/4 1280)
>[  9224.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9224.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9224.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9224.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9224.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d545a0]
>[  9224.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d545a0] width 1280 pitch 5120 (/4 1280)
>[  9228.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d23b40]
>[  9228.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d23b40] width 1280 pitch 5120 (/4 1280)
>[  9228.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfb60]
>[  9228.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfb60] width 1280 pitch 5120 (/4 1280)
>[  9228.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d236d0]
>[  9228.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d236d0] width 1280 pitch 5120 (/4 1280)
>[  9228.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfb60]
>[  9228.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfb60] width 1280 pitch 5120 (/4 1280)
>[  9228.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d236d0]
>[  9228.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d236d0] width 1280 pitch 5120 (/4 1280)
>[  9228.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d236d0]
>[  9228.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d236d0] width 1280 pitch 5120 (/4 1280)
>[  9228.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfb60]
>[  9228.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfb60] width 1280 pitch 5120 (/4 1280)
>[  9228.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d236d0]
>[  9228.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d236d0] width 1280 pitch 5120 (/4 1280)
>[  9232.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d51a28]
>[  9232.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d51a28] width 1280 pitch 5120 (/4 1280)
>[  9232.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca01e0]
>[  9232.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca01e0] width 1280 pitch 5120 (/4 1280)
>[  9232.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d51a28]
>[  9232.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d51a28] width 1280 pitch 5120 (/4 1280)
>[  9232.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d23910]
>[  9232.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d23910] width 1280 pitch 5120 (/4 1280)
>[  9232.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfb30]
>[  9232.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfb30] width 1280 pitch 5120 (/4 1280)
>[  9564.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d59638]
>[  9564.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d59638] width 1280 pitch 5120 (/4 1280)
>[  9564.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d58488]
>[  9564.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d58488] width 1280 pitch 5120 (/4 1280)
>[  9564.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2080]
>[  9564.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2080] width 1280 pitch 5120 (/4 1280)
>[  9564.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcbe60]
>[  9564.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcbe60] width 1280 pitch 5120 (/4 1280)
>[  9564.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2080]
>[  9564.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2080] width 1280 pitch 5120 (/4 1280)
>[  9564.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcbe60]
>[  9564.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcbe60] width 1280 pitch 5120 (/4 1280)
>[  9564.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6dc68]
>[  9564.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6dc68] width 1280 pitch 5120 (/4 1280)
>[  9564.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6aa20]
>[  9564.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6aa20] width 1280 pitch 5120 (/4 1280)
>[  9564.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6dc68]
>[  9564.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6dc68] width 1280 pitch 5120 (/4 1280)
>[  9588.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f6c50]
>[  9588.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f6c50] width 1280 pitch 5120 (/4 1280)
>[  9602.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4e290]
>[  9602.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4e290] width 1280 pitch 5120 (/4 1280)
>[  9604.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfd60]
>[  9604.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfd60] width 1280 pitch 5120 (/4 1280)
>[  9604.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d59638]
>[  9604.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d59638] width 1280 pitch 5120 (/4 1280)
>[  9604.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfd60]
>[  9604.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfd60] width 1280 pitch 5120 (/4 1280)
>[  9604.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3a080]
>[  9604.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3a080] width 1280 pitch 5120 (/4 1280)
>[  9604.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbfd60]
>[  9604.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbfd60] width 1280 pitch 5120 (/4 1280)
>[  9604.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfacf8]
>[  9604.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfacf8] width 1280 pitch 5120 (/4 1280)
>[  9977.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e262e0]
>[  9977.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e262e0] width 1280 pitch 5120 (/4 1280)
>[  9977.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e28cf8]
>[  9977.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e28cf8] width 1280 pitch 5120 (/4 1280)
>[  9978.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3a110]
>[  9978.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3a110] width 1280 pitch 5120 (/4 1280)
>[  9978.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e2a0b0]
>[  9978.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e2a0b0] width 1280 pitch 5120 (/4 1280)
>[  9978.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3a110]
>[  9978.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3a110] width 1280 pitch 5120 (/4 1280)
>[  9978.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e2a0b0]
>[  9978.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e2a0b0] width 1280 pitch 5120 (/4 1280)
>[  9978.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3a110]
>[  9978.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3a110] width 1280 pitch 5120 (/4 1280)
>[  9978.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e2a0b0]
>[  9978.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e2a0b0] width 1280 pitch 5120 (/4 1280)
>[  9981.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca2f70]
>[  9981.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca2f70] width 1280 pitch 5120 (/4 1280)
>[  9981.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47ec0]
>[  9981.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47ec0] width 1280 pitch 5120 (/4 1280)
>[  9981.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca2f70]
>[  9981.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca2f70] width 1280 pitch 5120 (/4 1280)
>[  9981.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47ec0]
>[  9981.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47ec0] width 1280 pitch 5120 (/4 1280)
>[  9981.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca2f70]
>[  9981.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca2f70] width 1280 pitch 5120 (/4 1280)
>[  9981.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcce30]
>[  9981.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcce30] width 1280 pitch 5120 (/4 1280)
>[  9981.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d22618]
>[  9981.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d22618] width 1280 pitch 5120 (/4 1280)
>[  9981.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcccc0]
>[  9981.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcccc0] width 1280 pitch 5120 (/4 1280)
>[  9986.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3cce0]
>[  9986.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3cce0] width 1280 pitch 5120 (/4 1280)
>[  9986.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d475f8]
>[  9986.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d475f8] width 1280 pitch 5120 (/4 1280)
>[  9986.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d5a208]
>[  9986.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d5a208] width 1280 pitch 5120 (/4 1280)
>[  9998.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4ab58]
>[  9998.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4ab58] width 1280 pitch 5120 (/4 1280)
>[ 10026.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25300]
>[ 10026.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25300] width 1280 pitch 5120 (/4 1280)
>[ 10026.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25300]
>[ 10026.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25300] width 1280 pitch 5120 (/4 1280)
>[ 10026.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6f440]
>[ 10026.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6f440] width 1280 pitch 5120 (/4 1280)
>[ 10026.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25300]
>[ 10026.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25300] width 1280 pitch 5120 (/4 1280)
>[ 10039.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25300]
>[ 10039.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25300] width 1280 pitch 5120 (/4 1280)
>[ 10039.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e28cf8]
>[ 10039.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e28cf8] width 1280 pitch 5120 (/4 1280)
>[ 10039.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d23370]
>[ 10039.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d23370] width 1280 pitch 5120 (/4 1280)
>[ 10039.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d58438]
>[ 10039.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d58438] width 1280 pitch 5120 (/4 1280)
>[ 10047.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d314e0]
>[ 10047.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d314e0] width 1280 pitch 5120 (/4 1280)
>[ 10051.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d69838]
>[ 10051.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d69838] width 1280 pitch 5120 (/4 1280)
>[ 10051.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25a20]
>[ 10051.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25a20] width 1280 pitch 5120 (/4 1280)
>[ 10051.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c432c0]
>[ 10051.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c432c0] width 1280 pitch 5120 (/4 1280)
>[ 10051.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c49830]
>[ 10051.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c49830] width 1280 pitch 5120 (/4 1280)
>[ 10051.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d67fb0]
>[ 10051.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d67fb0] width 1280 pitch 5120 (/4 1280)
>[ 10051.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c432c0]
>[ 10051.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c432c0] width 1280 pitch 5120 (/4 1280)
>[ 10051.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d27258]
>[ 10051.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d27258] width 1280 pitch 5120 (/4 1280)
>[ 10051.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d67fb0]
>[ 10051.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d67fb0] width 1280 pitch 5120 (/4 1280)
>[ 10070.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e21b20]
>[ 10070.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e21b20] width 1280 pitch 5120 (/4 1280)
>[ 10082.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d57a10]
>[ 10083.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d57a10] width 1280 pitch 5120 (/4 1280)
>[ 10097.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d579c8]
>[ 10097.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d579c8] width 1280 pitch 5120 (/4 1280)
>[ 10097.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2ae40]
>[ 10097.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2ae40] width 1280 pitch 5120 (/4 1280)
>[ 10097.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d579c8]
>[ 10098.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d579c8] width 1280 pitch 5120 (/4 1280)
>[ 10098.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2ae40]
>[ 10098.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2ae40] width 1280 pitch 5120 (/4 1280)
>[ 10098.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d579c8]
>[ 10098.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d579c8] width 1280 pitch 5120 (/4 1280)
>[ 10098.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d68da8]
>[ 10098.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d68da8] width 1280 pitch 5120 (/4 1280)
>[ 10098.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2ae40]
>[ 10098.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2ae40] width 1280 pitch 5120 (/4 1280)
>[ 10098.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfe758]
>[ 10098.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfe758] width 1280 pitch 5120 (/4 1280)
>[ 10113.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d22618]
>[ 10113.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d22618] width 1280 pitch 5120 (/4 1280)
>[ 10113.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47728]
>[ 10113.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47728] width 1280 pitch 5120 (/4 1280)
>[ 10114.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4ab58]
>[ 10114.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4ab58] width 1280 pitch 5120 (/4 1280)
>[ 10117.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94d20]
>[ 10117.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94d20] width 1280 pitch 5120 (/4 1280)
>[ 10117.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 10117.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 10117.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c42f00]
>[ 10117.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c42f00] width 1280 pitch 5120 (/4 1280)
>[ 10117.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 10117.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 10117.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52ad8]
>[ 10117.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52ad8] width 1280 pitch 5120 (/4 1280)
>[ 10140.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d58438]
>[ 10140.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d58438] width 1280 pitch 5120 (/4 1280)
>[ 10140.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d52590]
>[ 10140.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d52590] width 1280 pitch 5120 (/4 1280)
>[ 10338.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfd320]
>[ 10338.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfd320] width 1280 pitch 5120 (/4 1280)
>[ 10338.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfd320]
>[ 10338.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfd320] width 1280 pitch 5120 (/4 1280)
>[ 10348.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc61b0]
>[ 10348.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc61b0] width 1280 pitch 5120 (/4 1280)
>[ 10349.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb50]
>[ 10349.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb50] width 1280 pitch 5120 (/4 1280)
>[ 10355.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7a70]
>[ 10356.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7a70] width 1280 pitch 5120 (/4 1280)
>[ 10369.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5bb0]
>[ 10369.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5bb0] width 1280 pitch 5120 (/4 1280)
>[ 10417.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd6628]
>[ 10417.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd6628] width 1280 pitch 5120 (/4 1280)
>[ 10423.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbece8]
>[ 10423.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbece8] width 1280 pitch 5120 (/4 1280)
>[ 10423.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e408a8]
>[ 10423.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e408a8] width 1280 pitch 5120 (/4 1280)
>[ 10423.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c52480]
>[ 10423.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c52480] width 1280 pitch 5120 (/4 1280)
>[ 10437.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36b20]
>[ 10437.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36b20] width 1280 pitch 5120 (/4 1280)
>[ 10444.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbecb8]
>[ 10444.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbecb8] width 1280 pitch 5120 (/4 1280)
>[ 10455.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed53a0]
>[ 10455.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed53a0] width 1280 pitch 5120 (/4 1280)
>[ 10488.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c95bd0]
>[ 10488.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c95bd0] width 1280 pitch 5120 (/4 1280)
>[ 10488.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2010]
>[ 10488.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2010] width 1280 pitch 5120 (/4 1280)
>[ 10489.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1be0]
>[ 10489.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1be0] width 1280 pitch 5120 (/4 1280)
>[ 10489.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2010]
>[ 10489.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2010] width 1280 pitch 5120 (/4 1280)
>[ 10489.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1be0]
>[ 10489.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1be0] width 1280 pitch 5120 (/4 1280)
>[ 10489.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2010]
>[ 10489.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2010] width 1280 pitch 5120 (/4 1280)
>[ 10489.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1be0]
>[ 10489.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1be0] width 1280 pitch 5120 (/4 1280)
>[ 10489.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0f248]
>[ 10489.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0f248] width 1280 pitch 5120 (/4 1280)
>[ 10489.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1be0]
>[ 10489.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1be0] width 1280 pitch 5120 (/4 1280)
>[ 10489.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0f248]
>[ 10489.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0f248] width 1280 pitch 5120 (/4 1280)
>[ 10519.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22318]
>[ 10519.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22318] width 1280 pitch 5120 (/4 1280)
>[ 10520.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1758]
>[ 10520.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1758] width 1280 pitch 5120 (/4 1280)
>[ 10520.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22318]
>[ 10520.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22318] width 1280 pitch 5120 (/4 1280)
>[ 10520.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e0fc18]
>[ 10520.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e0fc18] width 1280 pitch 5120 (/4 1280)
>[ 10520.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94f80]
>[ 10520.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94f80] width 1280 pitch 5120 (/4 1280)
>[ 10520.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d740]
>[ 10520.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d740] width 1280 pitch 5120 (/4 1280)
>[ 10521.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94f80]
>[ 10521.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94f80] width 1280 pitch 5120 (/4 1280)
>[ 10522.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d740]
>[ 10522.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d740] width 1280 pitch 5120 (/4 1280)
>[ 10522.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1268]
>[ 10522.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1268] width 1280 pitch 5120 (/4 1280)
>[ 10522.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22318]
>[ 10522.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22318] width 1280 pitch 5120 (/4 1280)
>[ 10522.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1268]
>[ 10522.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1268] width 1280 pitch 5120 (/4 1280)
>[ 10522.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22318]
>[ 10522.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22318] width 1280 pitch 5120 (/4 1280)
>[ 10542.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd6a68]
>[ 10542.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd6a68] width 1280 pitch 5120 (/4 1280)
>[ 10542.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0d5e8]
>[ 10542.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0d5e8] width 1280 pitch 5120 (/4 1280)
>[ 10542.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6e3b0]
>[ 10542.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6e3b0] width 1280 pitch 5120 (/4 1280)
>[ 10542.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6e380]
>[ 10542.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6e380] width 1280 pitch 5120 (/4 1280)
>[ 10552.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc6bf0]
>[ 10552.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc6bf0] width 1280 pitch 5120 (/4 1280)
>[ 10552.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3120]
>[ 10552.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3120] width 1280 pitch 5120 (/4 1280)
>[ 10552.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbdcb0]
>[ 10552.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbdcb0] width 1280 pitch 5120 (/4 1280)
>[ 10552.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddee38]
>[ 10552.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddee38] width 1280 pitch 5120 (/4 1280)
>[ 10562.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4d2b8]
>[ 10562.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4d2b8] width 1280 pitch 5120 (/4 1280)
>[ 10584.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e496c0]
>[ 10584.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e496c0] width 1280 pitch 5120 (/4 1280)
>[ 10584.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2a278]
>[ 10584.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2a278] width 1280 pitch 5120 (/4 1280)
>[ 10584.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e496c0]
>[ 10584.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e496c0] width 1280 pitch 5120 (/4 1280)
>[ 10584.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb80]
>[ 10584.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb80] width 1280 pitch 5120 (/4 1280)
>[ 10584.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e496c0]
>[ 10584.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e496c0] width 1280 pitch 5120 (/4 1280)
>[ 10584.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb80]
>[ 10584.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb80] width 1280 pitch 5120 (/4 1280)
>[ 10584.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e496c0]
>[ 10584.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e496c0] width 1280 pitch 5120 (/4 1280)
>[ 10584.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb80]
>[ 10584.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb80] width 1280 pitch 5120 (/4 1280)
>[ 10584.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cde8]
>[ 10584.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cde8] width 1280 pitch 5120 (/4 1280)
>[ 10584.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb80]
>[ 10584.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb80] width 1280 pitch 5120 (/4 1280)
>[ 10584.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cde8]
>[ 10584.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cde8] width 1280 pitch 5120 (/4 1280)
>[ 10584.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbeb80]
>[ 10584.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbeb80] width 1280 pitch 5120 (/4 1280)
>[ 10585.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de0158]
>[ 10585.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de0158] width 1280 pitch 5120 (/4 1280)
>[ 10585.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cde8]
>[ 10585.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cde8] width 1280 pitch 5120 (/4 1280)
>[ 10585.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d41ca8]
>[ 10585.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d41ca8] width 1280 pitch 5120 (/4 1280)
>[ 10585.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3ce80]
>[ 10586.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3ce80] width 1280 pitch 5120 (/4 1280)
>[ 10586.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3ab98]
>[ 10586.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3ab98] width 1280 pitch 5120 (/4 1280)
>[ 10586.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cde8]
>[ 10586.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cde8] width 1280 pitch 5120 (/4 1280)
>[ 10586.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3ab98]
>[ 10586.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3ab98] width 1280 pitch 5120 (/4 1280)
>[ 10586.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d41ca8]
>[ 10586.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d41ca8] width 1280 pitch 5120 (/4 1280)
>[ 10586.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3ce80]
>[ 10586.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3ce80] width 1280 pitch 5120 (/4 1280)
>[ 10599.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc9d60]
>[ 10599.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc9d60] width 1280 pitch 5120 (/4 1280)
>[ 10600.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6400]
>[ 10600.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6400] width 1280 pitch 5120 (/4 1280)
>[ 10600.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7ab8]
>[ 10600.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7ab8] width 1280 pitch 5120 (/4 1280)
>[ 10600.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc8518]
>[ 10600.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc8518] width 1280 pitch 5120 (/4 1280)
>[ 10605.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e20668]
>[ 10605.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e20668] width 1280 pitch 5120 (/4 1280)
>[ 10613.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d56940]
>[ 10613.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d56940] width 1280 pitch 5120 (/4 1280)
>[ 10626.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e05468]
>[ 10626.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e05468] width 1280 pitch 5120 (/4 1280)
>[ 10626.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d740]
>[ 10626.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d740] width 1280 pitch 5120 (/4 1280)
>[ 10626.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d13000]
>[ 10626.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d13000] width 1280 pitch 5120 (/4 1280)
>[ 10626.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0508]
>[ 10626.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0508] width 1280 pitch 5120 (/4 1280)
>[ 10626.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e05208]
>[ 10626.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e05208] width 1280 pitch 5120 (/4 1280)
>[ 10626.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc9fc8]
>[ 10626.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc9fc8] width 1280 pitch 5120 (/4 1280)
>[ 10626.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62810]
>[ 10626.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62810] width 1280 pitch 5120 (/4 1280)
>[ 10626.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c627d0]
>[ 10626.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c627d0] width 1280 pitch 5120 (/4 1280)
>[ 10626.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62810]
>[ 10626.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62810] width 1280 pitch 5120 (/4 1280)
>[ 10630.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62650]
>[ 10630.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62650] width 1280 pitch 5120 (/4 1280)
>[ 10630.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10630.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62650]
>[ 10630.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62650] width 1280 pitch 5120 (/4 1280)
>[ 10630.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10630.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d740]
>[ 10630.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d740] width 1280 pitch 5120 (/4 1280)
>[ 10630.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9cb0]
>[ 10630.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9cb0] width 1280 pitch 5120 (/4 1280)
>[ 10630.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10630.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9cb0]
>[ 10630.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9cb0] width 1280 pitch 5120 (/4 1280)
>[ 10630.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10630.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9cb0]
>[ 10630.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9cb0] width 1280 pitch 5120 (/4 1280)
>[ 10630.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10630.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6d740]
>[ 10630.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6d740] width 1280 pitch 5120 (/4 1280)
>[ 10630.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62650]
>[ 10630.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62650] width 1280 pitch 5120 (/4 1280)
>[ 10630.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9288]
>[ 10630.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9288] width 1280 pitch 5120 (/4 1280)
>[ 10631.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10631.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10631.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7760]
>[ 10631.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7760] width 1280 pitch 5120 (/4 1280)
>[ 10631.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9debaf0]
>[ 10631.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9debaf0] width 1280 pitch 5120 (/4 1280)
>[ 10631.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec400]
>[ 10631.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec400] width 1280 pitch 5120 (/4 1280)
>[ 10631.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7760]
>[ 10631.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7760] width 1280 pitch 5120 (/4 1280)
>[ 10631.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9debaf0]
>[ 10631.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9debaf0] width 1280 pitch 5120 (/4 1280)
>[ 10631.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7760]
>[ 10631.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7760] width 1280 pitch 5120 (/4 1280)
>[ 10631.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9debaf0]
>[ 10631.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9debaf0] width 1280 pitch 5120 (/4 1280)
>[ 10631.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd7760]
>[ 10631.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd7760] width 1280 pitch 5120 (/4 1280)
>[ 10631.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9debaf0]
>[ 10631.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9debaf0] width 1280 pitch 5120 (/4 1280)
>[ 10631.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec400]
>[ 10631.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec400] width 1280 pitch 5120 (/4 1280)
>[ 10631.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d26f18]
>[ 10631.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d26f18] width 1280 pitch 5120 (/4 1280)
>[ 10631.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10631.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10631.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d26f18]
>[ 10631.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d26f18] width 1280 pitch 5120 (/4 1280)
>[ 10631.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10631.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10631.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e48e48]
>[ 10631.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e48e48] width 1280 pitch 5120 (/4 1280)
>[ 10631.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10631.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10631.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0508]
>[ 10631.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0508] width 1280 pitch 5120 (/4 1280)
>[ 10631.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10631.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10631.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0508]
>[ 10631.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0508] width 1280 pitch 5120 (/4 1280)
>[ 10632.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca04d8]
>[ 10632.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca04d8] width 1280 pitch 5120 (/4 1280)
>[ 10632.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0508]
>[ 10632.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0508] width 1280 pitch 5120 (/4 1280)
>[ 10632.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec400]
>[ 10632.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec400] width 1280 pitch 5120 (/4 1280)
>[ 10632.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d26f18]
>[ 10632.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d26f18] width 1280 pitch 5120 (/4 1280)
>[ 10632.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e48e48]
>[ 10632.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e48e48] width 1280 pitch 5120 (/4 1280)
>[ 10709.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d43518]
>[ 10709.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d43518] width 1280 pitch 5120 (/4 1280)
>[ 10709.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dea718]
>[ 10709.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dea718] width 1280 pitch 5120 (/4 1280)
>[ 10711.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4b7d0]
>[ 10711.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4b7d0] width 1280 pitch 5120 (/4 1280)
>[ 10711.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22190]
>[ 10711.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22190] width 1280 pitch 5120 (/4 1280)
>[ 10711.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d43518]
>[ 10711.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d43518] width 1280 pitch 5120 (/4 1280)
>[ 10711.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1238]
>[ 10711.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1238] width 1280 pitch 5120 (/4 1280)
>[ 10712.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d43518]
>[ 10712.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d43518] width 1280 pitch 5120 (/4 1280)
>[ 10713.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d43518]
>[ 10713.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d43518] width 1280 pitch 5120 (/4 1280)
>[ 10713.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d5a208]
>[ 10713.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d5a208] width 1280 pitch 5120 (/4 1280)
>[ 10713.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47728]
>[ 10713.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47728] width 1280 pitch 5120 (/4 1280)
>[ 10719.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b620c8]
>[ 10719.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b620c8] width 1280 pitch 5120 (/4 1280)
>[ 10719.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddc6f8]
>[ 10719.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddc6f8] width 1280 pitch 5120 (/4 1280)
>[ 10720.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b61a38]
>[ 10720.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b61a38] width 1280 pitch 5120 (/4 1280)
>[ 10720.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb3d60]
>[ 10720.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb3d60] width 1280 pitch 5120 (/4 1280)
>[ 10726.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc1238]
>[ 10726.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc1238] width 1280 pitch 5120 (/4 1280)
>[ 10726.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb4040]
>[ 10726.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb4040] width 1280 pitch 5120 (/4 1280)
>[ 10726.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d5a208]
>[ 10726.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d5a208] width 1280 pitch 5120 (/4 1280)
>[ 10726.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb4040]
>[ 10726.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb4040] width 1280 pitch 5120 (/4 1280)
>[ 10730.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3de28]
>[ 10730.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3de28] width 1280 pitch 5120 (/4 1280)
>[ 10735.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3eb68]
>[ 10735.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3eb68] width 1280 pitch 5120 (/4 1280)
>[ 10735.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd2998]
>[ 10735.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd2998] width 1280 pitch 5120 (/4 1280)
>[ 10735.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e988]
>[ 10735.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e988] width 1280 pitch 5120 (/4 1280)
>[ 10735.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd2998]
>[ 10735.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd2998] width 1280 pitch 5120 (/4 1280)
>[ 10735.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e988]
>[ 10735.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e988] width 1280 pitch 5120 (/4 1280)
>[ 10735.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de7158]
>[ 10735.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de7158] width 1280 pitch 5120 (/4 1280)
>[ 10735.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6e40]
>[ 10735.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6e40] width 1280 pitch 5120 (/4 1280)
>[ 10735.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de7158]
>[ 10735.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de7158] width 1280 pitch 5120 (/4 1280)
>[ 10743.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4de78]
>[ 10743.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4de78] width 1280 pitch 5120 (/4 1280)
>[ 10743.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e838]
>[ 10743.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e838] width 1280 pitch 5120 (/4 1280)
>[ 10743.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4de78]
>[ 10743.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4de78] width 1280 pitch 5120 (/4 1280)
>[ 10743.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e838]
>[ 10743.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e838] width 1280 pitch 5120 (/4 1280)
>[ 10743.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4de78]
>[ 10743.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4de78] width 1280 pitch 5120 (/4 1280)
>[ 10743.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbc710]
>[ 10743.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbc710] width 1280 pitch 5120 (/4 1280)
>[ 10743.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dce968]
>[ 10743.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dce968] width 1280 pitch 5120 (/4 1280)
>[ 10743.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbc710]
>[ 10743.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbc710] width 1280 pitch 5120 (/4 1280)
>[ 10743.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dce968]
>[ 10743.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dce968] width 1280 pitch 5120 (/4 1280)
>[ 10754.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e838]
>[ 10754.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e838] width 1280 pitch 5120 (/4 1280)
>[ 10759.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39f88]
>[ 10759.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39f88] width 1280 pitch 5120 (/4 1280)
>[ 10759.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc60a0]
>[ 10759.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc60a0] width 1280 pitch 5120 (/4 1280)
>[ 10759.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc60a0]
>[ 10759.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc60a0] width 1280 pitch 5120 (/4 1280)
>[ 10759.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39f88]
>[ 10759.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39f88] width 1280 pitch 5120 (/4 1280)
>[ 10759.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc60a0]
>[ 10759.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc60a0] width 1280 pitch 5120 (/4 1280)
>[ 10759.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39f88]
>[ 10759.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39f88] width 1280 pitch 5120 (/4 1280)
>[ 10759.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc60a0]
>[ 10759.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc60a0] width 1280 pitch 5120 (/4 1280)
>[ 10765.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d106f8]
>[ 10765.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d106f8] width 1280 pitch 5120 (/4 1280)
>[ 10765.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e394c0]
>[ 10766.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e394c0] width 1280 pitch 5120 (/4 1280)
>[ 10766.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d106f8]
>[ 10766.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d106f8] width 1280 pitch 5120 (/4 1280)
>[ 10766.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39630]
>[ 10766.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39630] width 1280 pitch 5120 (/4 1280)
>[ 10766.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e2a320]
>[ 10766.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e2a320] width 1280 pitch 5120 (/4 1280)
>[ 10766.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39630]
>[ 10766.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39630] width 1280 pitch 5120 (/4 1280)
>[ 10766.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e39630]
>[ 10766.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e39630] width 1280 pitch 5120 (/4 1280)
>[ 10766.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e2a320]
>[ 10766.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e2a320] width 1280 pitch 5120 (/4 1280)
>[ 10796.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9db9d18]
>[ 10796.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9db9d18] width 1280 pitch 5120 (/4 1280)
>[ 10796.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b612a0]
>[ 10796.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b612a0] width 1280 pitch 5120 (/4 1280)
>[ 10796.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e838]
>[ 10796.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e838] width 1280 pitch 5120 (/4 1280)
>[ 10796.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b612a0]
>[ 10796.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b612a0] width 1280 pitch 5120 (/4 1280)
>[ 10813.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd36d8]
>[ 10813.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd36d8] width 1280 pitch 5120 (/4 1280)
>[ 10813.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc54f8]
>[ 10813.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc54f8] width 1280 pitch 5120 (/4 1280)
>[ 10813.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3438]
>[ 10813.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3438] width 1280 pitch 5120 (/4 1280)
>[ 10813.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc54f8]
>[ 10813.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc54f8] width 1280 pitch 5120 (/4 1280)
>[ 10813.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3438]
>[ 10813.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3438] width 1280 pitch 5120 (/4 1280)
>[ 10829.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e03258]
>[ 10829.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e03258] width 1280 pitch 5120 (/4 1280)
>[ 10829.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d5b120]
>[ 10829.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d5b120] width 1280 pitch 5120 (/4 1280)
>[ 10829.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a008]
>[ 10829.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a008] width 1280 pitch 5120 (/4 1280)
>[ 10829.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4ca0]
>[ 10829.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4ca0] width 1280 pitch 5120 (/4 1280)
>[ 10840.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2d728]
>[ 10840.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2d728] width 1280 pitch 5120 (/4 1280)
>[ 10844.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4ca0]
>[ 10844.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4ca0] width 1280 pitch 5120 (/4 1280)
>[ 10844.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfe9b8]
>[ 10844.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfe9b8] width 1280 pitch 5120 (/4 1280)
>[ 10844.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3d018]
>[ 10844.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3d018] width 1280 pitch 5120 (/4 1280)
>[ 10845.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfe9b8]
>[ 10845.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfe9b8] width 1280 pitch 5120 (/4 1280)
>[ 10849.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d27d10]
>[ 10849.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d27d10] width 1280 pitch 5120 (/4 1280)
>[ 10852.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ead228]
>[ 10852.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ead228] width 1280 pitch 5120 (/4 1280)
>[ 10852.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e96320]
>[ 10852.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e96320] width 1280 pitch 5120 (/4 1280)
>[ 10852.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eac2f0]
>[ 10852.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eac2f0] width 1280 pitch 5120 (/4 1280)
>[ 10852.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e96320]
>[ 10852.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e96320] width 1280 pitch 5120 (/4 1280)
>[ 10852.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e96b00]
>[ 10852.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e96b00] width 1280 pitch 5120 (/4 1280)
>[ 10852.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab890]
>[ 10852.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab890] width 1280 pitch 5120 (/4 1280)
>[ 10852.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3e3d8]
>[ 10852.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3e3d8] width 1280 pitch 5120 (/4 1280)
>[ 10863.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc59b8]
>[ 10863.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc59b8] width 1280 pitch 5120 (/4 1280)
>[ 10863.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4e020]
>[ 10863.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4e020] width 1280 pitch 5120 (/4 1280)
>[ 10863.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc59b8]
>[ 10863.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc59b8] width 1280 pitch 5120 (/4 1280)
>[ 10863.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4e020]
>[ 10863.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4e020] width 1280 pitch 5120 (/4 1280)
>[ 10863.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9ba98]
>[ 10863.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9ba98] width 1280 pitch 5120 (/4 1280)
>[ 10863.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e47088]
>[ 10863.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e47088] width 1280 pitch 5120 (/4 1280)
>[ 10876.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9bcd0]
>[ 10876.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9bcd0] width 1280 pitch 5120 (/4 1280)
>[ 10876.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9ca18]
>[ 10876.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9ca18] width 1280 pitch 5120 (/4 1280)
>[ 10876.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4e0b0]
>[ 10876.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4e0b0] width 1280 pitch 5120 (/4 1280)
>[ 10876.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9ca18]
>[ 10876.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9ca18] width 1280 pitch 5120 (/4 1280)
>[ 10876.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4e0b0]
>[ 10876.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4e0b0] width 1280 pitch 5120 (/4 1280)
>[ 10876.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df8238]
>[ 10876.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df8238] width 1280 pitch 5120 (/4 1280)
>[ 10876.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df8238]
>[ 10876.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df8238] width 1280 pitch 5120 (/4 1280)
>[ 10876.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e462e8]
>[ 10876.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e462e8] width 1280 pitch 5120 (/4 1280)
>[ 10924.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecb880]
>[ 10924.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecb880] width 1280 pitch 5120 (/4 1280)
>[ 10926.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e54138]
>[ 10926.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e54138] width 1280 pitch 5120 (/4 1280)
>[ 10932.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e46880]
>[ 10932.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e46880] width 1280 pitch 5120 (/4 1280)
>[ 10932.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0a60]
>[ 10932.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0a60] width 1280 pitch 5120 (/4 1280)
>[ 10932.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e46880]
>[ 10932.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e46880] width 1280 pitch 5120 (/4 1280)
>[ 10932.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0a60]
>[ 10932.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0a60] width 1280 pitch 5120 (/4 1280)
>[ 10932.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e46880]
>[ 10932.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e46880] width 1280 pitch 5120 (/4 1280)
>[ 10932.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0a60]
>[ 10932.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0a60] width 1280 pitch 5120 (/4 1280)
>[ 10932.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e46880]
>[ 10932.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e46880] width 1280 pitch 5120 (/4 1280)
>[ 10932.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0a60]
>[ 10932.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0a60] width 1280 pitch 5120 (/4 1280)
>[ 10932.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3d178]
>[ 10932.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3d178] width 1280 pitch 5120 (/4 1280)
>[ 10991.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c930]
>[ 10991.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c930] width 1280 pitch 5120 (/4 1280)
>[ 10991.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfe9b8]
>[ 10991.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfe9b8] width 1280 pitch 5120 (/4 1280)
>[ 10991.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cbe0]
>[ 10991.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cbe0] width 1280 pitch 5120 (/4 1280)
>[ 10991.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e469f8]
>[ 10991.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e469f8] width 1280 pitch 5120 (/4 1280)
>[ 10991.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c51e48]
>[ 10991.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c51e48] width 1280 pitch 5120 (/4 1280)
>[ 10991.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6040]
>[ 10991.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6040] width 1280 pitch 5120 (/4 1280)
>[ 10991.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6040]
>[ 10991.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6040] width 1280 pitch 5120 (/4 1280)
>[ 10991.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6040]
>[ 10991.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6040] width 1280 pitch 5120 (/4 1280)
>[ 10991.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6040]
>[ 10991.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6040] width 1280 pitch 5120 (/4 1280)
>[ 10991.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10991.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10991.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6040]
>[ 10992.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6040] width 1280 pitch 5120 (/4 1280)
>[ 10992.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10992.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10992.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d29730]
>[ 10992.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d29730] width 1280 pitch 5120 (/4 1280)
>[ 10992.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f430]
>[ 10992.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f430] width 1280 pitch 5120 (/4 1280)
>[ 10992.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d29730]
>[ 10992.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d29730] width 1280 pitch 5120 (/4 1280)
>[ 11071.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e50d80]
>[ 11071.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e50d80] width 1280 pitch 5120 (/4 1280)
>[ 11071.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c3e8]
>[ 11071.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c3e8] width 1280 pitch 5120 (/4 1280)
>[ 11071.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c3e8]
>[ 11071.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c3e8] width 1280 pitch 5120 (/4 1280)
>[ 11071.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9b620]
>[ 11071.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9b620] width 1280 pitch 5120 (/4 1280)
>[ 11071.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c3e8]
>[ 11071.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c3e8] width 1280 pitch 5120 (/4 1280)
>[ 11071.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e507d0]
>[ 11071.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e507d0] width 1280 pitch 5120 (/4 1280)
>[ 11071.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cd48]
>[ 11071.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cd48] width 1280 pitch 5120 (/4 1280)
>[ 11071.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e513c0]
>[ 11071.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e513c0] width 1280 pitch 5120 (/4 1280)
>[ 11071.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4cd48]
>[ 11071.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4cd48] width 1280 pitch 5120 (/4 1280)
>[ 11076.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e507d8]
>[ 11076.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e507d8] width 1280 pitch 5120 (/4 1280)
>[ 11076.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3dac0]
>[ 11076.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3dac0] width 1280 pitch 5120 (/4 1280)
>[ 11076.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e507d8]
>[ 11076.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e507d8] width 1280 pitch 5120 (/4 1280)
>[ 11092.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e956c8]
>[ 11092.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e956c8] width 1280 pitch 5120 (/4 1280)
>[ 11092.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11092.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11092.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c288]
>[ 11092.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c288] width 1280 pitch 5120 (/4 1280)
>[ 11092.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11092.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11092.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c288]
>[ 11092.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c288] width 1280 pitch 5120 (/4 1280)
>[ 11092.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11092.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11092.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c288]
>[ 11092.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c288] width 1280 pitch 5120 (/4 1280)
>[ 11092.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11092.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11092.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c288]
>[ 11092.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c288] width 1280 pitch 5120 (/4 1280)
>[ 11092.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11092.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11111.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11111.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11111.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95478]
>[ 11111.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95478] width 1280 pitch 5120 (/4 1280)
>[ 11111.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11111.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11111.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95478]
>[ 11112.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95478] width 1280 pitch 5120 (/4 1280)
>[ 11112.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11112.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11112.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11112.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11112.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11112.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11112.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11112.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11112.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4800]
>[ 11112.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4800] width 1280 pitch 5120 (/4 1280)
>[ 11112.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e954f0]
>[ 11112.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e954f0] width 1280 pitch 5120 (/4 1280)
>[ 11112.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d10010]
>[ 11112.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d10010] width 1280 pitch 5120 (/4 1280)
>[ 11112.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb700]
>[ 11112.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb700] width 1280 pitch 5120 (/4 1280)
>[ 11112.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b62180]
>[ 11112.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b62180] width 1280 pitch 5120 (/4 1280)
>[ 11113.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d10010]
>[ 11113.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d10010] width 1280 pitch 5120 (/4 1280)
>[ 11119.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4e6c8]
>[ 11119.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4e6c8] width 1280 pitch 5120 (/4 1280)
>[ 11119.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de4cf8]
>[ 11119.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de4cf8] width 1280 pitch 5120 (/4 1280)
>[ 11141.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ccb0]
>[ 11141.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ccb0] width 1280 pitch 5120 (/4 1280)
>[ 11142.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89f38]
>[ 11142.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89f38] width 1280 pitch 5120 (/4 1280)
>[ 11142.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d721a0]
>[ 11142.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d721a0] width 1280 pitch 5120 (/4 1280)
>[ 11143.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89f38]
>[ 11143.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89f38] width 1280 pitch 5120 (/4 1280)
>[ 11143.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89f38]
>[ 11143.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89f38] width 1280 pitch 5120 (/4 1280)
>[ 11143.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e000f8]
>[ 11143.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e000f8] width 1280 pitch 5120 (/4 1280)
>[ 11157.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d58f58]
>[ 11157.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d58f58] width 1280 pitch 5120 (/4 1280)
>[ 11157.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5628]
>[ 11157.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5628] width 1280 pitch 5120 (/4 1280)
>[ 11161.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d27320]
>[ 11161.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d27320] width 1280 pitch 5120 (/4 1280)
>[ 11166.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39500]
>[ 11166.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39500] width 1280 pitch 5120 (/4 1280)
>[ 11170.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4f1a0]
>[ 11171.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4f1a0] width 1280 pitch 5120 (/4 1280)
>[ 11171.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5878]
>[ 11171.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5878] width 1280 pitch 5120 (/4 1280)
>[ 11171.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaa6a0]
>[ 11171.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaa6a0] width 1280 pitch 5120 (/4 1280)
>[ 11171.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5878]
>[ 11171.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5878] width 1280 pitch 5120 (/4 1280)
>[ 11171.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb8c18]
>[ 11171.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb8c18] width 1280 pitch 5120 (/4 1280)
>[ 11171.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5878]
>[ 11171.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5878] width 1280 pitch 5120 (/4 1280)
>[ 11171.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb8c18]
>[ 11171.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb8c18] width 1280 pitch 5120 (/4 1280)
>[ 11171.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5878]
>[ 11171.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5878] width 1280 pitch 5120 (/4 1280)
>[ 11176.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9ca40]
>[ 11176.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9ca40] width 1280 pitch 5120 (/4 1280)
>[ 11177.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4c428]
>[ 11177.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4c428] width 1280 pitch 5120 (/4 1280)
>[ 11177.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d391f0]
>[ 11177.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d391f0] width 1280 pitch 5120 (/4 1280)
>[ 11177.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d38368]
>[ 11177.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d38368] width 1280 pitch 5120 (/4 1280)
>[ 11177.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d391f0]
>[ 11177.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d391f0] width 1280 pitch 5120 (/4 1280)
>[ 11177.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d38368]
>[ 11177.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d38368] width 1280 pitch 5120 (/4 1280)
>[ 11177.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3af38]
>[ 11177.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3af38] width 1280 pitch 5120 (/4 1280)
>[ 11177.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca8c60]
>[ 11178.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca8c60] width 1280 pitch 5120 (/4 1280)
>[ 11178.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc5878]
>[ 11178.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc5878] width 1280 pitch 5120 (/4 1280)
>[ 11194.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e53488]
>[ 11194.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e53488] width 1280 pitch 5120 (/4 1280)
>[ 11194.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11194.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11194.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39fb0]
>[ 11194.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39fb0] width 1280 pitch 5120 (/4 1280)
>[ 11194.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11194.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11194.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39fb0]
>[ 11194.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39fb0] width 1280 pitch 5120 (/4 1280)
>[ 11194.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11195.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11195.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39fb0]
>[ 11195.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39fb0] width 1280 pitch 5120 (/4 1280)
>[ 11195.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11195.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11195.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39fb0]
>[ 11195.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39fb0] width 1280 pitch 5120 (/4 1280)
>[ 11195.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11195.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11195.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ea68]
>[ 11195.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ea68] width 1280 pitch 5120 (/4 1280)
>[ 11195.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93e68]
>[ 11195.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93e68] width 1280 pitch 5120 (/4 1280)
>[ 11195.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3c990]
>[ 11195.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3c990] width 1280 pitch 5120 (/4 1280)
>[ 11199.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c93520]
>[ 11199.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c93520] width 1280 pitch 5120 (/4 1280)
>[ 11208.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eafe00]
>[ 11208.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eafe00] width 1280 pitch 5120 (/4 1280)
>[ 11208.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3958]
>[ 11208.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3958] width 1280 pitch 5120 (/4 1280)
>[ 11208.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddc100]
>[ 11208.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddc100] width 1280 pitch 5120 (/4 1280)
>[ 11208.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3958]
>[ 11208.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3958] width 1280 pitch 5120 (/4 1280)
>[ 11208.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddc100]
>[ 11209.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddc100] width 1280 pitch 5120 (/4 1280)
>[ 11209.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4e528]
>[ 11209.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4e528] width 1280 pitch 5120 (/4 1280)
>[ 11209.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddc100]
>[ 11209.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddc100] width 1280 pitch 5120 (/4 1280)
>[ 11214.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaf8b8]
>[ 11214.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaf8b8] width 1280 pitch 5120 (/4 1280)
>[ 11214.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6afd8]
>[ 11214.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6afd8] width 1280 pitch 5120 (/4 1280)
>[ 11214.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaf8b8]
>[ 11214.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaf8b8] width 1280 pitch 5120 (/4 1280)
>[ 11214.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6afd8]
>[ 11214.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6afd8] width 1280 pitch 5120 (/4 1280)
>[ 11214.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaf8b8]
>[ 11214.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaf8b8] width 1280 pitch 5120 (/4 1280)
>[ 11214.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39200]
>[ 11214.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39200] width 1280 pitch 5120 (/4 1280)
>[ 11214.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39200]
>[ 11214.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39200] width 1280 pitch 5120 (/4 1280)
>[ 11218.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc6f58]
>[ 11218.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc6f58] width 1280 pitch 5120 (/4 1280)
>[ 11218.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3df30]
>[ 11218.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3df30] width 1280 pitch 5120 (/4 1280)
>[ 11218.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab680]
>[ 11218.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab680] width 1280 pitch 5120 (/4 1280)
>[ 11218.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbc90]
>[ 11218.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbc90] width 1280 pitch 5120 (/4 1280)
>[ 11218.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab680]
>[ 11218.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab680] width 1280 pitch 5120 (/4 1280)
>[ 11218.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab708]
>[ 11218.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab708] width 1280 pitch 5120 (/4 1280)
>[ 11218.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab680]
>[ 11218.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab680] width 1280 pitch 5120 (/4 1280)
>[ 11218.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab708]
>[ 11218.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab708] width 1280 pitch 5120 (/4 1280)
>[ 11218.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab680]
>[ 11218.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab680] width 1280 pitch 5120 (/4 1280)
>[ 11218.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab708]
>[ 11218.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab708] width 1280 pitch 5120 (/4 1280)
>[ 11223.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbc638]
>[ 11223.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbc638] width 1280 pitch 5120 (/4 1280)
>[ 11223.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab868]
>[ 11223.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab868] width 1280 pitch 5120 (/4 1280)
>[ 11223.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab868]
>[ 11223.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab868] width 1280 pitch 5120 (/4 1280)
>[ 11223.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2f740]
>[ 11223.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2f740] width 1280 pitch 5120 (/4 1280)
>[ 11223.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3df70]
>[ 11223.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3df70] width 1280 pitch 5120 (/4 1280)
>[ 11223.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3f000]
>[ 11223.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3f000] width 1280 pitch 5120 (/4 1280)
>[ 11223.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3f000]
>[ 11223.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3f000] width 1280 pitch 5120 (/4 1280)
>[ 11223.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e45718]
>[ 11223.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e45718] width 1280 pitch 5120 (/4 1280)
>[ 11223.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3f000]
>[ 11223.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3f000] width 1280 pitch 5120 (/4 1280)
>[ 11223.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e45718]
>[ 11223.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e45718] width 1280 pitch 5120 (/4 1280)
>[ 11223.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e47c98]
>[ 11223.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e47c98] width 1280 pitch 5120 (/4 1280)
>[ 11223.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a848a0]
>[ 11223.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a848a0] width 1280 pitch 5120 (/4 1280)
>[ 11223.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3f000]
>[ 11223.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3f000] width 1280 pitch 5120 (/4 1280)
>[ 11223.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3e500]
>[ 11223.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3e500] width 1280 pitch 5120 (/4 1280)
>[ 11226.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7250]
>[ 11226.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7250] width 1280 pitch 5120 (/4 1280)
>[ 11226.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4f030]
>[ 11226.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4f030] width 1280 pitch 5120 (/4 1280)
>[ 11226.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3eb60]
>[ 11226.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3eb60] width 1280 pitch 5120 (/4 1280)
>[ 11226.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4abe8]
>[ 11226.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4abe8] width 1280 pitch 5120 (/4 1280)
>[ 11226.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d391f0]
>[ 11227.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d391f0] width 1280 pitch 5120 (/4 1280)
>[ 11227.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2290]
>[ 11227.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2290] width 1280 pitch 5120 (/4 1280)
>[ 11227.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4ef10]
>[ 11227.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4ef10] width 1280 pitch 5120 (/4 1280)
>[ 11247.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaf328]
>[ 11247.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaf328] width 1280 pitch 5120 (/4 1280)
>[ 11262.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6370]
>[ 11262.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6370] width 1280 pitch 5120 (/4 1280)
>[ 11271.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d128a8]
>[ 11271.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d128a8] width 1280 pitch 5120 (/4 1280)
>[ 11316.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d42ec8]
>[ 11316.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d42ec8] width 1280 pitch 5120 (/4 1280)
>[ 11351.575] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 11351.575] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 11351.575] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 12043.088] (II) RADEON(0): RADEONSaveScreen(2)
>[ 12043.207] (II) RADEON(0): RADEONSaveScreen(0)
>[ 12731.663] (II) RADEON(0): RADEONSaveScreen(1)
>[ 12852.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6e4a8]
>[ 12852.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6e4a8] width 1280 pitch 5120 (/4 1280)
>[ 12857.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3eb60]
>[ 12857.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3eb60] width 1280 pitch 5120 (/4 1280)
>[ 12953.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb8f40]
>[ 12953.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb8f40] width 1280 pitch 5120 (/4 1280)
>[ 12953.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6370]
>[ 12953.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6370] width 1280 pitch 5120 (/4 1280)
>[ 12953.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4d2b8]
>[ 12953.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4d2b8] width 1280 pitch 5120 (/4 1280)
>[ 12953.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d45e10]
>[ 12953.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d45e10] width 1280 pitch 5120 (/4 1280)
>[ 12953.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4d2b8]
>[ 12953.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4d2b8] width 1280 pitch 5120 (/4 1280)
>[ 12953.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d45e10]
>[ 12953.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d45e10] width 1280 pitch 5120 (/4 1280)
>[ 12953.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4d2b8]
>[ 12953.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4d2b8] width 1280 pitch 5120 (/4 1280)
>[ 12953.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d45e10]
>[ 12953.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d45e10] width 1280 pitch 5120 (/4 1280)
>[ 12953.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4d2b8]
>[ 12953.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4d2b8] width 1280 pitch 5120 (/4 1280)
>[ 12957.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb8b28]
>[ 12957.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb8b28] width 1280 pitch 5120 (/4 1280)
>[ 12960.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1c10]
>[ 12960.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1c10] width 1280 pitch 5120 (/4 1280)
>[ 12960.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2290]
>[ 12960.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2290] width 1280 pitch 5120 (/4 1280)
>[ 12960.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d128a8]
>[ 12960.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d128a8] width 1280 pitch 5120 (/4 1280)
>[ 12960.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d45e10]
>[ 12960.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d45e10] width 1280 pitch 5120 (/4 1280)
>[ 12962.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dea798]
>[ 12962.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dea798] width 1280 pitch 5120 (/4 1280)
>[ 12963.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0b738]
>[ 12963.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0b738] width 1280 pitch 5120 (/4 1280)
>[ 12963.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddd4b8]
>[ 12963.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddd4b8] width 1280 pitch 5120 (/4 1280)
>[ 12963.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 12963.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 12963.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbb68]
>[ 12963.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbb68] width 1280 pitch 5120 (/4 1280)
>[ 12974.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2b480]
>[ 12974.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2b480] width 1280 pitch 5120 (/4 1280)
>[ 12980.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca94c8]
>[ 12980.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca94c8] width 1280 pitch 5120 (/4 1280)
>[ 12988.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86800]
>[ 12988.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86800] width 1280 pitch 5120 (/4 1280)
>[ 12989.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 12989.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 12989.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 12989.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 12990.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddd4b8]
>[ 12990.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddd4b8] width 1280 pitch 5120 (/4 1280)
>[ 12990.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 12990.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 12990.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86800]
>[ 12990.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86800] width 1280 pitch 5120 (/4 1280)
>[ 12990.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 12990.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 12994.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 12994.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 12994.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86800]
>[ 12994.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86800] width 1280 pitch 5120 (/4 1280)
>[ 12994.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 12994.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 12994.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 12994.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 12994.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d66bd0]
>[ 12994.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d66bd0] width 1280 pitch 5120 (/4 1280)
>[ 12997.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 12997.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 12997.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96660]
>[ 12998.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96660] width 1280 pitch 5120 (/4 1280)
>[ 12998.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96690]
>[ 12998.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96690] width 1280 pitch 5120 (/4 1280)
>[ 12998.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c966e8]
>[ 12998.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c966e8] width 1280 pitch 5120 (/4 1280)
>[ 13000.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5ad28]
>[ 13000.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5ad28] width 1280 pitch 5120 (/4 1280)
>[ 13000.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec2338]
>[ 13000.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec2338] width 1280 pitch 5120 (/4 1280)
>[ 13000.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e59e70]
>[ 13000.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e59e70] width 1280 pitch 5120 (/4 1280)
>[ 13007.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96778]
>[ 13007.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96778] width 1280 pitch 5120 (/4 1280)
>[ 13010.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8c328]
>[ 13010.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8c328] width 1280 pitch 5120 (/4 1280)
>[ 13010.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d66bd0]
>[ 13010.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d66bd0] width 1280 pitch 5120 (/4 1280)
>[ 13010.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 13010.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 13011.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de0fb8]
>[ 13011.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de0fb8] width 1280 pitch 5120 (/4 1280)
>[ 13011.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f40d98]
>[ 13011.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f40d98] width 1280 pitch 5120 (/4 1280)
>[ 13011.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 13011.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 13011.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6310]
>[ 13011.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6310] width 1280 pitch 5120 (/4 1280)
>[ 13013.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 13013.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 13013.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86800]
>[ 13013.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86800] width 1280 pitch 5120 (/4 1280)
>[ 13013.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d66bd0]
>[ 13013.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d66bd0] width 1280 pitch 5120 (/4 1280)
>[ 13013.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de0fb8]
>[ 13013.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de0fb8] width 1280 pitch 5120 (/4 1280)
>[ 13014.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 13014.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 13018.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddd4b8]
>[ 13018.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddd4b8] width 1280 pitch 5120 (/4 1280)
>[ 13018.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb62d8]
>[ 13018.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb62d8] width 1280 pitch 5120 (/4 1280)
>[ 13024.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f237c0]
>[ 13024.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f237c0] width 1280 pitch 5120 (/4 1280)
>[ 13044.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f23790]
>[ 13044.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f23790] width 1280 pitch 5120 (/4 1280)
>[ 13045.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f368b8]
>[ 13045.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f368b8] width 1280 pitch 5120 (/4 1280)
>[ 13045.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d094a0]
>[ 13046.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d094a0] width 1280 pitch 5120 (/4 1280)
>[ 13046.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f368b8]
>[ 13046.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f368b8] width 1280 pitch 5120 (/4 1280)
>[ 13046.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d094a0]
>[ 13046.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d094a0] width 1280 pitch 5120 (/4 1280)
>[ 13047.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f368d8]
>[ 13047.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f368d8] width 1280 pitch 5120 (/4 1280)
>[ 13047.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e800b8]
>[ 13047.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e800b8] width 1280 pitch 5120 (/4 1280)
>[ 13047.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f368d8]
>[ 13047.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f368d8] width 1280 pitch 5120 (/4 1280)
>[ 14271.163] (II) config/udev: removing device HID 1267:0103
>[ 14271.307] (II) evdev: HID 1267:0103: Close
>[ 14271.320] (II) UnloadModule: "evdev"
>[ 14271.341] (II) config/udev: removing device HID 1267:0103
>[ 14271.617] (II) evdev: HID 1267:0103: Close
>[ 14271.617] (II) UnloadModule: "evdev"
>[ 14271.634] (II) config/udev: removing device Logitech USB Optical Mouse
>[ 14271.636] (II) evdev: Logitech USB Optical Mouse: Close
>[ 14271.636] (II) UnloadModule: "evdev"
>[ 14340.368] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event5)
>[ 14340.368] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[ 14340.368] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[ 14340.369] 	Option "XkbRules" "evdev"
>[ 14340.369] 	Option "XkbModel" "evdev"
>[ 14340.369] 	Option "XkbLayout" "us"
>[ 14340.369] 	Option "_source" "server/udev"
>[ 14340.369] 	Option "name" "Logitech USB Optical Mouse"
>[ 14340.369] 	Option "path" "/dev/input/event5"
>[ 14340.369] 	Option "device" "/dev/input/event5"
>[ 14340.369] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.4/1-7.4:1.0/input/input12/event5"
>[ 14340.369] 	Option "driver" "evdev"
>[ 14340.369] (**) Logitech USB Optical Mouse: always reports core events
>[ 14340.369] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event5"
>[ 14340.434] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc018
>[ 14340.434] (--) evdev: Logitech USB Optical Mouse: Found 3 mouse buttons
>[ 14340.434] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[ 14340.434] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[ 14340.434] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[ 14340.434] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[ 14340.434] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[ 14340.434] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[ 14340.434] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[ 14340.434] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.4/1-7.4:1.0/input/input12/event5"
>[ 14340.434] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 9)
>[ 14340.435] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[ 14340.435] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[ 14340.435] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[ 14340.435] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[ 14340.435] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[ 14340.437] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse1)
>[ 14340.437] (II) No input driver specified, ignoring this device.
>[ 14340.437] (II) This device may have been added with another device file.
>[ 14340.538] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event11)
>[ 14340.538] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[ 14340.538] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[ 14340.538] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[ 14340.538] 	Option "XkbRules" "evdev"
>[ 14340.538] 	Option "XkbModel" "pc105+inet"
>[ 14340.538] 	Option "XkbLayout" "us"
>[ 14340.538] 	Option "_source" "server/udev"
>[ 14340.538] 	Option "name" "HID 1267:0103"
>[ 14340.538] 	Option "path" "/dev/input/event11"
>[ 14340.538] 	Option "device" "/dev/input/event11"
>[ 14340.538] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input14/event11"
>[ 14340.538] 	Option "driver" "evdev"
>[ 14340.538] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[ 14340.538] (**) HID 1267:0103: always reports core events
>[ 14340.538] (**) evdev: HID 1267:0103: Device: "/dev/input/event11"
>[ 14340.538] (--) evdev: HID 1267:0103: absolute axis 0x20 [572..0]
>[ 14340.538] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[ 14340.539] (--) evdev: HID 1267:0103: Found 1 mouse buttons
>[ 14340.539] (--) evdev: HID 1267:0103: Found scroll wheel(s)
>[ 14340.539] (--) evdev: HID 1267:0103: Found relative axes
>[ 14340.539] (II) evdev: HID 1267:0103: Forcing relative x/y axes to exist.
>[ 14340.539] (--) evdev: HID 1267:0103: Found absolute axes
>[ 14340.539] (II) evdev: HID 1267:0103: Forcing absolute x/y axes to exist.
>[ 14340.539] (--) evdev: HID 1267:0103: Found keys
>[ 14340.539] (II) evdev: HID 1267:0103: Configuring as mouse
>[ 14340.539] (II) evdev: HID 1267:0103: Configuring as keyboard
>[ 14340.539] (II) evdev: HID 1267:0103: Adding scrollwheel support
>[ 14340.539] (**) evdev: HID 1267:0103: YAxisMapping: buttons 4 and 5
>[ 14340.539] (**) evdev: HID 1267:0103: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[ 14340.539] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input14/event11"
>[ 14340.539] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 14)
>[ 14340.539] (**) Option "xkb_rules" "evdev"
>[ 14340.539] (**) Option "xkb_model" "pc105+inet"
>[ 14340.539] (**) Option "xkb_layout" "us"
>[ 14340.539] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[ 14340.539] (II) XKB: Reusing cached keymap
>[ 14340.609] (II) evdev: HID 1267:0103: initialized for relative axes.
>[ 14340.609] (WW) evdev: HID 1267:0103: ignoring absolute axes.
>[ 14340.610] (**) HID 1267:0103: (accel) keeping acceleration scheme 1
>[ 14340.610] (**) HID 1267:0103: (accel) acceleration profile 0
>[ 14340.610] (**) HID 1267:0103: (accel) acceleration factor: 2.000
>[ 14340.610] (**) HID 1267:0103: (accel) acceleration threshold: 4
>[ 14340.749] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event10)
>[ 14340.750] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[ 14340.750] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[ 14340.750] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[ 14340.750] 	Option "XkbRules" "evdev"
>[ 14340.750] 	Option "XkbModel" "pc105+inet"
>[ 14340.750] 	Option "XkbLayout" "us"
>[ 14340.750] 	Option "_source" "server/udev"
>[ 14340.750] 	Option "name" "HID 1267:0103"
>[ 14340.750] 	Option "path" "/dev/input/event10"
>[ 14340.750] 	Option "device" "/dev/input/event10"
>[ 14340.750] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input13/event10"
>[ 14340.750] 	Option "driver" "evdev"
>[ 14340.750] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[ 14340.750] (**) HID 1267:0103: always reports core events
>[ 14340.750] (**) evdev: HID 1267:0103: Device: "/dev/input/event10"
>[ 14340.750] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[ 14340.750] (--) evdev: HID 1267:0103: Found keys
>[ 14340.750] (II) evdev: HID 1267:0103: Configuring as keyboard
>[ 14340.750] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input13/event10"
>[ 14340.750] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 15)
>[ 14340.750] (**) Option "xkb_rules" "evdev"
>[ 14340.750] (**) Option "xkb_model" "pc105+inet"
>[ 14340.750] (**) Option "xkb_layout" "us"
>[ 14340.750] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[ 14340.750] (II) XKB: Reusing cached keymap
>[ 14356.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebfae0]
>[ 14356.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebfae0] width 1280 pitch 5120 (/4 1280)
>[ 14358.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f23650]
>[ 14358.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f23650] width 1280 pitch 5120 (/4 1280)
>[ 14362.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30cb8]
>[ 14362.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30cb8] width 1280 pitch 5120 (/4 1280)
>[ 14370.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1d4d0]
>[ 14370.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1d4d0] width 1280 pitch 5120 (/4 1280)
>[ 14370.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30cb8]
>[ 14370.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30cb8] width 1280 pitch 5120 (/4 1280)
>[ 14370.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcc570]
>[ 14370.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcc570] width 1280 pitch 5120 (/4 1280)
>[ 14370.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a31068]
>[ 14370.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a31068] width 1280 pitch 5120 (/4 1280)
>[ 14370.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fddc90]
>[ 14370.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fddc90] width 1280 pitch 5120 (/4 1280)
>[ 14370.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7c0c8]
>[ 14370.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7c0c8] width 1280 pitch 5120 (/4 1280)
>[ 14495.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2290]
>[ 14495.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2290] width 1280 pitch 5120 (/4 1280)
>[ 14501.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d40680]
>[ 14501.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d40680] width 1280 pitch 5120 (/4 1280)
>[ 14501.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e98700]
>[ 14501.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e98700] width 1280 pitch 5120 (/4 1280)
>[ 14501.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec2e68]
>[ 14501.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec2e68] width 1280 pitch 5120 (/4 1280)
>[ 14501.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d34b28]
>[ 14501.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d34b28] width 1280 pitch 5120 (/4 1280)
>[ 14501.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9490]
>[ 14501.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9490] width 1280 pitch 5120 (/4 1280)
>[ 14501.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93e0]
>[ 14501.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93e0] width 1280 pitch 5120 (/4 1280)
>[ 14501.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c49158]
>[ 14501.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c49158] width 1280 pitch 5120 (/4 1280)
>[ 14501.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd0e70]
>[ 14501.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd0e70] width 1280 pitch 5120 (/4 1280)
>[ 14501.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a008]
>[ 14501.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a008] width 1280 pitch 5120 (/4 1280)
>[ 14501.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea70d8]
>[ 14501.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea70d8] width 1280 pitch 5120 (/4 1280)
>[ 14501.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b193d0]
>[ 14501.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b193d0] width 1280 pitch 5120 (/4 1280)
>[ 14502.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d40680]
>[ 14502.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d40680] width 1280 pitch 5120 (/4 1280)
>[ 14502.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec2e68]
>[ 14502.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec2e68] width 1280 pitch 5120 (/4 1280)
>[ 14503.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e98700]
>[ 14503.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e98700] width 1280 pitch 5120 (/4 1280)
>[ 14503.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea9620]
>[ 14503.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea9620] width 1280 pitch 5120 (/4 1280)
>[ 14503.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c54430]
>[ 14503.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c54430] width 1280 pitch 5120 (/4 1280)
>[ 14503.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea70d8]
>[ 14503.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea70d8] width 1280 pitch 5120 (/4 1280)
>[ 14503.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd0e70]
>[ 14503.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd0e70] width 1280 pitch 5120 (/4 1280)
>[ 14503.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93e0]
>[ 14503.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93e0] width 1280 pitch 5120 (/4 1280)
>[ 14503.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b193d0]
>[ 14503.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b193d0] width 1280 pitch 5120 (/4 1280)
>[ 14504.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d34b28]
>[ 14504.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d34b28] width 1280 pitch 5120 (/4 1280)
>[ 14504.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b193d0]
>[ 14504.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b193d0] width 1280 pitch 5120 (/4 1280)
>[ 14504.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93e0]
>[ 14504.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93e0] width 1280 pitch 5120 (/4 1280)
>[ 14504.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a008]
>[ 14504.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a008] width 1280 pitch 5120 (/4 1280)
>[ 14505.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea9620]
>[ 14505.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea9620] width 1280 pitch 5120 (/4 1280)
>[ 14505.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd0e70]
>[ 14505.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd0e70] width 1280 pitch 5120 (/4 1280)
>[ 14505.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07c48]
>[ 14505.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07c48] width 1280 pitch 5120 (/4 1280)
>[ 14505.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d07c48]
>[ 14505.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d07c48] width 1280 pitch 5120 (/4 1280)
>[ 14507.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39ec0]
>[ 14507.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39ec0] width 1280 pitch 5120 (/4 1280)
>[ 14507.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d20868]
>[ 14507.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d20868] width 1280 pitch 5120 (/4 1280)
>[ 14507.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c39f60]
>[ 14507.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c39f60] width 1280 pitch 5120 (/4 1280)
>[ 14508.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d208d0]
>[ 14508.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d208d0] width 1280 pitch 5120 (/4 1280)
>[ 14508.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36148]
>[ 14508.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36148] width 1280 pitch 5120 (/4 1280)
>[ 14508.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 14508.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 14508.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36148]
>[ 14508.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36148] width 1280 pitch 5120 (/4 1280)
>[ 14516.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38db8]
>[ 14516.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38db8] width 1280 pitch 5120 (/4 1280)
>[ 14524.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e948b0]
>[ 14524.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e948b0] width 1280 pitch 5120 (/4 1280)
>[ 14524.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df5d78]
>[ 14524.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df5d78] width 1280 pitch 5120 (/4 1280)
>[ 14524.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4dc70]
>[ 14524.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4dc70] width 1280 pitch 5120 (/4 1280)
>[ 14524.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b1ae48]
>[ 14524.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b1ae48] width 1280 pitch 5120 (/4 1280)
>[ 14524.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cccbc8]
>[ 14524.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cccbc8] width 1280 pitch 5120 (/4 1280)
>[ 14524.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ef10]
>[ 14524.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ef10] width 1280 pitch 5120 (/4 1280)
>[ 14524.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cccbc8]
>[ 14525.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cccbc8] width 1280 pitch 5120 (/4 1280)
>[ 14543.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d079c0]
>[ 14543.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d079c0] width 1280 pitch 5120 (/4 1280)
>[ 14543.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e94880]
>[ 14543.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e94880] width 1280 pitch 5120 (/4 1280)
>[ 14543.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d8d0]
>[ 14543.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d8d0] width 1280 pitch 5120 (/4 1280)
>[ 14543.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccca40]
>[ 14543.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccca40] width 1280 pitch 5120 (/4 1280)
>[ 14543.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d8d0]
>[ 14543.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d8d0] width 1280 pitch 5120 (/4 1280)
>[ 14543.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df5c38]
>[ 14543.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df5c38] width 1280 pitch 5120 (/4 1280)
>[ 14543.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ea38]
>[ 14543.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ea38] width 1280 pitch 5120 (/4 1280)
>[ 14543.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ccca40]
>[ 14543.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ccca40] width 1280 pitch 5120 (/4 1280)
>[ 14547.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9338]
>[ 14547.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9338] width 1280 pitch 5120 (/4 1280)
>[ 14547.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d8d0]
>[ 14547.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d8d0] width 1280 pitch 5120 (/4 1280)
>[ 14547.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60d18]
>[ 14547.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60d18] width 1280 pitch 5120 (/4 1280)
>[ 14547.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9338]
>[ 14547.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9338] width 1280 pitch 5120 (/4 1280)
>[ 14547.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60d18]
>[ 14547.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60d18] width 1280 pitch 5120 (/4 1280)
>[ 14547.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb7df0]
>[ 14547.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb7df0] width 1280 pitch 5120 (/4 1280)
>[ 14547.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60d18]
>[ 14547.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60d18] width 1280 pitch 5120 (/4 1280)
>[ 14547.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb7df0]
>[ 14547.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb7df0] width 1280 pitch 5120 (/4 1280)
>[ 14550.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9bc30]
>[ 14550.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9bc30] width 1280 pitch 5120 (/4 1280)
>[ 14550.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38db8]
>[ 14550.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38db8] width 1280 pitch 5120 (/4 1280)
>[ 14550.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea5ed0]
>[ 14550.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea5ed0] width 1280 pitch 5120 (/4 1280)
>[ 14550.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9338]
>[ 14550.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9338] width 1280 pitch 5120 (/4 1280)
>[ 14550.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea5ed0]
>[ 14550.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea5ed0] width 1280 pitch 5120 (/4 1280)
>[ 14550.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb7df0]
>[ 14550.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb7df0] width 1280 pitch 5120 (/4 1280)
>[ 14550.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea5ed0]
>[ 14550.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea5ed0] width 1280 pitch 5120 (/4 1280)
>[ 14550.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 14550.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 14550.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea5ff0]
>[ 14550.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea5ff0] width 1280 pitch 5120 (/4 1280)
>[ 14550.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ea38]
>[ 14550.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ea38] width 1280 pitch 5120 (/4 1280)
>[ 14556.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60370]
>[ 14556.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60370] width 1280 pitch 5120 (/4 1280)
>[ 14556.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e602c0]
>[ 14556.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e602c0] width 1280 pitch 5120 (/4 1280)
>[ 14556.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be1178]
>[ 14556.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be1178] width 1280 pitch 5120 (/4 1280)
>[ 14556.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60780]
>[ 14556.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60780] width 1280 pitch 5120 (/4 1280)
>[ 14556.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2c188]
>[ 14556.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2c188] width 1280 pitch 5120 (/4 1280)
>[ 14556.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2c188]
>[ 14556.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2c188] width 1280 pitch 5120 (/4 1280)
>[ 14556.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e97eb8]
>[ 14556.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e97eb8] width 1280 pitch 5120 (/4 1280)
>[ 14556.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2c188]
>[ 14556.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2c188] width 1280 pitch 5120 (/4 1280)
>[ 14581.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d30d40]
>[ 14581.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d30d40] width 1280 pitch 5120 (/4 1280)
>[ 14581.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 14581.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 14581.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d30d40]
>[ 14581.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d30d40] width 1280 pitch 5120 (/4 1280)
>[ 14581.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 14581.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 14581.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60750]
>[ 14581.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60750] width 1280 pitch 5120 (/4 1280)
>[ 14581.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 14581.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 14581.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60750]
>[ 14581.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60750] width 1280 pitch 5120 (/4 1280)
>[ 14581.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbccc0]
>[ 14581.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbccc0] width 1280 pitch 5120 (/4 1280)
>[ 14581.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60750]
>[ 14581.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60750] width 1280 pitch 5120 (/4 1280)
>[ 14599.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f362a0]
>[ 14599.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f362a0] width 1280 pitch 5120 (/4 1280)
>[ 14640.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d46000]
>[ 14640.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d46000] width 1280 pitch 5120 (/4 1280)
>[ 14640.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 14640.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 14640.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fddd98]
>[ 14640.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fddd98] width 1280 pitch 5120 (/4 1280)
>[ 14652.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcd4c0]
>[ 14652.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcd4c0] width 1280 pitch 5120 (/4 1280)
>[ 14704.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d56140]
>[ 14704.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d56140] width 1280 pitch 5120 (/4 1280)
>[ 14705.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb84e8]
>[ 14705.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb84e8] width 1280 pitch 5120 (/4 1280)
>[ 14706.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52278]
>[ 14706.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52278] width 1280 pitch 5120 (/4 1280)
>[ 14706.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d56140]
>[ 14706.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d56140] width 1280 pitch 5120 (/4 1280)
>[ 14717.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e04990]
>[ 14717.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e04990] width 1280 pitch 5120 (/4 1280)
>[ 14721.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d012c0]
>[ 14721.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d012c0] width 1280 pitch 5120 (/4 1280)
>[ 14721.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6a398]
>[ 14721.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6a398] width 1280 pitch 5120 (/4 1280)
>[ 14721.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de67e0]
>[ 14721.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de67e0] width 1280 pitch 5120 (/4 1280)
>[ 14721.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f856c8]
>[ 14721.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f856c8] width 1280 pitch 5120 (/4 1280)
>[ 14721.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7eba8]
>[ 14721.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7eba8] width 1280 pitch 5120 (/4 1280)
>[ 14722.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6758]
>[ 14722.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6758] width 1280 pitch 5120 (/4 1280)
>[ 14722.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96eb8]
>[ 14722.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96eb8] width 1280 pitch 5120 (/4 1280)
>[ 14760.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5a6b0]
>[ 14760.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5a6b0] width 1280 pitch 5120 (/4 1280)
>[ 14760.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d01320]
>[ 14760.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d01320] width 1280 pitch 5120 (/4 1280)
>[ 14760.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86a60]
>[ 14760.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86a60] width 1280 pitch 5120 (/4 1280)
>[ 14760.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d01320]
>[ 14760.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d01320] width 1280 pitch 5120 (/4 1280)
>[ 14760.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86a60]
>[ 14760.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86a60] width 1280 pitch 5120 (/4 1280)
>[ 14760.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d01320]
>[ 14760.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d01320] width 1280 pitch 5120 (/4 1280)
>[ 14760.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec5df0]
>[ 14760.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec5df0] width 1280 pitch 5120 (/4 1280)
>[ 14760.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d01320]
>[ 14760.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d01320] width 1280 pitch 5120 (/4 1280)
>[ 14760.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec5df0]
>[ 14760.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec5df0] width 1280 pitch 5120 (/4 1280)
>[ 14776.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86ad8]
>[ 14776.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86ad8] width 1280 pitch 5120 (/4 1280)
>[ 14776.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91448]
>[ 14776.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91448] width 1280 pitch 5120 (/4 1280)
>[ 14776.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec48a8]
>[ 14776.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec48a8] width 1280 pitch 5120 (/4 1280)
>[ 14776.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec48a8]
>[ 14776.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec48a8] width 1280 pitch 5120 (/4 1280)
>[ 14776.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91448]
>[ 14776.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91448] width 1280 pitch 5120 (/4 1280)
>[ 14776.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91448]
>[ 14776.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91448] width 1280 pitch 5120 (/4 1280)
>[ 14776.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91508]
>[ 14776.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91508] width 1280 pitch 5120 (/4 1280)
>[ 14776.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91448]
>[ 14776.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91448] width 1280 pitch 5120 (/4 1280)
>[ 14799.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6e88]
>[ 14800.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6e88] width 1280 pitch 5120 (/4 1280)
>[ 14800.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec4a00]
>[ 14800.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec4a00] width 1280 pitch 5120 (/4 1280)
>[ 14800.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6e88]
>[ 14800.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6e88] width 1280 pitch 5120 (/4 1280)
>[ 14800.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e502d8]
>[ 14800.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e502d8] width 1280 pitch 5120 (/4 1280)
>[ 14800.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d64ba0]
>[ 14800.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d64ba0] width 1280 pitch 5120 (/4 1280)
>[ 14800.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec4a00]
>[ 14800.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec4a00] width 1280 pitch 5120 (/4 1280)
>[ 14800.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d64ba0]
>[ 14800.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d64ba0] width 1280 pitch 5120 (/4 1280)
>[ 14800.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f36380]
>[ 14800.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f36380] width 1280 pitch 5120 (/4 1280)
>[ 14800.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d64ba0]
>[ 14800.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d64ba0] width 1280 pitch 5120 (/4 1280)
>[ 14815.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a84340]
>[ 14815.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a84340] width 1280 pitch 5120 (/4 1280)
>[ 14827.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3810]
>[ 14827.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3810] width 1280 pitch 5120 (/4 1280)
>[ 14832.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1718]
>[ 14832.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1718] width 1280 pitch 5120 (/4 1280)
>[ 14832.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6ede0]
>[ 14832.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6ede0] width 1280 pitch 5120 (/4 1280)
>[ 14832.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66930]
>[ 14832.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66930] width 1280 pitch 5120 (/4 1280)
>[ 14832.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b420]
>[ 14832.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b420] width 1280 pitch 5120 (/4 1280)
>[ 14832.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaefd8]
>[ 14832.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaefd8] width 1280 pitch 5120 (/4 1280)
>[ 14833.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e664c8]
>[ 14833.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e664c8] width 1280 pitch 5120 (/4 1280)
>[ 14833.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6ede0]
>[ 14833.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6ede0] width 1280 pitch 5120 (/4 1280)
>[ 14835.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbb10]
>[ 14835.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbb10] width 1280 pitch 5120 (/4 1280)
>[ 14835.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9148]
>[ 14835.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9148] width 1280 pitch 5120 (/4 1280)
>[ 14835.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbb10]
>[ 14835.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbb10] width 1280 pitch 5120 (/4 1280)
>[ 14835.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9148]
>[ 14835.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9148] width 1280 pitch 5120 (/4 1280)
>[ 14835.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3810]
>[ 14835.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3810] width 1280 pitch 5120 (/4 1280)
>[ 14835.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9148]
>[ 14836.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9148] width 1280 pitch 5120 (/4 1280)
>[ 14836.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1748]
>[ 14836.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1748] width 1280 pitch 5120 (/4 1280)
>[ 14836.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14836.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14838.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66bd8]
>[ 14838.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66bd8] width 1280 pitch 5120 (/4 1280)
>[ 14838.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3a5b8]
>[ 14838.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3a5b8] width 1280 pitch 5120 (/4 1280)
>[ 14838.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65af8]
>[ 14838.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65af8] width 1280 pitch 5120 (/4 1280)
>[ 14838.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6dcb0]
>[ 14838.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6dcb0] width 1280 pitch 5120 (/4 1280)
>[ 14838.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b548]
>[ 14838.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b548] width 1280 pitch 5120 (/4 1280)
>[ 14838.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6dbd0]
>[ 14838.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6dbd0] width 1280 pitch 5120 (/4 1280)
>[ 14838.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6dcb0]
>[ 14838.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6dcb0] width 1280 pitch 5120 (/4 1280)
>[ 14843.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65088]
>[ 14843.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65088] width 1280 pitch 5120 (/4 1280)
>[ 14843.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14843.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14843.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3810]
>[ 14843.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3810] width 1280 pitch 5120 (/4 1280)
>[ 14843.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14843.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14843.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3810]
>[ 14843.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3810] width 1280 pitch 5120 (/4 1280)
>[ 14843.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652e0]
>[ 14843.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652e0] width 1280 pitch 5120 (/4 1280)
>[ 14843.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3810]
>[ 14843.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3810] width 1280 pitch 5120 (/4 1280)
>[ 14843.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652e0]
>[ 14843.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652e0] width 1280 pitch 5120 (/4 1280)
>[ 14846.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca1000]
>[ 14846.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca1000] width 1280 pitch 5120 (/4 1280)
>[ 14846.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652b0]
>[ 14846.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652b0] width 1280 pitch 5120 (/4 1280)
>[ 14846.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652b0]
>[ 14846.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652b0] width 1280 pitch 5120 (/4 1280)
>[ 14846.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652b0]
>[ 14846.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652b0] width 1280 pitch 5120 (/4 1280)
>[ 14846.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca1000]
>[ 14846.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca1000] width 1280 pitch 5120 (/4 1280)
>[ 14846.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e652b0]
>[ 14847.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e652b0] width 1280 pitch 5120 (/4 1280)
>[ 14853.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5ea40]
>[ 14853.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5ea40] width 1280 pitch 5120 (/4 1280)
>[ 14853.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b5f8]
>[ 14853.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b5f8] width 1280 pitch 5120 (/4 1280)
>[ 14853.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5d7e8]
>[ 14853.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5d7e8] width 1280 pitch 5120 (/4 1280)
>[ 14853.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b5f8]
>[ 14853.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b5f8] width 1280 pitch 5120 (/4 1280)
>[ 14853.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5d7e8]
>[ 14853.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5d7e8] width 1280 pitch 5120 (/4 1280)
>[ 14853.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb81b8]
>[ 14853.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb81b8] width 1280 pitch 5120 (/4 1280)
>[ 14853.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66ba8]
>[ 14853.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66ba8] width 1280 pitch 5120 (/4 1280)
>[ 14853.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb81b8]
>[ 14853.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb81b8] width 1280 pitch 5120 (/4 1280)
>[ 14859.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7ddf0]
>[ 14859.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7ddf0] width 1280 pitch 5120 (/4 1280)
>[ 14859.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7df20]
>[ 14859.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7df20] width 1280 pitch 5120 (/4 1280)
>[ 14859.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7ddf0]
>[ 14859.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7ddf0] width 1280 pitch 5120 (/4 1280)
>[ 14859.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7df20]
>[ 14859.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7df20] width 1280 pitch 5120 (/4 1280)
>[ 14859.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00e18]
>[ 14859.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00e18] width 1280 pitch 5120 (/4 1280)
>[ 14859.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7ddf0]
>[ 14859.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7ddf0] width 1280 pitch 5120 (/4 1280)
>[ 14859.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7df20]
>[ 14859.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7df20] width 1280 pitch 5120 (/4 1280)
>[ 14863.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39810]
>[ 14863.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39810] width 1280 pitch 5120 (/4 1280)
>[ 14863.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5d7e8]
>[ 14863.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5d7e8] width 1280 pitch 5120 (/4 1280)
>[ 14863.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1748]
>[ 14863.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1748] width 1280 pitch 5120 (/4 1280)
>[ 14863.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5d7e8]
>[ 14863.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5d7e8] width 1280 pitch 5120 (/4 1280)
>[ 14863.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66ba8]
>[ 14863.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66ba8] width 1280 pitch 5120 (/4 1280)
>[ 14863.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6800]
>[ 14863.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6800] width 1280 pitch 5120 (/4 1280)
>[ 14863.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66ba8]
>[ 14863.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66ba8] width 1280 pitch 5120 (/4 1280)
>[ 14863.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6800]
>[ 14863.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6800] width 1280 pitch 5120 (/4 1280)
>[ 14866.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d028]
>[ 14866.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d028] width 1280 pitch 5120 (/4 1280)
>[ 14866.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e658c0]
>[ 14866.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e658c0] width 1280 pitch 5120 (/4 1280)
>[ 14866.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72ce0]
>[ 14866.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72ce0] width 1280 pitch 5120 (/4 1280)
>[ 14866.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e555f8]
>[ 14866.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e555f8] width 1280 pitch 5120 (/4 1280)
>[ 14866.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eae530]
>[ 14866.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eae530] width 1280 pitch 5120 (/4 1280)
>[ 14867.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e658c0]
>[ 14867.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e658c0] width 1280 pitch 5120 (/4 1280)
>[ 14873.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6620]
>[ 14873.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6620] width 1280 pitch 5120 (/4 1280)
>[ 14873.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1748]
>[ 14873.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1748] width 1280 pitch 5120 (/4 1280)
>[ 14873.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb81b8]
>[ 14873.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb81b8] width 1280 pitch 5120 (/4 1280)
>[ 14873.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1748]
>[ 14873.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1748] width 1280 pitch 5120 (/4 1280)
>[ 14873.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b5f8]
>[ 14873.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b5f8] width 1280 pitch 5120 (/4 1280)
>[ 14873.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14873.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14873.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b5f8]
>[ 14873.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b5f8] width 1280 pitch 5120 (/4 1280)
>[ 14873.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14873.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14884.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c7b0]
>[ 14884.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c7b0] width 1280 pitch 5120 (/4 1280)
>[ 14886.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a048]
>[ 14886.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a048] width 1280 pitch 5120 (/4 1280)
>[ 14886.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a048]
>[ 14886.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a048] width 1280 pitch 5120 (/4 1280)
>[ 14886.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3300]
>[ 14886.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3300] width 1280 pitch 5120 (/4 1280)
>[ 14886.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a048]
>[ 14886.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a048] width 1280 pitch 5120 (/4 1280)
>[ 14886.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfb528]
>[ 14886.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfb528] width 1280 pitch 5120 (/4 1280)
>[ 14886.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff2388]
>[ 14886.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff2388] width 1280 pitch 5120 (/4 1280)
>[ 14886.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3300]
>[ 14886.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3300] width 1280 pitch 5120 (/4 1280)
>[ 14893.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b30638]
>[ 14893.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b30638] width 1280 pitch 5120 (/4 1280)
>[ 14893.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab280]
>[ 14893.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab280] width 1280 pitch 5120 (/4 1280)
>[ 14893.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b30638]
>[ 14893.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b30638] width 1280 pitch 5120 (/4 1280)
>[ 14893.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab280]
>[ 14893.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab280] width 1280 pitch 5120 (/4 1280)
>[ 14893.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66508]
>[ 14893.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66508] width 1280 pitch 5120 (/4 1280)
>[ 14893.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab280]
>[ 14893.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab280] width 1280 pitch 5120 (/4 1280)
>[ 14893.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e66ba8]
>[ 14893.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e66ba8] width 1280 pitch 5120 (/4 1280)
>[ 14893.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab280]
>[ 14893.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab280] width 1280 pitch 5120 (/4 1280)
>[ 14893.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d20988]
>[ 14893.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d20988] width 1280 pitch 5120 (/4 1280)
>[ 14906.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d10800]
>[ 14906.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d10800] width 1280 pitch 5120 (/4 1280)
>[ 14916.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfb3e8]
>[ 14916.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfb3e8] width 1280 pitch 5120 (/4 1280)
>[ 14916.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3a5c0]
>[ 14916.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3a5c0] width 1280 pitch 5120 (/4 1280)
>[ 14916.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3a5c0]
>[ 14916.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3a5c0] width 1280 pitch 5120 (/4 1280)
>[ 14916.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a560]
>[ 14916.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a560] width 1280 pitch 5120 (/4 1280)
>[ 14916.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3a5c0]
>[ 14916.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3a5c0] width 1280 pitch 5120 (/4 1280)
>[ 14916.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e59310]
>[ 14916.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e59310] width 1280 pitch 5120 (/4 1280)
>[ 14916.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6cd78]
>[ 14916.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6cd78] width 1280 pitch 5120 (/4 1280)
>[ 14927.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 14927.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 14927.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2428]
>[ 14927.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2428] width 1280 pitch 5120 (/4 1280)
>[ 14927.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 14927.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 14927.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2428]
>[ 14927.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2428] width 1280 pitch 5120 (/4 1280)
>[ 14927.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 14927.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 14927.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2428]
>[ 14927.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2428] width 1280 pitch 5120 (/4 1280)
>[ 14927.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 14927.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 14927.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2428]
>[ 14927.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2428] width 1280 pitch 5120 (/4 1280)
>[ 14927.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e47bc8]
>[ 14927.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e47bc8] width 1280 pitch 5120 (/4 1280)
>[ 14938.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14938.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14938.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e59150]
>[ 14938.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e59150] width 1280 pitch 5120 (/4 1280)
>[ 14938.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14938.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14938.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e59150]
>[ 14938.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e59150] width 1280 pitch 5120 (/4 1280)
>[ 14938.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14938.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14938.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e59150]
>[ 14938.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e59150] width 1280 pitch 5120 (/4 1280)
>[ 14938.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14938.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14938.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 14938.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 14951.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14951.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14951.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d10b80]
>[ 14951.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d10b80] width 1280 pitch 5120 (/4 1280)
>[ 14951.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14951.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14951.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d10b80]
>[ 14952.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d10b80] width 1280 pitch 5120 (/4 1280)
>[ 14952.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6d138]
>[ 14952.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6d138] width 1280 pitch 5120 (/4 1280)
>[ 14952.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58f90]
>[ 14952.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58f90] width 1280 pitch 5120 (/4 1280)
>[ 14952.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff51e8]
>[ 14952.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff51e8] width 1280 pitch 5120 (/4 1280)
>[ 14952.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 14952.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 14952.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14952.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14952.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 14952.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 14952.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2448]
>[ 14952.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2448] width 1280 pitch 5120 (/4 1280)
>[ 14952.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14952.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14952.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be2448]
>[ 14952.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be2448] width 1280 pitch 5120 (/4 1280)
>[ 14952.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 14952.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 14955.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58f90]
>[ 14955.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58f90] width 1280 pitch 5120 (/4 1280)
>[ 14956.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6480]
>[ 14956.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6480] width 1280 pitch 5120 (/4 1280)
>[ 14956.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6480]
>[ 14956.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6480] width 1280 pitch 5120 (/4 1280)
>[ 14956.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78200]
>[ 14956.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78200] width 1280 pitch 5120 (/4 1280)
>[ 14956.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58bf8]
>[ 14956.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58bf8] width 1280 pitch 5120 (/4 1280)
>[ 14956.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65bc8]
>[ 14956.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65bc8] width 1280 pitch 5120 (/4 1280)
>[ 14956.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6480]
>[ 14956.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6480] width 1280 pitch 5120 (/4 1280)
>[ 14956.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78200]
>[ 14956.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78200] width 1280 pitch 5120 (/4 1280)
>[ 14956.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6480]
>[ 14956.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6480] width 1280 pitch 5120 (/4 1280)
>[ 14956.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78200]
>[ 14956.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78200] width 1280 pitch 5120 (/4 1280)
>[ 14975.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e57818]
>[ 14975.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e57818] width 1280 pitch 5120 (/4 1280)
>[ 14989.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff82c8]
>[ 14989.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff82c8] width 1280 pitch 5120 (/4 1280)
>[ 14989.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14989.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14989.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14989.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14989.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14989.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14989.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14989.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14989.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 14989.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 14989.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c88e70]
>[ 14989.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c88e70] width 1280 pitch 5120 (/4 1280)
>[ 14989.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 14989.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 14992.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e47bc8]
>[ 14992.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e47bc8] width 1280 pitch 5120 (/4 1280)
>[ 14994.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfb7d0]
>[ 14994.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfb7d0] width 1280 pitch 5120 (/4 1280)
>[ 14994.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e63b70]
>[ 14994.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e63b70] width 1280 pitch 5120 (/4 1280)
>[ 14994.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76ac8]
>[ 14994.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76ac8] width 1280 pitch 5120 (/4 1280)
>[ 14994.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa036a60]
>[ 14994.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa036a60] width 1280 pitch 5120 (/4 1280)
>[ 14994.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76ac8]
>[ 14994.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76ac8] width 1280 pitch 5120 (/4 1280)
>[ 15002.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02e590]
>[ 15002.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02e590] width 1280 pitch 5120 (/4 1280)
>[ 15004.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eab1f0]
>[ 15004.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eab1f0] width 1280 pitch 5120 (/4 1280)
>[ 15004.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e43668]
>[ 15004.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e43668] width 1280 pitch 5120 (/4 1280)
>[ 15004.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbaa8]
>[ 15004.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbaa8] width 1280 pitch 5120 (/4 1280)
>[ 15004.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e43668]
>[ 15004.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e43668] width 1280 pitch 5120 (/4 1280)
>[ 15004.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbaa8]
>[ 15004.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbaa8] width 1280 pitch 5120 (/4 1280)
>[ 15004.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e43668]
>[ 15004.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e43668] width 1280 pitch 5120 (/4 1280)
>[ 15004.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbaa8]
>[ 15004.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbaa8] width 1280 pitch 5120 (/4 1280)
>[ 15004.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e43668]
>[ 15004.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e43668] width 1280 pitch 5120 (/4 1280)
>[ 15004.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 15004.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 15004.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a018]
>[ 15004.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a018] width 1280 pitch 5120 (/4 1280)
>[ 15004.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 15004.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 15004.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a018]
>[ 15004.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a018] width 1280 pitch 5120 (/4 1280)
>[ 15004.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebcb40]
>[ 15004.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebcb40] width 1280 pitch 5120 (/4 1280)
>[ 15004.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb81b8]
>[ 15004.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb81b8] width 1280 pitch 5120 (/4 1280)
>[ 15004.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15004.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e43668]
>[ 15005.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e43668] width 1280 pitch 5120 (/4 1280)
>[ 15005.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfbaa8]
>[ 15005.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfbaa8] width 1280 pitch 5120 (/4 1280)
>[ 15005.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8c20]
>[ 15005.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8c20] width 1280 pitch 5120 (/4 1280)
>[ 15005.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15005.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c418]
>[ 15005.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c418] width 1280 pitch 5120 (/4 1280)
>[ 15005.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0360b8]
>[ 15005.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0360b8] width 1280 pitch 5120 (/4 1280)
>[ 15007.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb3010]
>[ 15007.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb3010] width 1280 pitch 5120 (/4 1280)
>[ 15017.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebcb40]
>[ 15017.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebcb40] width 1280 pitch 5120 (/4 1280)
>[ 15017.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58c80]
>[ 15017.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58c80] width 1280 pitch 5120 (/4 1280)
>[ 15017.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e73550]
>[ 15017.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e73550] width 1280 pitch 5120 (/4 1280)
>[ 15017.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58c80]
>[ 15017.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58c80] width 1280 pitch 5120 (/4 1280)
>[ 15017.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58c80]
>[ 15017.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58c80] width 1280 pitch 5120 (/4 1280)
>[ 15017.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78500]
>[ 15017.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78500] width 1280 pitch 5120 (/4 1280)
>[ 15017.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e58c80]
>[ 15017.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e58c80] width 1280 pitch 5120 (/4 1280)
>[ 15017.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78500]
>[ 15017.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78500] width 1280 pitch 5120 (/4 1280)
>[ 15028.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bee0]
>[ 15028.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bee0] width 1280 pitch 5120 (/4 1280)
>[ 15028.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78500]
>[ 15028.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78500] width 1280 pitch 5120 (/4 1280)
>[ 15028.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bee0]
>[ 15028.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bee0] width 1280 pitch 5120 (/4 1280)
>[ 15028.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78500]
>[ 15028.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78500] width 1280 pitch 5120 (/4 1280)
>[ 15028.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bee0]
>[ 15028.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bee0] width 1280 pitch 5120 (/4 1280)
>[ 15028.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78500]
>[ 15028.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78500] width 1280 pitch 5120 (/4 1280)
>[ 15028.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 15028.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 15028.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e605f8]
>[ 15028.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e605f8] width 1280 pitch 5120 (/4 1280)
>[ 15028.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c578]
>[ 15028.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c578] width 1280 pitch 5120 (/4 1280)
>[ 15045.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1e560]
>[ 15045.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1e560] width 1280 pitch 5120 (/4 1280)
>[ 15059.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb81b8]
>[ 15059.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb81b8] width 1280 pitch 5120 (/4 1280)
>[ 15061.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff82c8]
>[ 15061.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff82c8] width 1280 pitch 5120 (/4 1280)
>[ 15061.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c5e8]
>[ 15061.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c5e8] width 1280 pitch 5120 (/4 1280)
>[ 15061.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e79888]
>[ 15061.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e79888] width 1280 pitch 5120 (/4 1280)
>[ 15061.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1be98]
>[ 15061.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1be98] width 1280 pitch 5120 (/4 1280)
>[ 15061.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c5e8]
>[ 15061.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c5e8] width 1280 pitch 5120 (/4 1280)
>[ 15061.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e646a8]
>[ 15061.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e646a8] width 1280 pitch 5120 (/4 1280)
>[ 15061.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c69ea8]
>[ 15061.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c69ea8] width 1280 pitch 5120 (/4 1280)
>[ 15061.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e646a8]
>[ 15061.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e646a8] width 1280 pitch 5120 (/4 1280)
>[ 15061.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c69ea8]
>[ 15061.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c69ea8] width 1280 pitch 5120 (/4 1280)
>[ 15063.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff82c8]
>[ 15063.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff82c8] width 1280 pitch 5120 (/4 1280)
>[ 15063.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39290]
>[ 15063.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39290] width 1280 pitch 5120 (/4 1280)
>[ 15063.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff82c8]
>[ 15063.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff82c8] width 1280 pitch 5120 (/4 1280)
>[ 15063.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39290]
>[ 15063.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39290] width 1280 pitch 5120 (/4 1280)
>[ 15063.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c3b8]
>[ 15063.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c3b8] width 1280 pitch 5120 (/4 1280)
>[ 15063.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa034140]
>[ 15063.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa034140] width 1280 pitch 5120 (/4 1280)
>[ 15063.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff82c8]
>[ 15063.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff82c8] width 1280 pitch 5120 (/4 1280)
>[ 15063.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa034140]
>[ 15063.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa034140] width 1280 pitch 5120 (/4 1280)
>[ 15063.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52c70]
>[ 15064.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52c70] width 1280 pitch 5120 (/4 1280)
>[ 15064.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e53010]
>[ 15064.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e53010] width 1280 pitch 5120 (/4 1280)
>[ 15064.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7c20]
>[ 15064.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7c20] width 1280 pitch 5120 (/4 1280)
>[ 15064.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c148]
>[ 15064.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c148] width 1280 pitch 5120 (/4 1280)
>[ 15064.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7c20]
>[ 15064.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7c20] width 1280 pitch 5120 (/4 1280)
>[ 15064.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c148]
>[ 15064.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c148] width 1280 pitch 5120 (/4 1280)
>[ 15064.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e53010]
>[ 15064.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e53010] width 1280 pitch 5120 (/4 1280)
>[ 15064.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52c18]
>[ 15064.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52c18] width 1280 pitch 5120 (/4 1280)
>[ 15068.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff26c8]
>[ 15069.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff26c8] width 1280 pitch 5120 (/4 1280)
>[ 15069.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52b20]
>[ 15069.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52b20] width 1280 pitch 5120 (/4 1280)
>[ 15069.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff26c8]
>[ 15069.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff26c8] width 1280 pitch 5120 (/4 1280)
>[ 15069.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52b20]
>[ 15069.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52b20] width 1280 pitch 5120 (/4 1280)
>[ 15069.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff26c8]
>[ 15069.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff26c8] width 1280 pitch 5120 (/4 1280)
>[ 15069.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5e780]
>[ 15069.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5e780] width 1280 pitch 5120 (/4 1280)
>[ 15069.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e53010]
>[ 15069.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e53010] width 1280 pitch 5120 (/4 1280)
>[ 15069.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5e780]
>[ 15069.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5e780] width 1280 pitch 5120 (/4 1280)
>[ 15069.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaaf28]
>[ 15069.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaaf28] width 1280 pitch 5120 (/4 1280)
>[ 15074.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd3998]
>[ 15074.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd3998] width 1280 pitch 5120 (/4 1280)
>[ 15080.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca408]
>[ 15080.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca408] width 1280 pitch 5120 (/4 1280)
>[ 15080.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca408]
>[ 15080.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca408] width 1280 pitch 5120 (/4 1280)
>[ 15080.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca408]
>[ 15080.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca408] width 1280 pitch 5120 (/4 1280)
>[ 15080.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60578]
>[ 15080.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60578] width 1280 pitch 5120 (/4 1280)
>[ 15080.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4e40]
>[ 15080.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4e40] width 1280 pitch 5120 (/4 1280)
>[ 15080.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e60578]
>[ 15080.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e60578] width 1280 pitch 5120 (/4 1280)
>[ 15080.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4e40]
>[ 15080.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4e40] width 1280 pitch 5120 (/4 1280)
>[ 15085.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d57c30]
>[ 15085.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d57c30] width 1280 pitch 5120 (/4 1280)
>[ 15085.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4740]
>[ 15085.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4740] width 1280 pitch 5120 (/4 1280)
>[ 15085.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4860]
>[ 15085.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4860] width 1280 pitch 5120 (/4 1280)
>[ 15085.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4740]
>[ 15085.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4740] width 1280 pitch 5120 (/4 1280)
>[ 15085.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4860]
>[ 15085.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4860] width 1280 pitch 5120 (/4 1280)
>[ 15085.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e960d0]
>[ 15085.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e960d0] width 1280 pitch 5120 (/4 1280)
>[ 15085.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4740]
>[ 15085.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4740] width 1280 pitch 5120 (/4 1280)
>[ 15100.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de5650]
>[ 15100.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de5650] width 1280 pitch 5120 (/4 1280)
>[ 15102.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5e4d0]
>[ 15102.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5e4d0] width 1280 pitch 5120 (/4 1280)
>[ 15111.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39928]
>[ 15111.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39928] width 1280 pitch 5120 (/4 1280)
>[ 15113.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bf80]
>[ 15113.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bf80] width 1280 pitch 5120 (/4 1280)
>[ 15114.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e55a98]
>[ 15114.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e55a98] width 1280 pitch 5120 (/4 1280)
>[ 15114.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bf80]
>[ 15114.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bf80] width 1280 pitch 5120 (/4 1280)
>[ 15114.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e55a98]
>[ 15114.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e55a98] width 1280 pitch 5120 (/4 1280)
>[ 15114.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7bf80]
>[ 15114.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7bf80] width 1280 pitch 5120 (/4 1280)
>[ 15114.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e55a98]
>[ 15114.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e55a98] width 1280 pitch 5120 (/4 1280)
>[ 15114.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6fc78]
>[ 15114.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6fc78] width 1280 pitch 5120 (/4 1280)
>[ 15134.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5c40]
>[ 15134.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5c40] width 1280 pitch 5120 (/4 1280)
>[ 15143.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4db00]
>[ 15144.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4db00] width 1280 pitch 5120 (/4 1280)
>[ 15144.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6fe28]
>[ 15144.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6fe28] width 1280 pitch 5120 (/4 1280)
>[ 15144.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4db00]
>[ 15144.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4db00] width 1280 pitch 5120 (/4 1280)
>[ 15144.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6fe28]
>[ 15144.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6fe28] width 1280 pitch 5120 (/4 1280)
>[ 15144.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4db00]
>[ 15144.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4db00] width 1280 pitch 5120 (/4 1280)
>[ 15144.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6ed50]
>[ 15144.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6ed50] width 1280 pitch 5120 (/4 1280)
>[ 15151.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6c4f8]
>[ 15151.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6c4f8] width 1280 pitch 5120 (/4 1280)
>[ 15158.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e50870]
>[ 15158.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e50870] width 1280 pitch 5120 (/4 1280)
>[ 15158.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00fb48]
>[ 15158.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00fb48] width 1280 pitch 5120 (/4 1280)
>[ 15158.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c697b8]
>[ 15158.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c697b8] width 1280 pitch 5120 (/4 1280)
>[ 15158.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e52ca0]
>[ 15158.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e52ca0] width 1280 pitch 5120 (/4 1280)
>[ 15158.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec0348]
>[ 15158.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec0348] width 1280 pitch 5120 (/4 1280)
>[ 15158.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6108]
>[ 15158.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6108] width 1280 pitch 5120 (/4 1280)
>[ 15173.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008278]
>[ 15173.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008278] width 1280 pitch 5120 (/4 1280)
>[ 15173.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c99888]
>[ 15173.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c99888] width 1280 pitch 5120 (/4 1280)
>[ 15173.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008278]
>[ 15173.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008278] width 1280 pitch 5120 (/4 1280)
>[ 15173.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c99888]
>[ 15173.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c99888] width 1280 pitch 5120 (/4 1280)
>[ 15173.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008278]
>[ 15173.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008278] width 1280 pitch 5120 (/4 1280)
>[ 15173.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4fd58]
>[ 15173.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4fd58] width 1280 pitch 5120 (/4 1280)
>[ 15173.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035e48]
>[ 15173.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035e48] width 1280 pitch 5120 (/4 1280)
>[ 15173.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4fd58]
>[ 15173.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4fd58] width 1280 pitch 5120 (/4 1280)
>[ 15173.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035e48]
>[ 15173.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035e48] width 1280 pitch 5120 (/4 1280)
>[ 15181.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033fa8]
>[ 15181.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033fa8] width 1280 pitch 5120 (/4 1280)
>[ 15181.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd9a08]
>[ 15181.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd9a08] width 1280 pitch 5120 (/4 1280)
>[ 15181.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033fa8]
>[ 15181.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033fa8] width 1280 pitch 5120 (/4 1280)
>[ 15181.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00fb40]
>[ 15181.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00fb40] width 1280 pitch 5120 (/4 1280)
>[ 15181.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033fa8]
>[ 15181.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033fa8] width 1280 pitch 5120 (/4 1280)
>[ 15181.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff76a8]
>[ 15181.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff76a8] width 1280 pitch 5120 (/4 1280)
>[ 15181.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033fa8]
>[ 15181.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033fa8] width 1280 pitch 5120 (/4 1280)
>[ 15181.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00fb40]
>[ 15181.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00fb40] width 1280 pitch 5120 (/4 1280)
>[ 15185.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72e18]
>[ 15185.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72e18] width 1280 pitch 5120 (/4 1280)
>[ 15185.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff21b0]
>[ 15185.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff21b0] width 1280 pitch 5120 (/4 1280)
>[ 15185.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72e18]
>[ 15185.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72e18] width 1280 pitch 5120 (/4 1280)
>[ 15185.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff21b0]
>[ 15186.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff21b0] width 1280 pitch 5120 (/4 1280)
>[ 15186.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5db40]
>[ 15186.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5db40] width 1280 pitch 5120 (/4 1280)
>[ 15186.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008278]
>[ 15186.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008278] width 1280 pitch 5120 (/4 1280)
>[ 15186.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ae7728]
>[ 15186.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ae7728] width 1280 pitch 5120 (/4 1280)
>[ 15186.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008278]
>[ 15186.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008278] width 1280 pitch 5120 (/4 1280)
>[ 15186.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ae7728]
>[ 15186.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ae7728] width 1280 pitch 5120 (/4 1280)
>[ 15195.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39928]
>[ 15195.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39928] width 1280 pitch 5120 (/4 1280)
>[ 15202.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e9c5a8]
>[ 15202.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e9c5a8] width 1280 pitch 5120 (/4 1280)
>[ 15216.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6e40]
>[ 15216.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6e40] width 1280 pitch 5120 (/4 1280)
>[ 15216.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa034dd8]
>[ 15216.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa034dd8] width 1280 pitch 5120 (/4 1280)
>[ 15216.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 15216.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 15216.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb6e40]
>[ 15217.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb6e40] width 1280 pitch 5120 (/4 1280)
>[ 15217.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 15217.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 15217.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd9520]
>[ 15217.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd9520] width 1280 pitch 5120 (/4 1280)
>[ 15223.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2e40]
>[ 15223.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2e40] width 1280 pitch 5120 (/4 1280)
>[ 15223.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 15223.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 15223.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2e40]
>[ 15223.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2e40] width 1280 pitch 5120 (/4 1280)
>[ 15223.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5e338]
>[ 15223.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5e338] width 1280 pitch 5120 (/4 1280)
>[ 15223.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c699f8]
>[ 15223.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c699f8] width 1280 pitch 5120 (/4 1280)
>[ 15223.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5e338]
>[ 15223.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5e338] width 1280 pitch 5120 (/4 1280)
>[ 15223.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c699f8]
>[ 15223.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c699f8] width 1280 pitch 5120 (/4 1280)
>[ 15223.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e70278]
>[ 15223.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e70278] width 1280 pitch 5120 (/4 1280)
>[ 15225.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 15225.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 15227.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc340]
>[ 15227.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc340] width 1280 pitch 5120 (/4 1280)
>[ 15227.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e702a8]
>[ 15227.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e702a8] width 1280 pitch 5120 (/4 1280)
>[ 15227.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc340]
>[ 15228.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc340] width 1280 pitch 5120 (/4 1280)
>[ 15258.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a870]
>[ 15258.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a870] width 1280 pitch 5120 (/4 1280)
>[ 15263.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a870]
>[ 15263.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a870] width 1280 pitch 5120 (/4 1280)
>[ 15263.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e71ce8]
>[ 15263.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e71ce8] width 1280 pitch 5120 (/4 1280)
>[ 15278.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e566f0]
>[ 15278.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e566f0] width 1280 pitch 5120 (/4 1280)
>[ 15317.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d42478]
>[ 15317.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d42478] width 1280 pitch 5120 (/4 1280)
>[ 15325.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0177c8]
>[ 15325.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0177c8] width 1280 pitch 5120 (/4 1280)
>[ 15328.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa016960]
>[ 15328.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa016960] width 1280 pitch 5120 (/4 1280)
>[ 15328.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7060]
>[ 15328.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7060] width 1280 pitch 5120 (/4 1280)
>[ 15328.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03dfa0]
>[ 15328.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03dfa0] width 1280 pitch 5120 (/4 1280)
>[ 15328.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7060]
>[ 15328.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7060] width 1280 pitch 5120 (/4 1280)
>[ 15331.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dded48]
>[ 15331.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dded48] width 1280 pitch 5120 (/4 1280)
>[ 15331.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01bda0]
>[ 15331.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01bda0] width 1280 pitch 5120 (/4 1280)
>[ 15331.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa024f98]
>[ 15332.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa024f98] width 1280 pitch 5120 (/4 1280)
>[ 15332.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01d178]
>[ 15332.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01d178] width 1280 pitch 5120 (/4 1280)
>[ 15332.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa024f98]
>[ 15332.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa024f98] width 1280 pitch 5120 (/4 1280)
>[ 15351.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c0e28]
>[ 15351.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c0e28] width 1280 pitch 5120 (/4 1280)
>[ 15371.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cfa40]
>[ 15371.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cfa40] width 1280 pitch 5120 (/4 1280)
>[ 15371.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4e958]
>[ 15371.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4e958] width 1280 pitch 5120 (/4 1280)
>[ 15371.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0fcd0]
>[ 15371.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0fcd0] width 1280 pitch 5120 (/4 1280)
>[ 15371.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7060]
>[ 15371.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7060] width 1280 pitch 5120 (/4 1280)
>[ 15371.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 15371.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 15371.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7060]
>[ 15371.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7060] width 1280 pitch 5120 (/4 1280)
>[ 15371.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 15371.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 15371.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7060]
>[ 15371.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7060] width 1280 pitch 5120 (/4 1280)
>[ 15371.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 15371.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 15376.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19d20]
>[ 15376.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19d20] width 1280 pitch 5120 (/4 1280)
>[ 15407.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d1378]
>[ 15407.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d1378] width 1280 pitch 5120 (/4 1280)
>[ 15407.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0fcd0]
>[ 15407.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0fcd0] width 1280 pitch 5120 (/4 1280)
>[ 15407.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e1c0]
>[ 15407.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e1c0] width 1280 pitch 5120 (/4 1280)
>[ 15407.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d03e8]
>[ 15407.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d03e8] width 1280 pitch 5120 (/4 1280)
>[ 15407.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0fcd0]
>[ 15407.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0fcd0] width 1280 pitch 5120 (/4 1280)
>[ 15407.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 15407.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 15407.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0fcd0]
>[ 15407.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0fcd0] width 1280 pitch 5120 (/4 1280)
>[ 15407.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 15407.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 15410.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a870]
>[ 15410.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a870] width 1280 pitch 5120 (/4 1280)
>[ 15410.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0ffe0]
>[ 15410.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0ffe0] width 1280 pitch 5120 (/4 1280)
>[ 15414.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 15414.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 15429.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e22530]
>[ 15429.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e22530] width 1280 pitch 5120 (/4 1280)
>[ 15432.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f86310]
>[ 15432.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f86310] width 1280 pitch 5120 (/4 1280)
>[ 15432.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e55c80]
>[ 15432.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e55c80] width 1280 pitch 5120 (/4 1280)
>[ 15432.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f86310]
>[ 15433.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f86310] width 1280 pitch 5120 (/4 1280)
>[ 15448.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec3918]
>[ 15448.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec3918] width 1280 pitch 5120 (/4 1280)
>[ 15450.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66bd0]
>[ 15450.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66bd0] width 1280 pitch 5120 (/4 1280)
>[ 15450.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e67f88]
>[ 15450.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e67f88] width 1280 pitch 5120 (/4 1280)
>[ 15450.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e67f88]
>[ 15450.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e67f88] width 1280 pitch 5120 (/4 1280)
>[ 15450.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9db0]
>[ 15450.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9db0] width 1280 pitch 5120 (/4 1280)
>[ 15450.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01a9d0]
>[ 15450.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01a9d0] width 1280 pitch 5120 (/4 1280)
>[ 15462.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4358]
>[ 15462.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4358] width 1280 pitch 5120 (/4 1280)
>[ 15462.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01aa00]
>[ 15462.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01aa00] width 1280 pitch 5120 (/4 1280)
>[ 15462.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9510]
>[ 15462.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9510] width 1280 pitch 5120 (/4 1280)
>[ 15462.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01aa00]
>[ 15462.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01aa00] width 1280 pitch 5120 (/4 1280)
>[ 15462.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9510]
>[ 15462.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9510] width 1280 pitch 5120 (/4 1280)
>[ 15462.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b19118]
>[ 15462.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b19118] width 1280 pitch 5120 (/4 1280)
>[ 15462.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9510]
>[ 15462.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9510] width 1280 pitch 5120 (/4 1280)
>[ 15462.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b19118]
>[ 15462.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b19118] width 1280 pitch 5120 (/4 1280)
>[ 15462.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01c600]
>[ 15462.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01c600] width 1280 pitch 5120 (/4 1280)
>[ 15462.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd4e08]
>[ 15462.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd4e08] width 1280 pitch 5120 (/4 1280)
>[ 15462.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01c600]
>[ 15462.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01c600] width 1280 pitch 5120 (/4 1280)
>[ 15462.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b19118]
>[ 15462.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b19118] width 1280 pitch 5120 (/4 1280)
>[ 15462.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9510]
>[ 15462.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9510] width 1280 pitch 5120 (/4 1280)
>[ 15462.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01c600]
>[ 15462.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01c600] width 1280 pitch 5120 (/4 1280)
>[ 15466.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e54be0]
>[ 15466.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e54be0] width 1280 pitch 5120 (/4 1280)
>[ 15480.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00a098]
>[ 15480.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00a098] width 1280 pitch 5120 (/4 1280)
>[ 15483.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff8408]
>[ 15483.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff8408] width 1280 pitch 5120 (/4 1280)
>[ 15483.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff8408]
>[ 15483.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff8408] width 1280 pitch 5120 (/4 1280)
>[ 15483.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff8408]
>[ 15484.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff8408] width 1280 pitch 5120 (/4 1280)
>[ 15484.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd9448]
>[ 15484.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd9448] width 1280 pitch 5120 (/4 1280)
>[ 15484.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea8ec0]
>[ 15484.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea8ec0] width 1280 pitch 5120 (/4 1280)
>[ 15484.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd9448]
>[ 15484.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd9448] width 1280 pitch 5120 (/4 1280)
>[ 15488.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff42e8]
>[ 15488.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff42e8] width 1280 pitch 5120 (/4 1280)
>[ 15488.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36650]
>[ 15488.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36650] width 1280 pitch 5120 (/4 1280)
>[ 15488.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01bf08]
>[ 15488.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01bf08] width 1280 pitch 5120 (/4 1280)
>[ 15488.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec4260]
>[ 15488.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec4260] width 1280 pitch 5120 (/4 1280)
>[ 15488.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01bf08]
>[ 15488.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01bf08] width 1280 pitch 5120 (/4 1280)
>[ 15488.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec4260]
>[ 15488.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec4260] width 1280 pitch 5120 (/4 1280)
>[ 15488.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36650]
>[ 15488.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36650] width 1280 pitch 5120 (/4 1280)
>[ 15488.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78ab8]
>[ 15488.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78ab8] width 1280 pitch 5120 (/4 1280)
>[ 15488.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36650]
>[ 15488.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36650] width 1280 pitch 5120 (/4 1280)
>[ 15492.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df5810]
>[ 15492.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df5810] width 1280 pitch 5120 (/4 1280)
>[ 15492.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c93d8]
>[ 15492.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c93d8] width 1280 pitch 5120 (/4 1280)
>[ 15492.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d285b8]
>[ 15492.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d285b8] width 1280 pitch 5120 (/4 1280)
>[ 15492.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df5810]
>[ 15492.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df5810] width 1280 pitch 5120 (/4 1280)
>[ 15492.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d285b8]
>[ 15492.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d285b8] width 1280 pitch 5120 (/4 1280)
>[ 15492.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df5810]
>[ 15492.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df5810] width 1280 pitch 5120 (/4 1280)
>[ 15492.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c93d8]
>[ 15492.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c93d8] width 1280 pitch 5120 (/4 1280)
>[ 15494.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb1c40]
>[ 15494.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb1c40] width 1280 pitch 5120 (/4 1280)
>[ 15494.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb1c70]
>[ 15494.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb1c70] width 1280 pitch 5120 (/4 1280)
>[ 15494.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb1c40]
>[ 15494.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb1c40] width 1280 pitch 5120 (/4 1280)
>[ 15494.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb1c70]
>[ 15494.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb1c70] width 1280 pitch 5120 (/4 1280)
>[ 15494.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76fd0]
>[ 15494.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76fd0] width 1280 pitch 5120 (/4 1280)
>[ 15494.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15494.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15494.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15494.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15494.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15494.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15494.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8ee8]
>[ 15494.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8ee8] width 1280 pitch 5120 (/4 1280)
>[ 15494.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15494.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15494.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8ee8]
>[ 15494.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8ee8] width 1280 pitch 5120 (/4 1280)
>[ 15494.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15494.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15494.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8ee8]
>[ 15494.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8ee8] width 1280 pitch 5120 (/4 1280)
>[ 15494.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15494.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15494.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e621c0]
>[ 15494.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e621c0] width 1280 pitch 5120 (/4 1280)
>[ 15495.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb7198]
>[ 15495.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb7198] width 1280 pitch 5120 (/4 1280)
>[ 15495.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b8a0]
>[ 15496.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b8a0] width 1280 pitch 5120 (/4 1280)
>[ 15496.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb7198]
>[ 15496.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb7198] width 1280 pitch 5120 (/4 1280)
>[ 15496.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d285b8]
>[ 15496.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d285b8] width 1280 pitch 5120 (/4 1280)
>[ 15496.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb7198]
>[ 15496.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb7198] width 1280 pitch 5120 (/4 1280)
>[ 15496.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec40e0]
>[ 15496.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec40e0] width 1280 pitch 5120 (/4 1280)
>[ 15496.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7008]
>[ 15496.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7008] width 1280 pitch 5120 (/4 1280)
>[ 15496.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec40e0]
>[ 15496.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec40e0] width 1280 pitch 5120 (/4 1280)
>[ 15496.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7008]
>[ 15496.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7008] width 1280 pitch 5120 (/4 1280)
>[ 15496.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec40e0]
>[ 15496.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec40e0] width 1280 pitch 5120 (/4 1280)
>[ 15496.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec40e0]
>[ 15496.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec40e0] width 1280 pitch 5120 (/4 1280)
>[ 15496.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e08cd0]
>[ 15496.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e08cd0] width 1280 pitch 5120 (/4 1280)
>[ 15496.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026238]
>[ 15496.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026238] width 1280 pitch 5120 (/4 1280)
>[ 15496.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e620e0]
>[ 15496.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e620e0] width 1280 pitch 5120 (/4 1280)
>[ 15496.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e768c8]
>[ 15496.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e768c8] width 1280 pitch 5120 (/4 1280)
>[ 15496.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e768c8]
>[ 15496.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e768c8] width 1280 pitch 5120 (/4 1280)
>[ 15496.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd2d98]
>[ 15496.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd2d98] width 1280 pitch 5120 (/4 1280)
>[ 15496.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e71b30]
>[ 15496.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e71b30] width 1280 pitch 5120 (/4 1280)
>[ 15500.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2c2c8]
>[ 15500.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2c2c8] width 1280 pitch 5120 (/4 1280)
>[ 15500.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df84a8]
>[ 15500.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df84a8] width 1280 pitch 5120 (/4 1280)
>[ 15500.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15500.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15500.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36a38]
>[ 15500.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36a38] width 1280 pitch 5120 (/4 1280)
>[ 15500.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15500.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15500.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36a38]
>[ 15500.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36a38] width 1280 pitch 5120 (/4 1280)
>[ 15500.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15500.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15500.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36a38]
>[ 15500.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36a38] width 1280 pitch 5120 (/4 1280)
>[ 15500.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01c680]
>[ 15500.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01c680] width 1280 pitch 5120 (/4 1280)
>[ 15500.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0087d0]
>[ 15500.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0087d0] width 1280 pitch 5120 (/4 1280)
>[ 15500.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15500.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15500.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b19840]
>[ 15500.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b19840] width 1280 pitch 5120 (/4 1280)
>[ 15500.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e70590]
>[ 15500.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e70590] width 1280 pitch 5120 (/4 1280)
>[ 15502.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c75a10]
>[ 15502.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c75a10] width 1280 pitch 5120 (/4 1280)
>[ 15506.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebd208]
>[ 15507.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebd208] width 1280 pitch 5120 (/4 1280)
>[ 15507.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebd208]
>[ 15507.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebd208] width 1280 pitch 5120 (/4 1280)
>[ 15507.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03c678]
>[ 15507.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03c678] width 1280 pitch 5120 (/4 1280)
>[ 15507.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebd208]
>[ 15507.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebd208] width 1280 pitch 5120 (/4 1280)
>[ 15507.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4608]
>[ 15507.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4608] width 1280 pitch 5120 (/4 1280)
>[ 15507.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed09d8]
>[ 15507.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed09d8] width 1280 pitch 5120 (/4 1280)
>[ 15507.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4608]
>[ 15507.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4608] width 1280 pitch 5120 (/4 1280)
>[ 15507.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed09d8]
>[ 15507.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed09d8] width 1280 pitch 5120 (/4 1280)
>[ 15507.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff4608]
>[ 15507.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff4608] width 1280 pitch 5120 (/4 1280)
>[ 15508.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc20]
>[ 15508.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc20] width 1280 pitch 5120 (/4 1280)
>[ 15508.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e38da8]
>[ 15508.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e38da8] width 1280 pitch 5120 (/4 1280)
>[ 15508.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc20]
>[ 15508.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc20] width 1280 pitch 5120 (/4 1280)
>[ 15508.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e38da8]
>[ 15508.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e38da8] width 1280 pitch 5120 (/4 1280)
>[ 15508.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e38d78]
>[ 15508.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e38d78] width 1280 pitch 5120 (/4 1280)
>[ 15508.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e38da8]
>[ 15508.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e38da8] width 1280 pitch 5120 (/4 1280)
>[ 15508.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d685f8]
>[ 15508.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d685f8] width 1280 pitch 5120 (/4 1280)
>[ 15508.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebd238]
>[ 15508.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebd238] width 1280 pitch 5120 (/4 1280)
>[ 15508.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bcd0]
>[ 15508.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bcd0] width 1280 pitch 5120 (/4 1280)
>[ 15510.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77e40]
>[ 15511.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77e40] width 1280 pitch 5120 (/4 1280)
>[ 15511.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc50]
>[ 15511.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc50] width 1280 pitch 5120 (/4 1280)
>[ 15511.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df59f8]
>[ 15511.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df59f8] width 1280 pitch 5120 (/4 1280)
>[ 15511.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea58f0]
>[ 15511.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea58f0] width 1280 pitch 5120 (/4 1280)
>[ 15511.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc50]
>[ 15511.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc50] width 1280 pitch 5120 (/4 1280)
>[ 15511.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d12a8]
>[ 15511.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d12a8] width 1280 pitch 5120 (/4 1280)
>[ 15511.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cf8d8]
>[ 15511.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cf8d8] width 1280 pitch 5120 (/4 1280)
>[ 15511.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa008488]
>[ 15511.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa008488] width 1280 pitch 5120 (/4 1280)
>[ 15511.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cf8d8]
>[ 15511.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cf8d8] width 1280 pitch 5120 (/4 1280)
>[ 15512.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc50]
>[ 15512.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc50] width 1280 pitch 5120 (/4 1280)
>[ 15512.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7ee0]
>[ 15512.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7ee0] width 1280 pitch 5120 (/4 1280)
>[ 15512.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6bc50]
>[ 15512.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6bc50] width 1280 pitch 5120 (/4 1280)
>[ 15512.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7ee0]
>[ 15512.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7ee0] width 1280 pitch 5120 (/4 1280)
>[ 15512.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d685f8]
>[ 15512.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d685f8] width 1280 pitch 5120 (/4 1280)
>[ 15512.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7ee0]
>[ 15512.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7ee0] width 1280 pitch 5120 (/4 1280)
>[ 15512.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d685f8]
>[ 15512.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d685f8] width 1280 pitch 5120 (/4 1280)
>[ 15512.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7ee0]
>[ 15512.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7ee0] width 1280 pitch 5120 (/4 1280)
>[ 15512.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d685f8]
>[ 15512.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d685f8] width 1280 pitch 5120 (/4 1280)
>[ 15527.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8498]
>[ 15527.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8498] width 1280 pitch 5120 (/4 1280)
>[ 15532.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0098e0]
>[ 15532.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0098e0] width 1280 pitch 5120 (/4 1280)
>[ 15533.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0098e0]
>[ 15533.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0098e0] width 1280 pitch 5120 (/4 1280)
>[ 15533.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037ef0]
>[ 15533.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037ef0] width 1280 pitch 5120 (/4 1280)
>[ 15533.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15533.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15539.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2bbf8]
>[ 15539.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2bbf8] width 1280 pitch 5120 (/4 1280)
>[ 15539.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed0988]
>[ 15539.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed0988] width 1280 pitch 5120 (/4 1280)
>[ 15551.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77148]
>[ 15551.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77148] width 1280 pitch 5120 (/4 1280)
>[ 15551.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8ec38]
>[ 15551.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8ec38] width 1280 pitch 5120 (/4 1280)
>[ 15551.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8ec38]
>[ 15551.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8ec38] width 1280 pitch 5120 (/4 1280)
>[ 15555.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8ec38]
>[ 15555.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8ec38] width 1280 pitch 5120 (/4 1280)
>[ 15565.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36a38]
>[ 15565.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36a38] width 1280 pitch 5120 (/4 1280)
>[ 15565.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15565.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15565.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4150]
>[ 15565.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4150] width 1280 pitch 5120 (/4 1280)
>[ 15565.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15565.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15569.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4ce0]
>[ 15569.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4ce0] width 1280 pitch 5120 (/4 1280)
>[ 15571.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa025d38]
>[ 15571.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa025d38] width 1280 pitch 5120 (/4 1280)
>[ 15571.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0226d0]
>[ 15571.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0226d0] width 1280 pitch 5120 (/4 1280)
>[ 15571.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03a990]
>[ 15571.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03a990] width 1280 pitch 5120 (/4 1280)
>[ 15571.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e74278]
>[ 15571.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e74278] width 1280 pitch 5120 (/4 1280)
>[ 15571.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03e200]
>[ 15571.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03e200] width 1280 pitch 5120 (/4 1280)
>[ 15576.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cac48]
>[ 15576.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cac48] width 1280 pitch 5120 (/4 1280)
>[ 15576.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa022700]
>[ 15576.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa022700] width 1280 pitch 5120 (/4 1280)
>[ 15576.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15576.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15576.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa022700]
>[ 15576.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa022700] width 1280 pitch 5120 (/4 1280)
>[ 15576.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc3cc0]
>[ 15576.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc3cc0] width 1280 pitch 5120 (/4 1280)
>[ 15576.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa022700]
>[ 15576.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa022700] width 1280 pitch 5120 (/4 1280)
>[ 15576.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4150]
>[ 15576.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4150] width 1280 pitch 5120 (/4 1280)
>[ 15576.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02bb58]
>[ 15576.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02bb58] width 1280 pitch 5120 (/4 1280)
>[ 15576.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4150]
>[ 15576.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4150] width 1280 pitch 5120 (/4 1280)
>[ 15576.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15576.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15576.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15576.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15576.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de6b18]
>[ 15576.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de6b18] width 1280 pitch 5120 (/4 1280)
>[ 15576.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7e2e8]
>[ 15576.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7e2e8] width 1280 pitch 5120 (/4 1280)
>[ 15579.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78d78]
>[ 15579.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78d78] width 1280 pitch 5120 (/4 1280)
>[ 15612.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0fb70]
>[ 15612.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0fb70] width 1280 pitch 5120 (/4 1280)
>[ 15612.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0369a8]
>[ 15612.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0369a8] width 1280 pitch 5120 (/4 1280)
>[ 15612.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4150]
>[ 15612.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4150] width 1280 pitch 5120 (/4 1280)
>[ 15612.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0369a8]
>[ 15612.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0369a8] width 1280 pitch 5120 (/4 1280)
>[ 15612.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc4150]
>[ 15612.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc4150] width 1280 pitch 5120 (/4 1280)
>[ 15612.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d13738]
>[ 15612.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d13738] width 1280 pitch 5120 (/4 1280)
>[ 15612.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa025878]
>[ 15613.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa025878] width 1280 pitch 5120 (/4 1280)
>[ 15613.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0f8b0]
>[ 15613.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0f8b0] width 1280 pitch 5120 (/4 1280)
>[ 15613.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa025cc0]
>[ 15613.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa025cc0] width 1280 pitch 5120 (/4 1280)
>[ 15613.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7e318]
>[ 15613.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7e318] width 1280 pitch 5120 (/4 1280)
>[ 15613.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d13738]
>[ 15613.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d13738] width 1280 pitch 5120 (/4 1280)
>[ 15613.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7e318]
>[ 15613.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7e318] width 1280 pitch 5120 (/4 1280)
>[ 15613.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d13738]
>[ 15613.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d13738] width 1280 pitch 5120 (/4 1280)
>[ 15613.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7e318]
>[ 15613.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7e318] width 1280 pitch 5120 (/4 1280)
>[ 15613.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f3c0]
>[ 15613.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f3c0] width 1280 pitch 5120 (/4 1280)
>[ 15613.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b880]
>[ 15613.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b880] width 1280 pitch 5120 (/4 1280)
>[ 15613.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e045e8]
>[ 15613.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e045e8] width 1280 pitch 5120 (/4 1280)
>[ 15613.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc3cc0]
>[ 15613.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc3cc0] width 1280 pitch 5120 (/4 1280)
>[ 15613.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b880]
>[ 15613.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b880] width 1280 pitch 5120 (/4 1280)
>[ 15613.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b770]
>[ 15613.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b770] width 1280 pitch 5120 (/4 1280)
>[ 15613.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0c420]
>[ 15614.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0c420] width 1280 pitch 5120 (/4 1280)
>[ 15614.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b770]
>[ 15614.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b770] width 1280 pitch 5120 (/4 1280)
>[ 15615.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36ef8]
>[ 15615.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36ef8] width 1280 pitch 5120 (/4 1280)
>[ 15615.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b770]
>[ 15615.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b770] width 1280 pitch 5120 (/4 1280)
>[ 15615.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36ef8]
>[ 15615.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36ef8] width 1280 pitch 5120 (/4 1280)
>[ 15615.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b770]
>[ 15615.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b770] width 1280 pitch 5120 (/4 1280)
>[ 15615.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36ef8]
>[ 15616.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36ef8] width 1280 pitch 5120 (/4 1280)
>[ 15616.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b770]
>[ 15616.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b770] width 1280 pitch 5120 (/4 1280)
>[ 15616.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36ef8]
>[ 15616.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36ef8] width 1280 pitch 5120 (/4 1280)
>[ 15616.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc3cc0]
>[ 15616.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc3cc0] width 1280 pitch 5120 (/4 1280)
>[ 15623.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e78d48]
>[ 15623.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e78d48] width 1280 pitch 5120 (/4 1280)
>[ 15626.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa009448]
>[ 15626.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa009448] width 1280 pitch 5120 (/4 1280)
>[ 15626.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaad58]
>[ 15626.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaad58] width 1280 pitch 5120 (/4 1280)
>[ 15626.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6def8]
>[ 15626.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6def8] width 1280 pitch 5120 (/4 1280)
>[ 15626.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaad58]
>[ 15626.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaad58] width 1280 pitch 5120 (/4 1280)
>[ 15626.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaad58]
>[ 15626.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaad58] width 1280 pitch 5120 (/4 1280)
>[ 15626.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6def8]
>[ 15626.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6def8] width 1280 pitch 5120 (/4 1280)
>[ 15626.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec8658]
>[ 15626.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec8658] width 1280 pitch 5120 (/4 1280)
>[ 15626.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6def8]
>[ 15626.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6def8] width 1280 pitch 5120 (/4 1280)
>[ 15626.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec8658]
>[ 15626.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec8658] width 1280 pitch 5120 (/4 1280)
>[ 15627.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caa558]
>[ 15627.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caa558] width 1280 pitch 5120 (/4 1280)
>[ 15627.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb3b38]
>[ 15627.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb3b38] width 1280 pitch 5120 (/4 1280)
>[ 15627.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15627.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15627.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb3b38]
>[ 15627.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb3b38] width 1280 pitch 5120 (/4 1280)
>[ 15627.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77b88]
>[ 15627.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77b88] width 1280 pitch 5120 (/4 1280)
>[ 15627.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa025a80]
>[ 15627.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa025a80] width 1280 pitch 5120 (/4 1280)
>[ 15627.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15627.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15627.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6ec70]
>[ 15627.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6ec70] width 1280 pitch 5120 (/4 1280)
>[ 15627.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfb960]
>[ 15627.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfb960] width 1280 pitch 5120 (/4 1280)
>[ 15629.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa024bd8]
>[ 15629.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa024bd8] width 1280 pitch 5120 (/4 1280)
>[ 15629.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9b70]
>[ 15629.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9b70] width 1280 pitch 5120 (/4 1280)
>[ 15629.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9b70]
>[ 15629.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9b70] width 1280 pitch 5120 (/4 1280)
>[ 15629.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa024bd8]
>[ 15629.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa024bd8] width 1280 pitch 5120 (/4 1280)
>[ 15629.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9b70]
>[ 15629.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9b70] width 1280 pitch 5120 (/4 1280)
>[ 15629.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53db8]
>[ 15629.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53db8] width 1280 pitch 5120 (/4 1280)
>[ 15629.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9b70]
>[ 15629.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9b70] width 1280 pitch 5120 (/4 1280)
>[ 15629.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53db8]
>[ 15629.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53db8] width 1280 pitch 5120 (/4 1280)
>[ 15629.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9b70]
>[ 15629.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9b70] width 1280 pitch 5120 (/4 1280)
>[ 15630.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f288]
>[ 15630.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f288] width 1280 pitch 5120 (/4 1280)
>[ 15630.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f088]
>[ 15630.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f088] width 1280 pitch 5120 (/4 1280)
>[ 15630.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f288]
>[ 15630.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f288] width 1280 pitch 5120 (/4 1280)
>[ 15630.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00b110]
>[ 15630.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00b110] width 1280 pitch 5120 (/4 1280)
>[ 15630.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f088]
>[ 15630.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f088] width 1280 pitch 5120 (/4 1280)
>[ 15630.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77b88]
>[ 15630.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77b88] width 1280 pitch 5120 (/4 1280)
>[ 15630.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f088]
>[ 15630.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f088] width 1280 pitch 5120 (/4 1280)
>[ 15632.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0231b0]
>[ 15632.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0231b0] width 1280 pitch 5120 (/4 1280)
>[ 15632.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d2d8]
>[ 15633.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d2d8] width 1280 pitch 5120 (/4 1280)
>[ 15633.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0231b0]
>[ 15633.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0231b0] width 1280 pitch 5120 (/4 1280)
>[ 15633.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9a08]
>[ 15633.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9a08] width 1280 pitch 5120 (/4 1280)
>[ 15633.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0231b0]
>[ 15633.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0231b0] width 1280 pitch 5120 (/4 1280)
>[ 15633.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc40f0]
>[ 15633.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc40f0] width 1280 pitch 5120 (/4 1280)
>[ 15633.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76ff0]
>[ 15633.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76ff0] width 1280 pitch 5120 (/4 1280)
>[ 15633.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cc40f0]
>[ 15633.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cc40f0] width 1280 pitch 5120 (/4 1280)
>[ 15633.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c99f8]
>[ 15633.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c99f8] width 1280 pitch 5120 (/4 1280)
>[ 15640.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95ab8]
>[ 15640.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95ab8] width 1280 pitch 5120 (/4 1280)
>[ 15641.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dda990]
>[ 15641.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dda990] width 1280 pitch 5120 (/4 1280)
>[ 15641.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95ab8]
>[ 15641.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95ab8] width 1280 pitch 5120 (/4 1280)
>[ 15641.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dda990]
>[ 15641.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dda990] width 1280 pitch 5120 (/4 1280)
>[ 15641.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d2a8]
>[ 15641.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d2a8] width 1280 pitch 5120 (/4 1280)
>[ 15641.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa025a50]
>[ 15641.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa025a50] width 1280 pitch 5120 (/4 1280)
>[ 15641.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95ab8]
>[ 15641.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95ab8] width 1280 pitch 5120 (/4 1280)
>[ 15641.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6ec70]
>[ 15641.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6ec70] width 1280 pitch 5120 (/4 1280)
>[ 15641.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e95ab8]
>[ 15641.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e95ab8] width 1280 pitch 5120 (/4 1280)
>[ 15646.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36bd8]
>[ 15646.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36bd8] width 1280 pitch 5120 (/4 1280)
>[ 15646.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa087218]
>[ 15646.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa087218] width 1280 pitch 5120 (/4 1280)
>[ 15646.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d578]
>[ 15646.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d578] width 1280 pitch 5120 (/4 1280)
>[ 15646.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e637a0]
>[ 15646.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e637a0] width 1280 pitch 5120 (/4 1280)
>[ 15646.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d578]
>[ 15646.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d578] width 1280 pitch 5120 (/4 1280)
>[ 15646.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f852d8]
>[ 15646.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f852d8] width 1280 pitch 5120 (/4 1280)
>[ 15646.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76c10]
>[ 15646.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76c10] width 1280 pitch 5120 (/4 1280)
>[ 15646.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e76ff0]
>[ 15646.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e76ff0] width 1280 pitch 5120 (/4 1280)
>[ 15646.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d4e8]
>[ 15646.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d4e8] width 1280 pitch 5120 (/4 1280)
>[ 15657.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec8058]
>[ 15657.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec8058] width 1280 pitch 5120 (/4 1280)
>[ 15657.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cfc68]
>[ 15657.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cfc68] width 1280 pitch 5120 (/4 1280)
>[ 15657.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec8058]
>[ 15657.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec8058] width 1280 pitch 5120 (/4 1280)
>[ 15657.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cfc68]
>[ 15657.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cfc68] width 1280 pitch 5120 (/4 1280)
>[ 15657.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0f9b8]
>[ 15657.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0f9b8] width 1280 pitch 5120 (/4 1280)
>[ 15657.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037a58]
>[ 15657.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037a58] width 1280 pitch 5120 (/4 1280)
>[ 15657.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0f9b8]
>[ 15657.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0f9b8] width 1280 pitch 5120 (/4 1280)
>[ 15671.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e775b0]
>[ 15671.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e775b0] width 1280 pitch 5120 (/4 1280)
>[ 15682.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15682.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15682.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d36de8]
>[ 15682.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d36de8] width 1280 pitch 5120 (/4 1280)
>[ 15682.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15682.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15682.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca9540]
>[ 15682.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca9540] width 1280 pitch 5120 (/4 1280)
>[ 15687.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037a58]
>[ 15687.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037a58] width 1280 pitch 5120 (/4 1280)
>[ 15689.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa028908]
>[ 15689.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa028908] width 1280 pitch 5120 (/4 1280)
>[ 15689.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cb560]
>[ 15689.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cb560] width 1280 pitch 5120 (/4 1280)
>[ 15689.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ba58]
>[ 15689.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ba58] width 1280 pitch 5120 (/4 1280)
>[ 15689.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec58c8]
>[ 15689.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec58c8] width 1280 pitch 5120 (/4 1280)
>[ 15689.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa087238]
>[ 15689.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa087238] width 1280 pitch 5120 (/4 1280)
>[ 15689.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cb560]
>[ 15689.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cb560] width 1280 pitch 5120 (/4 1280)
>[ 15689.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec58c8]
>[ 15689.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec58c8] width 1280 pitch 5120 (/4 1280)
>[ 15756.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa029370]
>[ 15756.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa029370] width 1280 pitch 5120 (/4 1280)
>[ 15756.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bba0]
>[ 15756.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bba0] width 1280 pitch 5120 (/4 1280)
>[ 15756.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa029370]
>[ 15756.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa029370] width 1280 pitch 5120 (/4 1280)
>[ 15756.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bba0]
>[ 15756.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bba0] width 1280 pitch 5120 (/4 1280)
>[ 15756.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44ed0]
>[ 15756.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44ed0] width 1280 pitch 5120 (/4 1280)
>[ 15756.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15756.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15756.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44ed0]
>[ 15756.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44ed0] width 1280 pitch 5120 (/4 1280)
>[ 15756.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e560b8]
>[ 15756.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e560b8] width 1280 pitch 5120 (/4 1280)
>[ 15756.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44ed0]
>[ 15756.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44ed0] width 1280 pitch 5120 (/4 1280)
>[ 15764.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e575c0]
>[ 15764.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e575c0] width 1280 pitch 5120 (/4 1280)
>[ 15764.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03bff8]
>[ 15764.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03bff8] width 1280 pitch 5120 (/4 1280)
>[ 15764.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cf050]
>[ 15765.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cf050] width 1280 pitch 5120 (/4 1280)
>[ 15765.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03bff8]
>[ 15765.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03bff8] width 1280 pitch 5120 (/4 1280)
>[ 15765.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00c4f0]
>[ 15765.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00c4f0] width 1280 pitch 5120 (/4 1280)
>[ 15765.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037cb8]
>[ 15765.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037cb8] width 1280 pitch 5120 (/4 1280)
>[ 15765.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff1678]
>[ 15765.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff1678] width 1280 pitch 5120 (/4 1280)
>[ 15765.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03a990]
>[ 15765.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03a990] width 1280 pitch 5120 (/4 1280)
>[ 15768.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bb70]
>[ 15769.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bb70] width 1280 pitch 5120 (/4 1280)
>[ 15769.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44f30]
>[ 15769.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44f30] width 1280 pitch 5120 (/4 1280)
>[ 15769.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bb70]
>[ 15769.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bb70] width 1280 pitch 5120 (/4 1280)
>[ 15769.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9a08]
>[ 15769.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9a08] width 1280 pitch 5120 (/4 1280)
>[ 15769.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037dd0]
>[ 15769.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037dd0] width 1280 pitch 5120 (/4 1280)
>[ 15769.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c9a08]
>[ 15769.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c9a08] width 1280 pitch 5120 (/4 1280)
>[ 15769.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6d990]
>[ 15769.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6d990] width 1280 pitch 5120 (/4 1280)
>[ 15777.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cbb018]
>[ 15777.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cbb018] width 1280 pitch 5120 (/4 1280)
>[ 15779.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01afb0]
>[ 15779.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01afb0] width 1280 pitch 5120 (/4 1280)
>[ 15779.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7db48]
>[ 15779.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7db48] width 1280 pitch 5120 (/4 1280)
>[ 15779.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01be00]
>[ 15779.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01be00] width 1280 pitch 5120 (/4 1280)
>[ 15779.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01be00]
>[ 15779.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01be00] width 1280 pitch 5120 (/4 1280)
>[ 15779.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01dc58]
>[ 15779.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01dc58] width 1280 pitch 5120 (/4 1280)
>[ 15789.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff2768]
>[ 15789.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff2768] width 1280 pitch 5120 (/4 1280)
>[ 15789.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bb70]
>[ 15789.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bb70] width 1280 pitch 5120 (/4 1280)
>[ 15789.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff2768]
>[ 15789.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff2768] width 1280 pitch 5120 (/4 1280)
>[ 15789.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44f30]
>[ 15790.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44f30] width 1280 pitch 5120 (/4 1280)
>[ 15790.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e44f30]
>[ 15790.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e44f30] width 1280 pitch 5120 (/4 1280)
>[ 15807.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e451b0]
>[ 15807.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e451b0] width 1280 pitch 5120 (/4 1280)
>[ 15811.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa090f18]
>[ 15811.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa090f18] width 1280 pitch 5120 (/4 1280)
>[ 15811.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca0e80]
>[ 15811.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca0e80] width 1280 pitch 5120 (/4 1280)
>[ 15811.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa090f18]
>[ 15811.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa090f18] width 1280 pitch 5120 (/4 1280)
>[ 15817.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa024e48]
>[ 15817.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa024e48] width 1280 pitch 5120 (/4 1280)
>[ 15826.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6b10]
>[ 15826.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6b10] width 1280 pitch 5120 (/4 1280)
>[ 15826.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6b10]
>[ 15826.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6b10] width 1280 pitch 5120 (/4 1280)
>[ 15826.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb12b0]
>[ 15826.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb12b0] width 1280 pitch 5120 (/4 1280)
>[ 15826.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6b10]
>[ 15826.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6b10] width 1280 pitch 5120 (/4 1280)
>[ 15828.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f298]
>[ 15828.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f298] width 1280 pitch 5120 (/4 1280)
>[ 15829.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3a3d8]
>[ 15829.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3a3d8] width 1280 pitch 5120 (/4 1280)
>[ 15829.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77a28]
>[ 15829.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77a28] width 1280 pitch 5120 (/4 1280)
>[ 15830.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e77a28]
>[ 15830.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e77a28] width 1280 pitch 5120 (/4 1280)
>[ 16548.682] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 16548.716] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 16548.716] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 16638.829] (II) RADEON(0): RADEONSaveScreen(2)
>[ 16638.838] (II) RADEON(0): RADEONSaveScreen(0)
>[ 17141.664] (II) RADEON(0): RADEONSaveScreen(1)
>[ 17152.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0279d8]
>[ 17152.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0279d8] width 1280 pitch 5120 (/4 1280)
>[ 17257.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b5e3b8]
>[ 17257.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b5e3b8] width 1280 pitch 5120 (/4 1280)
>[ 17263.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b917b0]
>[ 17263.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b917b0] width 1280 pitch 5120 (/4 1280)
>[ 17264.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30f68]
>[ 17264.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30f68] width 1280 pitch 5120 (/4 1280)
>[ 17264.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30d28]
>[ 17264.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30d28] width 1280 pitch 5120 (/4 1280)
>[ 17264.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30f68]
>[ 17264.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30f68] width 1280 pitch 5120 (/4 1280)
>[ 17264.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30d28]
>[ 17264.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30d28] width 1280 pitch 5120 (/4 1280)
>[ 17270.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17270.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17270.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17270.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17270.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17270.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65950]
>[ 17270.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65950] width 1280 pitch 5120 (/4 1280)
>[ 17270.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c9ad48]
>[ 17270.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c9ad48] width 1280 pitch 5120 (/4 1280)
>[ 17276.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17276.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17276.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8c328]
>[ 17276.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8c328] width 1280 pitch 5120 (/4 1280)
>[ 17276.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17276.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17276.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8c328]
>[ 17276.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8c328] width 1280 pitch 5120 (/4 1280)
>[ 17276.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e36148]
>[ 17276.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e36148] width 1280 pitch 5120 (/4 1280)
>[ 17277.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e8c328]
>[ 17277.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e8c328] width 1280 pitch 5120 (/4 1280)
>[ 17278.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17278.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17278.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17278.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17279.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17279.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17279.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17279.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17280.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17281.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17281.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17281.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17281.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17281.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17281.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17281.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17281.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17281.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 17281.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 17281.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5b0a8]
>[ 17281.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5b0a8] width 1280 pitch 5120 (/4 1280)
>[ 17282.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 17282.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 17282.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd6440]
>[ 17282.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd6440] width 1280 pitch 5120 (/4 1280)
>[ 17282.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17282.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17282.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd6440]
>[ 17282.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd6440] width 1280 pitch 5120 (/4 1280)
>[ 17282.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17282.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17282.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd6440]
>[ 17282.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd6440] width 1280 pitch 5120 (/4 1280)
>[ 17282.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7d5e8]
>[ 17282.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7d5e8] width 1280 pitch 5120 (/4 1280)
>[ 17282.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd6440]
>[ 17282.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd6440] width 1280 pitch 5120 (/4 1280)
>[ 17285.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17285.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17285.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17285.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17285.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d273a0]
>[ 17285.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d273a0] width 1280 pitch 5120 (/4 1280)
>[ 17285.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d273a0]
>[ 17285.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d273a0] width 1280 pitch 5120 (/4 1280)
>[ 17285.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d273a0]
>[ 17285.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d273a0] width 1280 pitch 5120 (/4 1280)
>[ 17285.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d273a0]
>[ 17285.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d273a0] width 1280 pitch 5120 (/4 1280)
>[ 17285.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17285.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d273a0]
>[ 17285.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d273a0] width 1280 pitch 5120 (/4 1280)
>[ 17285.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed1660]
>[ 17285.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed1660] width 1280 pitch 5120 (/4 1280)
>[ 17288.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f9e0]
>[ 17288.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f9e0] width 1280 pitch 5120 (/4 1280)
>[ 17289.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17289.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17289.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f9e0]
>[ 17289.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f9e0] width 1280 pitch 5120 (/4 1280)
>[ 17289.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17289.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17289.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6f9e0]
>[ 17289.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6f9e0] width 1280 pitch 5120 (/4 1280)
>[ 17289.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17289.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17289.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17289.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17289.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17289.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17289.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17289.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17289.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17290.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17290.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17290.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17290.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17290.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17290.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17290.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17290.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17290.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17290.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17290.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17355.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17355.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17355.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17355.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17355.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17355.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17357.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17357.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17357.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17357.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17357.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17357.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17357.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17357.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17357.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17357.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17357.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17357.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17357.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17357.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17357.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17357.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17358.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17358.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17358.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17358.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17358.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17358.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17358.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17358.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17358.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17358.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17358.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17359.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17359.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17359.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17359.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17359.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17359.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17359.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17359.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17359.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17359.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17359.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17359.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17359.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 17359.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 17359.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x99f7388]
>[ 17359.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x99f7388] width 1280 pitch 5120 (/4 1280)
>[ 17360.723] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 17360.741] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 17360.747] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 17367.006] (II) AIGLX: Suspending AIGLX clients for VT switch
>[ 17367.006] (II) RADEON(0): RADEONLeaveVT_KMS
>[ 17367.006] (II) RADEON(0): Ok, leaving now...
>[ 17373.345] (II) AIGLX: Resuming AIGLX clients after VT switch
>[ 17373.481] (II) RADEON(0): RADEONEnterVT_KMS
>[ 17373.576] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 17373.576] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 17373.576] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 17373.607] (II) RADEON(0): RADEONSaveScreen(2)
>[ 17374.303] (**) Option "Device" "/dev/input/event4"
>[ 17374.303] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[ 17374.303] (EE) evdev: HID 1267:0103: Unable to open evdev device "/dev/input/event11".
>[ 17374.486] [dix] couldn't enable device 14
>[ 17374.486] (EE) evdev: HID 1267:0103: Unable to open evdev device "/dev/input/event10".
>[ 17374.486] [dix] couldn't enable device 15
>[ 17374.487] (II) config/udev: removing device HID 1267:0103
>[ 17374.487] (II) evdev: HID 1267:0103: Close
>[ 17374.556] (II) UnloadModule: "evdev"
>[ 17374.558] (II) config/udev: removing device HID 1267:0103
>[ 17374.559] (II) evdev: HID 1267:0103: Close
>[ 17374.559] (II) UnloadModule: "evdev"
>[ 17422.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 17422.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 17441.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebec28]
>[ 17441.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebec28] width 1280 pitch 5120 (/4 1280)
>[ 17442.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 17442.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 17442.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebec28]
>[ 17442.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebec28] width 1280 pitch 5120 (/4 1280)
>[ 17442.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddbf70]
>[ 17442.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddbf70] width 1280 pitch 5120 (/4 1280)
>[ 17442.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebec28]
>[ 17442.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebec28] width 1280 pitch 5120 (/4 1280)
>[ 17442.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddbf70]
>[ 17442.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddbf70] width 1280 pitch 5120 (/4 1280)
>[ 17442.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebec28]
>[ 17442.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebec28] width 1280 pitch 5120 (/4 1280)
>[ 17443.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddbf70]
>[ 17443.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddbf70] width 1280 pitch 5120 (/4 1280)
>[ 17445.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebec28]
>[ 17445.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebec28] width 1280 pitch 5120 (/4 1280)
>[ 17445.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22128]
>[ 17445.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22128] width 1280 pitch 5120 (/4 1280)
>[ 17445.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 17445.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 17445.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22128]
>[ 17445.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22128] width 1280 pitch 5120 (/4 1280)
>[ 17445.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a7e0]
>[ 17445.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a7e0] width 1280 pitch 5120 (/4 1280)
>[ 17445.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22128]
>[ 17445.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22128] width 1280 pitch 5120 (/4 1280)
>[ 17445.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4fba0]
>[ 17445.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4fba0] width 1280 pitch 5120 (/4 1280)
>[ 17457.133] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event11)
>[ 17457.133] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[ 17457.133] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[ 17457.133] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[ 17457.133] 	Option "XkbRules" "evdev"
>[ 17457.133] 	Option "XkbModel" "pc105+inet"
>[ 17457.133] 	Option "XkbLayout" "us"
>[ 17457.133] 	Option "_source" "server/udev"
>[ 17457.133] 	Option "name" "HID 1267:0103"
>[ 17457.133] 	Option "path" "/dev/input/event11"
>[ 17457.133] 	Option "device" "/dev/input/event11"
>[ 17457.133] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input16/event11"
>[ 17457.133] 	Option "driver" "evdev"
>[ 17457.133] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[ 17457.133] (**) HID 1267:0103: always reports core events
>[ 17457.134] (**) evdev: HID 1267:0103: Device: "/dev/input/event11"
>[ 17457.134] (--) evdev: HID 1267:0103: absolute axis 0x20 [572..0]
>[ 17457.134] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[ 17457.134] (--) evdev: HID 1267:0103: Found 1 mouse buttons
>[ 17457.134] (--) evdev: HID 1267:0103: Found scroll wheel(s)
>[ 17457.134] (--) evdev: HID 1267:0103: Found relative axes
>[ 17457.134] (II) evdev: HID 1267:0103: Forcing relative x/y axes to exist.
>[ 17457.134] (--) evdev: HID 1267:0103: Found absolute axes
>[ 17457.134] (II) evdev: HID 1267:0103: Forcing absolute x/y axes to exist.
>[ 17457.134] (--) evdev: HID 1267:0103: Found keys
>[ 17457.134] (II) evdev: HID 1267:0103: Configuring as mouse
>[ 17457.134] (II) evdev: HID 1267:0103: Configuring as keyboard
>[ 17457.134] (II) evdev: HID 1267:0103: Adding scrollwheel support
>[ 17457.134] (**) evdev: HID 1267:0103: YAxisMapping: buttons 4 and 5
>[ 17457.134] (**) evdev: HID 1267:0103: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[ 17457.134] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.1/input/input16/event11"
>[ 17457.134] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 14)
>[ 17457.134] (**) Option "xkb_rules" "evdev"
>[ 17457.134] (**) Option "xkb_model" "pc105+inet"
>[ 17457.134] (**) Option "xkb_layout" "us"
>[ 17457.134] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[ 17457.134] (II) XKB: Reusing cached keymap
>[ 17457.134] (II) evdev: HID 1267:0103: initialized for relative axes.
>[ 17457.134] (WW) evdev: HID 1267:0103: ignoring absolute axes.
>[ 17457.135] (**) HID 1267:0103: (accel) keeping acceleration scheme 1
>[ 17457.135] (**) HID 1267:0103: (accel) acceleration profile 0
>[ 17457.135] (**) HID 1267:0103: (accel) acceleration factor: 2.000
>[ 17457.135] (**) HID 1267:0103: (accel) acceleration threshold: 4
>[ 17457.168] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event10)
>[ 17457.168] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[ 17457.168] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[ 17457.168] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[ 17457.168] 	Option "XkbRules" "evdev"
>[ 17457.168] 	Option "XkbModel" "pc105+inet"
>[ 17457.168] 	Option "XkbLayout" "us"
>[ 17457.168] 	Option "_source" "server/udev"
>[ 17457.168] 	Option "name" "HID 1267:0103"
>[ 17457.168] 	Option "path" "/dev/input/event10"
>[ 17457.168] 	Option "device" "/dev/input/event10"
>[ 17457.168] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input15/event10"
>[ 17457.168] 	Option "driver" "evdev"
>[ 17457.169] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[ 17457.169] (**) HID 1267:0103: always reports core events
>[ 17457.169] (**) evdev: HID 1267:0103: Device: "/dev/input/event10"
>[ 17457.169] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[ 17457.169] (--) evdev: HID 1267:0103: Found keys
>[ 17457.169] (II) evdev: HID 1267:0103: Configuring as keyboard
>[ 17457.169] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.7/usb1/1-7/1-7.2/1-7.2:1.0/input/input15/event10"
>[ 17457.169] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 15)
>[ 17457.169] (**) Option "xkb_rules" "evdev"
>[ 17457.169] (**) Option "xkb_model" "pc105+inet"
>[ 17457.169] (**) Option "xkb_layout" "us"
>[ 17457.169] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[ 17457.169] (II) XKB: Reusing cached keymap
>[ 17473.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e668]
>[ 17473.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e668] width 1280 pitch 5120 (/4 1280)
>[ 17473.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e1c0]
>[ 17473.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e1c0] width 1280 pitch 5120 (/4 1280)
>[ 17473.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17474.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17474.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17474.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17474.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17474.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17474.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17474.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17474.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17474.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17474.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17474.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17474.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17474.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17475.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17475.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17475.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17475.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17476.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17476.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17477.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcc398]
>[ 17477.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcc398] width 1280 pitch 5120 (/4 1280)
>[ 17477.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e1c0]
>[ 17477.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e1c0] width 1280 pitch 5120 (/4 1280)
>[ 17477.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17477.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17480.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e1c0]
>[ 17480.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e1c0] width 1280 pitch 5120 (/4 1280)
>[ 17480.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d00650]
>[ 17480.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d00650] width 1280 pitch 5120 (/4 1280)
>[ 17498.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4ea38]
>[ 17498.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4ea38] width 1280 pitch 5120 (/4 1280)
>[ 17498.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dea1f0]
>[ 17498.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dea1f0] width 1280 pitch 5120 (/4 1280)
>[ 17499.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc58e8]
>[ 17499.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc58e8] width 1280 pitch 5120 (/4 1280)
>[ 17500.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96f28]
>[ 17500.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96f28] width 1280 pitch 5120 (/4 1280)
>[ 17505.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0d790]
>[ 17505.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0d790] width 1280 pitch 5120 (/4 1280)
>[ 17505.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d378]
>[ 17505.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d378] width 1280 pitch 5120 (/4 1280)
>[ 17505.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0d790]
>[ 17505.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0d790] width 1280 pitch 5120 (/4 1280)
>[ 17505.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d378]
>[ 17505.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d378] width 1280 pitch 5120 (/4 1280)
>[ 17505.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0d790]
>[ 17505.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0d790] width 1280 pitch 5120 (/4 1280)
>[ 17505.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d378]
>[ 17505.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d378] width 1280 pitch 5120 (/4 1280)
>[ 17505.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0d790]
>[ 17505.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0d790] width 1280 pitch 5120 (/4 1280)
>[ 17505.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d378]
>[ 17505.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d378] width 1280 pitch 5120 (/4 1280)
>[ 17505.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c0d790]
>[ 17505.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c0d790] width 1280 pitch 5120 (/4 1280)
>[ 17505.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4d378]
>[ 17505.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4d378] width 1280 pitch 5120 (/4 1280)
>[ 17507.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c86800]
>[ 17507.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c86800] width 1280 pitch 5120 (/4 1280)
>[ 17507.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e993e0]
>[ 17507.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e993e0] width 1280 pitch 5120 (/4 1280)
>[ 17510.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c97280]
>[ 17510.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c97280] width 1280 pitch 5120 (/4 1280)
>[ 17510.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 17510.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 17510.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a218]
>[ 17510.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a218] width 1280 pitch 5120 (/4 1280)
>[ 17510.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 17510.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 17510.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a218]
>[ 17510.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a218] width 1280 pitch 5120 (/4 1280)
>[ 17510.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 17510.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 17511.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a218]
>[ 17511.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a218] width 1280 pitch 5120 (/4 1280)
>[ 17522.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 17522.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 17523.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7a218]
>[ 17523.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7a218] width 1280 pitch 5120 (/4 1280)
>[ 17523.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 17523.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 17523.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 17523.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 17523.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 17523.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 17523.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 17523.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 17523.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30e20]
>[ 17523.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30e20] width 1280 pitch 5120 (/4 1280)
>[ 17761.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e800e8]
>[ 17761.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e800e8] width 1280 pitch 5120 (/4 1280)
>[ 17762.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea9620]
>[ 17762.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea9620] width 1280 pitch 5120 (/4 1280)
>[ 17762.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed2028]
>[ 17762.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed2028] width 1280 pitch 5120 (/4 1280)
>[ 17763.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38de8]
>[ 17763.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38de8] width 1280 pitch 5120 (/4 1280)
>[ 17764.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e800e8]
>[ 17764.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e800e8] width 1280 pitch 5120 (/4 1280)
>[ 17764.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e800e8]
>[ 17764.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e800e8] width 1280 pitch 5120 (/4 1280)
>[ 17764.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e800e8]
>[ 17764.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e800e8] width 1280 pitch 5120 (/4 1280)
>[ 17770.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e50920]
>[ 17770.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e50920] width 1280 pitch 5120 (/4 1280)
>[ 17770.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0cc38]
>[ 17770.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0cc38] width 1280 pitch 5120 (/4 1280)
>[ 17775.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6160]
>[ 17775.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6160] width 1280 pitch 5120 (/4 1280)
>[ 17775.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d452b8]
>[ 17775.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d452b8] width 1280 pitch 5120 (/4 1280)
>[ 17775.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea6160]
>[ 17775.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea6160] width 1280 pitch 5120 (/4 1280)
>[ 17775.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d452b8]
>[ 17775.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d452b8] width 1280 pitch 5120 (/4 1280)
>[ 17788.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66ef0]
>[ 17788.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66ef0] width 1280 pitch 5120 (/4 1280)
>[ 17788.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17788.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17789.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66ef0]
>[ 17789.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66ef0] width 1280 pitch 5120 (/4 1280)
>[ 17790.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17790.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17790.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecaf20]
>[ 17790.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecaf20] width 1280 pitch 5120 (/4 1280)
>[ 17790.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17790.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17791.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17791.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17791.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66ef0]
>[ 17791.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66ef0] width 1280 pitch 5120 (/4 1280)
>[ 17791.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbee90]
>[ 17791.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbee90] width 1280 pitch 5120 (/4 1280)
>[ 17791.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17791.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17791.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbee90]
>[ 17791.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbee90] width 1280 pitch 5120 (/4 1280)
>[ 17792.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17792.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17793.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17793.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17793.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66ef0]
>[ 17793.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66ef0] width 1280 pitch 5120 (/4 1280)
>[ 17793.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17793.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17793.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66ef0]
>[ 17793.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66ef0] width 1280 pitch 5120 (/4 1280)
>[ 17793.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e93658]
>[ 17794.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e93658] width 1280 pitch 5120 (/4 1280)
>[ 17794.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecaf20]
>[ 17794.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecaf20] width 1280 pitch 5120 (/4 1280)
>[ 17794.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbee90]
>[ 17794.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbee90] width 1280 pitch 5120 (/4 1280)
>[ 17800.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ba0210]
>[ 17800.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ba0210] width 1280 pitch 5120 (/4 1280)
>[ 17800.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7238]
>[ 17800.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7238] width 1280 pitch 5120 (/4 1280)
>[ 17986.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66c50]
>[ 17986.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66c50] width 1280 pitch 5120 (/4 1280)
>[ 17986.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcfe28]
>[ 17986.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcfe28] width 1280 pitch 5120 (/4 1280)
>[ 17986.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72b68]
>[ 17986.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72b68] width 1280 pitch 5120 (/4 1280)
>[ 17986.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6fbf0]
>[ 17986.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6fbf0] width 1280 pitch 5120 (/4 1280)
>[ 17986.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66c50]
>[ 17986.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66c50] width 1280 pitch 5120 (/4 1280)
>[ 17986.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e63720]
>[ 17986.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e63720] width 1280 pitch 5120 (/4 1280)
>[ 17986.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66c50]
>[ 17986.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66c50] width 1280 pitch 5120 (/4 1280)
>[ 17986.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b909d8]
>[ 17986.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b909d8] width 1280 pitch 5120 (/4 1280)
>[ 17986.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb8188]
>[ 17986.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb8188] width 1280 pitch 5120 (/4 1280)
>[ 17986.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c41c10]
>[ 17986.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c41c10] width 1280 pitch 5120 (/4 1280)
>[ 17986.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2fd28]
>[ 17986.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2fd28] width 1280 pitch 5120 (/4 1280)
>[ 17987.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcfe28]
>[ 17987.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcfe28] width 1280 pitch 5120 (/4 1280)
>[ 17989.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89f20]
>[ 17989.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89f20] width 1280 pitch 5120 (/4 1280)
>[ 17990.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 17990.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 17998.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66c50]
>[ 17998.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66c50] width 1280 pitch 5120 (/4 1280)
>[ 18002.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e03ac0]
>[ 18002.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e03ac0] width 1280 pitch 5120 (/4 1280)
>[ 18003.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26c40]
>[ 18003.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26c40] width 1280 pitch 5120 (/4 1280)
>[ 18003.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d557d8]
>[ 18003.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d557d8] width 1280 pitch 5120 (/4 1280)
>[ 18004.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2fd28]
>[ 18004.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2fd28] width 1280 pitch 5120 (/4 1280)
>[ 18004.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c41c10]
>[ 18004.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c41c10] width 1280 pitch 5120 (/4 1280)
>[ 18004.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 18004.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 18004.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e03ac0]
>[ 18004.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e03ac0] width 1280 pitch 5120 (/4 1280)
>[ 18004.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 18004.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 18005.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 18005.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 18005.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c41c10]
>[ 18005.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c41c10] width 1280 pitch 5120 (/4 1280)
>[ 18007.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 18007.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 18007.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb8188]
>[ 18007.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb8188] width 1280 pitch 5120 (/4 1280)
>[ 18007.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e57060]
>[ 18007.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e57060] width 1280 pitch 5120 (/4 1280)
>[ 18007.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bca0c0]
>[ 18007.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bca0c0] width 1280 pitch 5120 (/4 1280)
>[ 18007.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f665b0]
>[ 18007.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f665b0] width 1280 pitch 5120 (/4 1280)
>[ 18008.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b56470]
>[ 18008.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b56470] width 1280 pitch 5120 (/4 1280)
>[ 18008.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f665b0]
>[ 18008.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f665b0] width 1280 pitch 5120 (/4 1280)
>[ 18017.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18017.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18057.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f816c8]
>[ 18057.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f816c8] width 1280 pitch 5120 (/4 1280)
>[ 18057.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18057.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18057.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f816c8]
>[ 18057.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f816c8] width 1280 pitch 5120 (/4 1280)
>[ 18057.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18057.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18057.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff8d0]
>[ 18057.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff8d0] width 1280 pitch 5120 (/4 1280)
>[ 18057.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18057.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18057.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff8d0]
>[ 18057.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff8d0] width 1280 pitch 5120 (/4 1280)
>[ 18057.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18057.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18057.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff8d0]
>[ 18057.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff8d0] width 1280 pitch 5120 (/4 1280)
>[ 18057.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18057.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18058.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18058.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18059.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18059.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18059.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b187d0]
>[ 18059.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b187d0] width 1280 pitch 5120 (/4 1280)
>[ 18059.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18059.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18059.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b187d0]
>[ 18059.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b187d0] width 1280 pitch 5120 (/4 1280)
>[ 18059.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18059.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18059.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18059.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18059.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18059.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18059.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18059.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18059.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ce4d8]
>[ 18059.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ce4d8] width 1280 pitch 5120 (/4 1280)
>[ 18059.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18059.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18060.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff8d0]
>[ 18060.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff8d0] width 1280 pitch 5120 (/4 1280)
>[ 18060.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18060.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18060.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff8d0]
>[ 18060.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff8d0] width 1280 pitch 5120 (/4 1280)
>[ 18060.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18060.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18060.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f816c8]
>[ 18060.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f816c8] width 1280 pitch 5120 (/4 1280)
>[ 18060.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18060.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18060.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f816c8]
>[ 18060.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f816c8] width 1280 pitch 5120 (/4 1280)
>[ 18060.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f668f0]
>[ 18060.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f668f0] width 1280 pitch 5120 (/4 1280)
>[ 18060.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f816c8]
>[ 18060.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f816c8] width 1280 pitch 5120 (/4 1280)
>[ 18092.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15e258]
>[ 18092.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15e258] width 1280 pitch 5120 (/4 1280)
>[ 18092.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18092.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18092.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6e8]
>[ 18092.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6e8] width 1280 pitch 5120 (/4 1280)
>[ 18092.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18092.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18092.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ed58]
>[ 18092.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ed58] width 1280 pitch 5120 (/4 1280)
>[ 18092.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18092.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18092.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ed58]
>[ 18092.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ed58] width 1280 pitch 5120 (/4 1280)
>[ 18092.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18092.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18093.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f548]
>[ 18093.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f548] width 1280 pitch 5120 (/4 1280)
>[ 18093.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18093.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f548]
>[ 18093.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f548] width 1280 pitch 5120 (/4 1280)
>[ 18093.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18093.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6e8]
>[ 18093.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6e8] width 1280 pitch 5120 (/4 1280)
>[ 18093.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18093.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6c9d0]
>[ 18093.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6c9d0] width 1280 pitch 5120 (/4 1280)
>[ 18093.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff6b8]
>[ 18093.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff6b8] width 1280 pitch 5120 (/4 1280)
>[ 18093.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6c9d0]
>[ 18093.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6c9d0] width 1280 pitch 5120 (/4 1280)
>[ 18093.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f548]
>[ 18093.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f548] width 1280 pitch 5120 (/4 1280)
>[ 18093.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6c9d0]
>[ 18093.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6c9d0] width 1280 pitch 5120 (/4 1280)
>[ 18093.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f548]
>[ 18093.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f548] width 1280 pitch 5120 (/4 1280)
>[ 18093.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15e0a8]
>[ 18093.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15e0a8] width 1280 pitch 5120 (/4 1280)
>[ 18100.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f43468]
>[ 18100.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f43468] width 1280 pitch 5120 (/4 1280)
>[ 18100.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45b70]
>[ 18100.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45b70] width 1280 pitch 5120 (/4 1280)
>[ 18100.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f46330]
>[ 18100.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f46330] width 1280 pitch 5120 (/4 1280)
>[ 18100.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f468b8]
>[ 18100.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f468b8] width 1280 pitch 5120 (/4 1280)
>[ 18100.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecd0e8]
>[ 18100.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecd0e8] width 1280 pitch 5120 (/4 1280)
>[ 18100.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18100.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18100.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecd0e8]
>[ 18100.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecd0e8] width 1280 pitch 5120 (/4 1280)
>[ 18100.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18100.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18100.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f46330]
>[ 18100.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f46330] width 1280 pitch 5120 (/4 1280)
>[ 18100.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45b70]
>[ 18100.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45b70] width 1280 pitch 5120 (/4 1280)
>[ 18100.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecd0e8]
>[ 18100.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecd0e8] width 1280 pitch 5120 (/4 1280)
>[ 18100.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18100.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18100.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecd0e8]
>[ 18101.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecd0e8] width 1280 pitch 5120 (/4 1280)
>[ 18101.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18101.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18101.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecd0e8]
>[ 18101.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecd0e8] width 1280 pitch 5120 (/4 1280)
>[ 18101.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18101.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18116.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18116.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18116.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2e898]
>[ 18116.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2e898] width 1280 pitch 5120 (/4 1280)
>[ 18116.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f698]
>[ 18116.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f698] width 1280 pitch 5120 (/4 1280)
>[ 18116.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15f668]
>[ 18116.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15f668] width 1280 pitch 5120 (/4 1280)
>[ 18116.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45b90]
>[ 18116.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45b90] width 1280 pitch 5120 (/4 1280)
>[ 18116.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2e898]
>[ 18116.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2e898] width 1280 pitch 5120 (/4 1280)
>[ 18116.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2e898]
>[ 18116.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2e898] width 1280 pitch 5120 (/4 1280)
>[ 18116.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18116.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18116.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45b90]
>[ 18116.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45b90] width 1280 pitch 5120 (/4 1280)
>[ 18116.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b562c8]
>[ 18116.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b562c8] width 1280 pitch 5120 (/4 1280)
>[ 18116.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45b90]
>[ 18116.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45b90] width 1280 pitch 5120 (/4 1280)
>[ 18116.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2e898]
>[ 18116.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2e898] width 1280 pitch 5120 (/4 1280)
>[ 18116.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18116.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18116.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18116.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18116.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b562c8]
>[ 18116.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b562c8] width 1280 pitch 5120 (/4 1280)
>[ 18117.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18117.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18123.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eccf28]
>[ 18123.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eccf28] width 1280 pitch 5120 (/4 1280)
>[ 18126.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94450]
>[ 18126.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94450] width 1280 pitch 5120 (/4 1280)
>[ 18132.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ccbe8]
>[ 18132.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ccbe8] width 1280 pitch 5120 (/4 1280)
>[ 18132.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18133.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18133.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18133.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18133.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18133.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18138.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d4a0]
>[ 18138.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d4a0] width 1280 pitch 5120 (/4 1280)
>[ 18141.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0897a8]
>[ 18141.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0897a8] width 1280 pitch 5120 (/4 1280)
>[ 18141.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa088680]
>[ 18141.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa088680] width 1280 pitch 5120 (/4 1280)
>[ 18141.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08be88]
>[ 18141.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08be88] width 1280 pitch 5120 (/4 1280)
>[ 18141.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0886f8]
>[ 18141.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0886f8] width 1280 pitch 5120 (/4 1280)
>[ 18141.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08be88]
>[ 18141.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08be88] width 1280 pitch 5120 (/4 1280)
>[ 18141.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa010128]
>[ 18141.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa010128] width 1280 pitch 5120 (/4 1280)
>[ 18141.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08c288]
>[ 18142.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08c288] width 1280 pitch 5120 (/4 1280)
>[ 18142.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa010128]
>[ 18142.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa010128] width 1280 pitch 5120 (/4 1280)
>[ 18144.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0884b0]
>[ 18144.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0884b0] width 1280 pitch 5120 (/4 1280)
>[ 18162.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d557d8]
>[ 18162.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d557d8] width 1280 pitch 5120 (/4 1280)
>[ 18162.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c41c10]
>[ 18162.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c41c10] width 1280 pitch 5120 (/4 1280)
>[ 18162.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e03ac0]
>[ 18162.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e03ac0] width 1280 pitch 5120 (/4 1280)
>[ 18162.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1758]
>[ 18162.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1758] width 1280 pitch 5120 (/4 1280)
>[ 18162.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa09fd60]
>[ 18162.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa09fd60] width 1280 pitch 5120 (/4 1280)
>[ 18162.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f66e00]
>[ 18162.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f66e00] width 1280 pitch 5120 (/4 1280)
>[ 18164.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18164.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18164.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1728]
>[ 18164.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1728] width 1280 pitch 5120 (/4 1280)
>[ 18164.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2d9e8]
>[ 18164.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2d9e8] width 1280 pitch 5120 (/4 1280)
>[ 18164.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0101f8]
>[ 18164.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0101f8] width 1280 pitch 5120 (/4 1280)
>[ 18164.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18164.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18164.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1728]
>[ 18164.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1728] width 1280 pitch 5120 (/4 1280)
>[ 18164.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18164.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18164.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1728]
>[ 18164.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1728] width 1280 pitch 5120 (/4 1280)
>[ 18165.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18166.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18166.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc1de0]
>[ 18166.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc1de0] width 1280 pitch 5120 (/4 1280)
>[ 18166.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1728]
>[ 18166.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1728] width 1280 pitch 5120 (/4 1280)
>[ 18166.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc1de0]
>[ 18166.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc1de0] width 1280 pitch 5120 (/4 1280)
>[ 18166.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c1728]
>[ 18166.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c1728] width 1280 pitch 5120 (/4 1280)
>[ 18174.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d68bb0]
>[ 18174.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d68bb0] width 1280 pitch 5120 (/4 1280)
>[ 18174.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c27f60]
>[ 18174.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c27f60] width 1280 pitch 5120 (/4 1280)
>[ 18174.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc1de0]
>[ 18174.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc1de0] width 1280 pitch 5120 (/4 1280)
>[ 18174.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc1de0]
>[ 18174.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc1de0] width 1280 pitch 5120 (/4 1280)
>[ 18175.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b784b8]
>[ 18175.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b784b8] width 1280 pitch 5120 (/4 1280)
>[ 18175.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f264e0]
>[ 18175.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f264e0] width 1280 pitch 5120 (/4 1280)
>[ 18176.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b784b8]
>[ 18176.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b784b8] width 1280 pitch 5120 (/4 1280)
>[ 18177.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc4f28]
>[ 18177.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc4f28] width 1280 pitch 5120 (/4 1280)
>[ 18177.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f264e0]
>[ 18177.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f264e0] width 1280 pitch 5120 (/4 1280)
>[ 18177.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f31bb8]
>[ 18177.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f31bb8] width 1280 pitch 5120 (/4 1280)
>[ 18177.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa101a88]
>[ 18177.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa101a88] width 1280 pitch 5120 (/4 1280)
>[ 18177.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c514a0]
>[ 18177.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c514a0] width 1280 pitch 5120 (/4 1280)
>[ 18177.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18177.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18177.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c514a0]
>[ 18177.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c514a0] width 1280 pitch 5120 (/4 1280)
>[ 18177.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18177.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18178.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00c148]
>[ 18178.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00c148] width 1280 pitch 5120 (/4 1280)
>[ 18178.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa010490]
>[ 18178.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa010490] width 1280 pitch 5120 (/4 1280)
>[ 18178.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa09f748]
>[ 18178.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa09f748] width 1280 pitch 5120 (/4 1280)
>[ 18178.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18178.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18178.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18178.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18178.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1caf8]
>[ 18179.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1caf8] width 1280 pitch 5120 (/4 1280)
>[ 18179.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18179.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18198.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94420]
>[ 18198.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94420] width 1280 pitch 5120 (/4 1280)
>[ 18198.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa018100]
>[ 18198.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa018100] width 1280 pitch 5120 (/4 1280)
>[ 18199.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ebc0]
>[ 18199.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ebc0] width 1280 pitch 5120 (/4 1280)
>[ 18199.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18199.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18199.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b891b8]
>[ 18199.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b891b8] width 1280 pitch 5120 (/4 1280)
>[ 18199.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d49a8]
>[ 18199.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d49a8] width 1280 pitch 5120 (/4 1280)
>[ 18199.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18199.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18199.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d49a8]
>[ 18199.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d49a8] width 1280 pitch 5120 (/4 1280)
>[ 18199.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18199.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18199.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18199.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18199.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d49a8]
>[ 18199.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d49a8] width 1280 pitch 5120 (/4 1280)
>[ 18199.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d49a8]
>[ 18199.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d49a8] width 1280 pitch 5120 (/4 1280)
>[ 18199.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d57d8]
>[ 18199.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d57d8] width 1280 pitch 5120 (/4 1280)
>[ 18199.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18199.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18199.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18199.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18199.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18199.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18199.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18199.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcc820]
>[ 18203.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcc820] width 1280 pitch 5120 (/4 1280)
>[ 18203.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcc820]
>[ 18203.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcc820] width 1280 pitch 5120 (/4 1280)
>[ 18203.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fccb00]
>[ 18203.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fccb00] width 1280 pitch 5120 (/4 1280)
>[ 18203.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fccb00]
>[ 18203.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fccb00] width 1280 pitch 5120 (/4 1280)
>[ 18203.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fccb00]
>[ 18203.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fccb00] width 1280 pitch 5120 (/4 1280)
>[ 18203.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f50340]
>[ 18203.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f50340] width 1280 pitch 5120 (/4 1280)
>[ 18203.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f50340]
>[ 18203.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f50340] width 1280 pitch 5120 (/4 1280)
>[ 18203.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba118]
>[ 18203.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba118] width 1280 pitch 5120 (/4 1280)
>[ 18203.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fccb00]
>[ 18203.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fccb00] width 1280 pitch 5120 (/4 1280)
>[ 18207.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f50340]
>[ 18207.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f50340] width 1280 pitch 5120 (/4 1280)
>[ 18207.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f50340]
>[ 18207.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f50340] width 1280 pitch 5120 (/4 1280)
>[ 18207.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa09fb00]
>[ 18207.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa09fb00] width 1280 pitch 5120 (/4 1280)
>[ 18207.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18207.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18221.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89858]
>[ 18221.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89858] width 1280 pitch 5120 (/4 1280)
>[ 18221.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89858]
>[ 18221.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89858] width 1280 pitch 5120 (/4 1280)
>[ 18221.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89858]
>[ 18221.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89858] width 1280 pitch 5120 (/4 1280)
>[ 18221.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89858]
>[ 18221.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89858] width 1280 pitch 5120 (/4 1280)
>[ 18221.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89858]
>[ 18221.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89858] width 1280 pitch 5120 (/4 1280)
>[ 18221.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f636f0]
>[ 18221.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f636f0] width 1280 pitch 5120 (/4 1280)
>[ 18221.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18221.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f636f0]
>[ 18221.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f636f0] width 1280 pitch 5120 (/4 1280)
>[ 18221.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8130]
>[ 18221.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8130] width 1280 pitch 5120 (/4 1280)
>[ 18223.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f62530]
>[ 18223.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f62530] width 1280 pitch 5120 (/4 1280)
>[ 18223.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa012350]
>[ 18223.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa012350] width 1280 pitch 5120 (/4 1280)
>[ 18223.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f62530]
>[ 18223.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f62530] width 1280 pitch 5120 (/4 1280)
>[ 18223.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f62530]
>[ 18223.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f62530] width 1280 pitch 5120 (/4 1280)
>[ 18223.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18223.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18223.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7a6a8]
>[ 18223.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7a6a8] width 1280 pitch 5120 (/4 1280)
>[ 18223.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18223.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18223.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7a6a8]
>[ 18223.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7a6a8] width 1280 pitch 5120 (/4 1280)
>[ 18223.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18224.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18224.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7a6a8]
>[ 18224.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7a6a8] width 1280 pitch 5120 (/4 1280)
>[ 18224.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18224.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18224.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7a6a8]
>[ 18224.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7a6a8] width 1280 pitch 5120 (/4 1280)
>[ 18224.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18224.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18224.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f62530]
>[ 18224.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f62530] width 1280 pitch 5120 (/4 1280)
>[ 18224.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18224.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18224.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f62530]
>[ 18224.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f62530] width 1280 pitch 5120 (/4 1280)
>[ 18224.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bd718]
>[ 18224.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bd718] width 1280 pitch 5120 (/4 1280)
>[ 18225.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0be050]
>[ 18225.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0be050] width 1280 pitch 5120 (/4 1280)
>[ 18225.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18225.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18225.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0be050]
>[ 18225.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0be050] width 1280 pitch 5120 (/4 1280)
>[ 18225.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f65db8]
>[ 18225.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f65db8] width 1280 pitch 5120 (/4 1280)
>[ 18226.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8100]
>[ 18226.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8100] width 1280 pitch 5120 (/4 1280)
>[ 18226.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa010650]
>[ 18226.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa010650] width 1280 pitch 5120 (/4 1280)
>[ 18226.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f624c0]
>[ 18226.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f624c0] width 1280 pitch 5120 (/4 1280)
>[ 18227.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18228.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18228.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18228.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18228.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18229.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d570]
>[ 18229.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d570] width 1280 pitch 5120 (/4 1280)
>[ 18229.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c940c0]
>[ 18229.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c940c0] width 1280 pitch 5120 (/4 1280)
>[ 18229.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be16d0]
>[ 18229.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be16d0] width 1280 pitch 5120 (/4 1280)
>[ 18229.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7f70]
>[ 18229.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7f70] width 1280 pitch 5120 (/4 1280)
>[ 18236.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5d58]
>[ 18236.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5d58] width 1280 pitch 5120 (/4 1280)
>[ 18236.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03a4c8]
>[ 18236.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03a4c8] width 1280 pitch 5120 (/4 1280)
>[ 18237.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec7928]
>[ 18237.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec7928] width 1280 pitch 5120 (/4 1280)
>[ 18250.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f31300]
>[ 18250.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f31300] width 1280 pitch 5120 (/4 1280)
>[ 18303.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ed88]
>[ 18303.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ed88] width 1280 pitch 5120 (/4 1280)
>[ 18323.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ede8]
>[ 18323.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ede8] width 1280 pitch 5120 (/4 1280)
>[ 18324.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffb890]
>[ 18324.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffb890] width 1280 pitch 5120 (/4 1280)
>[ 18324.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5d58]
>[ 18324.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5d58] width 1280 pitch 5120 (/4 1280)
>[ 18324.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d298]
>[ 18324.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d298] width 1280 pitch 5120 (/4 1280)
>[ 18326.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5d58]
>[ 18326.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5d58] width 1280 pitch 5120 (/4 1280)
>[ 18326.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89168]
>[ 18326.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89168] width 1280 pitch 5120 (/4 1280)
>[ 18326.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5d58]
>[ 18326.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5d58] width 1280 pitch 5120 (/4 1280)
>[ 18326.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff9d8]
>[ 18326.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff9d8] width 1280 pitch 5120 (/4 1280)
>[ 18333.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08d018]
>[ 18333.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08d018] width 1280 pitch 5120 (/4 1280)
>[ 18369.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffb890]
>[ 18369.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffb890] width 1280 pitch 5120 (/4 1280)
>[ 18369.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037440]
>[ 18369.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037440] width 1280 pitch 5120 (/4 1280)
>[ 18369.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffb890]
>[ 18369.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffb890] width 1280 pitch 5120 (/4 1280)
>[ 18369.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037440]
>[ 18369.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037440] width 1280 pitch 5120 (/4 1280)
>[ 18369.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f82968]
>[ 18369.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f82968] width 1280 pitch 5120 (/4 1280)
>[ 18369.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc7678]
>[ 18369.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc7678] width 1280 pitch 5120 (/4 1280)
>[ 18369.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45678]
>[ 18369.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45678] width 1280 pitch 5120 (/4 1280)
>[ 18369.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc7678]
>[ 18369.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc7678] width 1280 pitch 5120 (/4 1280)
>[ 18373.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037440]
>[ 18373.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037440] width 1280 pitch 5120 (/4 1280)
>[ 18373.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df58c0]
>[ 18373.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df58c0] width 1280 pitch 5120 (/4 1280)
>[ 18373.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037440]
>[ 18373.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037440] width 1280 pitch 5120 (/4 1280)
>[ 18373.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df58c0]
>[ 18374.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df58c0] width 1280 pitch 5120 (/4 1280)
>[ 18374.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc7678]
>[ 18374.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc7678] width 1280 pitch 5120 (/4 1280)
>[ 18374.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bbdb10]
>[ 18374.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bbdb10] width 1280 pitch 5120 (/4 1280)
>[ 18378.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa037440]
>[ 18378.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa037440] width 1280 pitch 5120 (/4 1280)
>[ 18378.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa087a30]
>[ 18378.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa087a30] width 1280 pitch 5120 (/4 1280)
>[ 18378.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffb890]
>[ 18378.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffb890] width 1280 pitch 5120 (/4 1280)
>[ 18378.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa087a30]
>[ 18378.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa087a30] width 1280 pitch 5120 (/4 1280)
>[ 18378.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffb890]
>[ 18378.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffb890] width 1280 pitch 5120 (/4 1280)
>[ 18378.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa087a30]
>[ 18378.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa087a30] width 1280 pitch 5120 (/4 1280)
>[ 18385.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f340c8]
>[ 18385.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f340c8] width 1280 pitch 5120 (/4 1280)
>[ 18416.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45608]
>[ 18416.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45608] width 1280 pitch 5120 (/4 1280)
>[ 18416.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f348b8]
>[ 18416.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f348b8] width 1280 pitch 5120 (/4 1280)
>[ 18416.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45608]
>[ 18416.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45608] width 1280 pitch 5120 (/4 1280)
>[ 18416.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc6db0]
>[ 18416.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc6db0] width 1280 pitch 5120 (/4 1280)
>[ 18418.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f349b8]
>[ 18418.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f349b8] width 1280 pitch 5120 (/4 1280)
>[ 18419.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45608]
>[ 18419.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45608] width 1280 pitch 5120 (/4 1280)
>[ 18419.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 18419.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 18420.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45608]
>[ 18420.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45608] width 1280 pitch 5120 (/4 1280)
>[ 18426.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 18426.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 18426.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026ec0]
>[ 18426.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026ec0] width 1280 pitch 5120 (/4 1280)
>[ 18426.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 18426.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 18472.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e48a98]
>[ 18472.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e48a98] width 1280 pitch 5120 (/4 1280)
>[ 18478.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f618f0]
>[ 18478.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f618f0] width 1280 pitch 5120 (/4 1280)
>[ 18478.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7dab0]
>[ 18478.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7dab0] width 1280 pitch 5120 (/4 1280)
>[ 18478.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7dab0]
>[ 18479.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7dab0] width 1280 pitch 5120 (/4 1280)
>[ 18479.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c6cdb8]
>[ 18479.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c6cdb8] width 1280 pitch 5120 (/4 1280)
>[ 18541.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3cbd0]
>[ 18541.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3cbd0] width 1280 pitch 5120 (/4 1280)
>[ 18545.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cd330]
>[ 18545.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cd330] width 1280 pitch 5120 (/4 1280)
>[ 18545.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1ddb0]
>[ 18545.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1ddb0] width 1280 pitch 5120 (/4 1280)
>[ 18545.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cd330]
>[ 18545.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cd330] width 1280 pitch 5120 (/4 1280)
>[ 18545.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7dab0]
>[ 18545.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7dab0] width 1280 pitch 5120 (/4 1280)
>[ 18585.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c6ee8]
>[ 18585.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c6ee8] width 1280 pitch 5120 (/4 1280)
>[ 18585.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e20638]
>[ 18585.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e20638] width 1280 pitch 5120 (/4 1280)
>[ 18585.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc9db8]
>[ 18585.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc9db8] width 1280 pitch 5120 (/4 1280)
>[ 18586.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e20638]
>[ 18586.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e20638] width 1280 pitch 5120 (/4 1280)
>[ 18586.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc9db8]
>[ 18586.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc9db8] width 1280 pitch 5120 (/4 1280)
>[ 18592.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dda620]
>[ 18592.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dda620] width 1280 pitch 5120 (/4 1280)
>[ 18612.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fff9d8]
>[ 18612.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fff9d8] width 1280 pitch 5120 (/4 1280)
>[ 18612.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d2e040]
>[ 18612.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d2e040] width 1280 pitch 5120 (/4 1280)
>[ 18612.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 18612.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 18612.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc9db8]
>[ 18612.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc9db8] width 1280 pitch 5120 (/4 1280)
>[ 18619.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e49278]
>[ 18619.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e49278] width 1280 pitch 5120 (/4 1280)
>[ 18625.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e07b10]
>[ 18625.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e07b10] width 1280 pitch 5120 (/4 1280)
>[ 18625.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4fc00]
>[ 18625.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4fc00] width 1280 pitch 5120 (/4 1280)
>[ 18625.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e447a8]
>[ 18625.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e447a8] width 1280 pitch 5120 (/4 1280)
>[ 18625.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e40c58]
>[ 18625.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e40c58] width 1280 pitch 5120 (/4 1280)
>[ 18625.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff41e8]
>[ 18625.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff41e8] width 1280 pitch 5120 (/4 1280)
>[ 18625.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e40c58]
>[ 18625.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e40c58] width 1280 pitch 5120 (/4 1280)
>[ 18655.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18655.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18655.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4f928]
>[ 18655.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4f928] width 1280 pitch 5120 (/4 1280)
>[ 18655.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18655.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18655.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d858]
>[ 18655.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d858] width 1280 pitch 5120 (/4 1280)
>[ 18655.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18655.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18655.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3d858]
>[ 18655.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3d858] width 1280 pitch 5120 (/4 1280)
>[ 18655.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18655.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18657.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3da80]
>[ 18658.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3da80] width 1280 pitch 5120 (/4 1280)
>[ 18658.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3da80]
>[ 18658.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3da80] width 1280 pitch 5120 (/4 1280)
>[ 18658.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25c20]
>[ 18658.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25c20] width 1280 pitch 5120 (/4 1280)
>[ 18658.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3da80]
>[ 18658.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3da80] width 1280 pitch 5120 (/4 1280)
>[ 18658.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffc568]
>[ 18658.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffc568] width 1280 pitch 5120 (/4 1280)
>[ 18658.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb8ce8]
>[ 18658.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb8ce8] width 1280 pitch 5120 (/4 1280)
>[ 18658.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3da80]
>[ 18658.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3da80] width 1280 pitch 5120 (/4 1280)
>[ 18658.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb8ce8]
>[ 18658.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb8ce8] width 1280 pitch 5120 (/4 1280)
>[ 18741.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6e160]
>[ 18741.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6e160] width 1280 pitch 5120 (/4 1280)
>[ 18742.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc73e8]
>[ 18742.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc73e8] width 1280 pitch 5120 (/4 1280)
>[ 18742.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6e160]
>[ 18742.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6e160] width 1280 pitch 5120 (/4 1280)
>[ 18742.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7e918]
>[ 18742.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7e918] width 1280 pitch 5120 (/4 1280)
>[ 18743.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d35d20]
>[ 18743.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d35d20] width 1280 pitch 5120 (/4 1280)
>[ 18743.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb5a40]
>[ 18743.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb5a40] width 1280 pitch 5120 (/4 1280)
>[ 18743.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d35d20]
>[ 18743.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d35d20] width 1280 pitch 5120 (/4 1280)
>[ 18743.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb5a40]
>[ 18743.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb5a40] width 1280 pitch 5120 (/4 1280)
>[ 18752.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4c270]
>[ 18752.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4c270] width 1280 pitch 5120 (/4 1280)
>[ 18752.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18752.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18752.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4c270]
>[ 18752.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4c270] width 1280 pitch 5120 (/4 1280)
>[ 18752.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18752.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18752.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4c270]
>[ 18752.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4c270] width 1280 pitch 5120 (/4 1280)
>[ 18752.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18752.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18825.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18825.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18825.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18825.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18825.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18825.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18825.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18825.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18825.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18825.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18825.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc5b80]
>[ 18825.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc5b80] width 1280 pitch 5120 (/4 1280)
>[ 18829.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91cb0]
>[ 18829.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91cb0] width 1280 pitch 5120 (/4 1280)
>[ 18829.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e210]
>[ 18829.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e210] width 1280 pitch 5120 (/4 1280)
>[ 18829.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b7d98]
>[ 18829.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b7d98] width 1280 pitch 5120 (/4 1280)
>[ 18829.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb0710]
>[ 18829.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb0710] width 1280 pitch 5120 (/4 1280)
>[ 18829.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bf6f0]
>[ 18829.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bf6f0] width 1280 pitch 5120 (/4 1280)
>[ 18829.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb0710]
>[ 18829.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb0710] width 1280 pitch 5120 (/4 1280)
>[ 18829.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bf6f0]
>[ 18829.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bf6f0] width 1280 pitch 5120 (/4 1280)
>[ 18829.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb0710]
>[ 18829.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb0710] width 1280 pitch 5120 (/4 1280)
>[ 18928.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18928.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18928.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80648]
>[ 18928.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80648] width 1280 pitch 5120 (/4 1280)
>[ 18928.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e710]
>[ 18928.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e710] width 1280 pitch 5120 (/4 1280)
>[ 18928.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d4a60]
>[ 18928.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d4a60] width 1280 pitch 5120 (/4 1280)
>[ 18928.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e710]
>[ 18928.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e710] width 1280 pitch 5120 (/4 1280)
>[ 18928.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7fd20]
>[ 18928.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7fd20] width 1280 pitch 5120 (/4 1280)
>[ 18957.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3ff00]
>[ 18957.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3ff00] width 1280 pitch 5120 (/4 1280)
>[ 18957.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3fe58]
>[ 18957.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3fe58] width 1280 pitch 5120 (/4 1280)
>[ 18957.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e5fb48]
>[ 18957.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e5fb48] width 1280 pitch 5120 (/4 1280)
>[ 18957.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b7ec0]
>[ 18957.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b7ec0] width 1280 pitch 5120 (/4 1280)
>[ 18957.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08ab30]
>[ 18957.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08ab30] width 1280 pitch 5120 (/4 1280)
>[ 18957.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b7ec0]
>[ 18957.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b7ec0] width 1280 pitch 5120 (/4 1280)
>[ 18957.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08ab30]
>[ 18957.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08ab30] width 1280 pitch 5120 (/4 1280)
>[ 18963.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18963.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18963.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc5b80]
>[ 18963.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc5b80] width 1280 pitch 5120 (/4 1280)
>[ 18963.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18964.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18964.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08c0a8]
>[ 18964.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08c0a8] width 1280 pitch 5120 (/4 1280)
>[ 18964.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7fd20]
>[ 18964.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7fd20] width 1280 pitch 5120 (/4 1280)
>[ 18964.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18964.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18964.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7fd20]
>[ 18964.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7fd20] width 1280 pitch 5120 (/4 1280)
>[ 18964.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18964.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18968.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cafcc0]
>[ 18968.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cafcc0] width 1280 pitch 5120 (/4 1280)
>[ 18968.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6e6e8]
>[ 18968.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6e6e8] width 1280 pitch 5120 (/4 1280)
>[ 18968.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2f218]
>[ 18968.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2f218] width 1280 pitch 5120 (/4 1280)
>[ 18968.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fb2e0]
>[ 18968.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fb2e0] width 1280 pitch 5120 (/4 1280)
>[ 18969.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb08b0]
>[ 18969.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb08b0] width 1280 pitch 5120 (/4 1280)
>[ 18969.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e618]
>[ 18969.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e618] width 1280 pitch 5120 (/4 1280)
>[ 18969.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb08b0]
>[ 18969.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb08b0] width 1280 pitch 5120 (/4 1280)
>[ 18969.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e618]
>[ 18969.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e618] width 1280 pitch 5120 (/4 1280)
>[ 18977.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d4ae0]
>[ 18977.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d4ae0] width 1280 pitch 5120 (/4 1280)
>[ 18977.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e07b10]
>[ 18977.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e07b10] width 1280 pitch 5120 (/4 1280)
>[ 18977.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0d4ae0]
>[ 18977.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0d4ae0] width 1280 pitch 5120 (/4 1280)
>[ 18977.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18977.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18977.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0178a8]
>[ 18977.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0178a8] width 1280 pitch 5120 (/4 1280)
>[ 18977.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18977.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18979.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb0580]
>[ 18979.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb0580] width 1280 pitch 5120 (/4 1280)
>[ 18979.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdc348]
>[ 18979.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdc348] width 1280 pitch 5120 (/4 1280)
>[ 18979.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08ab30]
>[ 18979.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08ab30] width 1280 pitch 5120 (/4 1280)
>[ 18979.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08ab30]
>[ 18979.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08ab30] width 1280 pitch 5120 (/4 1280)
>[ 18979.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0faaa8]
>[ 18979.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0faaa8] width 1280 pitch 5120 (/4 1280)
>[ 18979.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08ab30]
>[ 18979.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08ab30] width 1280 pitch 5120 (/4 1280)
>[ 18979.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0faaa8]
>[ 18979.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0faaa8] width 1280 pitch 5120 (/4 1280)
>[ 18983.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0178a8]
>[ 18983.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0178a8] width 1280 pitch 5120 (/4 1280)
>[ 18983.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ac6170]
>[ 18983.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ac6170] width 1280 pitch 5120 (/4 1280)
>[ 18983.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0178a8]
>[ 18983.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0178a8] width 1280 pitch 5120 (/4 1280)
>[ 18983.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18983.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18983.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f80570]
>[ 18983.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f80570] width 1280 pitch 5120 (/4 1280)
>[ 18983.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18983.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18983.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0178a8]
>[ 18983.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0178a8] width 1280 pitch 5120 (/4 1280)
>[ 18983.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 18983.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 18994.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa086028]
>[ 18994.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa086028] width 1280 pitch 5120 (/4 1280)
>[ 19006.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d3fb38]
>[ 19006.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d3fb38] width 1280 pitch 5120 (/4 1280)
>[ 19006.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb3208]
>[ 19006.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb3208] width 1280 pitch 5120 (/4 1280)
>[ 19006.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de8900]
>[ 19006.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de8900] width 1280 pitch 5120 (/4 1280)
>[ 19006.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c620c8]
>[ 19007.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c620c8] width 1280 pitch 5120 (/4 1280)
>[ 19007.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c620c8]
>[ 19007.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c620c8] width 1280 pitch 5120 (/4 1280)
>[ 19026.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c2798]
>[ 19027.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c2798] width 1280 pitch 5120 (/4 1280)
>[ 19041.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c62478]
>[ 19042.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c62478] width 1280 pitch 5120 (/4 1280)
>[ 19045.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11e790]
>[ 19045.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11e790] width 1280 pitch 5120 (/4 1280)
>[ 19045.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b73b0]
>[ 19045.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b73b0] width 1280 pitch 5120 (/4 1280)
>[ 19045.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e41960]
>[ 19045.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e41960] width 1280 pitch 5120 (/4 1280)
>[ 19045.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b73b0]
>[ 19045.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b73b0] width 1280 pitch 5120 (/4 1280)
>[ 19103.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ec28]
>[ 19103.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ec28] width 1280 pitch 5120 (/4 1280)
>[ 19103.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b73b0]
>[ 19103.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b73b0] width 1280 pitch 5120 (/4 1280)
>[ 19103.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30e88]
>[ 19103.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30e88] width 1280 pitch 5120 (/4 1280)
>[ 19103.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa086270]
>[ 19103.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa086270] width 1280 pitch 5120 (/4 1280)
>[ 19103.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30e88]
>[ 19103.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30e88] width 1280 pitch 5120 (/4 1280)
>[ 19103.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa086270]
>[ 19103.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa086270] width 1280 pitch 5120 (/4 1280)
>[ 19103.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30e88]
>[ 19103.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30e88] width 1280 pitch 5120 (/4 1280)
>[ 19103.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa086270]
>[ 19103.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa086270] width 1280 pitch 5120 (/4 1280)
>[ 19103.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30e88]
>[ 19103.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30e88] width 1280 pitch 5120 (/4 1280)
>[ 19103.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc6db0]
>[ 19103.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc6db0] width 1280 pitch 5120 (/4 1280)
>[ 19122.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19122.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19134.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b8058]
>[ 19134.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b8058] width 1280 pitch 5120 (/4 1280)
>[ 19134.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b60e68]
>[ 19134.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b60e68] width 1280 pitch 5120 (/4 1280)
>[ 19134.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b8058]
>[ 19134.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b8058] width 1280 pitch 5120 (/4 1280)
>[ 19134.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b60e68]
>[ 19134.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b60e68] width 1280 pitch 5120 (/4 1280)
>[ 19134.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1b8058]
>[ 19134.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1b8058] width 1280 pitch 5120 (/4 1280)
>[ 19134.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b60e68]
>[ 19134.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b60e68] width 1280 pitch 5120 (/4 1280)
>[ 19134.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b60e68]
>[ 19135.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b60e68] width 1280 pitch 5120 (/4 1280)
>[ 19152.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5940]
>[ 19152.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5940] width 1280 pitch 5120 (/4 1280)
>[ 19152.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a3b0]
>[ 19152.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a3b0] width 1280 pitch 5120 (/4 1280)
>[ 19152.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5940]
>[ 19152.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5940] width 1280 pitch 5120 (/4 1280)
>[ 19152.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a3b0]
>[ 19152.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a3b0] width 1280 pitch 5120 (/4 1280)
>[ 19152.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5940]
>[ 19153.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5940] width 1280 pitch 5120 (/4 1280)
>[ 19153.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5690]
>[ 19153.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5690] width 1280 pitch 5120 (/4 1280)
>[ 19153.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5940]
>[ 19153.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5940] width 1280 pitch 5120 (/4 1280)
>[ 19153.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5690]
>[ 19153.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5690] width 1280 pitch 5120 (/4 1280)
>[ 19157.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed57b0]
>[ 19157.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed57b0] width 1280 pitch 5120 (/4 1280)
>[ 19157.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0728]
>[ 19157.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0728] width 1280 pitch 5120 (/4 1280)
>[ 19157.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e40f30]
>[ 19157.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e40f30] width 1280 pitch 5120 (/4 1280)
>[ 19157.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0728]
>[ 19157.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0728] width 1280 pitch 5120 (/4 1280)
>[ 19157.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e40f30]
>[ 19157.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e40f30] width 1280 pitch 5120 (/4 1280)
>[ 19157.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e00e30]
>[ 19157.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e00e30] width 1280 pitch 5120 (/4 1280)
>[ 19157.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15cd18]
>[ 19157.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15cd18] width 1280 pitch 5120 (/4 1280)
>[ 19160.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e92868]
>[ 19160.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e92868] width 1280 pitch 5120 (/4 1280)
>[ 19160.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a380]
>[ 19160.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a380] width 1280 pitch 5120 (/4 1280)
>[ 19160.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19160.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19160.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19160.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19160.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5690]
>[ 19160.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5690] width 1280 pitch 5120 (/4 1280)
>[ 19160.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19160.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19160.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5690]
>[ 19160.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5690] width 1280 pitch 5120 (/4 1280)
>[ 19174.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f324b0]
>[ 19174.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f324b0] width 1280 pitch 5120 (/4 1280)
>[ 19174.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f324b0]
>[ 19174.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f324b0] width 1280 pitch 5120 (/4 1280)
>[ 19174.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f325e0]
>[ 19174.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f325e0] width 1280 pitch 5120 (/4 1280)
>[ 19174.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ff5e8]
>[ 19174.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ff5e8] width 1280 pitch 5120 (/4 1280)
>[ 19174.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f325e0]
>[ 19174.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f325e0] width 1280 pitch 5120 (/4 1280)
>[ 19174.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e92088]
>[ 19174.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e92088] width 1280 pitch 5120 (/4 1280)
>[ 19174.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f325e0]
>[ 19174.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f325e0] width 1280 pitch 5120 (/4 1280)
>[ 19188.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa157e38]
>[ 19188.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa157e38] width 1280 pitch 5120 (/4 1280)
>[ 19188.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19188.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19188.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa157e38]
>[ 19188.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa157e38] width 1280 pitch 5120 (/4 1280)
>[ 19188.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19188.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19188.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa157e38]
>[ 19188.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa157e38] width 1280 pitch 5120 (/4 1280)
>[ 19188.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19188.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19188.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed5690]
>[ 19188.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed5690] width 1280 pitch 5120 (/4 1280)
>[ 19188.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19188.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19200.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0368]
>[ 19200.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0368] width 1280 pitch 5120 (/4 1280)
>[ 19200.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0368]
>[ 19200.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0368] width 1280 pitch 5120 (/4 1280)
>[ 19200.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bba428]
>[ 19200.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bba428] width 1280 pitch 5120 (/4 1280)
>[ 19200.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb9bf0]
>[ 19200.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb9bf0] width 1280 pitch 5120 (/4 1280)
>[ 19200.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0368]
>[ 19200.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0368] width 1280 pitch 5120 (/4 1280)
>[ 19200.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb9bf0]
>[ 19200.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb9bf0] width 1280 pitch 5120 (/4 1280)
>[ 19200.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0368]
>[ 19200.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0368] width 1280 pitch 5120 (/4 1280)
>[ 19200.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb9bf0]
>[ 19200.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb9bf0] width 1280 pitch 5120 (/4 1280)
>[ 19201.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ccf0]
>[ 19201.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ccf0] width 1280 pitch 5120 (/4 1280)
>[ 19201.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19201.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19201.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15ccf0]
>[ 19201.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15ccf0] width 1280 pitch 5120 (/4 1280)
>[ 19201.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb73b8]
>[ 19201.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb73b8] width 1280 pitch 5120 (/4 1280)
>[ 19201.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19201.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19201.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa158158]
>[ 19201.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa158158] width 1280 pitch 5120 (/4 1280)
>[ 19201.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19201.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19201.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa158158]
>[ 19201.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa158158] width 1280 pitch 5120 (/4 1280)
>[ 19201.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d0f80]
>[ 19201.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d0f80] width 1280 pitch 5120 (/4 1280)
>[ 19229.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e07b10]
>[ 19230.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e07b10] width 1280 pitch 5120 (/4 1280)
>[ 19230.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4e710]
>[ 19230.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4e710] width 1280 pitch 5120 (/4 1280)
>[ 19230.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb900]
>[ 19230.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb900] width 1280 pitch 5120 (/4 1280)
>[ 19279.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b98b58]
>[ 19279.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b98b58] width 1280 pitch 5120 (/4 1280)
>[ 19286.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026ec0]
>[ 19286.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026ec0] width 1280 pitch 5120 (/4 1280)
>[ 19286.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3f898]
>[ 19286.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3f898] width 1280 pitch 5120 (/4 1280)
>[ 19286.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e20638]
>[ 19286.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e20638] width 1280 pitch 5120 (/4 1280)
>[ 19306.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9caf0b0]
>[ 19306.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9caf0b0] width 1280 pitch 5120 (/4 1280)
>[ 19308.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc92c0]
>[ 19308.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc92c0] width 1280 pitch 5120 (/4 1280)
>[ 19308.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f3e0]
>[ 19308.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f3e0] width 1280 pitch 5120 (/4 1280)
>[ 19308.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc92c0]
>[ 19308.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc92c0] width 1280 pitch 5120 (/4 1280)
>[ 19308.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f3e0]
>[ 19308.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f3e0] width 1280 pitch 5120 (/4 1280)
>[ 19308.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc92c0]
>[ 19308.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc92c0] width 1280 pitch 5120 (/4 1280)
>[ 19308.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f3e0]
>[ 19308.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f3e0] width 1280 pitch 5120 (/4 1280)
>[ 19308.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc92c0]
>[ 19308.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc92c0] width 1280 pitch 5120 (/4 1280)
>[ 19308.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f3e0]
>[ 19308.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f3e0] width 1280 pitch 5120 (/4 1280)
>[ 19308.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc92c0]
>[ 19308.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc92c0] width 1280 pitch 5120 (/4 1280)
>[ 19308.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f3e0]
>[ 19308.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f3e0] width 1280 pitch 5120 (/4 1280)
>[ 19308.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f31928]
>[ 19308.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f31928] width 1280 pitch 5120 (/4 1280)
>[ 19321.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5dc0]
>[ 19321.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5dc0] width 1280 pitch 5120 (/4 1280)
>[ 19321.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2ed8]
>[ 19321.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2ed8] width 1280 pitch 5120 (/4 1280)
>[ 19321.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5dc0]
>[ 19321.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5dc0] width 1280 pitch 5120 (/4 1280)
>[ 19321.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2ed8]
>[ 19321.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2ed8] width 1280 pitch 5120 (/4 1280)
>[ 19321.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5dc0]
>[ 19321.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5dc0] width 1280 pitch 5120 (/4 1280)
>[ 19321.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2ed8]
>[ 19321.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2ed8] width 1280 pitch 5120 (/4 1280)
>[ 19321.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5dc0]
>[ 19321.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5dc0] width 1280 pitch 5120 (/4 1280)
>[ 19321.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc2ed8]
>[ 19321.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc2ed8] width 1280 pitch 5120 (/4 1280)
>[ 19325.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19325.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff5d90]
>[ 19325.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff5d90] width 1280 pitch 5120 (/4 1280)
>[ 19325.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22fe8]
>[ 19325.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22fe8] width 1280 pitch 5120 (/4 1280)
>[ 19327.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19327.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19327.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19327.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19327.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19327.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19327.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19328.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19328.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19328.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19328.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19329.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19329.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19329.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19329.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19329.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19329.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19329.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19329.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19329.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19329.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19329.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19329.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19329.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19329.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19330.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19330.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19330.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19330.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19330.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d480d0]
>[ 19330.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d480d0] width 1280 pitch 5120 (/4 1280)
>[ 19330.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb0788]
>[ 19330.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb0788] width 1280 pitch 5120 (/4 1280)
>[ 19330.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 19330.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 19332.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f22128]
>[ 19332.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f22128] width 1280 pitch 5120 (/4 1280)
>[ 19336.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd38b0]
>[ 19336.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd38b0] width 1280 pitch 5120 (/4 1280)
>[ 19336.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d64ba0]
>[ 19336.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d64ba0] width 1280 pitch 5120 (/4 1280)
>[ 19336.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd38b0]
>[ 19336.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd38b0] width 1280 pitch 5120 (/4 1280)
>[ 19336.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d64ba0]
>[ 19336.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d64ba0] width 1280 pitch 5120 (/4 1280)
>[ 19336.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd38b0]
>[ 19336.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd38b0] width 1280 pitch 5120 (/4 1280)
>[ 19336.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19336.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19336.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd38b0]
>[ 19336.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd38b0] width 1280 pitch 5120 (/4 1280)
>[ 19336.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f140]
>[ 19336.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f140] width 1280 pitch 5120 (/4 1280)
>[ 19336.892] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 19336.892] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 19336.892] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 19336.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 19336.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 20026.851] (II) RADEON(0): RADEONSaveScreen(2)
>[ 20026.894] (II) RADEON(0): RADEONSaveScreen(0)
>[ 23393.892] (II) RADEON(0): RADEONSaveScreen(1)
>[ 23636.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d53d40]
>[ 23636.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d53d40] width 1280 pitch 5120 (/4 1280)
>[ 23636.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bafe40]
>[ 23636.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bafe40] width 1280 pitch 5120 (/4 1280)
>[ 23637.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23637.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23637.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc3668]
>[ 23637.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc3668] width 1280 pitch 5120 (/4 1280)
>[ 23637.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23637.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23637.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23637.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23637.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23637.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23637.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23637.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23638.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23638.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23639.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23639.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23639.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23639.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23640.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23640.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23640.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23640.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23641.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23641.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23642.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23642.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23642.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23642.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23642.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23642.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23642.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23642.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23642.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23642.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23642.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23642.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23642.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23642.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23642.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23642.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23643.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23643.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23643.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d19660]
>[ 23643.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d19660] width 1280 pitch 5120 (/4 1280)
>[ 23646.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23646.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23646.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ddd738]
>[ 23646.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ddd738] width 1280 pitch 5120 (/4 1280)
>[ 23646.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc3668]
>[ 23646.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc3668] width 1280 pitch 5120 (/4 1280)
>[ 23646.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23646.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23646.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39928]
>[ 23646.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39928] width 1280 pitch 5120 (/4 1280)
>[ 23646.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cacd50]
>[ 23646.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cacd50] width 1280 pitch 5120 (/4 1280)
>[ 23652.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4a258]
>[ 23652.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4a258] width 1280 pitch 5120 (/4 1280)
>[ 23657.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d0cc38]
>[ 23657.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d0cc38] width 1280 pitch 5120 (/4 1280)
>[ 23657.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c866a0]
>[ 23657.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c866a0] width 1280 pitch 5120 (/4 1280)
>[ 23657.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e058e0]
>[ 23657.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e058e0] width 1280 pitch 5120 (/4 1280)
>[ 23669.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b56470]
>[ 23669.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b56470] width 1280 pitch 5120 (/4 1280)
>[ 23669.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6f8f8]
>[ 23669.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6f8f8] width 1280 pitch 5120 (/4 1280)
>[ 23669.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3b428]
>[ 23669.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3b428] width 1280 pitch 5120 (/4 1280)
>[ 23669.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dea1f0]
>[ 23669.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dea1f0] width 1280 pitch 5120 (/4 1280)
>[ 23669.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 23669.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 23669.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c559e8]
>[ 23669.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c559e8] width 1280 pitch 5120 (/4 1280)
>[ 23669.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30a20]
>[ 23669.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30a20] width 1280 pitch 5120 (/4 1280)
>[ 23669.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3bc28]
>[ 23669.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3bc28] width 1280 pitch 5120 (/4 1280)
>[ 23669.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d47bb8]
>[ 23669.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d47bb8] width 1280 pitch 5120 (/4 1280)
>[ 23669.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3bc28]
>[ 23669.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3bc28] width 1280 pitch 5120 (/4 1280)
>[ 23672.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a30c40]
>[ 23672.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a30c40] width 1280 pitch 5120 (/4 1280)
>[ 23672.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc36a8]
>[ 23672.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc36a8] width 1280 pitch 5120 (/4 1280)
>[ 23672.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23672.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23672.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23672.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23672.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23672.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23672.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23672.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23672.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23672.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23672.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23672.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23672.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23672.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23672.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23672.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23673.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23673.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23673.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23673.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23673.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23673.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23673.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f637f8]
>[ 23673.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f637f8] width 1280 pitch 5120 (/4 1280)
>[ 23673.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23673.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23673.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f637f8]
>[ 23673.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f637f8] width 1280 pitch 5120 (/4 1280)
>[ 23673.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f6ca40]
>[ 23673.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f6ca40] width 1280 pitch 5120 (/4 1280)
>[ 23673.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f637f8]
>[ 23673.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f637f8] width 1280 pitch 5120 (/4 1280)
>[ 23674.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f637f8]
>[ 23674.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f637f8] width 1280 pitch 5120 (/4 1280)
>[ 23674.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23674.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23674.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f637f8]
>[ 23674.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f637f8] width 1280 pitch 5120 (/4 1280)
>[ 23675.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23675.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23675.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 23675.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 23675.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23675.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23675.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec9da0]
>[ 23675.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec9da0] width 1280 pitch 5120 (/4 1280)
>[ 23675.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23675.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23675.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 23675.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 23675.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f26540]
>[ 23675.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f26540] width 1280 pitch 5120 (/4 1280)
>[ 23675.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c53c68]
>[ 23675.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c53c68] width 1280 pitch 5120 (/4 1280)
>[ 23676.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b46df0]
>[ 23676.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b46df0] width 1280 pitch 5120 (/4 1280)
>[ 23676.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b46df0]
>[ 23676.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b46df0] width 1280 pitch 5120 (/4 1280)
>[ 23676.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3b798]
>[ 23676.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3b798] width 1280 pitch 5120 (/4 1280)
>[ 23822.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd6948]
>[ 23822.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd6948] width 1280 pitch 5120 (/4 1280)
>[ 23822.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cec098]
>[ 23822.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cec098] width 1280 pitch 5120 (/4 1280)
>[ 23823.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec480]
>[ 23823.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec480] width 1280 pitch 5120 (/4 1280)
>[ 23823.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94e60]
>[ 23823.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94e60] width 1280 pitch 5120 (/4 1280)
>[ 23823.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec480]
>[ 23823.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec480] width 1280 pitch 5120 (/4 1280)
>[ 23823.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94e60]
>[ 23823.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94e60] width 1280 pitch 5120 (/4 1280)
>[ 23823.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94e60]
>[ 23823.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94e60] width 1280 pitch 5120 (/4 1280)
>[ 23825.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cec098]
>[ 23825.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cec098] width 1280 pitch 5120 (/4 1280)
>[ 23825.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dec480]
>[ 23825.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dec480] width 1280 pitch 5120 (/4 1280)
>[ 23826.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08c1f0]
>[ 23826.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08c1f0] width 1280 pitch 5120 (/4 1280)
>[ 23826.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94e60]
>[ 23826.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94e60] width 1280 pitch 5120 (/4 1280)
>[ 23826.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08c1f0]
>[ 23826.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08c1f0] width 1280 pitch 5120 (/4 1280)
>[ 23826.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c94e60]
>[ 23826.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c94e60] width 1280 pitch 5120 (/4 1280)
>[ 23826.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa08c1f0]
>[ 23826.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa08c1f0] width 1280 pitch 5120 (/4 1280)
>[ 23954.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8fc8]
>[ 23954.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8fc8] width 1280 pitch 5120 (/4 1280)
>[ 23955.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df7bb8]
>[ 23955.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df7bb8] width 1280 pitch 5120 (/4 1280)
>[ 23955.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9a83a18]
>[ 23955.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9a83a18] width 1280 pitch 5120 (/4 1280)
>[ 23955.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89630]
>[ 23955.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89630] width 1280 pitch 5120 (/4 1280)
>[ 23957.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4c690]
>[ 23957.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4c690] width 1280 pitch 5120 (/4 1280)
>[ 23957.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02be88]
>[ 23957.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02be88] width 1280 pitch 5120 (/4 1280)
>[ 23959.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02be88]
>[ 23959.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02be88] width 1280 pitch 5120 (/4 1280)
>[ 23959.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02be88]
>[ 23959.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02be88] width 1280 pitch 5120 (/4 1280)
>[ 23959.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f070]
>[ 23959.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f070] width 1280 pitch 5120 (/4 1280)
>[ 23959.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9880]
>[ 23959.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9880] width 1280 pitch 5120 (/4 1280)
>[ 23985.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4c690]
>[ 23985.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4c690] width 1280 pitch 5120 (/4 1280)
>[ 23985.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4c690]
>[ 23985.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4c690] width 1280 pitch 5120 (/4 1280)
>[ 23988.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a998]
>[ 23988.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a998] width 1280 pitch 5120 (/4 1280)
>[ 23988.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff65a0]
>[ 23988.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff65a0] width 1280 pitch 5120 (/4 1280)
>[ 23998.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb9880]
>[ 23998.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb9880] width 1280 pitch 5120 (/4 1280)
>[ 23998.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa018e30]
>[ 23998.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa018e30] width 1280 pitch 5120 (/4 1280)
>[ 23998.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa018e30]
>[ 23998.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa018e30] width 1280 pitch 5120 (/4 1280)
>[ 23998.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbf578]
>[ 23998.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbf578] width 1280 pitch 5120 (/4 1280)
>[ 23999.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d390d0]
>[ 23999.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d390d0] width 1280 pitch 5120 (/4 1280)
>[ 24000.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff65a0]
>[ 24000.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff65a0] width 1280 pitch 5120 (/4 1280)
>[ 24014.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8fc8]
>[ 24014.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8fc8] width 1280 pitch 5120 (/4 1280)
>[ 24014.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa018fe8]
>[ 24014.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa018fe8] width 1280 pitch 5120 (/4 1280)
>[ 24015.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d34d08]
>[ 24015.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d34d08] width 1280 pitch 5120 (/4 1280)
>[ 24015.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbe298]
>[ 24015.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbe298] width 1280 pitch 5120 (/4 1280)
>[ 24015.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f070]
>[ 24015.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f070] width 1280 pitch 5120 (/4 1280)
>[ 24015.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d540f0]
>[ 24016.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d540f0] width 1280 pitch 5120 (/4 1280)
>[ 24016.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9e2d0]
>[ 24016.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9e2d0] width 1280 pitch 5120 (/4 1280)
>[ 24016.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d540f0]
>[ 24016.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d540f0] width 1280 pitch 5120 (/4 1280)
>[ 24016.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89ae8]
>[ 24016.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89ae8] width 1280 pitch 5120 (/4 1280)
>[ 24016.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8fc8]
>[ 24016.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8fc8] width 1280 pitch 5120 (/4 1280)
>[ 24016.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de3f80]
>[ 24016.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de3f80] width 1280 pitch 5120 (/4 1280)
>[ 24017.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a998]
>[ 24017.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a998] width 1280 pitch 5120 (/4 1280)
>[ 24018.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d540f0]
>[ 24018.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d540f0] width 1280 pitch 5120 (/4 1280)
>[ 24018.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3310]
>[ 24018.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3310] width 1280 pitch 5120 (/4 1280)
>[ 24018.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df7bb8]
>[ 24018.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df7bb8] width 1280 pitch 5120 (/4 1280)
>[ 24018.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d45b50]
>[ 24018.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d45b50] width 1280 pitch 5120 (/4 1280)
>[ 24020.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd9840]
>[ 24020.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd9840] width 1280 pitch 5120 (/4 1280)
>[ 24020.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65780]
>[ 24020.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65780] width 1280 pitch 5120 (/4 1280)
>[ 24020.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1bae38]
>[ 24020.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1bae38] width 1280 pitch 5120 (/4 1280)
>[ 24031.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f21838]
>[ 24031.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f21838] width 1280 pitch 5120 (/4 1280)
>[ 24070.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f21838]
>[ 24070.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f21838] width 1280 pitch 5120 (/4 1280)
>[ 24070.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e4aa18]
>[ 24070.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e4aa18] width 1280 pitch 5120 (/4 1280)
>[ 24070.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e657b8]
>[ 24070.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e657b8] width 1280 pitch 5120 (/4 1280)
>[ 24070.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e657b8]
>[ 24071.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e657b8] width 1280 pitch 5120 (/4 1280)
>[ 24078.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89ae8]
>[ 24078.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89ae8] width 1280 pitch 5120 (/4 1280)
>[ 24078.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3310]
>[ 24078.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3310] width 1280 pitch 5120 (/4 1280)
>[ 24085.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3c7a0]
>[ 24085.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3c7a0] width 1280 pitch 5120 (/4 1280)
>[ 24085.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8fc8]
>[ 24085.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8fc8] width 1280 pitch 5120 (/4 1280)
>[ 24085.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b89630]
>[ 24085.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b89630] width 1280 pitch 5120 (/4 1280)
>[ 24085.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaf8d8]
>[ 24085.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaf8d8] width 1280 pitch 5120 (/4 1280)
>[ 24085.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6a998]
>[ 24085.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6a998] width 1280 pitch 5120 (/4 1280)
>[ 24085.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d34d08]
>[ 24086.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d34d08] width 1280 pitch 5120 (/4 1280)
>[ 24086.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d390d0]
>[ 24086.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d390d0] width 1280 pitch 5120 (/4 1280)
>[ 24086.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff65a0]
>[ 24086.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff65a0] width 1280 pitch 5120 (/4 1280)
>[ 24086.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bad910]
>[ 24086.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bad910] width 1280 pitch 5120 (/4 1280)
>[ 24087.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c3c7a0]
>[ 24087.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c3c7a0] width 1280 pitch 5120 (/4 1280)
>[ 24087.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed3310]
>[ 24087.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed3310] width 1280 pitch 5120 (/4 1280)
>[ 24087.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d540f0]
>[ 24087.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d540f0] width 1280 pitch 5120 (/4 1280)
>[ 24087.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c89ae8]
>[ 24087.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c89ae8] width 1280 pitch 5120 (/4 1280)
>[ 24087.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e1f070]
>[ 24087.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e1f070] width 1280 pitch 5120 (/4 1280)
>[ 24087.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b6dc00]
>[ 24087.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b6dc00] width 1280 pitch 5120 (/4 1280)
>[ 24091.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f23618]
>[ 24091.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f23618] width 1280 pitch 5120 (/4 1280)
>[ 24091.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2d070]
>[ 24091.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2d070] width 1280 pitch 5120 (/4 1280)
>[ 24097.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24097.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f466d8]
>[ 24097.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f466d8] width 1280 pitch 5120 (/4 1280)
>[ 24097.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24097.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a1b0]
>[ 24097.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a1b0] width 1280 pitch 5120 (/4 1280)
>[ 24097.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24097.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24097.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a1b0]
>[ 24097.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a1b0] width 1280 pitch 5120 (/4 1280)
>[ 24097.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24097.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a1b0]
>[ 24097.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a1b0] width 1280 pitch 5120 (/4 1280)
>[ 24097.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4a1b0]
>[ 24097.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4a1b0] width 1280 pitch 5120 (/4 1280)
>[ 24097.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e72170]
>[ 24097.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e72170] width 1280 pitch 5120 (/4 1280)
>[ 24099.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d25da8]
>[ 24099.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d25da8] width 1280 pitch 5120 (/4 1280)
>[ 24104.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e993e0]
>[ 24105.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e993e0] width 1280 pitch 5120 (/4 1280)
>[ 24105.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01ac08]
>[ 24105.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01ac08] width 1280 pitch 5120 (/4 1280)
>[ 24105.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa01ac08]
>[ 24105.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa01ac08] width 1280 pitch 5120 (/4 1280)
>[ 24105.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e993e0]
>[ 24105.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e993e0] width 1280 pitch 5120 (/4 1280)
>[ 24109.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7d1a8]
>[ 24109.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7d1a8] width 1280 pitch 5120 (/4 1280)
>[ 24125.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffd1a8]
>[ 24125.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffd1a8] width 1280 pitch 5120 (/4 1280)
>[ 24125.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7d1a8]
>[ 24125.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7d1a8] width 1280 pitch 5120 (/4 1280)
>[ 24125.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7d1a8]
>[ 24125.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7d1a8] width 1280 pitch 5120 (/4 1280)
>[ 24125.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033148]
>[ 24125.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033148] width 1280 pitch 5120 (/4 1280)
>[ 24126.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24126.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24127.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e435e8]
>[ 24127.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e435e8] width 1280 pitch 5120 (/4 1280)
>[ 24129.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24129.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24129.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec6598]
>[ 24129.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec6598] width 1280 pitch 5120 (/4 1280)
>[ 24130.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa033148]
>[ 24130.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa033148] width 1280 pitch 5120 (/4 1280)
>[ 24131.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ec6598]
>[ 24131.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ec6598] width 1280 pitch 5120 (/4 1280)
>[ 24134.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e435e8]
>[ 24134.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e435e8] width 1280 pitch 5120 (/4 1280)
>[ 24134.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9dfe0]
>[ 24134.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9dfe0] width 1280 pitch 5120 (/4 1280)
>[ 24136.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eafc08]
>[ 24136.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eafc08] width 1280 pitch 5120 (/4 1280)
>[ 24142.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e91c80]
>[ 24142.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e91c80] width 1280 pitch 5120 (/4 1280)
>[ 24145.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c5a1c8]
>[ 24145.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c5a1c8] width 1280 pitch 5120 (/4 1280)
>[ 24147.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55900]
>[ 24147.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55900] width 1280 pitch 5120 (/4 1280)
>[ 24147.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fb1e8]
>[ 24147.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fb1e8] width 1280 pitch 5120 (/4 1280)
>[ 24147.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d22f98]
>[ 24147.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d22f98] width 1280 pitch 5120 (/4 1280)
>[ 24147.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55900]
>[ 24147.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55900] width 1280 pitch 5120 (/4 1280)
>[ 24147.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24147.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24147.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24147.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24147.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24147.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24147.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55900]
>[ 24147.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55900] width 1280 pitch 5120 (/4 1280)
>[ 24147.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d22f98]
>[ 24147.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d22f98] width 1280 pitch 5120 (/4 1280)
>[ 24147.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d224a8]
>[ 24147.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d224a8] width 1280 pitch 5120 (/4 1280)
>[ 24147.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24147.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24148.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24148.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24149.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55938]
>[ 24149.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55938] width 1280 pitch 5120 (/4 1280)
>[ 24149.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24149.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24149.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24149.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24149.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24149.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24149.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24149.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24149.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24149.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24149.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24149.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24153.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24153.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24153.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55938]
>[ 24153.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55938] width 1280 pitch 5120 (/4 1280)
>[ 24153.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24153.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24159.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55938]
>[ 24159.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55938] width 1280 pitch 5120 (/4 1280)
>[ 24159.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55938]
>[ 24159.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55938] width 1280 pitch 5120 (/4 1280)
>[ 24159.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24159.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24159.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24159.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24160.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7f178]
>[ 24160.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7f178] width 1280 pitch 5120 (/4 1280)
>[ 24160.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e7f178]
>[ 24160.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e7f178] width 1280 pitch 5120 (/4 1280)
>[ 24160.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24160.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24160.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24160.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24160.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24160.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24160.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24160.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24160.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24160.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24160.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24160.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24160.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24160.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24160.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24160.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24160.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24160.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24160.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24160.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24160.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24160.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24160.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24160.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24163.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d42798]
>[ 24163.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d42798] width 1280 pitch 5120 (/4 1280)
>[ 24163.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24163.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24163.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24163.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24163.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55900]
>[ 24163.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55900] width 1280 pitch 5120 (/4 1280)
>[ 24163.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c55900]
>[ 24163.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c55900] width 1280 pitch 5120 (/4 1280)
>[ 24163.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2db8]
>[ 24163.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2db8] width 1280 pitch 5120 (/4 1280)
>[ 24163.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24163.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24163.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2db8]
>[ 24163.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2db8] width 1280 pitch 5120 (/4 1280)
>[ 24163.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24163.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24164.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2db8]
>[ 24164.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2db8] width 1280 pitch 5120 (/4 1280)
>[ 24164.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2db8]
>[ 24164.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2db8] width 1280 pitch 5120 (/4 1280)
>[ 24165.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb2db8]
>[ 24165.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb2db8] width 1280 pitch 5120 (/4 1280)
>[ 24165.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24165.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24165.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24166.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24166.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24166.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24166.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24166.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24166.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b3fd40]
>[ 24166.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b3fd40] width 1280 pitch 5120 (/4 1280)
>[ 24166.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24166.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24167.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24167.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24167.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24167.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24167.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 24167.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 24168.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 24168.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 24168.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93e0]
>[ 24168.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93e0] width 1280 pitch 5120 (/4 1280)
>[ 24168.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eaaaa8]
>[ 24168.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eaaaa8] width 1280 pitch 5120 (/4 1280)
>[ 24168.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03e4e8]
>[ 24168.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03e4e8] width 1280 pitch 5120 (/4 1280)
>[ 24169.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d22f10]
>[ 24169.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d22f10] width 1280 pitch 5120 (/4 1280)
>[ 24169.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24169.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24169.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24169.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24169.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24169.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd2f58]
>[ 24169.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd2f58] width 1280 pitch 5120 (/4 1280)
>[ 24169.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d427e0]
>[ 24169.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d427e0] width 1280 pitch 5120 (/4 1280)
>[ 24174.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd4160]
>[ 24174.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd4160] width 1280 pitch 5120 (/4 1280)
>[ 24184.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24184.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24184.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24184.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24184.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24184.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24184.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24184.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24184.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24184.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24184.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24184.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24184.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24184.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24184.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd4510]
>[ 24184.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd4510] width 1280 pitch 5120 (/4 1280)
>[ 24184.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd4510]
>[ 24184.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd4510] width 1280 pitch 5120 (/4 1280)
>[ 24184.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd4510]
>[ 24184.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd4510] width 1280 pitch 5120 (/4 1280)
>[ 24184.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24184.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24184.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24184.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24184.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24184.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24184.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24184.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24184.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24184.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24185.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24185.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24185.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24185.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24185.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24185.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24185.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24185.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24185.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24185.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24185.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24185.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24185.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24185.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24185.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24185.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24185.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24185.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24186.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24186.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24186.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24186.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24186.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24186.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24186.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24186.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24186.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24186.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24186.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24186.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24186.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24186.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24186.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24186.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24186.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24186.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24187.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24187.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24187.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24187.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24187.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24187.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24187.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24187.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24187.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24187.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24187.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24187.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24187.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24187.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24187.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24187.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24187.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24187.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24188.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24188.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24188.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24188.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24188.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24188.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24188.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24188.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24188.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24188.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24188.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24188.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24188.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24188.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24188.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24188.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24188.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24188.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24189.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24189.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24189.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24189.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24189.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24189.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24189.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24189.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24189.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24189.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24189.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24189.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24189.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24189.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24189.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24189.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24189.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24189.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24190.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24190.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24190.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24190.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24190.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24190.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24190.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24190.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24190.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24190.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24190.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24190.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24190.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24190.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24190.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24190.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24190.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24190.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24191.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24191.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24191.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24191.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24191.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24191.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24191.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24191.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24191.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24191.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24191.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24191.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24191.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24191.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24191.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24191.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24191.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24191.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24192.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24192.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24192.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24192.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24192.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24192.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24192.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24192.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24192.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24192.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24192.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24192.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24192.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24192.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24192.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24192.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24192.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24192.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24193.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24193.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24193.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24193.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24193.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24193.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24193.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24193.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24193.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24193.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24193.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24193.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24193.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24193.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24193.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24193.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24193.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24193.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24194.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24194.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24194.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24194.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24194.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24194.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24194.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24194.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24194.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24194.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24194.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24194.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24194.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24194.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24194.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24194.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24194.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24194.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24195.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24195.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24195.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24195.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24195.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24195.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24195.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24195.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24195.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24195.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24195.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24195.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24195.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24195.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24195.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24195.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24195.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24195.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24196.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24196.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24196.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24196.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24196.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24196.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24196.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24196.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24196.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24196.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24196.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24196.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24196.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24196.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24196.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24196.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24196.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24196.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24197.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24197.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24197.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24197.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24197.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24197.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24197.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24197.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24197.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24197.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24197.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24197.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24197.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24197.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24197.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24197.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24197.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24197.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24198.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24198.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24198.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24198.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24198.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24198.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24198.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24198.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24198.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24198.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24198.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd41d0]
>[ 24198.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd41d0] width 1280 pitch 5120 (/4 1280)
>[ 24198.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24198.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24198.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24198.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24198.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24198.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24199.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24199.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24199.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24199.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24199.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24199.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24199.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24199.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24200.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24200.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24200.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24200.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24200.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24200.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24200.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24200.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24200.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24200.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24200.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24200.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24200.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24200.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24200.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24200.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24203.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24203.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24203.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24203.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24204.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa948]
>[ 24204.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa948] width 1280 pitch 5120 (/4 1280)
>[ 24204.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24204.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24204.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24204.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24204.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24204.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24204.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24204.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24209.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24209.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24209.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24209.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24209.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24209.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24209.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24209.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24209.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24209.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24209.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24209.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24209.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24209.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24210.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24210.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24210.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24210.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24210.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24210.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24210.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24210.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24210.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24210.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24213.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24213.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24216.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24216.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24216.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24216.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24226.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24226.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24229.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24229.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24230.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dc7100]
>[ 24230.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dc7100] width 1280 pitch 5120 (/4 1280)
>[ 24231.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f1bfa0]
>[ 24231.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f1bfa0] width 1280 pitch 5120 (/4 1280)
>[ 24231.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24231.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24231.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24231.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24231.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24231.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24231.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24231.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24231.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6588]
>[ 24231.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6588] width 1280 pitch 5120 (/4 1280)
>[ 24233.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea93c8]
>[ 24233.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea93c8] width 1280 pitch 5120 (/4 1280)
>[ 24233.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24233.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24233.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24233.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24234.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24234.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24234.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ffd678]
>[ 24234.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ffd678] width 1280 pitch 5120 (/4 1280)
>[ 24234.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ee54d8]
>[ 24234.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ee54d8] width 1280 pitch 5120 (/4 1280)
>[ 24282.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39928]
>[ 24282.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39928] width 1280 pitch 5120 (/4 1280)
>[ 24282.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eceaa8]
>[ 24282.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eceaa8] width 1280 pitch 5120 (/4 1280)
>[ 24282.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f39928]
>[ 24282.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f39928] width 1280 pitch 5120 (/4 1280)
>[ 24285.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7a518]
>[ 24285.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7a518] width 1280 pitch 5120 (/4 1280)
>[ 24285.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbf578]
>[ 24285.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbf578] width 1280 pitch 5120 (/4 1280)
>[ 24285.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dcd020]
>[ 24285.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dcd020] width 1280 pitch 5120 (/4 1280)
>[ 24286.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c7c648]
>[ 24286.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c7c648] width 1280 pitch 5120 (/4 1280)
>[ 24288.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca018]
>[ 24288.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca018] width 1280 pitch 5120 (/4 1280)
>[ 24288.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24288.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24425.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a8f0]
>[ 24425.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a8f0] width 1280 pitch 5120 (/4 1280)
>[ 24425.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cca018]
>[ 24425.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cca018] width 1280 pitch 5120 (/4 1280)
>[ 24425.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a8f0]
>[ 24425.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a8f0] width 1280 pitch 5120 (/4 1280)
>[ 24425.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24425.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24425.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a8f0]
>[ 24425.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a8f0] width 1280 pitch 5120 (/4 1280)
>[ 24425.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24425.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24426.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24426.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24428.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa006f28]
>[ 24428.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa006f28] width 1280 pitch 5120 (/4 1280)
>[ 24428.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa006f28]
>[ 24428.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa006f28] width 1280 pitch 5120 (/4 1280)
>[ 24428.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa006f28]
>[ 24428.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa006f28] width 1280 pitch 5120 (/4 1280)
>[ 24428.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0102e0]
>[ 24428.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0102e0] width 1280 pitch 5120 (/4 1280)
>[ 24482.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e3eaa8]
>[ 24482.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e3eaa8] width 1280 pitch 5120 (/4 1280)
>[ 24491.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa158148]
>[ 24491.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa158148] width 1280 pitch 5120 (/4 1280)
>[ 24491.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0f8e98]
>[ 24491.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0f8e98] width 1280 pitch 5120 (/4 1280)
>[ 24491.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df8c88]
>[ 24491.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df8c88] width 1280 pitch 5120 (/4 1280)
>[ 24492.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dfed40]
>[ 24492.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dfed40] width 1280 pitch 5120 (/4 1280)
>[ 24492.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9dff0]
>[ 24492.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9dff0] width 1280 pitch 5120 (/4 1280)
>[ 24492.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa027e08]
>[ 24492.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa027e08] width 1280 pitch 5120 (/4 1280)
>[ 24526.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb67f0]
>[ 24526.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb67f0] width 1280 pitch 5120 (/4 1280)
>[ 24526.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2f570]
>[ 24526.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2f570] width 1280 pitch 5120 (/4 1280)
>[ 24526.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24526.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24526.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e0ad18]
>[ 24526.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e0ad18] width 1280 pitch 5120 (/4 1280)
>[ 24532.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b76dd0]
>[ 24532.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b76dd0] width 1280 pitch 5120 (/4 1280)
>[ 24532.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24532.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24532.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e0ad18]
>[ 24532.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e0ad18] width 1280 pitch 5120 (/4 1280)
>[ 24532.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fdd5d0]
>[ 24532.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fdd5d0] width 1280 pitch 5120 (/4 1280)
>[ 24543.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035af8]
>[ 24543.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035af8] width 1280 pitch 5120 (/4 1280)
>[ 24543.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035b98]
>[ 24543.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035b98] width 1280 pitch 5120 (/4 1280)
>[ 24543.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb67f0]
>[ 24543.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb67f0] width 1280 pitch 5120 (/4 1280)
>[ 24543.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035b98]
>[ 24543.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035b98] width 1280 pitch 5120 (/4 1280)
>[ 24545.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2f570]
>[ 24545.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2f570] width 1280 pitch 5120 (/4 1280)
>[ 24545.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035af8]
>[ 24545.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035af8] width 1280 pitch 5120 (/4 1280)
>[ 24546.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 24546.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 24546.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbdef0]
>[ 24546.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbdef0] width 1280 pitch 5120 (/4 1280)
>[ 24575.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035b98]
>[ 24575.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035b98] width 1280 pitch 5120 (/4 1280)
>[ 24578.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035b98]
>[ 24578.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035b98] width 1280 pitch 5120 (/4 1280)
>[ 24578.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dbebb0]
>[ 24578.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dbebb0] width 1280 pitch 5120 (/4 1280)
>[ 24578.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa948]
>[ 24578.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa948] width 1280 pitch 5120 (/4 1280)
>[ 24578.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb550]
>[ 24578.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb550] width 1280 pitch 5120 (/4 1280)
>[ 24580.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24580.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24580.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24580.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24580.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 24580.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 24580.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f32c48]
>[ 24580.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f32c48] width 1280 pitch 5120 (/4 1280)
>[ 24580.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f32c48]
>[ 24580.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f32c48] width 1280 pitch 5120 (/4 1280)
>[ 24581.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490a0]
>[ 24581.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490a0] width 1280 pitch 5120 (/4 1280)
>[ 24581.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6b7e8]
>[ 24581.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6b7e8] width 1280 pitch 5120 (/4 1280)
>[ 24582.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc980]
>[ 24582.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc980] width 1280 pitch 5120 (/4 1280)
>[ 24583.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490a0]
>[ 24583.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490a0] width 1280 pitch 5120 (/4 1280)
>[ 24583.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c4e8a0]
>[ 24583.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c4e8a0] width 1280 pitch 5120 (/4 1280)
>[ 24583.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2f9c0]
>[ 24583.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2f9c0] width 1280 pitch 5120 (/4 1280)
>[ 24618.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f7dd28]
>[ 24618.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f7dd28] width 1280 pitch 5120 (/4 1280)
>[ 24619.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24619.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24619.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24619.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24619.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24619.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24671.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24671.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24671.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24671.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24671.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24671.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24671.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24671.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24672.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24672.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24672.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24672.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24672.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 24672.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 24672.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24672.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24717.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ff7090]
>[ 24717.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ff7090] width 1280 pitch 5120 (/4 1280)
>[ 24717.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2f9c8]
>[ 24717.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2f9c8] width 1280 pitch 5120 (/4 1280)
>[ 24718.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dba270]
>[ 24718.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dba270] width 1280 pitch 5120 (/4 1280)
>[ 24718.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24718.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24720.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11e6e0]
>[ 24720.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11e6e0] width 1280 pitch 5120 (/4 1280)
>[ 24720.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7160]
>[ 24720.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7160] width 1280 pitch 5120 (/4 1280)
>[ 24720.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24720.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24720.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ea7160]
>[ 24720.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ea7160] width 1280 pitch 5120 (/4 1280)
>[ 24730.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24730.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24730.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f720]
>[ 24730.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f720] width 1280 pitch 5120 (/4 1280)
>[ 24730.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c96a20]
>[ 24730.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c96a20] width 1280 pitch 5120 (/4 1280)
>[ 24730.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2d9b0]
>[ 24731.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2d9b0] width 1280 pitch 5120 (/4 1280)
>[ 24731.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c966c0]
>[ 24731.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c966c0] width 1280 pitch 5120 (/4 1280)
>[ 24731.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24731.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24739.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24739.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24739.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24739.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24739.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24739.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24739.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24739.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24740.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24740.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24740.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24740.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24741.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24741.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24741.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24741.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24741.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24741.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24741.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24742.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24746.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24746.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24746.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24746.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24753.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24753.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24753.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24753.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24753.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24753.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24753.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24753.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24753.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24753.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24753.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24753.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24753.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24753.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24753.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 24753.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 24754.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24754.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24754.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24754.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24754.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24754.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24755.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24755.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24755.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24755.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24755.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24755.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24755.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24756.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24756.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24756.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24758.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24758.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24766.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24766.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24766.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24766.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24768.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24768.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24772.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24772.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24772.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24772.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24772.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24772.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24772.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24772.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24772.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24772.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24790.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b2c8f0]
>[ 24790.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b2c8f0] width 1280 pitch 5120 (/4 1280)
>[ 24792.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24792.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24792.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf6ce8]
>[ 24792.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf6ce8] width 1280 pitch 5120 (/4 1280)
>[ 24792.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ebf8e8]
>[ 24792.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ebf8e8] width 1280 pitch 5120 (/4 1280)
>[ 24799.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9be4a08]
>[ 24799.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9be4a08] width 1280 pitch 5120 (/4 1280)
>[ 24807.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dd1968]
>[ 24807.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dd1968] width 1280 pitch 5120 (/4 1280)
>[ 24807.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd09f0]
>[ 24807.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd09f0] width 1280 pitch 5120 (/4 1280)
>[ 24807.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa00bab8]
>[ 24807.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa00bab8] width 1280 pitch 5120 (/4 1280)
>[ 24819.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e821d0]
>[ 24819.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e821d0] width 1280 pitch 5120 (/4 1280)
>[ 24863.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa020b78]
>[ 24863.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa020b78] width 1280 pitch 5120 (/4 1280)
>[ 24871.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c98f58]
>[ 24871.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c98f58] width 1280 pitch 5120 (/4 1280)
>[ 24873.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9efaba8]
>[ 24873.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9efaba8] width 1280 pitch 5120 (/4 1280)
>[ 24873.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd09f0]
>[ 24873.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd09f0] width 1280 pitch 5120 (/4 1280)
>[ 24873.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e69010]
>[ 24873.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e69010] width 1280 pitch 5120 (/4 1280)
>[ 24875.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e69010]
>[ 24875.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e69010] width 1280 pitch 5120 (/4 1280)
>[ 24875.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa03a270]
>[ 24875.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa03a270] width 1280 pitch 5120 (/4 1280)
>[ 24875.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de8ee0]
>[ 24875.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de8ee0] width 1280 pitch 5120 (/4 1280)
>[ 24875.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b86d60]
>[ 24875.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b86d60] width 1280 pitch 5120 (/4 1280)
>[ 24876.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcf730]
>[ 24876.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcf730] width 1280 pitch 5120 (/4 1280)
>[ 24877.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd09f0]
>[ 24877.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd09f0] width 1280 pitch 5120 (/4 1280)
>[ 24877.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd09f0]
>[ 24877.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd09f0] width 1280 pitch 5120 (/4 1280)
>[ 24877.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 24877.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 24995.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c48790]
>[ 24995.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c48790] width 1280 pitch 5120 (/4 1280)
>[ 24995.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b86d60]
>[ 24995.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b86d60] width 1280 pitch 5120 (/4 1280)
>[ 24996.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf7298]
>[ 24996.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf7298] width 1280 pitch 5120 (/4 1280)
>[ 24996.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 24996.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 25001.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 25001.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 25001.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d73590]
>[ 25001.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d73590] width 1280 pitch 5120 (/4 1280)
>[ 25010.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e862b8]
>[ 25010.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e862b8] width 1280 pitch 5120 (/4 1280)
>[ 25017.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f528]
>[ 25017.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f528] width 1280 pitch 5120 (/4 1280)
>[ 25017.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7dc98]
>[ 25017.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7dc98] width 1280 pitch 5120 (/4 1280)
>[ 25018.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f528]
>[ 25018.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f528] width 1280 pitch 5120 (/4 1280)
>[ 25018.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7dc98]
>[ 25018.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7dc98] width 1280 pitch 5120 (/4 1280)
>[ 25021.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f528]
>[ 25021.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f528] width 1280 pitch 5120 (/4 1280)
>[ 25026.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cb22c0]
>[ 25026.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cb22c0] width 1280 pitch 5120 (/4 1280)
>[ 25026.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6a88]
>[ 25026.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6a88] width 1280 pitch 5120 (/4 1280)
>[ 25035.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf7298]
>[ 25035.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf7298] width 1280 pitch 5120 (/4 1280)
>[ 25037.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0209c8]
>[ 25037.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0209c8] width 1280 pitch 5120 (/4 1280)
>[ 25040.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bcc00]
>[ 25040.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bcc00] width 1280 pitch 5120 (/4 1280)
>[ 25041.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa948]
>[ 25041.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa948] width 1280 pitch 5120 (/4 1280)
>[ 25044.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e083b0]
>[ 25044.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e083b0] width 1280 pitch 5120 (/4 1280)
>[ 25044.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b520]
>[ 25044.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b520] width 1280 pitch 5120 (/4 1280)
>[ 25044.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8a08]
>[ 25044.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8a08] width 1280 pitch 5120 (/4 1280)
>[ 25044.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b520]
>[ 25044.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b520] width 1280 pitch 5120 (/4 1280)
>[ 25044.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035998]
>[ 25044.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035998] width 1280 pitch 5120 (/4 1280)
>[ 25044.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8a08]
>[ 25044.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8a08] width 1280 pitch 5120 (/4 1280)
>[ 25044.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035998]
>[ 25044.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035998] width 1280 pitch 5120 (/4 1280)
>[ 25044.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8a08]
>[ 25044.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8a08] width 1280 pitch 5120 (/4 1280)
>[ 25044.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035998]
>[ 25044.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035998] width 1280 pitch 5120 (/4 1280)
>[ 25044.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8a08]
>[ 25044.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8a08] width 1280 pitch 5120 (/4 1280)
>[ 25044.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035998]
>[ 25044.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035998] width 1280 pitch 5120 (/4 1280)
>[ 25045.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa035998]
>[ 25045.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa035998] width 1280 pitch 5120 (/4 1280)
>[ 25047.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c8be0]
>[ 25047.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c8be0] width 1280 pitch 5120 (/4 1280)
>[ 25047.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4a28]
>[ 25047.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4a28] width 1280 pitch 5120 (/4 1280)
>[ 25047.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bceb18]
>[ 25047.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bceb18] width 1280 pitch 5120 (/4 1280)
>[ 25047.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4a28]
>[ 25047.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4a28] width 1280 pitch 5120 (/4 1280)
>[ 25047.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bceb18]
>[ 25047.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bceb18] width 1280 pitch 5120 (/4 1280)
>[ 25047.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4a28]
>[ 25047.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4a28] width 1280 pitch 5120 (/4 1280)
>[ 25047.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bceb18]
>[ 25047.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bceb18] width 1280 pitch 5120 (/4 1280)
>[ 25047.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4a28]
>[ 25047.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4a28] width 1280 pitch 5120 (/4 1280)
>[ 25057.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed69f8]
>[ 25057.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed69f8] width 1280 pitch 5120 (/4 1280)
>[ 25061.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25061.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25061.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 25061.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 25120.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e73f98]
>[ 25120.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e73f98] width 1280 pitch 5120 (/4 1280)
>[ 25121.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d6e3c0]
>[ 25121.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d6e3c0] width 1280 pitch 5120 (/4 1280)
>[ 25126.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb3308]
>[ 25126.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb3308] width 1280 pitch 5120 (/4 1280)
>[ 25133.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02b690]
>[ 25133.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02b690] width 1280 pitch 5120 (/4 1280)
>[ 25136.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9de8ee0]
>[ 25137.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9de8ee0] width 1280 pitch 5120 (/4 1280)
>[ 25137.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa021780]
>[ 25137.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa021780] width 1280 pitch 5120 (/4 1280)
>[ 25137.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4da68]
>[ 25137.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4da68] width 1280 pitch 5120 (/4 1280)
>[ 25137.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa021780]
>[ 25137.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa021780] width 1280 pitch 5120 (/4 1280)
>[ 25137.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4da68]
>[ 25137.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4da68] width 1280 pitch 5120 (/4 1280)
>[ 25137.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa021780]
>[ 25137.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa021780] width 1280 pitch 5120 (/4 1280)
>[ 25137.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4da68]
>[ 25137.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4da68] width 1280 pitch 5120 (/4 1280)
>[ 25137.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa021780]
>[ 25137.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa021780] width 1280 pitch 5120 (/4 1280)
>[ 25137.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4da68]
>[ 25137.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4da68] width 1280 pitch 5120 (/4 1280)
>[ 25137.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa021780]
>[ 25137.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa021780] width 1280 pitch 5120 (/4 1280)
>[ 25176.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7c8b0]
>[ 25176.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7c8b0] width 1280 pitch 5120 (/4 1280)
>[ 25177.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f4da68]
>[ 25177.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f4da68] width 1280 pitch 5120 (/4 1280)
>[ 25178.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa013f00]
>[ 25178.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa013f00] width 1280 pitch 5120 (/4 1280)
>[ 25178.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e033c8]
>[ 25178.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e033c8] width 1280 pitch 5120 (/4 1280)
>[ 25178.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa013f00]
>[ 25178.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa013f00] width 1280 pitch 5120 (/4 1280)
>[ 25178.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e033c8]
>[ 25178.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e033c8] width 1280 pitch 5120 (/4 1280)
>[ 25178.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b86a10]
>[ 25178.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b86a10] width 1280 pitch 5120 (/4 1280)
>[ 25178.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa013f00]
>[ 25178.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa013f00] width 1280 pitch 5120 (/4 1280)
>[ 25220.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b865d0]
>[ 25220.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b865d0] width 1280 pitch 5120 (/4 1280)
>[ 25222.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8cb20]
>[ 25222.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8cb20] width 1280 pitch 5120 (/4 1280)
>[ 25222.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b864f8]
>[ 25222.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b864f8] width 1280 pitch 5120 (/4 1280)
>[ 25222.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8cb20]
>[ 25222.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8cb20] width 1280 pitch 5120 (/4 1280)
>[ 25228.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25228.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25228.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb2b18]
>[ 25228.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb2b18] width 1280 pitch 5120 (/4 1280)
>[ 25235.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb2b18]
>[ 25235.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb2b18] width 1280 pitch 5120 (/4 1280)
>[ 25285.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490d0]
>[ 25285.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490d0] width 1280 pitch 5120 (/4 1280)
>[ 25285.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0881c0]
>[ 25285.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0881c0] width 1280 pitch 5120 (/4 1280)
>[ 25300.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3bbf8]
>[ 25300.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3bbf8] width 1280 pitch 5120 (/4 1280)
>[ 25305.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf18]
>[ 25305.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf18] width 1280 pitch 5120 (/4 1280)
>[ 25327.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa109c98]
>[ 25327.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa109c98] width 1280 pitch 5120 (/4 1280)
>[ 25327.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11d318]
>[ 25327.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11d318] width 1280 pitch 5120 (/4 1280)
>[ 25327.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa109c98]
>[ 25327.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa109c98] width 1280 pitch 5120 (/4 1280)
>[ 25327.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11d318]
>[ 25327.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11d318] width 1280 pitch 5120 (/4 1280)
>[ 25388.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11ac20]
>[ 25388.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11ac20] width 1280 pitch 5120 (/4 1280)
>[ 25388.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d4c690]
>[ 25388.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d4c690] width 1280 pitch 5120 (/4 1280)
>[ 25389.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11b6d0]
>[ 25389.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11b6d0] width 1280 pitch 5120 (/4 1280)
>[ 25389.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1a8f0]
>[ 25389.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1a8f0] width 1280 pitch 5120 (/4 1280)
>[ 25389.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd0ae0]
>[ 25389.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd0ae0] width 1280 pitch 5120 (/4 1280)
>[ 25401.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25401.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25401.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25401.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25401.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25401.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb8d0]
>[ 25401.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb8d0] width 1280 pitch 5120 (/4 1280)
>[ 25401.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d1d710]
>[ 25401.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d1d710] width 1280 pitch 5120 (/4 1280)
>[ 25401.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e6ea00]
>[ 25401.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e6ea00] width 1280 pitch 5120 (/4 1280)
>[ 25401.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0cc610]
>[ 25401.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0cc610] width 1280 pitch 5120 (/4 1280)
>[ 25401.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25401.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25407.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9d920]
>[ 25407.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9d920] width 1280 pitch 5120 (/4 1280)
>[ 25407.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1e9608]
>[ 25407.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1e9608] width 1280 pitch 5120 (/4 1280)
>[ 25407.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9d920]
>[ 25407.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9d920] width 1280 pitch 5120 (/4 1280)
>[ 25407.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9d920]
>[ 25407.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9d920] width 1280 pitch 5120 (/4 1280)
>[ 25407.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9d920]
>[ 25407.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9d920] width 1280 pitch 5120 (/4 1280)
>[ 25407.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb8d0]
>[ 25407.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb8d0] width 1280 pitch 5120 (/4 1280)
>[ 25407.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb8d0]
>[ 25407.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb8d0] width 1280 pitch 5120 (/4 1280)
>[ 25407.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb8d0]
>[ 25407.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb8d0] width 1280 pitch 5120 (/4 1280)
>[ 25407.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25407.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb8d0]
>[ 25407.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb8d0] width 1280 pitch 5120 (/4 1280)
>[ 25407.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25407.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25428.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1380a0]
>[ 25428.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1380a0] width 1280 pitch 5120 (/4 1280)
>[ 25430.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f408]
>[ 25430.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f408] width 1280 pitch 5120 (/4 1280)
>[ 25430.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa114560]
>[ 25430.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa114560] width 1280 pitch 5120 (/4 1280)
>[ 25430.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b87a10]
>[ 25430.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b87a10] width 1280 pitch 5120 (/4 1280)
>[ 25431.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25431.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25431.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa8d8]
>[ 25431.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa8d8] width 1280 pitch 5120 (/4 1280)
>[ 25431.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25431.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25431.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa8d8]
>[ 25431.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa8d8] width 1280 pitch 5120 (/4 1280)
>[ 25431.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25431.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25431.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa8d8]
>[ 25431.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa8d8] width 1280 pitch 5120 (/4 1280)
>[ 25431.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25431.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25431.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0fa8d8]
>[ 25431.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0fa8d8] width 1280 pitch 5120 (/4 1280)
>[ 25431.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25431.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25438.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25438.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25439.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25439.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25440.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25440.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25441.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25441.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25441.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25441.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25441.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25442.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25442.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25442.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25443.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 25443.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 25446.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f45178]
>[ 25446.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f45178] width 1280 pitch 5120 (/4 1280)
>[ 25447.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcb610]
>[ 25447.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcb610] width 1280 pitch 5120 (/4 1280)
>[ 25457.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f44638]
>[ 25457.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f44638] width 1280 pitch 5120 (/4 1280)
>[ 25480.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f387f0]
>[ 25480.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f387f0] width 1280 pitch 5120 (/4 1280)
>[ 25480.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5230]
>[ 25480.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5230] width 1280 pitch 5120 (/4 1280)
>[ 25480.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9efa110]
>[ 25480.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9efa110] width 1280 pitch 5120 (/4 1280)
>[ 25480.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5320]
>[ 25480.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5320] width 1280 pitch 5120 (/4 1280)
>[ 25480.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5230]
>[ 25480.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5230] width 1280 pitch 5120 (/4 1280)
>[ 25480.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5320]
>[ 25480.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5320] width 1280 pitch 5120 (/4 1280)
>[ 25480.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5230]
>[ 25480.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5230] width 1280 pitch 5120 (/4 1280)
>[ 25480.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5320]
>[ 25481.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5320] width 1280 pitch 5120 (/4 1280)
>[ 25481.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5230]
>[ 25481.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5230] width 1280 pitch 5120 (/4 1280)
>[ 25481.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490d0]
>[ 25481.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490d0] width 1280 pitch 5120 (/4 1280)
>[ 25481.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25481.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25481.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490d0]
>[ 25481.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490d0] width 1280 pitch 5120 (/4 1280)
>[ 25481.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25481.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25481.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9efa110]
>[ 25481.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9efa110] width 1280 pitch 5120 (/4 1280)
>[ 25481.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcadd0]
>[ 25481.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcadd0] width 1280 pitch 5120 (/4 1280)
>[ 25481.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9efa110]
>[ 25481.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9efa110] width 1280 pitch 5120 (/4 1280)
>[ 25481.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8cb20]
>[ 25481.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8cb20] width 1280 pitch 5120 (/4 1280)
>[ 25481.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 25481.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 25481.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c5320]
>[ 25481.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c5320] width 1280 pitch 5120 (/4 1280)
>[ 25492.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25492.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25492.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cfb0]
>[ 25492.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cfb0] width 1280 pitch 5120 (/4 1280)
>[ 25492.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cfb0]
>[ 25493.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cfb0] width 1280 pitch 5120 (/4 1280)
>[ 25493.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cfb0]
>[ 25493.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cfb0] width 1280 pitch 5120 (/4 1280)
>[ 25493.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bdd60]
>[ 25493.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bdd60] width 1280 pitch 5120 (/4 1280)
>[ 25493.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bdd60]
>[ 25493.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bdd60] width 1280 pitch 5120 (/4 1280)
>[ 25493.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bdd60]
>[ 25493.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bdd60] width 1280 pitch 5120 (/4 1280)
>[ 25493.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25493.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0bdd60]
>[ 25493.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0bdd60] width 1280 pitch 5120 (/4 1280)
>[ 25493.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3210]
>[ 25493.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3210] width 1280 pitch 5120 (/4 1280)
>[ 25618.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25618.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25618.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38538]
>[ 25618.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38538] width 1280 pitch 5120 (/4 1280)
>[ 25618.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25618.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25618.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38538]
>[ 25618.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38538] width 1280 pitch 5120 (/4 1280)
>[ 25618.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25618.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25618.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38538]
>[ 25618.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38538] width 1280 pitch 5120 (/4 1280)
>[ 25618.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25618.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25618.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f38538]
>[ 25619.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f38538] width 1280 pitch 5120 (/4 1280)
>[ 25619.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25619.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25619.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25619.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25619.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3270]
>[ 25619.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3270] width 1280 pitch 5120 (/4 1280)
>[ 25619.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d39c8]
>[ 25619.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d39c8] width 1280 pitch 5120 (/4 1280)
>[ 25619.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3270]
>[ 25619.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3270] width 1280 pitch 5120 (/4 1280)
>[ 25619.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e648f8]
>[ 25619.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e648f8] width 1280 pitch 5120 (/4 1280)
>[ 25619.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d3270]
>[ 25619.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d3270] width 1280 pitch 5120 (/4 1280)
>[ 25653.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa124d00]
>[ 25653.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa124d00] width 1280 pitch 5120 (/4 1280)
>[ 25655.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d968d0]
>[ 25655.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d968d0] width 1280 pitch 5120 (/4 1280)
>[ 25656.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d96060]
>[ 25656.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d96060] width 1280 pitch 5120 (/4 1280)
>[ 25675.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10b600]
>[ 25675.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10b600] width 1280 pitch 5120 (/4 1280)
>[ 25688.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 25688.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 25688.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 25688.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 25688.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7b878]
>[ 25688.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7b878] width 1280 pitch 5120 (/4 1280)
>[ 25688.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 25688.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 25688.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7b878]
>[ 25688.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7b878] width 1280 pitch 5120 (/4 1280)
>[ 25688.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d816d8]
>[ 25688.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d816d8] width 1280 pitch 5120 (/4 1280)
>[ 25688.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa134dd0]
>[ 25688.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa134dd0] width 1280 pitch 5120 (/4 1280)
>[ 25693.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7b848]
>[ 25693.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7b848] width 1280 pitch 5120 (/4 1280)
>[ 25702.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa164f00]
>[ 25702.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa164f00] width 1280 pitch 5120 (/4 1280)
>[ 25711.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 25711.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 25711.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa164628]
>[ 25711.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa164628] width 1280 pitch 5120 (/4 1280)
>[ 25711.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 25711.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 25711.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa164628]
>[ 25711.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa164628] width 1280 pitch 5120 (/4 1280)
>[ 25711.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6700]
>[ 25711.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6700] width 1280 pitch 5120 (/4 1280)
>[ 25711.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e561a0]
>[ 25711.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e561a0] width 1280 pitch 5120 (/4 1280)
>[ 25711.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0c4810]
>[ 25711.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0c4810] width 1280 pitch 5120 (/4 1280)
>[ 25711.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e561a0]
>[ 25711.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e561a0] width 1280 pitch 5120 (/4 1280)
>[ 25711.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6700]
>[ 25711.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6700] width 1280 pitch 5120 (/4 1280)
>[ 25718.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d9bac8]
>[ 25718.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d9bac8] width 1280 pitch 5120 (/4 1280)
>[ 25720.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e56170]
>[ 25720.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e56170] width 1280 pitch 5120 (/4 1280)
>[ 25734.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cf18]
>[ 25734.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cf18] width 1280 pitch 5120 (/4 1280)
>[ 25734.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cf18]
>[ 25734.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cf18] width 1280 pitch 5120 (/4 1280)
>[ 25734.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10cf18]
>[ 25734.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10cf18] width 1280 pitch 5120 (/4 1280)
>[ 25734.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1631b0]
>[ 25734.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1631b0] width 1280 pitch 5120 (/4 1280)
>[ 25734.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1631b0]
>[ 25734.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1631b0] width 1280 pitch 5120 (/4 1280)
>[ 25734.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1631b0]
>[ 25734.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1631b0] width 1280 pitch 5120 (/4 1280)
>[ 25734.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25734.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1631b0]
>[ 25734.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1631b0] width 1280 pitch 5120 (/4 1280)
>[ 25734.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25734.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25739.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163088]
>[ 25739.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163088] width 1280 pitch 5120 (/4 1280)
>[ 25739.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163088]
>[ 25739.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163088] width 1280 pitch 5120 (/4 1280)
>[ 25739.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163088]
>[ 25739.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163088] width 1280 pitch 5120 (/4 1280)
>[ 25739.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163088]
>[ 25739.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163088] width 1280 pitch 5120 (/4 1280)
>[ 25739.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163088]
>[ 25739.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163088] width 1280 pitch 5120 (/4 1280)
>[ 25739.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa136540]
>[ 25739.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa136540] width 1280 pitch 5120 (/4 1280)
>[ 25739.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1632d8]
>[ 25739.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1632d8] width 1280 pitch 5120 (/4 1280)
>[ 25739.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da1300]
>[ 25739.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da1300] width 1280 pitch 5120 (/4 1280)
>[ 25885.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa167b68]
>[ 25885.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa167b68] width 1280 pitch 5120 (/4 1280)
>[ 25976.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1677f8]
>[ 25976.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1677f8] width 1280 pitch 5120 (/4 1280)
>[ 25978.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca00a0]
>[ 25978.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca00a0] width 1280 pitch 5120 (/4 1280)
>[ 25978.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0ba1c8]
>[ 25978.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0ba1c8] width 1280 pitch 5120 (/4 1280)
>[ 25978.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cc00]
>[ 25979.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cc00] width 1280 pitch 5120 (/4 1280)
>[ 25979.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e821d0]
>[ 25979.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e821d0] width 1280 pitch 5120 (/4 1280)
>[ 25989.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9efa1a8]
>[ 25989.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9efa1a8] width 1280 pitch 5120 (/4 1280)
>[ 25989.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10b570]
>[ 25989.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10b570] width 1280 pitch 5120 (/4 1280)
>[ 26016.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa22f9d0]
>[ 26016.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa22f9d0] width 1280 pitch 5120 (/4 1280)
>[ 26026.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc03a8]
>[ 26026.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc03a8] width 1280 pitch 5120 (/4 1280)
>[ 26026.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc03f8]
>[ 26026.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc03f8] width 1280 pitch 5120 (/4 1280)
>[ 26026.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc03a8]
>[ 26026.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc03a8] width 1280 pitch 5120 (/4 1280)
>[ 26026.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc03f8]
>[ 26026.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc03f8] width 1280 pitch 5120 (/4 1280)
>[ 26048.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b5e20]
>[ 26048.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b5e20] width 1280 pitch 5120 (/4 1280)
>[ 26048.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da0290]
>[ 26048.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da0290] width 1280 pitch 5120 (/4 1280)
>[ 26049.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b5d30]
>[ 26049.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b5d30] width 1280 pitch 5120 (/4 1280)
>[ 26049.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fd38b0]
>[ 26049.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fd38b0] width 1280 pitch 5120 (/4 1280)
>[ 26049.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6a88]
>[ 26049.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6a88] width 1280 pitch 5120 (/4 1280)
>[ 26049.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f2f760]
>[ 26049.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f2f760] width 1280 pitch 5120 (/4 1280)
>[ 26049.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ed6a88]
>[ 26049.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ed6a88] width 1280 pitch 5120 (/4 1280)
>[ 26049.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c8cb20]
>[ 26049.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c8cb20] width 1280 pitch 5120 (/4 1280)
>[ 26049.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf08]
>[ 26049.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf08] width 1280 pitch 5120 (/4 1280)
>[ 26049.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cf68]
>[ 26049.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cf68] width 1280 pitch 5120 (/4 1280)
>[ 26049.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da8fc8]
>[ 26049.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da8fc8] width 1280 pitch 5120 (/4 1280)
>[ 26049.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f300]
>[ 26049.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f300] width 1280 pitch 5120 (/4 1280)
>[ 26049.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10b570]
>[ 26049.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10b570] width 1280 pitch 5120 (/4 1280)
>[ 26062.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b7f50]
>[ 26062.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b7f50] width 1280 pitch 5120 (/4 1280)
>[ 26068.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa0b8ca8]
>[ 26068.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa0b8ca8] width 1280 pitch 5120 (/4 1280)
>[ 26073.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1d2f60]
>[ 26073.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1d2f60] width 1280 pitch 5120 (/4 1280)
>[ 26074.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa127e98]
>[ 26074.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa127e98] width 1280 pitch 5120 (/4 1280)
>[ 26074.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa02df40]
>[ 26074.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa02df40] width 1280 pitch 5120 (/4 1280)
>[ 26074.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa127e98]
>[ 26074.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa127e98] width 1280 pitch 5120 (/4 1280)
>[ 26074.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa126028]
>[ 26074.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa126028] width 1280 pitch 5120 (/4 1280)
>[ 26090.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa103a80]
>[ 26090.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa103a80] width 1280 pitch 5120 (/4 1280)
>[ 26090.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26090.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26090.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26090.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26090.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26090.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26090.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26090.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26090.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26090.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26090.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26090.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26090.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26090.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26090.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26090.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26090.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26090.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26090.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26091.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26091.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26091.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26091.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa163b80]
>[ 26091.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa163b80] width 1280 pitch 5120 (/4 1280)
>[ 26091.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 26091.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 26109.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e83a88]
>[ 26109.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e83a88] width 1280 pitch 5120 (/4 1280)
>[ 26122.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b17828]
>[ 26122.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b17828] width 1280 pitch 5120 (/4 1280)
>[ 26124.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa137350]
>[ 26124.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa137350] width 1280 pitch 5120 (/4 1280)
>[ 26124.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e84168]
>[ 26124.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e84168] width 1280 pitch 5120 (/4 1280)
>[ 26124.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa137350]
>[ 26124.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa137350] width 1280 pitch 5120 (/4 1280)
>[ 26742.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa137298]
>[ 26742.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa137298] width 1280 pitch 5120 (/4 1280)
>[ 26750.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa105d30]
>[ 26750.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa105d30] width 1280 pitch 5120 (/4 1280)
>[ 26759.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c490d0]
>[ 26759.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c490d0] width 1280 pitch 5120 (/4 1280)
>[ 26759.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ecc5c8]
>[ 26759.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ecc5c8] width 1280 pitch 5120 (/4 1280)
>[ 26759.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb46a0]
>[ 26759.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb46a0] width 1280 pitch 5120 (/4 1280)
>[ 26759.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da2ba8]
>[ 26759.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da2ba8] width 1280 pitch 5120 (/4 1280)
>[ 26759.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b7f300]
>[ 26759.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b7f300] width 1280 pitch 5120 (/4 1280)
>[ 26759.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9eb8088]
>[ 26759.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9eb8088] width 1280 pitch 5120 (/4 1280)
>[ 26766.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da11a8]
>[ 26766.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da11a8] width 1280 pitch 5120 (/4 1280)
>[ 26777.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b18178]
>[ 26777.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b18178] width 1280 pitch 5120 (/4 1280)
>[ 26814.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da17a0]
>[ 26814.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da17a0] width 1280 pitch 5120 (/4 1280)
>[ 26816.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7aae0]
>[ 26816.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7aae0] width 1280 pitch 5120 (/4 1280)
>[ 26816.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26816.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26816.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7aae0]
>[ 26816.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7aae0] width 1280 pitch 5120 (/4 1280)
>[ 26816.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26816.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26816.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7aae0]
>[ 26816.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7aae0] width 1280 pitch 5120 (/4 1280)
>[ 26817.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26817.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26817.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7aae0]
>[ 26817.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7aae0] width 1280 pitch 5120 (/4 1280)
>[ 26817.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26817.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26817.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d7aae0]
>[ 26817.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d7aae0] width 1280 pitch 5120 (/4 1280)
>[ 26819.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d833c0]
>[ 26819.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d833c0] width 1280 pitch 5120 (/4 1280)
>[ 26819.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26819.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26819.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd3748]
>[ 26819.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd3748] width 1280 pitch 5120 (/4 1280)
>[ 26819.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc6fa0]
>[ 26819.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc6fa0] width 1280 pitch 5120 (/4 1280)
>[ 26819.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9c4c8]
>[ 26819.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9c4c8] width 1280 pitch 5120 (/4 1280)
>[ 26820.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa118ab8]
>[ 26820.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa118ab8] width 1280 pitch 5120 (/4 1280)
>[ 26830.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d833c0]
>[ 26830.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d833c0] width 1280 pitch 5120 (/4 1280)
>[ 26830.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26830.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26839.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd3748]
>[ 26839.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd3748] width 1280 pitch 5120 (/4 1280)
>[ 26839.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bc6fa0]
>[ 26839.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bc6fa0] width 1280 pitch 5120 (/4 1280)
>[ 26839.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9c4c8]
>[ 26839.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9c4c8] width 1280 pitch 5120 (/4 1280)
>[ 26839.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa118ab8]
>[ 26839.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa118ab8] width 1280 pitch 5120 (/4 1280)
>[ 26839.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d833c0]
>[ 26839.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d833c0] width 1280 pitch 5120 (/4 1280)
>[ 26840.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9b9bf20]
>[ 26840.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9b9bf20] width 1280 pitch 5120 (/4 1280)
>[ 26840.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bd3748]
>[ 26840.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bd3748] width 1280 pitch 5120 (/4 1280)
>[ 27423.795] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 27423.795] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 27423.827] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 27512.857] (II) RADEON(0): RADEONSaveScreen(2)
>[ 27512.867] (II) RADEON(0): RADEONSaveScreen(0)
>[ 28614.436] (II) RADEON(0): RADEONSaveScreen(1)
>[ 28629.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d04250]
>[ 28629.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d04250] width 1280 pitch 5120 (/4 1280)
>[ 28629.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bbfff0]
>[ 28629.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bbfff0] width 1280 pitch 5120 (/4 1280)
>[ 28630.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bbfff0]
>[ 28630.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bbfff0] width 1280 pitch 5120 (/4 1280)
>[ 28631.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca00a0]
>[ 28631.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca00a0] width 1280 pitch 5120 (/4 1280)
>[ 28632.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bbfff0]
>[ 28632.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bbfff0] width 1280 pitch 5120 (/4 1280)
>[ 28632.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa104f18]
>[ 28632.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa104f18] width 1280 pitch 5120 (/4 1280)
>[ 28632.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca00a0]
>[ 28632.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca00a0] width 1280 pitch 5120 (/4 1280)
>[ 28633.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa104f18]
>[ 28633.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa104f18] width 1280 pitch 5120 (/4 1280)
>[ 28634.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca00a0]
>[ 28634.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca00a0] width 1280 pitch 5120 (/4 1280)
>[ 28634.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa118ab8]
>[ 28634.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa118ab8] width 1280 pitch 5120 (/4 1280)
>[ 28634.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9ca5538]
>[ 28634.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9ca5538] width 1280 pitch 5120 (/4 1280)
>[ 28634.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bbfff0]
>[ 28634.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bbfff0] width 1280 pitch 5120 (/4 1280)
>[ 28634.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa118ab8]
>[ 28635.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa118ab8] width 1280 pitch 5120 (/4 1280)
>[ 28678.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28678.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28678.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28678.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28678.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28678.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28678.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28678.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28678.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28678.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28678.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28678.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28678.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28678.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28678.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28678.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28678.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28678.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28679.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28679.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28680.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28680.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28680.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28680.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28680.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a610]
>[ 28680.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a610] width 1280 pitch 5120 (/4 1280)
>[ 28680.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28680.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28680.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a610]
>[ 28680.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a610] width 1280 pitch 5120 (/4 1280)
>[ 28681.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a610]
>[ 28681.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a610] width 1280 pitch 5120 (/4 1280)
>[ 28681.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28681.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28682.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a610]
>[ 28682.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a610] width 1280 pitch 5120 (/4 1280)
>[ 28682.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28682.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28682.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa15a610]
>[ 28682.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa15a610] width 1280 pitch 5120 (/4 1280)
>[ 28683.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28683.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28683.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa132e90]
>[ 28683.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa132e90] width 1280 pitch 5120 (/4 1280)
>[ 28683.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9fcd9f0]
>[ 28683.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9fcd9f0] width 1280 pitch 5120 (/4 1280)
>[ 28683.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa132e90]
>[ 28683.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa132e90] width 1280 pitch 5120 (/4 1280)
>[ 28697.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9da8fc8]
>[ 28697.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9da8fc8] width 1280 pitch 5120 (/4 1280)
>[ 28707.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9dad638]
>[ 28707.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9dad638] width 1280 pitch 5120 (/4 1280)
>[ 28707.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12f978]
>[ 28707.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12f978] width 1280 pitch 5120 (/4 1280)
>[ 28707.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12f918]
>[ 28707.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12f918] width 1280 pitch 5120 (/4 1280)
>[ 28707.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12f918]
>[ 28708.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12f918] width 1280 pitch 5120 (/4 1280)
>[ 28711.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12c638]
>[ 28711.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12c638] width 1280 pitch 5120 (/4 1280)
>[ 28711.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1370a8]
>[ 28712.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1370a8] width 1280 pitch 5120 (/4 1280)
>[ 28712.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12c638]
>[ 28712.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12c638] width 1280 pitch 5120 (/4 1280)
>[ 28712.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1370a8]
>[ 28712.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1370a8] width 1280 pitch 5120 (/4 1280)
>[ 28712.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12c638]
>[ 28712.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12c638] width 1280 pitch 5120 (/4 1280)
>[ 28712.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1370a8]
>[ 28712.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1370a8] width 1280 pitch 5120 (/4 1280)
>[ 28712.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12c638]
>[ 28712.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12c638] width 1280 pitch 5120 (/4 1280)
>[ 28712.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1370a8]
>[ 28712.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1370a8] width 1280 pitch 5120 (/4 1280)
>[ 28712.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e65718]
>[ 28712.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e65718] width 1280 pitch 5120 (/4 1280)
>[ 28742.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa10ce70]
>[ 28742.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa10ce70] width 1280 pitch 5120 (/4 1280)
>[ 28742.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa164678]
>[ 28742.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa164678] width 1280 pitch 5120 (/4 1280)
>[ 28742.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb45a0]
>[ 28742.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb45a0] width 1280 pitch 5120 (/4 1280)
>[ 28742.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa136518]
>[ 28743.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa136518] width 1280 pitch 5120 (/4 1280)
>[ 28748.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb45a0]
>[ 28748.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb45a0] width 1280 pitch 5120 (/4 1280)
>[ 28751.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e821d0]
>[ 28751.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e821d0] width 1280 pitch 5120 (/4 1280)
>[ 28751.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa132e90]
>[ 28751.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa132e90] width 1280 pitch 5120 (/4 1280)
>[ 28751.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cb50]
>[ 28752.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cb50] width 1280 pitch 5120 (/4 1280)
>[ 28752.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa132e90]
>[ 28752.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa132e90] width 1280 pitch 5120 (/4 1280)
>[ 28758.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12e838]
>[ 28758.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12e838] width 1280 pitch 5120 (/4 1280)
>[ 28758.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d9f210]
>[ 28758.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d9f210] width 1280 pitch 5120 (/4 1280)
>[ 28758.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12e838]
>[ 28758.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12e838] width 1280 pitch 5120 (/4 1280)
>[ 28758.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa107258]
>[ 28758.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa107258] width 1280 pitch 5120 (/4 1280)
>[ 28758.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa107228]
>[ 28758.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa107228] width 1280 pitch 5120 (/4 1280)
>[ 28758.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa107258]
>[ 28758.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa107258] width 1280 pitch 5120 (/4 1280)
>[ 28758.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa107228]
>[ 28758.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa107228] width 1280 pitch 5120 (/4 1280)
>[ 28758.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa107258]
>[ 28758.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa107258] width 1280 pitch 5120 (/4 1280)
>[ 28758.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12e838]
>[ 28758.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12e838] width 1280 pitch 5120 (/4 1280)
>[ 28762.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28762.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28762.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa12e838]
>[ 28762.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa12e838] width 1280 pitch 5120 (/4 1280)
>[ 28762.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28762.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28762.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1162d0]
>[ 28762.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1162d0] width 1280 pitch 5120 (/4 1280)
>[ 28762.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb45a0]
>[ 28762.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb45a0] width 1280 pitch 5120 (/4 1280)
>[ 28762.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28762.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28762.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1194b8]
>[ 28763.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1194b8] width 1280 pitch 5120 (/4 1280)
>[ 28763.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28763.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28763.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1194b8]
>[ 28763.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1194b8] width 1280 pitch 5120 (/4 1280)
>[ 28763.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28763.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28763.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1194b8]
>[ 28763.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1194b8] width 1280 pitch 5120 (/4 1280)
>[ 28763.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa026d50]
>[ 28763.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa026d50] width 1280 pitch 5120 (/4 1280)
>[ 28763.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1194b8]
>[ 28763.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1194b8] width 1280 pitch 5120 (/4 1280)
>[ 28763.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f65570]
>[ 28763.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f65570] width 1280 pitch 5120 (/4 1280)
>[ 28763.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa13a2b8]
>[ 28763.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa13a2b8] width 1280 pitch 5120 (/4 1280)
>[ 28763.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f65570]
>[ 28763.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f65570] width 1280 pitch 5120 (/4 1280)
>[ 28763.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f3cb50]
>[ 28763.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f3cb50] width 1280 pitch 5120 (/4 1280)
>[ 28763.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9e86230]
>[ 28763.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9e86230] width 1280 pitch 5120 (/4 1280)
>[ 28763.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa13a2b8]
>[ 28764.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa13a2b8] width 1280 pitch 5120 (/4 1280)
>[ 28764.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9db22d8]
>[ 28764.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9db22d8] width 1280 pitch 5120 (/4 1280)
>[ 28764.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f65570]
>[ 28764.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f65570] width 1280 pitch 5120 (/4 1280)
>[ 28764.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9db2608]
>[ 28764.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9db2608] width 1280 pitch 5120 (/4 1280)
>[ 28772.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d88700]
>[ 28772.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d88700] width 1280 pitch 5120 (/4 1280)
>[ 28772.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d95af0]
>[ 28772.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d95af0] width 1280 pitch 5120 (/4 1280)
>[ 28772.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d88700]
>[ 28772.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d88700] width 1280 pitch 5120 (/4 1280)
>[ 28772.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d95af0]
>[ 28772.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d95af0] width 1280 pitch 5120 (/4 1280)
>[ 28772.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d88700]
>[ 28772.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d88700] width 1280 pitch 5120 (/4 1280)
>[ 28772.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d85838]
>[ 28772.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d85838] width 1280 pitch 5120 (/4 1280)
>[ 28772.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d88700]
>[ 28772.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d88700] width 1280 pitch 5120 (/4 1280)
>[ 28772.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d85838]
>[ 28772.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d85838] width 1280 pitch 5120 (/4 1280)
>[ 28772.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9d88700]
>[ 28773.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9d88700] width 1280 pitch 5120 (/4 1280)
>[ 28816.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1e2e90]
>[ 28816.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1e2e90] width 1280 pitch 5120 (/4 1280)
>[ 28821.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa16a928]
>[ 28821.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa16a928] width 1280 pitch 5120 (/4 1280)
>[ 28826.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa11b7f0]
>[ 28826.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa11b7f0] width 1280 pitch 5120 (/4 1280)
>[ 28830.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9f65610]
>[ 28830.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9f65610] width 1280 pitch 5120 (/4 1280)
>[ 28978.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa178390]
>[ 28979.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa178390] width 1280 pitch 5120 (/4 1280)
>[ 28982.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9df9d70]
>[ 28982.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9df9d70] width 1280 pitch 5120 (/4 1280)
>[ 28984.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9c93848]
>[ 28984.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9c93848] width 1280 pitch 5120 (/4 1280)
>[ 28987.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9cf72c8]
>[ 28987.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9cf72c8] width 1280 pitch 5120 (/4 1280)
>[ 28999.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa16d288]
>[ 28999.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa16d288] width 1280 pitch 5120 (/4 1280)
>[ 29008.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4300]
>[ 29008.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4300] width 1280 pitch 5120 (/4 1280)
>[ 29008.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1dff48]
>[ 29008.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1dff48] width 1280 pitch 5120 (/4 1280)
>[ 29008.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4300]
>[ 29008.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4300] width 1280 pitch 5120 (/4 1280)
>[ 29008.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1dff48]
>[ 29008.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1dff48] width 1280 pitch 5120 (/4 1280)
>[ 29008.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4300]
>[ 29008.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4300] width 1280 pitch 5120 (/4 1280)
>[ 29008.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1dff48]
>[ 29008.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1dff48] width 1280 pitch 5120 (/4 1280)
>[ 29008.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4300]
>[ 29008.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4300] width 1280 pitch 5120 (/4 1280)
>[ 29008.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1dff48]
>[ 29008.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1dff48] width 1280 pitch 5120 (/4 1280)
>[ 29008.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x9bb4300]
>[ 29008.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x9bb4300] width 1280 pitch 5120 (/4 1280)
>[ 29010.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1e0770]
>[ 29010.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1e0770] width 1280 pitch 5120 (/4 1280)
>[ 29024.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa282560]
>[ 29024.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa282560] width 1280 pitch 5120 (/4 1280)
>[ 29033.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1696c0]
>[ 29033.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1696c0] width 1280 pitch 5120 (/4 1280)
>[ 29095.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa199660]
>[ 29095.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa199660] width 1280 pitch 5120 (/4 1280)
>[ 29095.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1dff48]
>[ 29095.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1dff48] width 1280 pitch 5120 (/4 1280)
>[ 29111.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa281ce8]
>[ 29111.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa281ce8] width 1280 pitch 5120 (/4 1280)
>[ 29113.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa172e38]
>[ 29113.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa172e38] width 1280 pitch 5120 (/4 1280)
>[ 29120.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa16e8a8]
>[ 29121.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa16e8a8] width 1280 pitch 5120 (/4 1280)
>[ 29139.429] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[ 29139.429] 
>[ 29139.429] Backtrace:
>[ 29141.643] 0: /usr/bin/Xorg (xorg_backtrace+0x4a) [0x80ac51a]
>[ 29141.643] 1: /usr/bin/Xorg (mieqEnqueue+0x22b) [0x81aaa4b]
>[ 29141.643] 2: /usr/bin/Xorg (0x8047000+0x4593c) [0x808c93c]
>[ 29141.643] 3: /usr/bin/Xorg (xf86PostMotionEventM+0x253) [0x80da033]
>[ 29141.643] 4: /usr/lib/xorg/modules/input/evdev_drv.so (0xb6e08000+0x3e2e) [0xb6e0be2e]
>[ 29141.643] 5: /usr/lib/xorg/modules/input/evdev_drv.so (0xb6e08000+0x5534) [0xb6e0d534]
>[ 29141.643] 6: /usr/bin/Xorg (0x8047000+0x82432) [0x80c9432]
>[ 29141.643] 7: /usr/bin/Xorg (0x8047000+0xa8803) [0x80ef803]
>[ 29141.643] 8: (vdso) (__kernel_sigreturn+0x0) [0xb773a400]
>[ 29141.643] 9: /usr/bin/Xorg (0x8047000+0x6afd0) [0x80b1fd0]
>[ 29141.643] 10: (vdso) (__kernel_sigreturn+0x0) [0xb773a400]
>[ 29141.644] 11: /lib/libc.so.6 (cfree+0x36) [0x4ab980c6]
>[ 29141.644] 12: /usr/bin/Xorg (0x8047000+0x4c6e5) [0x80936e5]
>[ 29141.644] 13: /usr/bin/Xorg (0x8047000+0x495d3) [0x80905d3]
>[ 29141.692] 14: /usr/bin/Xorg (DeletePassiveGrab+0x44) [0x80907f4]
>[ 29141.692] 15: /usr/bin/Xorg (0x8047000+0x53ddd) [0x809addd]
>[ 29141.692] 16: /usr/bin/Xorg (FreeResource+0xec) [0x809b5ac]
>[ 29141.692] 17: /usr/bin/Xorg (DeletePassiveGrabFromList+0x469) [0x8090e59]
>[ 29141.692] 18: /usr/bin/Xorg (ProcUngrabKey+0x115) [0x8085165]
>[ 29141.692] 19: /usr/bin/Xorg (0x8047000+0x3044d) [0x807744d]
>[ 29141.692] 20: /usr/bin/Xorg (0x8047000+0x1dce5) [0x8064ce5]
>[ 29141.692] 21: /lib/libc.so.6 (__libc_start_main+0xf5) [0x4ab38635]
>[ 29141.692] 22: /usr/bin/Xorg (0x8047000+0x1e029) [0x8065029]
>[ 29141.692] 
>[ 29141.692] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[ 29141.692] [mi] mieq is *NOT* the cause.  It is a victim.
>[ 29142.249] [mi] Increasing EQ size to 512 to prevent dropped events.
>[ 29142.249] [mi] EQ processing has resumed after 17 dropped events.
>[ 29142.249] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.
>[ 29152.930] (II) RADEON(0): EDID vendor "SEC", prod id 16706
>[ 29154.062] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 29154.062] (II) RADEON(0): Modeline "1280x800"x0.0   68.94  1280 1292 1356 1408  800 803 806 816 -hsync -vsync (49.0 kHz eP)
>[ 29168.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0xa1186c0]
>[ 29168.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0xa1186c0] width 1280 pitch 5120 (/4 1280)

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Attachments on bug 890056: 668570 | 668571 | 668572 | 668573 | 668574 | 668575